14f04d8f0SCatalin Marinas /* 24f04d8f0SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 34f04d8f0SCatalin Marinas * 44f04d8f0SCatalin Marinas * This program is free software; you can redistribute it and/or modify 54f04d8f0SCatalin Marinas * it under the terms of the GNU General Public License version 2 as 64f04d8f0SCatalin Marinas * published by the Free Software Foundation. 74f04d8f0SCatalin Marinas * 84f04d8f0SCatalin Marinas * This program is distributed in the hope that it will be useful, 94f04d8f0SCatalin Marinas * but WITHOUT ANY WARRANTY; without even the implied warranty of 104f04d8f0SCatalin Marinas * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 114f04d8f0SCatalin Marinas * GNU General Public License for more details. 124f04d8f0SCatalin Marinas * 134f04d8f0SCatalin Marinas * You should have received a copy of the GNU General Public License 144f04d8f0SCatalin Marinas * along with this program. If not, see <http://www.gnu.org/licenses/>. 154f04d8f0SCatalin Marinas */ 164f04d8f0SCatalin Marinas #ifndef __ASM_PGTABLE_H 174f04d8f0SCatalin Marinas #define __ASM_PGTABLE_H 184f04d8f0SCatalin Marinas 192f4b829cSCatalin Marinas #include <asm/bug.h> 204f04d8f0SCatalin Marinas #include <asm/proc-fns.h> 214f04d8f0SCatalin Marinas 224f04d8f0SCatalin Marinas #include <asm/memory.h> 234f04d8f0SCatalin Marinas #include <asm/pgtable-hwdef.h> 243eca86e7SMark Rutland #include <asm/pgtable-prot.h> 254f04d8f0SCatalin Marinas 264f04d8f0SCatalin Marinas /* 273e1907d5SArd Biesheuvel * VMALLOC range. 2808375198SCatalin Marinas * 29f9040773SArd Biesheuvel * VMALLOC_START: beginning of the kernel vmalloc space 303e1907d5SArd Biesheuvel * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space 313e1907d5SArd Biesheuvel * and fixed mappings 324f04d8f0SCatalin Marinas */ 33f9040773SArd Biesheuvel #define VMALLOC_START (MODULES_END) 3408375198SCatalin Marinas #define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K) 354f04d8f0SCatalin Marinas 363bab79edSArd Biesheuvel #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 374f04d8f0SCatalin Marinas 38d016bf7eSKirill A. Shutemov #define FIRST_USER_ADDRESS 0UL 394f04d8f0SCatalin Marinas 404f04d8f0SCatalin Marinas #ifndef __ASSEMBLY__ 412f4b829cSCatalin Marinas 423bbf7157SCatalin Marinas #include <asm/cmpxchg.h> 43961faac1SMark Rutland #include <asm/fixmap.h> 442f4b829cSCatalin Marinas #include <linux/mmdebug.h> 452f4b829cSCatalin Marinas 464f04d8f0SCatalin Marinas extern void __pte_error(const char *file, int line, unsigned long val); 474f04d8f0SCatalin Marinas extern void __pmd_error(const char *file, int line, unsigned long val); 48c79b954bSJungseok Lee extern void __pud_error(const char *file, int line, unsigned long val); 494f04d8f0SCatalin Marinas extern void __pgd_error(const char *file, int line, unsigned long val); 504f04d8f0SCatalin Marinas 514f04d8f0SCatalin Marinas /* 524f04d8f0SCatalin Marinas * ZERO_PAGE is a global shared page that is always zero: used 534f04d8f0SCatalin Marinas * for zero-mapped memory areas etc.. 544f04d8f0SCatalin Marinas */ 555227cfa7SMark Rutland extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 562077be67SLaura Abbott #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 574f04d8f0SCatalin Marinas 587078db46SCatalin Marinas #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) 597078db46SCatalin Marinas 604f04d8f0SCatalin Marinas #define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT) 614f04d8f0SCatalin Marinas 624f04d8f0SCatalin Marinas #define pfn_pte(pfn,prot) (__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) 634f04d8f0SCatalin Marinas 644f04d8f0SCatalin Marinas #define pte_none(pte) (!pte_val(pte)) 654f04d8f0SCatalin Marinas #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 664f04d8f0SCatalin Marinas #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 677078db46SCatalin Marinas 684f04d8f0SCatalin Marinas /* 694f04d8f0SCatalin Marinas * The following only work if pte_present(). Undefined behaviour otherwise. 704f04d8f0SCatalin Marinas */ 7184fe6826SSteve Capper #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 7284fe6826SSteve Capper #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 7384fe6826SSteve Capper #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 7484fe6826SSteve Capper #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 75ec663d96SCatalin Marinas #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 7693ef666aSJeremy Linton #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 774f04d8f0SCatalin Marinas 78d27cfa1fSArd Biesheuvel #define pte_cont_addr_end(addr, end) \ 79d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 80d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 81d27cfa1fSArd Biesheuvel }) 82d27cfa1fSArd Biesheuvel 83d27cfa1fSArd Biesheuvel #define pmd_cont_addr_end(addr, end) \ 84d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 85d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 86d27cfa1fSArd Biesheuvel }) 87d27cfa1fSArd Biesheuvel 88b847415cSCatalin Marinas #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) 892f4b829cSCatalin Marinas #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 902f4b829cSCatalin Marinas #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 912f4b829cSCatalin Marinas 92766ffb69SWill Deacon #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 93ec663d96SCatalin Marinas /* 94ec663d96SCatalin Marinas * Execute-only user mappings do not have the PTE_USER bit set. All valid 95ec663d96SCatalin Marinas * kernel mappings have the PTE_UXN bit set. 96ec663d96SCatalin Marinas */ 97ec663d96SCatalin Marinas #define pte_valid_not_user(pte) \ 98ec663d96SCatalin Marinas ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 9976c714beSWill Deacon #define pte_valid_young(pte) \ 10076c714beSWill Deacon ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF)) 101*6218f96cSCatalin Marinas #define pte_valid_user(pte) \ 102*6218f96cSCatalin Marinas ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) 10376c714beSWill Deacon 10476c714beSWill Deacon /* 10576c714beSWill Deacon * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 10676c714beSWill Deacon * so that we don't erroneously return false for pages that have been 10776c714beSWill Deacon * remapped as PROT_NONE but are yet to be flushed from the TLB. 10876c714beSWill Deacon */ 10976c714beSWill Deacon #define pte_accessible(mm, pte) \ 11076c714beSWill Deacon (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte)) 1114f04d8f0SCatalin Marinas 112*6218f96cSCatalin Marinas /* 113*6218f96cSCatalin Marinas * p??_access_permitted() is true for valid user mappings (subject to the 114*6218f96cSCatalin Marinas * write permission check) other than user execute-only which do not have the 115*6218f96cSCatalin Marinas * PTE_USER bit set. PROT_NONE mappings do not have the PTE_VALID bit set. 116*6218f96cSCatalin Marinas */ 117*6218f96cSCatalin Marinas #define pte_access_permitted(pte, write) \ 118*6218f96cSCatalin Marinas (pte_valid_user(pte) && (!(write) || pte_write(pte))) 119*6218f96cSCatalin Marinas #define pmd_access_permitted(pmd, write) \ 120*6218f96cSCatalin Marinas (pte_access_permitted(pmd_pte(pmd), (write))) 121*6218f96cSCatalin Marinas #define pud_access_permitted(pud, write) \ 122*6218f96cSCatalin Marinas (pte_access_permitted(pud_pte(pud), (write))) 123*6218f96cSCatalin Marinas 124b6d4f280SLaura Abbott static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 125b6d4f280SLaura Abbott { 126b6d4f280SLaura Abbott pte_val(pte) &= ~pgprot_val(prot); 127b6d4f280SLaura Abbott return pte; 128b6d4f280SLaura Abbott } 129b6d4f280SLaura Abbott 130b6d4f280SLaura Abbott static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 131b6d4f280SLaura Abbott { 132b6d4f280SLaura Abbott pte_val(pte) |= pgprot_val(prot); 133b6d4f280SLaura Abbott return pte; 134b6d4f280SLaura Abbott } 135b6d4f280SLaura Abbott 13644b6dfc5SSteve Capper static inline pte_t pte_wrprotect(pte_t pte) 13744b6dfc5SSteve Capper { 13873e86cb0SCatalin Marinas pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 13973e86cb0SCatalin Marinas pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 14073e86cb0SCatalin Marinas return pte; 14144b6dfc5SSteve Capper } 1424f04d8f0SCatalin Marinas 14344b6dfc5SSteve Capper static inline pte_t pte_mkwrite(pte_t pte) 14444b6dfc5SSteve Capper { 14573e86cb0SCatalin Marinas pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 14673e86cb0SCatalin Marinas pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 14773e86cb0SCatalin Marinas return pte; 14844b6dfc5SSteve Capper } 14944b6dfc5SSteve Capper 15044b6dfc5SSteve Capper static inline pte_t pte_mkclean(pte_t pte) 15144b6dfc5SSteve Capper { 152b6d4f280SLaura Abbott return clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 15344b6dfc5SSteve Capper } 15444b6dfc5SSteve Capper 15544b6dfc5SSteve Capper static inline pte_t pte_mkdirty(pte_t pte) 15644b6dfc5SSteve Capper { 157b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_DIRTY)); 15844b6dfc5SSteve Capper } 15944b6dfc5SSteve Capper 16044b6dfc5SSteve Capper static inline pte_t pte_mkold(pte_t pte) 16144b6dfc5SSteve Capper { 162b6d4f280SLaura Abbott return clear_pte_bit(pte, __pgprot(PTE_AF)); 16344b6dfc5SSteve Capper } 16444b6dfc5SSteve Capper 16544b6dfc5SSteve Capper static inline pte_t pte_mkyoung(pte_t pte) 16644b6dfc5SSteve Capper { 167b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_AF)); 16844b6dfc5SSteve Capper } 16944b6dfc5SSteve Capper 17044b6dfc5SSteve Capper static inline pte_t pte_mkspecial(pte_t pte) 17144b6dfc5SSteve Capper { 172b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 17344b6dfc5SSteve Capper } 1744f04d8f0SCatalin Marinas 17593ef666aSJeremy Linton static inline pte_t pte_mkcont(pte_t pte) 17693ef666aSJeremy Linton { 17766b3923aSDavid Woods pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 17866b3923aSDavid Woods return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 17993ef666aSJeremy Linton } 18093ef666aSJeremy Linton 18193ef666aSJeremy Linton static inline pte_t pte_mknoncont(pte_t pte) 18293ef666aSJeremy Linton { 18393ef666aSJeremy Linton return clear_pte_bit(pte, __pgprot(PTE_CONT)); 18493ef666aSJeremy Linton } 18593ef666aSJeremy Linton 1865ebe3a44SJames Morse static inline pte_t pte_mkpresent(pte_t pte) 1875ebe3a44SJames Morse { 1885ebe3a44SJames Morse return set_pte_bit(pte, __pgprot(PTE_VALID)); 1895ebe3a44SJames Morse } 1905ebe3a44SJames Morse 19166b3923aSDavid Woods static inline pmd_t pmd_mkcont(pmd_t pmd) 19266b3923aSDavid Woods { 19366b3923aSDavid Woods return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 19466b3923aSDavid Woods } 19566b3923aSDavid Woods 1964f04d8f0SCatalin Marinas static inline void set_pte(pte_t *ptep, pte_t pte) 1974f04d8f0SCatalin Marinas { 1984f04d8f0SCatalin Marinas *ptep = pte; 1997f0b1bf0SCatalin Marinas 2007f0b1bf0SCatalin Marinas /* 2017f0b1bf0SCatalin Marinas * Only if the new pte is valid and kernel, otherwise TLB maintenance 2027f0b1bf0SCatalin Marinas * or update_mmu_cache() have the necessary barriers. 2037f0b1bf0SCatalin Marinas */ 204ec663d96SCatalin Marinas if (pte_valid_not_user(pte)) { 2057f0b1bf0SCatalin Marinas dsb(ishst); 2067f0b1bf0SCatalin Marinas isb(); 2077f0b1bf0SCatalin Marinas } 2084f04d8f0SCatalin Marinas } 2094f04d8f0SCatalin Marinas 2102f4b829cSCatalin Marinas struct mm_struct; 2112f4b829cSCatalin Marinas struct vm_area_struct; 2122f4b829cSCatalin Marinas 2134f04d8f0SCatalin Marinas extern void __sync_icache_dcache(pte_t pteval, unsigned long addr); 2144f04d8f0SCatalin Marinas 2152f4b829cSCatalin Marinas /* 2162f4b829cSCatalin Marinas * PTE bits configuration in the presence of hardware Dirty Bit Management 2172f4b829cSCatalin Marinas * (PTE_WRITE == PTE_DBM): 2182f4b829cSCatalin Marinas * 2192f4b829cSCatalin Marinas * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 2202f4b829cSCatalin Marinas * 0 0 | 1 0 0 2212f4b829cSCatalin Marinas * 0 1 | 1 1 0 2222f4b829cSCatalin Marinas * 1 0 | 1 0 1 2232f4b829cSCatalin Marinas * 1 1 | 0 1 x 2242f4b829cSCatalin Marinas * 2252f4b829cSCatalin Marinas * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 2262f4b829cSCatalin Marinas * the page fault mechanism. Checking the dirty status of a pte becomes: 2272f4b829cSCatalin Marinas * 228b847415cSCatalin Marinas * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 2292f4b829cSCatalin Marinas */ 2304f04d8f0SCatalin Marinas static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 2314f04d8f0SCatalin Marinas pte_t *ptep, pte_t pte) 2324f04d8f0SCatalin Marinas { 23373e86cb0SCatalin Marinas if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 234ac15bd63SCatalin Marinas __sync_icache_dcache(pte, addr); 23502522463SWill Deacon 2362f4b829cSCatalin Marinas /* 2372f4b829cSCatalin Marinas * If the existing pte is valid, check for potential race with 2382f4b829cSCatalin Marinas * hardware updates of the pte (ptep_set_access_flags safely changes 2392f4b829cSCatalin Marinas * valid ptes without going through an invalid entry). 2402f4b829cSCatalin Marinas */ 241af29678fSCatalin Marinas if (pte_valid(*ptep) && pte_valid(pte)) { 24282d34008SCatalin Marinas VM_WARN_ONCE(!pte_young(pte), 24382d34008SCatalin Marinas "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 24482d34008SCatalin Marinas __func__, pte_val(*ptep), pte_val(pte)); 24582d34008SCatalin Marinas VM_WARN_ONCE(pte_write(*ptep) && !pte_dirty(pte), 24682d34008SCatalin Marinas "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 24782d34008SCatalin Marinas __func__, pte_val(*ptep), pte_val(pte)); 2482f4b829cSCatalin Marinas } 2492f4b829cSCatalin Marinas 2504f04d8f0SCatalin Marinas set_pte(ptep, pte); 2514f04d8f0SCatalin Marinas } 2524f04d8f0SCatalin Marinas 253747a70e6SSteve Capper #define __HAVE_ARCH_PTE_SAME 254747a70e6SSteve Capper static inline int pte_same(pte_t pte_a, pte_t pte_b) 255747a70e6SSteve Capper { 256747a70e6SSteve Capper pteval_t lhs, rhs; 257747a70e6SSteve Capper 258747a70e6SSteve Capper lhs = pte_val(pte_a); 259747a70e6SSteve Capper rhs = pte_val(pte_b); 260747a70e6SSteve Capper 261747a70e6SSteve Capper if (pte_present(pte_a)) 262747a70e6SSteve Capper lhs &= ~PTE_RDONLY; 263747a70e6SSteve Capper 264747a70e6SSteve Capper if (pte_present(pte_b)) 265747a70e6SSteve Capper rhs &= ~PTE_RDONLY; 266747a70e6SSteve Capper 267747a70e6SSteve Capper return (lhs == rhs); 268747a70e6SSteve Capper } 269747a70e6SSteve Capper 2704f04d8f0SCatalin Marinas /* 2714f04d8f0SCatalin Marinas * Huge pte definitions. 2724f04d8f0SCatalin Marinas */ 273084bd298SSteve Capper #define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT)) 274084bd298SSteve Capper #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 275084bd298SSteve Capper 276084bd298SSteve Capper /* 277084bd298SSteve Capper * Hugetlb definitions. 278084bd298SSteve Capper */ 27966b3923aSDavid Woods #define HUGE_MAX_HSTATE 4 280084bd298SSteve Capper #define HPAGE_SHIFT PMD_SHIFT 281084bd298SSteve Capper #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 282084bd298SSteve Capper #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 283084bd298SSteve Capper #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 2844f04d8f0SCatalin Marinas 2854f04d8f0SCatalin Marinas #define __HAVE_ARCH_PTE_SPECIAL 2864f04d8f0SCatalin Marinas 28729e56940SSteve Capper static inline pte_t pud_pte(pud_t pud) 28829e56940SSteve Capper { 28929e56940SSteve Capper return __pte(pud_val(pud)); 29029e56940SSteve Capper } 29129e56940SSteve Capper 29229e56940SSteve Capper static inline pmd_t pud_pmd(pud_t pud) 29329e56940SSteve Capper { 29429e56940SSteve Capper return __pmd(pud_val(pud)); 29529e56940SSteve Capper } 29629e56940SSteve Capper 2979c7e535fSSteve Capper static inline pte_t pmd_pte(pmd_t pmd) 2989c7e535fSSteve Capper { 2999c7e535fSSteve Capper return __pte(pmd_val(pmd)); 3009c7e535fSSteve Capper } 301af074848SSteve Capper 3029c7e535fSSteve Capper static inline pmd_t pte_pmd(pte_t pte) 3039c7e535fSSteve Capper { 3049c7e535fSSteve Capper return __pmd(pte_val(pte)); 3059c7e535fSSteve Capper } 306af074848SSteve Capper 3078ce837ceSArd Biesheuvel static inline pgprot_t mk_sect_prot(pgprot_t prot) 3088ce837ceSArd Biesheuvel { 3098ce837ceSArd Biesheuvel return __pgprot(pgprot_val(prot) & ~PTE_TABLE_BIT); 3108ce837ceSArd Biesheuvel } 3118ce837ceSArd Biesheuvel 31256166230SGanapatrao Kulkarni #ifdef CONFIG_NUMA_BALANCING 31356166230SGanapatrao Kulkarni /* 31456166230SGanapatrao Kulkarni * See the comment in include/asm-generic/pgtable.h 31556166230SGanapatrao Kulkarni */ 31656166230SGanapatrao Kulkarni static inline int pte_protnone(pte_t pte) 31756166230SGanapatrao Kulkarni { 31856166230SGanapatrao Kulkarni return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; 31956166230SGanapatrao Kulkarni } 32056166230SGanapatrao Kulkarni 32156166230SGanapatrao Kulkarni static inline int pmd_protnone(pmd_t pmd) 32256166230SGanapatrao Kulkarni { 32356166230SGanapatrao Kulkarni return pte_protnone(pmd_pte(pmd)); 32456166230SGanapatrao Kulkarni } 32556166230SGanapatrao Kulkarni #endif 32656166230SGanapatrao Kulkarni 327af074848SSteve Capper /* 328af074848SSteve Capper * THP definitions. 329af074848SSteve Capper */ 330af074848SSteve Capper 331af074848SSteve Capper #ifdef CONFIG_TRANSPARENT_HUGEPAGE 332af074848SSteve Capper #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) 33329e56940SSteve Capper #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 334af074848SSteve Capper 3355bb1cc0fSCatalin Marinas #define pmd_present(pmd) pte_present(pmd_pte(pmd)) 336c164e038SKirill A. Shutemov #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 3379c7e535fSSteve Capper #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 3389c7e535fSSteve Capper #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 3399c7e535fSSteve Capper #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 3409c7e535fSSteve Capper #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 34105ee26d9SMinchan Kim #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 3429c7e535fSSteve Capper #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 3439c7e535fSSteve Capper #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 3445bb1cc0fSCatalin Marinas #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_SECT_VALID)) 345af074848SSteve Capper 3460dbd3b18SSuzuki K Poulose #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 3470dbd3b18SSuzuki K Poulose 3489c7e535fSSteve Capper #define __HAVE_ARCH_PMD_WRITE 3499c7e535fSSteve Capper #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 350af074848SSteve Capper 351af074848SSteve Capper #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 352af074848SSteve Capper 353af074848SSteve Capper #define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT) 354af074848SSteve Capper #define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) 355af074848SSteve Capper #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 356af074848SSteve Capper 35729e56940SSteve Capper #define pud_write(pud) pte_write(pud_pte(pud)) 358206a2a73SSteve Capper #define pud_pfn(pud) (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT) 359af074848SSteve Capper 360ceb21835SWill Deacon #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) 361af074848SSteve Capper 362a501e324SCatalin Marinas #define __pgprot_modify(prot,mask,bits) \ 363a501e324SCatalin Marinas __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 364a501e324SCatalin Marinas 365af074848SSteve Capper /* 3664f04d8f0SCatalin Marinas * Mark the prot value as uncacheable and unbufferable. 3674f04d8f0SCatalin Marinas */ 3684f04d8f0SCatalin Marinas #define pgprot_noncached(prot) \ 369de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 3704f04d8f0SCatalin Marinas #define pgprot_writecombine(prot) \ 371de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 372d1e6dc91SLiviu Dudau #define pgprot_device(prot) \ 373d1e6dc91SLiviu Dudau __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 3744f04d8f0SCatalin Marinas #define __HAVE_PHYS_MEM_ACCESS_PROT 3754f04d8f0SCatalin Marinas struct file; 3764f04d8f0SCatalin Marinas extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 3774f04d8f0SCatalin Marinas unsigned long size, pgprot_t vma_prot); 3784f04d8f0SCatalin Marinas 3794f04d8f0SCatalin Marinas #define pmd_none(pmd) (!pmd_val(pmd)) 3804f04d8f0SCatalin Marinas 381ab4db1f2SCatalin Marinas #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT)) 3824f04d8f0SCatalin Marinas 38336311607SMarc Zyngier #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 38436311607SMarc Zyngier PMD_TYPE_TABLE) 38536311607SMarc Zyngier #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 38636311607SMarc Zyngier PMD_TYPE_SECT) 38736311607SMarc Zyngier 388cac4b8cdSCatalin Marinas #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 389206a2a73SSteve Capper #define pud_sect(pud) (0) 390523d6e9fSzhichang.yuan #define pud_table(pud) (1) 391206a2a73SSteve Capper #else 392206a2a73SSteve Capper #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 393206a2a73SSteve Capper PUD_TYPE_SECT) 394523d6e9fSzhichang.yuan #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 395523d6e9fSzhichang.yuan PUD_TYPE_TABLE) 396206a2a73SSteve Capper #endif 39736311607SMarc Zyngier 3984f04d8f0SCatalin Marinas static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 3994f04d8f0SCatalin Marinas { 4004f04d8f0SCatalin Marinas *pmdp = pmd; 40198f7685eSWill Deacon dsb(ishst); 4027f0b1bf0SCatalin Marinas isb(); 4034f04d8f0SCatalin Marinas } 4044f04d8f0SCatalin Marinas 4054f04d8f0SCatalin Marinas static inline void pmd_clear(pmd_t *pmdp) 4064f04d8f0SCatalin Marinas { 4074f04d8f0SCatalin Marinas set_pmd(pmdp, __pmd(0)); 4084f04d8f0SCatalin Marinas } 4094f04d8f0SCatalin Marinas 410dca56dcaSMark Rutland static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 4114f04d8f0SCatalin Marinas { 412dca56dcaSMark Rutland return pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK; 4134f04d8f0SCatalin Marinas } 4144f04d8f0SCatalin Marinas 415053520f7SMark Rutland /* Find an entry in the third-level page table. */ 416053520f7SMark Rutland #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 417053520f7SMark Rutland 418f069fabaSWill Deacon #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 419dca56dcaSMark Rutland #define pte_offset_kernel(dir,addr) ((pte_t *)__va(pte_offset_phys((dir), (addr)))) 420053520f7SMark Rutland 421053520f7SMark Rutland #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 422053520f7SMark Rutland #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr)) 423053520f7SMark Rutland #define pte_unmap(pte) do { } while (0) 424053520f7SMark Rutland #define pte_unmap_nested(pte) do { } while (0) 425053520f7SMark Rutland 426961faac1SMark Rutland #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 427961faac1SMark Rutland #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 428961faac1SMark Rutland #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 429961faac1SMark Rutland 4304f04d8f0SCatalin Marinas #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK)) 4314f04d8f0SCatalin Marinas 4326533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 4336533945aSArd Biesheuvel #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 4346533945aSArd Biesheuvel 4354f04d8f0SCatalin Marinas /* 4364f04d8f0SCatalin Marinas * Conversion functions: convert a page and protection to a page entry, 4374f04d8f0SCatalin Marinas * and a page entry and page directory to the page they refer to. 4384f04d8f0SCatalin Marinas */ 4394f04d8f0SCatalin Marinas #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 4404f04d8f0SCatalin Marinas 4419f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 2 4424f04d8f0SCatalin Marinas 4437078db46SCatalin Marinas #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) 4447078db46SCatalin Marinas 4454f04d8f0SCatalin Marinas #define pud_none(pud) (!pud_val(pud)) 446ab4db1f2SCatalin Marinas #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT)) 447f02ab08aSPunit Agrawal #define pud_present(pud) pte_present(pud_pte(pud)) 4484f04d8f0SCatalin Marinas 4494f04d8f0SCatalin Marinas static inline void set_pud(pud_t *pudp, pud_t pud) 4504f04d8f0SCatalin Marinas { 4514f04d8f0SCatalin Marinas *pudp = pud; 45298f7685eSWill Deacon dsb(ishst); 4537f0b1bf0SCatalin Marinas isb(); 4544f04d8f0SCatalin Marinas } 4554f04d8f0SCatalin Marinas 4564f04d8f0SCatalin Marinas static inline void pud_clear(pud_t *pudp) 4574f04d8f0SCatalin Marinas { 4584f04d8f0SCatalin Marinas set_pud(pudp, __pud(0)); 4594f04d8f0SCatalin Marinas } 4604f04d8f0SCatalin Marinas 461dca56dcaSMark Rutland static inline phys_addr_t pud_page_paddr(pud_t pud) 4624f04d8f0SCatalin Marinas { 463dca56dcaSMark Rutland return pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK; 4644f04d8f0SCatalin Marinas } 4654f04d8f0SCatalin Marinas 4667078db46SCatalin Marinas /* Find an entry in the second-level page table. */ 4677078db46SCatalin Marinas #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) 4687078db46SCatalin Marinas 469dca56dcaSMark Rutland #define pmd_offset_phys(dir, addr) (pud_page_paddr(*(dir)) + pmd_index(addr) * sizeof(pmd_t)) 470dca56dcaSMark Rutland #define pmd_offset(dir, addr) ((pmd_t *)__va(pmd_offset_phys((dir), (addr)))) 4717078db46SCatalin Marinas 472961faac1SMark Rutland #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 473961faac1SMark Rutland #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 474961faac1SMark Rutland #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 4754f04d8f0SCatalin Marinas 4765d96e0cbSJungseok Lee #define pud_page(pud) pfn_to_page(__phys_to_pfn(pud_val(pud) & PHYS_MASK)) 47729e56940SSteve Capper 4786533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 4796533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 4806533945aSArd Biesheuvel 481dca56dcaSMark Rutland #else 482dca56dcaSMark Rutland 483dca56dcaSMark Rutland #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 484dca56dcaSMark Rutland 485961faac1SMark Rutland /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 486961faac1SMark Rutland #define pmd_set_fixmap(addr) NULL 487961faac1SMark Rutland #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 488961faac1SMark Rutland #define pmd_clear_fixmap() 489961faac1SMark Rutland 4906533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 4916533945aSArd Biesheuvel 4929f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 4934f04d8f0SCatalin Marinas 4949f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 3 495c79b954bSJungseok Lee 4967078db46SCatalin Marinas #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud)) 4977078db46SCatalin Marinas 498c79b954bSJungseok Lee #define pgd_none(pgd) (!pgd_val(pgd)) 499c79b954bSJungseok Lee #define pgd_bad(pgd) (!(pgd_val(pgd) & 2)) 500c79b954bSJungseok Lee #define pgd_present(pgd) (pgd_val(pgd)) 501c79b954bSJungseok Lee 502c79b954bSJungseok Lee static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 503c79b954bSJungseok Lee { 504c79b954bSJungseok Lee *pgdp = pgd; 505c79b954bSJungseok Lee dsb(ishst); 506c79b954bSJungseok Lee } 507c79b954bSJungseok Lee 508c79b954bSJungseok Lee static inline void pgd_clear(pgd_t *pgdp) 509c79b954bSJungseok Lee { 510c79b954bSJungseok Lee set_pgd(pgdp, __pgd(0)); 511c79b954bSJungseok Lee } 512c79b954bSJungseok Lee 513dca56dcaSMark Rutland static inline phys_addr_t pgd_page_paddr(pgd_t pgd) 514c79b954bSJungseok Lee { 515dca56dcaSMark Rutland return pgd_val(pgd) & PHYS_MASK & (s32)PAGE_MASK; 516c79b954bSJungseok Lee } 517c79b954bSJungseok Lee 5187078db46SCatalin Marinas /* Find an entry in the frst-level page table. */ 5197078db46SCatalin Marinas #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 5207078db46SCatalin Marinas 521dca56dcaSMark Rutland #define pud_offset_phys(dir, addr) (pgd_page_paddr(*(dir)) + pud_index(addr) * sizeof(pud_t)) 522dca56dcaSMark Rutland #define pud_offset(dir, addr) ((pud_t *)__va(pud_offset_phys((dir), (addr)))) 5237078db46SCatalin Marinas 524961faac1SMark Rutland #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) 525961faac1SMark Rutland #define pud_set_fixmap_offset(pgd, addr) pud_set_fixmap(pud_offset_phys(pgd, addr)) 526961faac1SMark Rutland #define pud_clear_fixmap() clear_fixmap(FIX_PUD) 527c79b954bSJungseok Lee 5285d96e0cbSJungseok Lee #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(pgd_val(pgd) & PHYS_MASK)) 5295d96e0cbSJungseok Lee 5306533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 5316533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) 5326533945aSArd Biesheuvel 533dca56dcaSMark Rutland #else 534dca56dcaSMark Rutland 535dca56dcaSMark Rutland #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) 536dca56dcaSMark Rutland 537961faac1SMark Rutland /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 538961faac1SMark Rutland #define pud_set_fixmap(addr) NULL 539961faac1SMark Rutland #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 540961faac1SMark Rutland #define pud_clear_fixmap() 541961faac1SMark Rutland 5426533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 5436533945aSArd Biesheuvel 5449f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 545c79b954bSJungseok Lee 5467078db46SCatalin Marinas #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) 5477078db46SCatalin Marinas 5484f04d8f0SCatalin Marinas /* to find an entry in a page-table-directory */ 5494f04d8f0SCatalin Marinas #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 5504f04d8f0SCatalin Marinas 551dca56dcaSMark Rutland #define pgd_offset_raw(pgd, addr) ((pgd) + pgd_index(addr)) 552dca56dcaSMark Rutland 553dca56dcaSMark Rutland #define pgd_offset(mm, addr) (pgd_offset_raw((mm)->pgd, (addr))) 5544f04d8f0SCatalin Marinas 5554f04d8f0SCatalin Marinas /* to find an entry in a kernel page-table-directory */ 5564f04d8f0SCatalin Marinas #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) 5574f04d8f0SCatalin Marinas 558961faac1SMark Rutland #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 559961faac1SMark Rutland #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 560961faac1SMark Rutland 5614f04d8f0SCatalin Marinas static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 5624f04d8f0SCatalin Marinas { 563a6fadf7eSWill Deacon const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 5641a541b4eSSteve Capper PTE_PROT_NONE | PTE_VALID | PTE_WRITE; 5652f4b829cSCatalin Marinas /* preserve the hardware dirty information */ 5662f4b829cSCatalin Marinas if (pte_hw_dirty(pte)) 56762d96c71SCatalin Marinas pte = pte_mkdirty(pte); 5684f04d8f0SCatalin Marinas pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 5694f04d8f0SCatalin Marinas return pte; 5704f04d8f0SCatalin Marinas } 5714f04d8f0SCatalin Marinas 5729c7e535fSSteve Capper static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 5739c7e535fSSteve Capper { 5749c7e535fSSteve Capper return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 5759c7e535fSSteve Capper } 5769c7e535fSSteve Capper 57766dbd6e6SCatalin Marinas #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 57866dbd6e6SCatalin Marinas extern int ptep_set_access_flags(struct vm_area_struct *vma, 57966dbd6e6SCatalin Marinas unsigned long address, pte_t *ptep, 58066dbd6e6SCatalin Marinas pte_t entry, int dirty); 58166dbd6e6SCatalin Marinas 582282aa705SCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 583282aa705SCatalin Marinas #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 584282aa705SCatalin Marinas static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 585282aa705SCatalin Marinas unsigned long address, pmd_t *pmdp, 586282aa705SCatalin Marinas pmd_t entry, int dirty) 587282aa705SCatalin Marinas { 588282aa705SCatalin Marinas return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 589282aa705SCatalin Marinas } 590282aa705SCatalin Marinas #endif 591282aa705SCatalin Marinas 5922f4b829cSCatalin Marinas /* 5932f4b829cSCatalin Marinas * Atomic pte/pmd modifications. 5942f4b829cSCatalin Marinas */ 5952f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 59606485053SCatalin Marinas static inline int __ptep_test_and_clear_young(pte_t *ptep) 5972f4b829cSCatalin Marinas { 5983bbf7157SCatalin Marinas pte_t old_pte, pte; 5992f4b829cSCatalin Marinas 6003bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 6013bbf7157SCatalin Marinas do { 6023bbf7157SCatalin Marinas old_pte = pte; 6033bbf7157SCatalin Marinas pte = pte_mkold(pte); 6043bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 6053bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 6063bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 6072f4b829cSCatalin Marinas 6083bbf7157SCatalin Marinas return pte_young(pte); 6092f4b829cSCatalin Marinas } 6102f4b829cSCatalin Marinas 61106485053SCatalin Marinas static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 61206485053SCatalin Marinas unsigned long address, 61306485053SCatalin Marinas pte_t *ptep) 61406485053SCatalin Marinas { 61506485053SCatalin Marinas return __ptep_test_and_clear_young(ptep); 61606485053SCatalin Marinas } 61706485053SCatalin Marinas 6182f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 6192f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 6202f4b829cSCatalin Marinas static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 6212f4b829cSCatalin Marinas unsigned long address, 6222f4b829cSCatalin Marinas pmd_t *pmdp) 6232f4b829cSCatalin Marinas { 6242f4b829cSCatalin Marinas return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 6252f4b829cSCatalin Marinas } 6262f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 6272f4b829cSCatalin Marinas 6282f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 6292f4b829cSCatalin Marinas static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 6302f4b829cSCatalin Marinas unsigned long address, pte_t *ptep) 6312f4b829cSCatalin Marinas { 6323bbf7157SCatalin Marinas return __pte(xchg_relaxed(&pte_val(*ptep), 0)); 6332f4b829cSCatalin Marinas } 6342f4b829cSCatalin Marinas 6352f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 636911f56eeSCatalin Marinas #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 637911f56eeSCatalin Marinas static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 6382f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 6392f4b829cSCatalin Marinas { 6402f4b829cSCatalin Marinas return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); 6412f4b829cSCatalin Marinas } 6422f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 6432f4b829cSCatalin Marinas 6442f4b829cSCatalin Marinas /* 64564c26841SCatalin Marinas * ptep_set_wrprotect - mark read-only while preserving the hardware update of 64664c26841SCatalin Marinas * the Access Flag. 6472f4b829cSCatalin Marinas */ 6482f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_SET_WRPROTECT 6492f4b829cSCatalin Marinas static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 6502f4b829cSCatalin Marinas { 6513bbf7157SCatalin Marinas pte_t old_pte, pte; 6522f4b829cSCatalin Marinas 65364c26841SCatalin Marinas /* 65464c26841SCatalin Marinas * ptep_set_wrprotect() is only called on CoW mappings which are 65564c26841SCatalin Marinas * private (!VM_SHARED) with the pte either read-only (!PTE_WRITE && 65664c26841SCatalin Marinas * PTE_RDONLY) or writable and software-dirty (PTE_WRITE && 65764c26841SCatalin Marinas * !PTE_RDONLY && PTE_DIRTY); see is_cow_mapping() and 65864c26841SCatalin Marinas * protection_map[]. There is no race with the hardware update of the 65964c26841SCatalin Marinas * dirty state: clearing of PTE_RDONLY when PTE_WRITE (a.k.a. PTE_DBM) 66064c26841SCatalin Marinas * is set. 66164c26841SCatalin Marinas */ 66264c26841SCatalin Marinas VM_WARN_ONCE(pte_write(*ptep) && !pte_dirty(*ptep), 66364c26841SCatalin Marinas "%s: potential race with hardware DBM", __func__); 6643bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 6653bbf7157SCatalin Marinas do { 6663bbf7157SCatalin Marinas old_pte = pte; 6673bbf7157SCatalin Marinas pte = pte_wrprotect(pte); 6683bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 6693bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 6703bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 6712f4b829cSCatalin Marinas } 6722f4b829cSCatalin Marinas 6732f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 6742f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_SET_WRPROTECT 6752f4b829cSCatalin Marinas static inline void pmdp_set_wrprotect(struct mm_struct *mm, 6762f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 6772f4b829cSCatalin Marinas { 6782f4b829cSCatalin Marinas ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 6792f4b829cSCatalin Marinas } 6802f4b829cSCatalin Marinas #endif 6812f4b829cSCatalin Marinas 6824f04d8f0SCatalin Marinas extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 6834f04d8f0SCatalin Marinas extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 6844f04d8f0SCatalin Marinas 6854f04d8f0SCatalin Marinas /* 6864f04d8f0SCatalin Marinas * Encode and decode a swap entry: 6873676f9efSCatalin Marinas * bits 0-1: present (must be zero) 6889b3e661eSKirill A. Shutemov * bits 2-7: swap type 6899b3e661eSKirill A. Shutemov * bits 8-57: swap offset 690fdc69e7dSCatalin Marinas * bit 58: PTE_PROT_NONE (must be zero) 6914f04d8f0SCatalin Marinas */ 6929b3e661eSKirill A. Shutemov #define __SWP_TYPE_SHIFT 2 6934f04d8f0SCatalin Marinas #define __SWP_TYPE_BITS 6 6949b3e661eSKirill A. Shutemov #define __SWP_OFFSET_BITS 50 6954f04d8f0SCatalin Marinas #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 6964f04d8f0SCatalin Marinas #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 6973676f9efSCatalin Marinas #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 6984f04d8f0SCatalin Marinas 6994f04d8f0SCatalin Marinas #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 7003676f9efSCatalin Marinas #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 7014f04d8f0SCatalin Marinas #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 7024f04d8f0SCatalin Marinas 7034f04d8f0SCatalin Marinas #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 7044f04d8f0SCatalin Marinas #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 7054f04d8f0SCatalin Marinas 7064f04d8f0SCatalin Marinas /* 7074f04d8f0SCatalin Marinas * Ensure that there are not more swap files than can be encoded in the kernel 708aad9061bSGeert Uytterhoeven * PTEs. 7094f04d8f0SCatalin Marinas */ 7104f04d8f0SCatalin Marinas #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 7114f04d8f0SCatalin Marinas 7124f04d8f0SCatalin Marinas extern int kern_addr_valid(unsigned long addr); 7134f04d8f0SCatalin Marinas 7144f04d8f0SCatalin Marinas #include <asm-generic/pgtable.h> 7154f04d8f0SCatalin Marinas 71639b5be9bSWill Deacon void pgd_cache_init(void); 71739b5be9bSWill Deacon #define pgtable_cache_init pgd_cache_init 7184f04d8f0SCatalin Marinas 719cba3574fSWill Deacon /* 720cba3574fSWill Deacon * On AArch64, the cache coherency is handled via the set_pte_at() function. 721cba3574fSWill Deacon */ 722cba3574fSWill Deacon static inline void update_mmu_cache(struct vm_area_struct *vma, 723cba3574fSWill Deacon unsigned long addr, pte_t *ptep) 724cba3574fSWill Deacon { 725cba3574fSWill Deacon /* 726120798d2SWill Deacon * We don't do anything here, so there's a very small chance of 727120798d2SWill Deacon * us retaking a user fault which we just fixed up. The alternative 728120798d2SWill Deacon * is doing a dsb(ishst), but that penalises the fastpath. 729cba3574fSWill Deacon */ 730cba3574fSWill Deacon } 731cba3574fSWill Deacon 732cba3574fSWill Deacon #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 733cba3574fSWill Deacon 73403875ad5Syalin wang #define kc_vaddr_to_offset(v) ((v) & ~VA_START) 73503875ad5Syalin wang #define kc_offset_to_vaddr(o) ((o) | VA_START) 7367db743c6SCatalin Marinas 7374f04d8f0SCatalin Marinas #endif /* !__ASSEMBLY__ */ 7384f04d8f0SCatalin Marinas 7394f04d8f0SCatalin Marinas #endif /* __ASM_PGTABLE_H */ 740