1caab277bSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 24f04d8f0SCatalin Marinas /* 34f04d8f0SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 44f04d8f0SCatalin Marinas */ 54f04d8f0SCatalin Marinas #ifndef __ASM_PGTABLE_H 64f04d8f0SCatalin Marinas #define __ASM_PGTABLE_H 74f04d8f0SCatalin Marinas 82f4b829cSCatalin Marinas #include <asm/bug.h> 94f04d8f0SCatalin Marinas #include <asm/proc-fns.h> 104f04d8f0SCatalin Marinas 114f04d8f0SCatalin Marinas #include <asm/memory.h> 1234bfeea4SCatalin Marinas #include <asm/mte.h> 134f04d8f0SCatalin Marinas #include <asm/pgtable-hwdef.h> 143eca86e7SMark Rutland #include <asm/pgtable-prot.h> 153403e56bSAlex Van Brunt #include <asm/tlbflush.h> 164f04d8f0SCatalin Marinas 174f04d8f0SCatalin Marinas /* 183e1907d5SArd Biesheuvel * VMALLOC range. 1908375198SCatalin Marinas * 20f9040773SArd Biesheuvel * VMALLOC_START: beginning of the kernel vmalloc space 21d432b8d5SArd Biesheuvel * VMALLOC_END: extends to the available space below vmemmap 224f04d8f0SCatalin Marinas */ 23f9040773SArd Biesheuvel #define VMALLOC_START (MODULES_END) 24d432b8d5SArd Biesheuvel #if VA_BITS == VA_BITS_MIN 25b730b0f2SArd Biesheuvel #define VMALLOC_END (VMEMMAP_START - SZ_8M) 26d432b8d5SArd Biesheuvel #else 27d432b8d5SArd Biesheuvel #define VMEMMAP_UNUSED_NPAGES ((_PAGE_OFFSET(vabits_actual) - PAGE_OFFSET) >> PAGE_SHIFT) 28d432b8d5SArd Biesheuvel #define VMALLOC_END (VMEMMAP_START + VMEMMAP_UNUSED_NPAGES * sizeof(struct page) - SZ_8M) 29d432b8d5SArd Biesheuvel #endif 304f04d8f0SCatalin Marinas 317bc1a0f9SArd Biesheuvel #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 327bc1a0f9SArd Biesheuvel 334f04d8f0SCatalin Marinas #ifndef __ASSEMBLY__ 342f4b829cSCatalin Marinas 353bbf7157SCatalin Marinas #include <asm/cmpxchg.h> 36961faac1SMark Rutland #include <asm/fixmap.h> 372f4b829cSCatalin Marinas #include <linux/mmdebug.h> 3886c9e812SWill Deacon #include <linux/mm_types.h> 3986c9e812SWill Deacon #include <linux/sched.h> 4042b25471SKefeng Wang #include <linux/page_table_check.h> 412f4b829cSCatalin Marinas 42a7ac1cfaSZhenyu Ye #ifdef CONFIG_TRANSPARENT_HUGEPAGE 43a7ac1cfaSZhenyu Ye #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 44a7ac1cfaSZhenyu Ye 45a7ac1cfaSZhenyu Ye /* Set stride and tlb_level in flush_*_tlb_range */ 46a7ac1cfaSZhenyu Ye #define flush_pmd_tlb_range(vma, addr, end) \ 47a7ac1cfaSZhenyu Ye __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) 48a7ac1cfaSZhenyu Ye #define flush_pud_tlb_range(vma, addr, end) \ 49a7ac1cfaSZhenyu Ye __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) 50a7ac1cfaSZhenyu Ye #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 51a7ac1cfaSZhenyu Ye 52d0637c50SBarry Song static inline bool arch_thp_swp_supported(void) 53d0637c50SBarry Song { 54d0637c50SBarry Song return !system_supports_mte(); 55d0637c50SBarry Song } 56d0637c50SBarry Song #define arch_thp_swp_supported arch_thp_swp_supported 57d0637c50SBarry Song 584f04d8f0SCatalin Marinas /* 596a1bdb17SWill Deacon * Outside of a few very special situations (e.g. hibernation), we always 606a1bdb17SWill Deacon * use broadcast TLB invalidation instructions, therefore a spurious page 616a1bdb17SWill Deacon * fault on one CPU which has been handled concurrently by another CPU 626a1bdb17SWill Deacon * does not need to perform additional invalidation. 636a1bdb17SWill Deacon */ 6499c29133SGerald Schaefer #define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0) 656a1bdb17SWill Deacon 666a1bdb17SWill Deacon /* 674f04d8f0SCatalin Marinas * ZERO_PAGE is a global shared page that is always zero: used 684f04d8f0SCatalin Marinas * for zero-mapped memory areas etc.. 694f04d8f0SCatalin Marinas */ 705227cfa7SMark Rutland extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 712077be67SLaura Abbott #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 724f04d8f0SCatalin Marinas 732cf660ebSGavin Shan #define pte_ERROR(e) \ 742cf660ebSGavin Shan pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) 757078db46SCatalin Marinas 7675387b92SKristina Martsenko /* 7775387b92SKristina Martsenko * Macros to convert between a physical address and its placement in a 7875387b92SKristina Martsenko * page table entry, taking care of 52-bit addresses. 7975387b92SKristina Martsenko */ 8075387b92SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 81c7c386fbSArnd Bergmann static inline phys_addr_t __pte_to_phys(pte_t pte) 82c7c386fbSArnd Bergmann { 83925a0eb4SArd Biesheuvel pte_val(pte) &= ~PTE_MAYBE_SHARED; 84c7c386fbSArnd Bergmann return (pte_val(pte) & PTE_ADDR_LOW) | 85a4ee2861SAnshuman Khandual ((pte_val(pte) & PTE_ADDR_HIGH) << PTE_ADDR_HIGH_SHIFT); 86c7c386fbSArnd Bergmann } 87c7c386fbSArnd Bergmann static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 88c7c386fbSArnd Bergmann { 89925a0eb4SArd Biesheuvel return (phys | (phys >> PTE_ADDR_HIGH_SHIFT)) & PHYS_TO_PTE_ADDR_MASK; 90c7c386fbSArnd Bergmann } 9175387b92SKristina Martsenko #else 92925a0eb4SArd Biesheuvel #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_LOW) 9375387b92SKristina Martsenko #define __phys_to_pte_val(phys) (phys) 9475387b92SKristina Martsenko #endif 954f04d8f0SCatalin Marinas 9675387b92SKristina Martsenko #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 9775387b92SKristina Martsenko #define pfn_pte(pfn,prot) \ 9875387b92SKristina Martsenko __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 994f04d8f0SCatalin Marinas 1004f04d8f0SCatalin Marinas #define pte_none(pte) (!pte_val(pte)) 1015a00bfd6SRyan Roberts #define __pte_clear(mm, addr, ptep) \ 1025a00bfd6SRyan Roberts __set_pte(ptep, __pte(0)) 1034f04d8f0SCatalin Marinas #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 1047078db46SCatalin Marinas 1054f04d8f0SCatalin Marinas /* 1064f04d8f0SCatalin Marinas * The following only work if pte_present(). Undefined behaviour otherwise. 1074f04d8f0SCatalin Marinas */ 108f0f5863aSRyan Roberts #define pte_present(pte) (pte_valid(pte) || pte_present_invalid(pte)) 10984fe6826SSteve Capper #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 11084fe6826SSteve Capper #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 11184fe6826SSteve Capper #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 112d0ba9612SAnshuman Khandual #define pte_rdonly(pte) (!!(pte_val(pte) & PTE_RDONLY)) 11342b25471SKefeng Wang #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) 114ec663d96SCatalin Marinas #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 11593ef666aSJeremy Linton #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 11673b20c84SRobin Murphy #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 11734bfeea4SCatalin Marinas #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \ 11834bfeea4SCatalin Marinas PTE_ATTRINDX(MT_NORMAL_TAGGED)) 1194f04d8f0SCatalin Marinas 120d27cfa1fSArd Biesheuvel #define pte_cont_addr_end(addr, end) \ 121d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 122d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 123d27cfa1fSArd Biesheuvel }) 124d27cfa1fSArd Biesheuvel 125d27cfa1fSArd Biesheuvel #define pmd_cont_addr_end(addr, end) \ 126d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 127d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 128d27cfa1fSArd Biesheuvel }) 129d27cfa1fSArd Biesheuvel 130d0ba9612SAnshuman Khandual #define pte_hw_dirty(pte) (pte_write(pte) && !pte_rdonly(pte)) 1312f4b829cSCatalin Marinas #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 1322f4b829cSCatalin Marinas #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 1332f4b829cSCatalin Marinas 134766ffb69SWill Deacon #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 135b28c74e2SRyan Roberts #define pte_present_invalid(pte) \ 136b28c74e2SRyan Roberts ((pte_val(pte) & (PTE_VALID | PTE_PRESENT_INVALID)) == PTE_PRESENT_INVALID) 13718107f8aSVladimir Murzin /* 13818107f8aSVladimir Murzin * Execute-only user mappings do not have the PTE_USER bit set. All valid 13918107f8aSVladimir Murzin * kernel mappings have the PTE_UXN bit set. 14018107f8aSVladimir Murzin */ 141ec663d96SCatalin Marinas #define pte_valid_not_user(pte) \ 14218107f8aSVladimir Murzin ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 14376c714beSWill Deacon /* 1444602e575SRyan Roberts * Returns true if the pte is valid and has the contiguous bit set. 1454602e575SRyan Roberts */ 1464602e575SRyan Roberts #define pte_valid_cont(pte) (pte_valid(pte) && pte_cont(pte)) 1474602e575SRyan Roberts /* 14876c714beSWill Deacon * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 14976c714beSWill Deacon * so that we don't erroneously return false for pages that have been 15076c714beSWill Deacon * remapped as PROT_NONE but are yet to be flushed from the TLB. 15107509e10SWill Deacon * Note that we can't make any assumptions based on the state of the access 1525a00bfd6SRyan Roberts * flag, since __ptep_clear_flush_young() elides a DSB when invalidating the 15307509e10SWill Deacon * TLB. 15476c714beSWill Deacon */ 15576c714beSWill Deacon #define pte_accessible(mm, pte) \ 15607509e10SWill Deacon (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) 1574f04d8f0SCatalin Marinas 1586218f96cSCatalin Marinas /* 15918107f8aSVladimir Murzin * p??_access_permitted() is true for valid user mappings (PTE_USER 16018107f8aSVladimir Murzin * bit set, subject to the write permission check). For execute-only 16118107f8aSVladimir Murzin * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits 16218107f8aSVladimir Murzin * not set) must return false. PROT_NONE mappings do not have the 16318107f8aSVladimir Murzin * PTE_VALID bit set. 1646218f96cSCatalin Marinas */ 1656218f96cSCatalin Marinas #define pte_access_permitted(pte, write) \ 16618107f8aSVladimir Murzin (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte))) 1676218f96cSCatalin Marinas #define pmd_access_permitted(pmd, write) \ 1686218f96cSCatalin Marinas (pte_access_permitted(pmd_pte(pmd), (write))) 1696218f96cSCatalin Marinas #define pud_access_permitted(pud, write) \ 1706218f96cSCatalin Marinas (pte_access_permitted(pud_pte(pud), (write))) 1716218f96cSCatalin Marinas 172b6d4f280SLaura Abbott static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 173b6d4f280SLaura Abbott { 174b6d4f280SLaura Abbott pte_val(pte) &= ~pgprot_val(prot); 175b6d4f280SLaura Abbott return pte; 176b6d4f280SLaura Abbott } 177b6d4f280SLaura Abbott 178b6d4f280SLaura Abbott static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 179b6d4f280SLaura Abbott { 180b6d4f280SLaura Abbott pte_val(pte) |= pgprot_val(prot); 181b6d4f280SLaura Abbott return pte; 182b6d4f280SLaura Abbott } 183b6d4f280SLaura Abbott 184b65399f6SAnshuman Khandual static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 185b65399f6SAnshuman Khandual { 186b65399f6SAnshuman Khandual pmd_val(pmd) &= ~pgprot_val(prot); 187b65399f6SAnshuman Khandual return pmd; 188b65399f6SAnshuman Khandual } 189b65399f6SAnshuman Khandual 190b65399f6SAnshuman Khandual static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 191b65399f6SAnshuman Khandual { 192b65399f6SAnshuman Khandual pmd_val(pmd) |= pgprot_val(prot); 193b65399f6SAnshuman Khandual return pmd; 194b65399f6SAnshuman Khandual } 195b65399f6SAnshuman Khandual 1962f0584f3SRick Edgecombe static inline pte_t pte_mkwrite_novma(pte_t pte) 19744b6dfc5SSteve Capper { 19873e86cb0SCatalin Marinas pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 19973e86cb0SCatalin Marinas pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 20073e86cb0SCatalin Marinas return pte; 20144b6dfc5SSteve Capper } 20244b6dfc5SSteve Capper 20344b6dfc5SSteve Capper static inline pte_t pte_mkclean(pte_t pte) 20444b6dfc5SSteve Capper { 2058781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 2068781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 2078781bcbcSSteve Capper 2088781bcbcSSteve Capper return pte; 20944b6dfc5SSteve Capper } 21044b6dfc5SSteve Capper 21144b6dfc5SSteve Capper static inline pte_t pte_mkdirty(pte_t pte) 21244b6dfc5SSteve Capper { 2138781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 2148781bcbcSSteve Capper 2158781bcbcSSteve Capper if (pte_write(pte)) 2168781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 2178781bcbcSSteve Capper 2188781bcbcSSteve Capper return pte; 21944b6dfc5SSteve Capper } 22044b6dfc5SSteve Capper 221ff1712f9SWill Deacon static inline pte_t pte_wrprotect(pte_t pte) 222ff1712f9SWill Deacon { 223ff1712f9SWill Deacon /* 224ff1712f9SWill Deacon * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 225ff1712f9SWill Deacon * clear), set the PTE_DIRTY bit. 226ff1712f9SWill Deacon */ 227ff1712f9SWill Deacon if (pte_hw_dirty(pte)) 2286477c388SAnshuman Khandual pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 229ff1712f9SWill Deacon 230ff1712f9SWill Deacon pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 231ff1712f9SWill Deacon pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 232ff1712f9SWill Deacon return pte; 233ff1712f9SWill Deacon } 234ff1712f9SWill Deacon 23544b6dfc5SSteve Capper static inline pte_t pte_mkold(pte_t pte) 23644b6dfc5SSteve Capper { 237b6d4f280SLaura Abbott return clear_pte_bit(pte, __pgprot(PTE_AF)); 23844b6dfc5SSteve Capper } 23944b6dfc5SSteve Capper 24044b6dfc5SSteve Capper static inline pte_t pte_mkyoung(pte_t pte) 24144b6dfc5SSteve Capper { 242b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_AF)); 24344b6dfc5SSteve Capper } 24444b6dfc5SSteve Capper 24544b6dfc5SSteve Capper static inline pte_t pte_mkspecial(pte_t pte) 24644b6dfc5SSteve Capper { 247b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 24844b6dfc5SSteve Capper } 2494f04d8f0SCatalin Marinas 25093ef666aSJeremy Linton static inline pte_t pte_mkcont(pte_t pte) 25193ef666aSJeremy Linton { 25266b3923aSDavid Woods pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 25366b3923aSDavid Woods return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 25493ef666aSJeremy Linton } 25593ef666aSJeremy Linton 25693ef666aSJeremy Linton static inline pte_t pte_mknoncont(pte_t pte) 25793ef666aSJeremy Linton { 25893ef666aSJeremy Linton return clear_pte_bit(pte, __pgprot(PTE_CONT)); 25993ef666aSJeremy Linton } 26093ef666aSJeremy Linton 2615ebe3a44SJames Morse static inline pte_t pte_mkpresent(pte_t pte) 2625ebe3a44SJames Morse { 2635ebe3a44SJames Morse return set_pte_bit(pte, __pgprot(PTE_VALID)); 2645ebe3a44SJames Morse } 2655ebe3a44SJames Morse 266b28c74e2SRyan Roberts static inline pte_t pte_mkinvalid(pte_t pte) 267b28c74e2SRyan Roberts { 268b28c74e2SRyan Roberts pte = set_pte_bit(pte, __pgprot(PTE_PRESENT_INVALID)); 269b28c74e2SRyan Roberts pte = clear_pte_bit(pte, __pgprot(PTE_VALID)); 270b28c74e2SRyan Roberts return pte; 271b28c74e2SRyan Roberts } 272b28c74e2SRyan Roberts 27366b3923aSDavid Woods static inline pmd_t pmd_mkcont(pmd_t pmd) 27466b3923aSDavid Woods { 27566b3923aSDavid Woods return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 27666b3923aSDavid Woods } 27766b3923aSDavid Woods 27873b20c84SRobin Murphy static inline pte_t pte_mkdevmap(pte_t pte) 27973b20c84SRobin Murphy { 28030e23538SJia He return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 28173b20c84SRobin Murphy } 28273b20c84SRobin Murphy 2831fcb7ceaSRyan Roberts static inline void __set_pte_nosync(pte_t *ptep, pte_t pte) 2844f04d8f0SCatalin Marinas { 28520a004e7SWill Deacon WRITE_ONCE(*ptep, pte); 2861fcb7ceaSRyan Roberts } 2871fcb7ceaSRyan Roberts 2881fcb7ceaSRyan Roberts static inline void __set_pte(pte_t *ptep, pte_t pte) 2891fcb7ceaSRyan Roberts { 2901fcb7ceaSRyan Roberts __set_pte_nosync(ptep, pte); 2917f0b1bf0SCatalin Marinas 2927f0b1bf0SCatalin Marinas /* 2937f0b1bf0SCatalin Marinas * Only if the new pte is valid and kernel, otherwise TLB maintenance 2947f0b1bf0SCatalin Marinas * or update_mmu_cache() have the necessary barriers. 2957f0b1bf0SCatalin Marinas */ 296d0b7a302SWill Deacon if (pte_valid_not_user(pte)) { 2977f0b1bf0SCatalin Marinas dsb(ishst); 298d0b7a302SWill Deacon isb(); 299d0b7a302SWill Deacon } 3004f04d8f0SCatalin Marinas } 3014f04d8f0SCatalin Marinas 3025a00bfd6SRyan Roberts static inline pte_t __ptep_get(pte_t *ptep) 30353273655SRyan Roberts { 30453273655SRyan Roberts return READ_ONCE(*ptep); 30553273655SRyan Roberts } 30653273655SRyan Roberts 307907e21c1SShaokun Zhang extern void __sync_icache_dcache(pte_t pteval); 308004fc58fSAnshuman Khandual bool pgattr_change_is_safe(u64 old, u64 new); 3094f04d8f0SCatalin Marinas 3102f4b829cSCatalin Marinas /* 3112f4b829cSCatalin Marinas * PTE bits configuration in the presence of hardware Dirty Bit Management 3122f4b829cSCatalin Marinas * (PTE_WRITE == PTE_DBM): 3132f4b829cSCatalin Marinas * 3142f4b829cSCatalin Marinas * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 3152f4b829cSCatalin Marinas * 0 0 | 1 0 0 3162f4b829cSCatalin Marinas * 0 1 | 1 1 0 3172f4b829cSCatalin Marinas * 1 0 | 1 0 1 3182f4b829cSCatalin Marinas * 1 1 | 0 1 x 3192f4b829cSCatalin Marinas * 3202f4b829cSCatalin Marinas * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 3212f4b829cSCatalin Marinas * the page fault mechanism. Checking the dirty status of a pte becomes: 3222f4b829cSCatalin Marinas * 323b847415cSCatalin Marinas * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 3242f4b829cSCatalin Marinas */ 3259b604722SMark Rutland 326004fc58fSAnshuman Khandual static inline void __check_safe_pte_update(struct mm_struct *mm, pte_t *ptep, 3279b604722SMark Rutland pte_t pte) 3284f04d8f0SCatalin Marinas { 32920a004e7SWill Deacon pte_t old_pte; 33020a004e7SWill Deacon 3319b604722SMark Rutland if (!IS_ENABLED(CONFIG_DEBUG_VM)) 3329b604722SMark Rutland return; 3339b604722SMark Rutland 3345a00bfd6SRyan Roberts old_pte = __ptep_get(ptep); 3359b604722SMark Rutland 3369b604722SMark Rutland if (!pte_valid(old_pte) || !pte_valid(pte)) 3379b604722SMark Rutland return; 3389b604722SMark Rutland if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 3399b604722SMark Rutland return; 34002522463SWill Deacon 3412f4b829cSCatalin Marinas /* 3429b604722SMark Rutland * Check for potential race with hardware updates of the pte 3435a00bfd6SRyan Roberts * (__ptep_set_access_flags safely changes valid ptes without going 3449b604722SMark Rutland * through an invalid entry). 3452f4b829cSCatalin Marinas */ 34682d34008SCatalin Marinas VM_WARN_ONCE(!pte_young(pte), 34782d34008SCatalin Marinas "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 34820a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 34920a004e7SWill Deacon VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 35082d34008SCatalin Marinas "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 35120a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 352004fc58fSAnshuman Khandual VM_WARN_ONCE(!pgattr_change_is_safe(pte_val(old_pte), pte_val(pte)), 353004fc58fSAnshuman Khandual "%s: unsafe attribute change: 0x%016llx -> 0x%016llx", 354004fc58fSAnshuman Khandual __func__, pte_val(old_pte), pte_val(pte)); 3552f4b829cSCatalin Marinas } 3562f4b829cSCatalin Marinas 3573425cec4SRyan Roberts static inline void __sync_cache_and_tags(pte_t pte, unsigned int nr_pages) 3589b604722SMark Rutland { 3599b604722SMark Rutland if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 3609b604722SMark Rutland __sync_icache_dcache(pte); 3619b604722SMark Rutland 36269e3b846SSteven Price /* 36369e3b846SSteven Price * If the PTE would provide user space access to the tags associated 36469e3b846SSteven Price * with it then ensure that the MTE tags are synchronised. Although 36569e3b846SSteven Price * pte_access_permitted() returns false for exec only mappings, they 36669e3b846SSteven Price * don't expose tags (instruction fetches don't check tags). 36769e3b846SSteven Price */ 36869e3b846SSteven Price if (system_supports_mte() && pte_access_permitted(pte, false) && 369332c151cSPeter Collingbourne !pte_special(pte) && pte_tagged(pte)) 3703425cec4SRyan Roberts mte_sync_tags(pte, nr_pages); 3714f04d8f0SCatalin Marinas } 3724f04d8f0SCatalin Marinas 3736e8f5887SRyan Roberts /* 3746e8f5887SRyan Roberts * Select all bits except the pfn 3756e8f5887SRyan Roberts */ 3766e8f5887SRyan Roberts static inline pgprot_t pte_pgprot(pte_t pte) 3776e8f5887SRyan Roberts { 3786e8f5887SRyan Roberts unsigned long pfn = pte_pfn(pte); 3796e8f5887SRyan Roberts 3806e8f5887SRyan Roberts return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); 3816e8f5887SRyan Roberts } 3826e8f5887SRyan Roberts 383c1bd2b40SRyan Roberts #define pte_advance_pfn pte_advance_pfn 384c1bd2b40SRyan Roberts static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr) 3856e8f5887SRyan Roberts { 386c1bd2b40SRyan Roberts return pfn_pte(pte_pfn(pte) + nr, pte_pgprot(pte)); 3876e8f5887SRyan Roberts } 3886e8f5887SRyan Roberts 3895a00bfd6SRyan Roberts static inline void __set_ptes(struct mm_struct *mm, 390dba2ff49SCatalin Marinas unsigned long __always_unused addr, 3914a169d61SMatthew Wilcox (Oracle) pte_t *ptep, pte_t pte, unsigned int nr) 39242b25471SKefeng Wang { 3934a169d61SMatthew Wilcox (Oracle) page_table_check_ptes_set(mm, ptep, pte, nr); 3943425cec4SRyan Roberts __sync_cache_and_tags(pte, nr); 3954a169d61SMatthew Wilcox (Oracle) 3964a169d61SMatthew Wilcox (Oracle) for (;;) { 3973425cec4SRyan Roberts __check_safe_pte_update(mm, ptep, pte); 3985a00bfd6SRyan Roberts __set_pte(ptep, pte); 3994a169d61SMatthew Wilcox (Oracle) if (--nr == 0) 4004a169d61SMatthew Wilcox (Oracle) break; 4014a169d61SMatthew Wilcox (Oracle) ptep++; 402c1bd2b40SRyan Roberts pte = pte_advance_pfn(pte, 1); 40342b25471SKefeng Wang } 4044a169d61SMatthew Wilcox (Oracle) } 40542b25471SKefeng Wang 4064f04d8f0SCatalin Marinas /* 4074f04d8f0SCatalin Marinas * Huge pte definitions. 4084f04d8f0SCatalin Marinas */ 409084bd298SSteve Capper #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 410084bd298SSteve Capper 411084bd298SSteve Capper /* 412084bd298SSteve Capper * Hugetlb definitions. 413084bd298SSteve Capper */ 41466b3923aSDavid Woods #define HUGE_MAX_HSTATE 4 415084bd298SSteve Capper #define HPAGE_SHIFT PMD_SHIFT 416084bd298SSteve Capper #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 417084bd298SSteve Capper #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 418084bd298SSteve Capper #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 4194f04d8f0SCatalin Marinas 42075387b92SKristina Martsenko static inline pte_t pgd_pte(pgd_t pgd) 42175387b92SKristina Martsenko { 42275387b92SKristina Martsenko return __pte(pgd_val(pgd)); 42375387b92SKristina Martsenko } 42475387b92SKristina Martsenko 425e9f63768SMike Rapoport static inline pte_t p4d_pte(p4d_t p4d) 426e9f63768SMike Rapoport { 427e9f63768SMike Rapoport return __pte(p4d_val(p4d)); 428e9f63768SMike Rapoport } 429e9f63768SMike Rapoport 43029e56940SSteve Capper static inline pte_t pud_pte(pud_t pud) 43129e56940SSteve Capper { 43229e56940SSteve Capper return __pte(pud_val(pud)); 43329e56940SSteve Capper } 43429e56940SSteve Capper 435eb3f0624SPunit Agrawal static inline pud_t pte_pud(pte_t pte) 436eb3f0624SPunit Agrawal { 437eb3f0624SPunit Agrawal return __pud(pte_val(pte)); 438eb3f0624SPunit Agrawal } 439eb3f0624SPunit Agrawal 44029e56940SSteve Capper static inline pmd_t pud_pmd(pud_t pud) 44129e56940SSteve Capper { 44229e56940SSteve Capper return __pmd(pud_val(pud)); 44329e56940SSteve Capper } 44429e56940SSteve Capper 4459c7e535fSSteve Capper static inline pte_t pmd_pte(pmd_t pmd) 4469c7e535fSSteve Capper { 4479c7e535fSSteve Capper return __pte(pmd_val(pmd)); 4489c7e535fSSteve Capper } 449af074848SSteve Capper 4509c7e535fSSteve Capper static inline pmd_t pte_pmd(pte_t pte) 4519c7e535fSSteve Capper { 4529c7e535fSSteve Capper return __pmd(pte_val(pte)); 4539c7e535fSSteve Capper } 454af074848SSteve Capper 455f7f0097aSAnshuman Khandual static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 4568ce837ceSArd Biesheuvel { 457f7f0097aSAnshuman Khandual return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 458f7f0097aSAnshuman Khandual } 459f7f0097aSAnshuman Khandual 460f7f0097aSAnshuman Khandual static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 461f7f0097aSAnshuman Khandual { 462f7f0097aSAnshuman Khandual return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 4638ce837ceSArd Biesheuvel } 4648ce837ceSArd Biesheuvel 465570ef363SDavid Hildenbrand static inline pte_t pte_swp_mkexclusive(pte_t pte) 466570ef363SDavid Hildenbrand { 467570ef363SDavid Hildenbrand return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 468570ef363SDavid Hildenbrand } 469570ef363SDavid Hildenbrand 470570ef363SDavid Hildenbrand static inline int pte_swp_exclusive(pte_t pte) 471570ef363SDavid Hildenbrand { 472570ef363SDavid Hildenbrand return pte_val(pte) & PTE_SWP_EXCLUSIVE; 473570ef363SDavid Hildenbrand } 474570ef363SDavid Hildenbrand 475570ef363SDavid Hildenbrand static inline pte_t pte_swp_clear_exclusive(pte_t pte) 476570ef363SDavid Hildenbrand { 477570ef363SDavid Hildenbrand return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 478570ef363SDavid Hildenbrand } 479570ef363SDavid Hildenbrand 48056166230SGanapatrao Kulkarni #ifdef CONFIG_NUMA_BALANCING 48156166230SGanapatrao Kulkarni /* 482ca5999fdSMike Rapoport * See the comment in include/linux/pgtable.h 48356166230SGanapatrao Kulkarni */ 48456166230SGanapatrao Kulkarni static inline int pte_protnone(pte_t pte) 48556166230SGanapatrao Kulkarni { 486f0f5863aSRyan Roberts /* 487f0f5863aSRyan Roberts * pte_present_invalid() tells us that the pte is invalid from HW 488f0f5863aSRyan Roberts * perspective but present from SW perspective, so the fields are to be 489f0f5863aSRyan Roberts * interpretted as per the HW layout. The second 2 checks are the unique 490f0f5863aSRyan Roberts * encoding that we use for PROT_NONE. It is insufficient to only use 491f0f5863aSRyan Roberts * the first check because we share the same encoding scheme with pmds 492f0f5863aSRyan Roberts * which support pmd_mkinvalid(), so can be present-invalid without 493f0f5863aSRyan Roberts * being PROT_NONE. 494f0f5863aSRyan Roberts */ 495f0f5863aSRyan Roberts return pte_present_invalid(pte) && !pte_user(pte) && !pte_user_exec(pte); 49656166230SGanapatrao Kulkarni } 49756166230SGanapatrao Kulkarni 49856166230SGanapatrao Kulkarni static inline int pmd_protnone(pmd_t pmd) 49956166230SGanapatrao Kulkarni { 50056166230SGanapatrao Kulkarni return pte_protnone(pmd_pte(pmd)); 50156166230SGanapatrao Kulkarni } 50256166230SGanapatrao Kulkarni #endif 50356166230SGanapatrao Kulkarni 504f0f5863aSRyan Roberts #define pmd_present(pmd) pte_present(pmd_pte(pmd)) 505b65399f6SAnshuman Khandual 506af074848SSteve Capper /* 507af074848SSteve Capper * THP definitions. 508af074848SSteve Capper */ 509af074848SSteve Capper 510af074848SSteve Capper #ifdef CONFIG_TRANSPARENT_HUGEPAGE 511b65399f6SAnshuman Khandual static inline int pmd_trans_huge(pmd_t pmd) 512b65399f6SAnshuman Khandual { 513b65399f6SAnshuman Khandual return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT); 514b65399f6SAnshuman Khandual } 51529e56940SSteve Capper #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 516af074848SSteve Capper 517c164e038SKirill A. Shutemov #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 5189c7e535fSSteve Capper #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 5190795edafSWill Deacon #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 52042b25471SKefeng Wang #define pmd_user(pmd) pte_user(pmd_pte(pmd)) 52142b25471SKefeng Wang #define pmd_user_exec(pmd) pte_user_exec(pmd_pte(pmd)) 522d55863dbSPeter Zijlstra #define pmd_cont(pmd) pte_cont(pmd_pte(pmd)) 5239c7e535fSSteve Capper #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 5249c7e535fSSteve Capper #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 5252f0584f3SRick Edgecombe #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))) 52605ee26d9SMinchan Kim #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 5279c7e535fSSteve Capper #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 5289c7e535fSSteve Capper #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 529b28c74e2SRyan Roberts #define pmd_mkinvalid(pmd) pte_pmd(pte_mkinvalid(pmd_pte(pmd))) 530af074848SSteve Capper 5310dbd3b18SSuzuki K Poulose #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 5320dbd3b18SSuzuki K Poulose 5339c7e535fSSteve Capper #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 534af074848SSteve Capper 535af074848SSteve Capper #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 536af074848SSteve Capper 53773b20c84SRobin Murphy #ifdef CONFIG_TRANSPARENT_HUGEPAGE 53873b20c84SRobin Murphy #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 53973b20c84SRobin Murphy #endif 54030e23538SJia He static inline pmd_t pmd_mkdevmap(pmd_t pmd) 54130e23538SJia He { 54230e23538SJia He return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 54330e23538SJia He } 54473b20c84SRobin Murphy 54575387b92SKristina Martsenko #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 54675387b92SKristina Martsenko #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 54775387b92SKristina Martsenko #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 54875387b92SKristina Martsenko #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 549af074848SSteve Capper #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 550af074848SSteve Capper 55135a63966SPunit Agrawal #define pud_young(pud) pte_young(pud_pte(pud)) 552eb3f0624SPunit Agrawal #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 55329e56940SSteve Capper #define pud_write(pud) pte_write(pud_pte(pud)) 55475387b92SKristina Martsenko 555b8e0ba7cSPunit Agrawal #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 556b8e0ba7cSPunit Agrawal 55775387b92SKristina Martsenko #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 55875387b92SKristina Martsenko #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 55975387b92SKristina Martsenko #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 56075387b92SKristina Martsenko #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 561af074848SSteve Capper 562dba2ff49SCatalin Marinas static inline void __set_pte_at(struct mm_struct *mm, 563dba2ff49SCatalin Marinas unsigned long __always_unused addr, 5643425cec4SRyan Roberts pte_t *ptep, pte_t pte, unsigned int nr) 5653425cec4SRyan Roberts { 5663425cec4SRyan Roberts __sync_cache_and_tags(pte, nr); 5673425cec4SRyan Roberts __check_safe_pte_update(mm, ptep, pte); 5685a00bfd6SRyan Roberts __set_pte(ptep, pte); 5693425cec4SRyan Roberts } 5703425cec4SRyan Roberts 57142b25471SKefeng Wang static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 57242b25471SKefeng Wang pmd_t *pmdp, pmd_t pmd) 57342b25471SKefeng Wang { 574a3b83713SKemeng Shi page_table_check_pmd_set(mm, pmdp, pmd); 5753425cec4SRyan Roberts return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd), 5763425cec4SRyan Roberts PMD_SIZE >> PAGE_SHIFT); 57742b25471SKefeng Wang } 57842b25471SKefeng Wang 57942b25471SKefeng Wang static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 58042b25471SKefeng Wang pud_t *pudp, pud_t pud) 58142b25471SKefeng Wang { 5826d144436SKemeng Shi page_table_check_pud_set(mm, pudp, pud); 5833425cec4SRyan Roberts return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud), 5843425cec4SRyan Roberts PUD_SIZE >> PAGE_SHIFT); 58542b25471SKefeng Wang } 586af074848SSteve Capper 587e9f63768SMike Rapoport #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 588e9f63768SMike Rapoport #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 589e9f63768SMike Rapoport 59075387b92SKristina Martsenko #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 59175387b92SKristina Martsenko #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 59275387b92SKristina Martsenko 593a501e324SCatalin Marinas #define __pgprot_modify(prot,mask,bits) \ 594a501e324SCatalin Marinas __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 595a501e324SCatalin Marinas 596cca98e9fSChristoph Hellwig #define pgprot_nx(prot) \ 597034aa9cdSWill Deacon __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 598cca98e9fSChristoph Hellwig 599af074848SSteve Capper /* 6004f04d8f0SCatalin Marinas * Mark the prot value as uncacheable and unbufferable. 6014f04d8f0SCatalin Marinas */ 6024f04d8f0SCatalin Marinas #define pgprot_noncached(prot) \ 603de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 6044f04d8f0SCatalin Marinas #define pgprot_writecombine(prot) \ 605de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 606d1e6dc91SLiviu Dudau #define pgprot_device(prot) \ 607d1e6dc91SLiviu Dudau __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 608d15dfd31SCatalin Marinas #define pgprot_tagged(prot) \ 609d15dfd31SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED)) 610d15dfd31SCatalin Marinas #define pgprot_mhp pgprot_tagged 6113e4e1d3fSChristoph Hellwig /* 6123e4e1d3fSChristoph Hellwig * DMA allocations for non-coherent devices use what the Arm architecture calls 6133e4e1d3fSChristoph Hellwig * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 6143e4e1d3fSChristoph Hellwig * and merging of writes. This is different from "Device-nGnR[nE]" memory which 6153e4e1d3fSChristoph Hellwig * is intended for MMIO and thus forbids speculation, preserves access size, 6163e4e1d3fSChristoph Hellwig * requires strict alignment and can also force write responses to come from the 6173e4e1d3fSChristoph Hellwig * endpoint. 6183e4e1d3fSChristoph Hellwig */ 619419e2f18SChristoph Hellwig #define pgprot_dmacoherent(prot) \ 620419e2f18SChristoph Hellwig __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 621419e2f18SChristoph Hellwig PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 622419e2f18SChristoph Hellwig 6234f04d8f0SCatalin Marinas #define __HAVE_PHYS_MEM_ACCESS_PROT 6244f04d8f0SCatalin Marinas struct file; 6254f04d8f0SCatalin Marinas extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 6264f04d8f0SCatalin Marinas unsigned long size, pgprot_t vma_prot); 6274f04d8f0SCatalin Marinas 6284f04d8f0SCatalin Marinas #define pmd_none(pmd) (!pmd_val(pmd)) 6294f04d8f0SCatalin Marinas 63036311607SMarc Zyngier #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 63136311607SMarc Zyngier PMD_TYPE_TABLE) 63236311607SMarc Zyngier #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 63336311607SMarc Zyngier PMD_TYPE_SECT) 63423bc8f69SMuchun Song #define pmd_leaf(pmd) (pmd_present(pmd) && !pmd_table(pmd)) 635e377ab82SAnshuman Khandual #define pmd_bad(pmd) (!pmd_table(pmd)) 63636311607SMarc Zyngier 637d55863dbSPeter Zijlstra #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE) 638d55863dbSPeter Zijlstra #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE) 639d55863dbSPeter Zijlstra 640cac4b8cdSCatalin Marinas #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 6417d4e2dcfSQian Cai static inline bool pud_sect(pud_t pud) { return false; } 6427d4e2dcfSQian Cai static inline bool pud_table(pud_t pud) { return true; } 643206a2a73SSteve Capper #else 644206a2a73SSteve Capper #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 645206a2a73SSteve Capper PUD_TYPE_SECT) 646523d6e9fSzhichang.yuan #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 647523d6e9fSzhichang.yuan PUD_TYPE_TABLE) 648206a2a73SSteve Capper #endif 64936311607SMarc Zyngier 6506ed8a3a0SArd Biesheuvel extern pgd_t init_pg_dir[]; 6512330b7caSJun Yao extern pgd_t init_pg_end[]; 6526ed8a3a0SArd Biesheuvel extern pgd_t swapper_pg_dir[]; 6536ed8a3a0SArd Biesheuvel extern pgd_t idmap_pg_dir[]; 6546ed8a3a0SArd Biesheuvel extern pgd_t tramp_pg_dir[]; 6556ed8a3a0SArd Biesheuvel extern pgd_t reserved_pg_dir[]; 6562330b7caSJun Yao 6572330b7caSJun Yao extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 6582330b7caSJun Yao 6592330b7caSJun Yao static inline bool in_swapper_pgdir(void *addr) 6602330b7caSJun Yao { 6612330b7caSJun Yao return ((unsigned long)addr & PAGE_MASK) == 6622330b7caSJun Yao ((unsigned long)swapper_pg_dir & PAGE_MASK); 6632330b7caSJun Yao } 6642330b7caSJun Yao 6654f04d8f0SCatalin Marinas static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 6664f04d8f0SCatalin Marinas { 667e9ed821bSJames Morse #ifdef __PAGETABLE_PMD_FOLDED 668e9ed821bSJames Morse if (in_swapper_pgdir(pmdp)) { 6692330b7caSJun Yao set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 6702330b7caSJun Yao return; 6712330b7caSJun Yao } 672e9ed821bSJames Morse #endif /* __PAGETABLE_PMD_FOLDED */ 6732330b7caSJun Yao 67420a004e7SWill Deacon WRITE_ONCE(*pmdp, pmd); 6750795edafSWill Deacon 676d0b7a302SWill Deacon if (pmd_valid(pmd)) { 67798f7685eSWill Deacon dsb(ishst); 678d0b7a302SWill Deacon isb(); 679d0b7a302SWill Deacon } 6804f04d8f0SCatalin Marinas } 6814f04d8f0SCatalin Marinas 6824f04d8f0SCatalin Marinas static inline void pmd_clear(pmd_t *pmdp) 6834f04d8f0SCatalin Marinas { 6844f04d8f0SCatalin Marinas set_pmd(pmdp, __pmd(0)); 6854f04d8f0SCatalin Marinas } 6864f04d8f0SCatalin Marinas 687dca56dcaSMark Rutland static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 6884f04d8f0SCatalin Marinas { 68975387b92SKristina Martsenko return __pmd_to_phys(pmd); 6904f04d8f0SCatalin Marinas } 6914f04d8f0SCatalin Marinas 692974b9b2cSMike Rapoport static inline unsigned long pmd_page_vaddr(pmd_t pmd) 693974b9b2cSMike Rapoport { 694974b9b2cSMike Rapoport return (unsigned long)__va(pmd_page_paddr(pmd)); 695974b9b2cSMike Rapoport } 69674dd022fSQian Cai 697053520f7SMark Rutland /* Find an entry in the third-level page table. */ 698f069fabaSWill Deacon #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 699053520f7SMark Rutland 700961faac1SMark Rutland #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 701961faac1SMark Rutland #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 702961faac1SMark Rutland #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 703961faac1SMark Rutland 70468ecabd0SGavin Shan #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 7054f04d8f0SCatalin Marinas 7066533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 7076533945aSArd Biesheuvel #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 7086533945aSArd Biesheuvel 7094f04d8f0SCatalin Marinas /* 7104f04d8f0SCatalin Marinas * Conversion functions: convert a page and protection to a page entry, 7114f04d8f0SCatalin Marinas * and a page entry and page directory to the page they refer to. 7124f04d8f0SCatalin Marinas */ 7134f04d8f0SCatalin Marinas #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 7144f04d8f0SCatalin Marinas 7159f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 2 7164f04d8f0SCatalin Marinas 7172cf660ebSGavin Shan #define pmd_ERROR(e) \ 7182cf660ebSGavin Shan pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) 7197078db46SCatalin Marinas 7204f04d8f0SCatalin Marinas #define pud_none(pud) (!pud_val(pud)) 721e377ab82SAnshuman Khandual #define pud_bad(pud) (!pud_table(pud)) 722f02ab08aSPunit Agrawal #define pud_present(pud) pte_present(pud_pte(pud)) 72323bc8f69SMuchun Song #define pud_leaf(pud) (pud_present(pud) && !pud_table(pud)) 7240795edafSWill Deacon #define pud_valid(pud) pte_valid(pud_pte(pud)) 72542b25471SKefeng Wang #define pud_user(pud) pte_user(pud_pte(pud)) 726730a11f9SLiu Shixin #define pud_user_exec(pud) pte_user_exec(pud_pte(pud)) 7274f04d8f0SCatalin Marinas 72890e636f6SArd Biesheuvel static inline bool pgtable_l4_enabled(void); 72990e636f6SArd Biesheuvel 7304f04d8f0SCatalin Marinas static inline void set_pud(pud_t *pudp, pud_t pud) 7314f04d8f0SCatalin Marinas { 73290e636f6SArd Biesheuvel if (!pgtable_l4_enabled() && in_swapper_pgdir(pudp)) { 7332330b7caSJun Yao set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 7342330b7caSJun Yao return; 7352330b7caSJun Yao } 7362330b7caSJun Yao 73720a004e7SWill Deacon WRITE_ONCE(*pudp, pud); 7380795edafSWill Deacon 739d0b7a302SWill Deacon if (pud_valid(pud)) { 74098f7685eSWill Deacon dsb(ishst); 741d0b7a302SWill Deacon isb(); 742d0b7a302SWill Deacon } 7434f04d8f0SCatalin Marinas } 7444f04d8f0SCatalin Marinas 7454f04d8f0SCatalin Marinas static inline void pud_clear(pud_t *pudp) 7464f04d8f0SCatalin Marinas { 7474f04d8f0SCatalin Marinas set_pud(pudp, __pud(0)); 7484f04d8f0SCatalin Marinas } 7494f04d8f0SCatalin Marinas 750dca56dcaSMark Rutland static inline phys_addr_t pud_page_paddr(pud_t pud) 7514f04d8f0SCatalin Marinas { 75275387b92SKristina Martsenko return __pud_to_phys(pud); 7534f04d8f0SCatalin Marinas } 7544f04d8f0SCatalin Marinas 7559cf6fa24SAneesh Kumar K.V static inline pmd_t *pud_pgtable(pud_t pud) 756974b9b2cSMike Rapoport { 7579cf6fa24SAneesh Kumar K.V return (pmd_t *)__va(pud_page_paddr(pud)); 758974b9b2cSMike Rapoport } 7597078db46SCatalin Marinas 760974b9b2cSMike Rapoport /* Find an entry in the second-level page table. */ 76120a004e7SWill Deacon #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 7627078db46SCatalin Marinas 763961faac1SMark Rutland #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 764961faac1SMark Rutland #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 765961faac1SMark Rutland #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 7664f04d8f0SCatalin Marinas 76768ecabd0SGavin Shan #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 76829e56940SSteve Capper 7696533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 7706533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 7716533945aSArd Biesheuvel 772dca56dcaSMark Rutland #else 773dca56dcaSMark Rutland 774dca56dcaSMark Rutland #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 7754e4ff23aSWill Deacon #define pud_user_exec(pud) pud_user(pud) /* Always 0 with folding */ 776dca56dcaSMark Rutland 777961faac1SMark Rutland /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 778961faac1SMark Rutland #define pmd_set_fixmap(addr) NULL 779961faac1SMark Rutland #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 780961faac1SMark Rutland #define pmd_clear_fixmap() 781961faac1SMark Rutland 7826533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 7836533945aSArd Biesheuvel 7849f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 7854f04d8f0SCatalin Marinas 7869f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 3 787c79b954bSJungseok Lee 7880dd4f60aSArd Biesheuvel static __always_inline bool pgtable_l4_enabled(void) 7890dd4f60aSArd Biesheuvel { 7900dd4f60aSArd Biesheuvel if (CONFIG_PGTABLE_LEVELS > 4 || !IS_ENABLED(CONFIG_ARM64_LPA2)) 7910dd4f60aSArd Biesheuvel return true; 7920dd4f60aSArd Biesheuvel if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 7930dd4f60aSArd Biesheuvel return vabits_actual == VA_BITS; 7940dd4f60aSArd Biesheuvel return alternative_has_cap_unlikely(ARM64_HAS_VA52); 7950dd4f60aSArd Biesheuvel } 7960dd4f60aSArd Biesheuvel 7970dd4f60aSArd Biesheuvel static inline bool mm_pud_folded(const struct mm_struct *mm) 7980dd4f60aSArd Biesheuvel { 7990dd4f60aSArd Biesheuvel return !pgtable_l4_enabled(); 8000dd4f60aSArd Biesheuvel } 8010dd4f60aSArd Biesheuvel #define mm_pud_folded mm_pud_folded 8020dd4f60aSArd Biesheuvel 8032cf660ebSGavin Shan #define pud_ERROR(e) \ 8042cf660ebSGavin Shan pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) 8057078db46SCatalin Marinas 8060dd4f60aSArd Biesheuvel #define p4d_none(p4d) (pgtable_l4_enabled() && !p4d_val(p4d)) 8070dd4f60aSArd Biesheuvel #define p4d_bad(p4d) (pgtable_l4_enabled() && !(p4d_val(p4d) & 2)) 8080dd4f60aSArd Biesheuvel #define p4d_present(p4d) (!p4d_none(p4d)) 809c79b954bSJungseok Lee 810e9f63768SMike Rapoport static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 811c79b954bSJungseok Lee { 812e9f63768SMike Rapoport if (in_swapper_pgdir(p4dp)) { 813e9f63768SMike Rapoport set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 8142330b7caSJun Yao return; 8152330b7caSJun Yao } 8162330b7caSJun Yao 817e9f63768SMike Rapoport WRITE_ONCE(*p4dp, p4d); 818c79b954bSJungseok Lee dsb(ishst); 819eb6a4dccSWill Deacon isb(); 820c79b954bSJungseok Lee } 821c79b954bSJungseok Lee 822e9f63768SMike Rapoport static inline void p4d_clear(p4d_t *p4dp) 823c79b954bSJungseok Lee { 8240dd4f60aSArd Biesheuvel if (pgtable_l4_enabled()) 825e9f63768SMike Rapoport set_p4d(p4dp, __p4d(0)); 826c79b954bSJungseok Lee } 827c79b954bSJungseok Lee 828e9f63768SMike Rapoport static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 829c79b954bSJungseok Lee { 830e9f63768SMike Rapoport return __p4d_to_phys(p4d); 831c79b954bSJungseok Lee } 832c79b954bSJungseok Lee 8330dd4f60aSArd Biesheuvel #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 8340dd4f60aSArd Biesheuvel 8350dd4f60aSArd Biesheuvel static inline pud_t *p4d_to_folded_pud(p4d_t *p4dp, unsigned long addr) 8360dd4f60aSArd Biesheuvel { 8370dd4f60aSArd Biesheuvel return (pud_t *)PTR_ALIGN_DOWN(p4dp, PAGE_SIZE) + pud_index(addr); 8380dd4f60aSArd Biesheuvel } 8390dd4f60aSArd Biesheuvel 840dc4875f0SAneesh Kumar K.V static inline pud_t *p4d_pgtable(p4d_t p4d) 841974b9b2cSMike Rapoport { 842dc4875f0SAneesh Kumar K.V return (pud_t *)__va(p4d_page_paddr(p4d)); 843974b9b2cSMike Rapoport } 8447078db46SCatalin Marinas 8450dd4f60aSArd Biesheuvel static inline phys_addr_t pud_offset_phys(p4d_t *p4dp, unsigned long addr) 8460dd4f60aSArd Biesheuvel { 8470dd4f60aSArd Biesheuvel BUG_ON(!pgtable_l4_enabled()); 8487078db46SCatalin Marinas 8490dd4f60aSArd Biesheuvel return p4d_page_paddr(READ_ONCE(*p4dp)) + pud_index(addr) * sizeof(pud_t); 8500dd4f60aSArd Biesheuvel } 8510dd4f60aSArd Biesheuvel 8520dd4f60aSArd Biesheuvel static inline 8530dd4f60aSArd Biesheuvel pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long addr) 8540dd4f60aSArd Biesheuvel { 8550dd4f60aSArd Biesheuvel if (!pgtable_l4_enabled()) 8560dd4f60aSArd Biesheuvel return p4d_to_folded_pud(p4dp, addr); 8570dd4f60aSArd Biesheuvel return (pud_t *)__va(p4d_page_paddr(p4d)) + pud_index(addr); 8580dd4f60aSArd Biesheuvel } 8590dd4f60aSArd Biesheuvel #define pud_offset_lockless pud_offset_lockless 8600dd4f60aSArd Biesheuvel 8610dd4f60aSArd Biesheuvel static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long addr) 8620dd4f60aSArd Biesheuvel { 8630dd4f60aSArd Biesheuvel return pud_offset_lockless(p4dp, READ_ONCE(*p4dp), addr); 8640dd4f60aSArd Biesheuvel } 8650dd4f60aSArd Biesheuvel #define pud_offset pud_offset 8660dd4f60aSArd Biesheuvel 8670dd4f60aSArd Biesheuvel static inline pud_t *pud_set_fixmap(unsigned long addr) 8680dd4f60aSArd Biesheuvel { 8690dd4f60aSArd Biesheuvel if (!pgtable_l4_enabled()) 8700dd4f60aSArd Biesheuvel return NULL; 8710dd4f60aSArd Biesheuvel return (pud_t *)set_fixmap_offset(FIX_PUD, addr); 8720dd4f60aSArd Biesheuvel } 8730dd4f60aSArd Biesheuvel 8740dd4f60aSArd Biesheuvel static inline pud_t *pud_set_fixmap_offset(p4d_t *p4dp, unsigned long addr) 8750dd4f60aSArd Biesheuvel { 8760dd4f60aSArd Biesheuvel if (!pgtable_l4_enabled()) 8770dd4f60aSArd Biesheuvel return p4d_to_folded_pud(p4dp, addr); 8780dd4f60aSArd Biesheuvel return pud_set_fixmap(pud_offset_phys(p4dp, addr)); 8790dd4f60aSArd Biesheuvel } 8800dd4f60aSArd Biesheuvel 8810dd4f60aSArd Biesheuvel static inline void pud_clear_fixmap(void) 8820dd4f60aSArd Biesheuvel { 8830dd4f60aSArd Biesheuvel if (pgtable_l4_enabled()) 8840dd4f60aSArd Biesheuvel clear_fixmap(FIX_PUD); 8850dd4f60aSArd Biesheuvel } 8860dd4f60aSArd Biesheuvel 8870dd4f60aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 8880dd4f60aSArd Biesheuvel static inline pud_t *pud_offset_kimg(p4d_t *p4dp, u64 addr) 8890dd4f60aSArd Biesheuvel { 8900dd4f60aSArd Biesheuvel if (!pgtable_l4_enabled()) 8910dd4f60aSArd Biesheuvel return p4d_to_folded_pud(p4dp, addr); 8920dd4f60aSArd Biesheuvel return (pud_t *)__phys_to_kimg(pud_offset_phys(p4dp, addr)); 8930dd4f60aSArd Biesheuvel } 894c79b954bSJungseok Lee 895e9f63768SMike Rapoport #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 8965d96e0cbSJungseok Lee 897dca56dcaSMark Rutland #else 898dca56dcaSMark Rutland 8990dd4f60aSArd Biesheuvel static inline bool pgtable_l4_enabled(void) { return false; } 9000dd4f60aSArd Biesheuvel 901e9f63768SMike Rapoport #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 902dca56dcaSMark Rutland 903961faac1SMark Rutland /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 904961faac1SMark Rutland #define pud_set_fixmap(addr) NULL 905961faac1SMark Rutland #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 906961faac1SMark Rutland #define pud_clear_fixmap() 907961faac1SMark Rutland 9086533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 9096533945aSArd Biesheuvel 9109f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 911c79b954bSJungseok Lee 912a6bbf5d4SArd Biesheuvel #if CONFIG_PGTABLE_LEVELS > 4 913a6bbf5d4SArd Biesheuvel 914a6bbf5d4SArd Biesheuvel static __always_inline bool pgtable_l5_enabled(void) 915a6bbf5d4SArd Biesheuvel { 916a6bbf5d4SArd Biesheuvel if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 917a6bbf5d4SArd Biesheuvel return vabits_actual == VA_BITS; 918a6bbf5d4SArd Biesheuvel return alternative_has_cap_unlikely(ARM64_HAS_VA52); 919a6bbf5d4SArd Biesheuvel } 920a6bbf5d4SArd Biesheuvel 921a6bbf5d4SArd Biesheuvel static inline bool mm_p4d_folded(const struct mm_struct *mm) 922a6bbf5d4SArd Biesheuvel { 923a6bbf5d4SArd Biesheuvel return !pgtable_l5_enabled(); 924a6bbf5d4SArd Biesheuvel } 925a6bbf5d4SArd Biesheuvel #define mm_p4d_folded mm_p4d_folded 926a6bbf5d4SArd Biesheuvel 927a6bbf5d4SArd Biesheuvel #define p4d_ERROR(e) \ 928a6bbf5d4SArd Biesheuvel pr_err("%s:%d: bad p4d %016llx.\n", __FILE__, __LINE__, p4d_val(e)) 929a6bbf5d4SArd Biesheuvel 930a6bbf5d4SArd Biesheuvel #define pgd_none(pgd) (pgtable_l5_enabled() && !pgd_val(pgd)) 931a6bbf5d4SArd Biesheuvel #define pgd_bad(pgd) (pgtable_l5_enabled() && !(pgd_val(pgd) & 2)) 932a6bbf5d4SArd Biesheuvel #define pgd_present(pgd) (!pgd_none(pgd)) 933a6bbf5d4SArd Biesheuvel 934a6bbf5d4SArd Biesheuvel static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 935a6bbf5d4SArd Biesheuvel { 936a6bbf5d4SArd Biesheuvel if (in_swapper_pgdir(pgdp)) { 937a6bbf5d4SArd Biesheuvel set_swapper_pgd(pgdp, __pgd(pgd_val(pgd))); 938a6bbf5d4SArd Biesheuvel return; 939a6bbf5d4SArd Biesheuvel } 940a6bbf5d4SArd Biesheuvel 941a6bbf5d4SArd Biesheuvel WRITE_ONCE(*pgdp, pgd); 942a6bbf5d4SArd Biesheuvel dsb(ishst); 943a6bbf5d4SArd Biesheuvel isb(); 944a6bbf5d4SArd Biesheuvel } 945a6bbf5d4SArd Biesheuvel 946a6bbf5d4SArd Biesheuvel static inline void pgd_clear(pgd_t *pgdp) 947a6bbf5d4SArd Biesheuvel { 948a6bbf5d4SArd Biesheuvel if (pgtable_l5_enabled()) 949a6bbf5d4SArd Biesheuvel set_pgd(pgdp, __pgd(0)); 950a6bbf5d4SArd Biesheuvel } 951a6bbf5d4SArd Biesheuvel 952a6bbf5d4SArd Biesheuvel static inline phys_addr_t pgd_page_paddr(pgd_t pgd) 953a6bbf5d4SArd Biesheuvel { 954a6bbf5d4SArd Biesheuvel return __pgd_to_phys(pgd); 955a6bbf5d4SArd Biesheuvel } 956a6bbf5d4SArd Biesheuvel 957a6bbf5d4SArd Biesheuvel #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 958a6bbf5d4SArd Biesheuvel 959a6bbf5d4SArd Biesheuvel static inline p4d_t *pgd_to_folded_p4d(pgd_t *pgdp, unsigned long addr) 960a6bbf5d4SArd Biesheuvel { 961a6bbf5d4SArd Biesheuvel return (p4d_t *)PTR_ALIGN_DOWN(pgdp, PAGE_SIZE) + p4d_index(addr); 962a6bbf5d4SArd Biesheuvel } 963a6bbf5d4SArd Biesheuvel 964a6bbf5d4SArd Biesheuvel static inline phys_addr_t p4d_offset_phys(pgd_t *pgdp, unsigned long addr) 965a6bbf5d4SArd Biesheuvel { 966a6bbf5d4SArd Biesheuvel BUG_ON(!pgtable_l5_enabled()); 967a6bbf5d4SArd Biesheuvel 968a6bbf5d4SArd Biesheuvel return pgd_page_paddr(READ_ONCE(*pgdp)) + p4d_index(addr) * sizeof(p4d_t); 969a6bbf5d4SArd Biesheuvel } 970a6bbf5d4SArd Biesheuvel 971a6bbf5d4SArd Biesheuvel static inline 972a6bbf5d4SArd Biesheuvel p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long addr) 973a6bbf5d4SArd Biesheuvel { 974a6bbf5d4SArd Biesheuvel if (!pgtable_l5_enabled()) 975a6bbf5d4SArd Biesheuvel return pgd_to_folded_p4d(pgdp, addr); 976a6bbf5d4SArd Biesheuvel return (p4d_t *)__va(pgd_page_paddr(pgd)) + p4d_index(addr); 977a6bbf5d4SArd Biesheuvel } 978a6bbf5d4SArd Biesheuvel #define p4d_offset_lockless p4d_offset_lockless 979a6bbf5d4SArd Biesheuvel 980a6bbf5d4SArd Biesheuvel static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long addr) 981a6bbf5d4SArd Biesheuvel { 982a6bbf5d4SArd Biesheuvel return p4d_offset_lockless(pgdp, READ_ONCE(*pgdp), addr); 983a6bbf5d4SArd Biesheuvel } 984a6bbf5d4SArd Biesheuvel 9856ed8a3a0SArd Biesheuvel static inline p4d_t *p4d_set_fixmap(unsigned long addr) 9866ed8a3a0SArd Biesheuvel { 9876ed8a3a0SArd Biesheuvel if (!pgtable_l5_enabled()) 9886ed8a3a0SArd Biesheuvel return NULL; 9896ed8a3a0SArd Biesheuvel return (p4d_t *)set_fixmap_offset(FIX_P4D, addr); 9906ed8a3a0SArd Biesheuvel } 9916ed8a3a0SArd Biesheuvel 9926ed8a3a0SArd Biesheuvel static inline p4d_t *p4d_set_fixmap_offset(pgd_t *pgdp, unsigned long addr) 9936ed8a3a0SArd Biesheuvel { 9946ed8a3a0SArd Biesheuvel if (!pgtable_l5_enabled()) 9956ed8a3a0SArd Biesheuvel return pgd_to_folded_p4d(pgdp, addr); 9966ed8a3a0SArd Biesheuvel return p4d_set_fixmap(p4d_offset_phys(pgdp, addr)); 9976ed8a3a0SArd Biesheuvel } 9986ed8a3a0SArd Biesheuvel 9996ed8a3a0SArd Biesheuvel static inline void p4d_clear_fixmap(void) 10006ed8a3a0SArd Biesheuvel { 10016ed8a3a0SArd Biesheuvel if (pgtable_l5_enabled()) 10026ed8a3a0SArd Biesheuvel clear_fixmap(FIX_P4D); 10036ed8a3a0SArd Biesheuvel } 10046ed8a3a0SArd Biesheuvel 10056ed8a3a0SArd Biesheuvel /* use ONLY for statically allocated translation tables */ 10066ed8a3a0SArd Biesheuvel static inline p4d_t *p4d_offset_kimg(pgd_t *pgdp, u64 addr) 10076ed8a3a0SArd Biesheuvel { 10086ed8a3a0SArd Biesheuvel if (!pgtable_l5_enabled()) 10096ed8a3a0SArd Biesheuvel return pgd_to_folded_p4d(pgdp, addr); 10106ed8a3a0SArd Biesheuvel return (p4d_t *)__phys_to_kimg(p4d_offset_phys(pgdp, addr)); 10116ed8a3a0SArd Biesheuvel } 10126ed8a3a0SArd Biesheuvel 1013a6bbf5d4SArd Biesheuvel #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd))) 1014a6bbf5d4SArd Biesheuvel 1015a6bbf5d4SArd Biesheuvel #else 1016a6bbf5d4SArd Biesheuvel 1017a6bbf5d4SArd Biesheuvel static inline bool pgtable_l5_enabled(void) { return false; } 1018a6bbf5d4SArd Biesheuvel 10190e9df1c9SRyan Roberts #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 10200e9df1c9SRyan Roberts 10216ed8a3a0SArd Biesheuvel /* Match p4d_offset folding in <asm/generic/pgtable-nop4d.h> */ 10226ed8a3a0SArd Biesheuvel #define p4d_set_fixmap(addr) NULL 10236ed8a3a0SArd Biesheuvel #define p4d_set_fixmap_offset(p4dp, addr) ((p4d_t *)p4dp) 10246ed8a3a0SArd Biesheuvel #define p4d_clear_fixmap() 10256ed8a3a0SArd Biesheuvel 10266ed8a3a0SArd Biesheuvel #define p4d_offset_kimg(dir,addr) ((p4d_t *)dir) 10276ed8a3a0SArd Biesheuvel 1028a6bbf5d4SArd Biesheuvel #endif /* CONFIG_PGTABLE_LEVELS > 4 */ 1029a6bbf5d4SArd Biesheuvel 10302cf660ebSGavin Shan #define pgd_ERROR(e) \ 10312cf660ebSGavin Shan pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) 10327078db46SCatalin Marinas 1033961faac1SMark Rutland #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 1034961faac1SMark Rutland #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 1035961faac1SMark Rutland 10364f04d8f0SCatalin Marinas static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 10374f04d8f0SCatalin Marinas { 10389f341931SCatalin Marinas /* 10399f341931SCatalin Marinas * Normal and Normal-Tagged are two different memory types and indices 10409f341931SCatalin Marinas * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK. 10419f341931SCatalin Marinas */ 1042a6fadf7eSWill Deacon const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 1043f0f5863aSRyan Roberts PTE_PRESENT_INVALID | PTE_VALID | PTE_WRITE | 1044f0f5863aSRyan Roberts PTE_GP | PTE_ATTRINDX_MASK; 10452f4b829cSCatalin Marinas /* preserve the hardware dirty information */ 10462f4b829cSCatalin Marinas if (pte_hw_dirty(pte)) 10476477c388SAnshuman Khandual pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 10486477c388SAnshuman Khandual 10494f04d8f0SCatalin Marinas pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 10503c069607SJames Houghton /* 10513c069607SJames Houghton * If we end up clearing hw dirtiness for a sw-dirty PTE, set hardware 10523c069607SJames Houghton * dirtiness again. 10533c069607SJames Houghton */ 10543c069607SJames Houghton if (pte_sw_dirty(pte)) 10553c069607SJames Houghton pte = pte_mkdirty(pte); 10564f04d8f0SCatalin Marinas return pte; 10574f04d8f0SCatalin Marinas } 10584f04d8f0SCatalin Marinas 10599c7e535fSSteve Capper static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 10609c7e535fSSteve Capper { 10619c7e535fSSteve Capper return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 10629c7e535fSSteve Capper } 10639c7e535fSSteve Capper 10645a00bfd6SRyan Roberts extern int __ptep_set_access_flags(struct vm_area_struct *vma, 106566dbd6e6SCatalin Marinas unsigned long address, pte_t *ptep, 106666dbd6e6SCatalin Marinas pte_t entry, int dirty); 106766dbd6e6SCatalin Marinas 1068282aa705SCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1069282aa705SCatalin Marinas #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1070282aa705SCatalin Marinas static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1071282aa705SCatalin Marinas unsigned long address, pmd_t *pmdp, 1072282aa705SCatalin Marinas pmd_t entry, int dirty) 1073282aa705SCatalin Marinas { 10745a00bfd6SRyan Roberts return __ptep_set_access_flags(vma, address, (pte_t *)pmdp, 10755a00bfd6SRyan Roberts pmd_pte(entry), dirty); 1076282aa705SCatalin Marinas } 107773b20c84SRobin Murphy 107873b20c84SRobin Murphy static inline int pud_devmap(pud_t pud) 107973b20c84SRobin Murphy { 108073b20c84SRobin Murphy return 0; 108173b20c84SRobin Murphy } 108273b20c84SRobin Murphy 108373b20c84SRobin Murphy static inline int pgd_devmap(pgd_t pgd) 108473b20c84SRobin Murphy { 108573b20c84SRobin Murphy return 0; 108673b20c84SRobin Murphy } 1087282aa705SCatalin Marinas #endif 1088282aa705SCatalin Marinas 1089ed928a34STong Tiangen #ifdef CONFIG_PAGE_TABLE_CHECK 1090ed928a34STong Tiangen static inline bool pte_user_accessible_page(pte_t pte) 1091ed928a34STong Tiangen { 1092f0f5863aSRyan Roberts return pte_valid(pte) && (pte_user(pte) || pte_user_exec(pte)); 1093ed928a34STong Tiangen } 1094ed928a34STong Tiangen 1095ed928a34STong Tiangen static inline bool pmd_user_accessible_page(pmd_t pmd) 1096ed928a34STong Tiangen { 1097f0f5863aSRyan Roberts return pmd_valid(pmd) && !pmd_table(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd)); 1098ed928a34STong Tiangen } 1099ed928a34STong Tiangen 1100ed928a34STong Tiangen static inline bool pud_user_accessible_page(pud_t pud) 1101ed928a34STong Tiangen { 1102f0f5863aSRyan Roberts return pud_valid(pud) && !pud_table(pud) && (pud_user(pud) || pud_user_exec(pud)); 1103ed928a34STong Tiangen } 1104ed928a34STong Tiangen #endif 1105ed928a34STong Tiangen 11062f4b829cSCatalin Marinas /* 11072f4b829cSCatalin Marinas * Atomic pte/pmd modifications. 11082f4b829cSCatalin Marinas */ 11095a00bfd6SRyan Roberts static inline int __ptep_test_and_clear_young(struct vm_area_struct *vma, 11105a00bfd6SRyan Roberts unsigned long address, 11115a00bfd6SRyan Roberts pte_t *ptep) 11122f4b829cSCatalin Marinas { 11133bbf7157SCatalin Marinas pte_t old_pte, pte; 11142f4b829cSCatalin Marinas 11155a00bfd6SRyan Roberts pte = __ptep_get(ptep); 11163bbf7157SCatalin Marinas do { 11173bbf7157SCatalin Marinas old_pte = pte; 11183bbf7157SCatalin Marinas pte = pte_mkold(pte); 11193bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 11203bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 11213bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 11222f4b829cSCatalin Marinas 11233bbf7157SCatalin Marinas return pte_young(pte); 11242f4b829cSCatalin Marinas } 11252f4b829cSCatalin Marinas 11265a00bfd6SRyan Roberts static inline int __ptep_clear_flush_young(struct vm_area_struct *vma, 11273403e56bSAlex Van Brunt unsigned long address, pte_t *ptep) 11283403e56bSAlex Van Brunt { 11295a00bfd6SRyan Roberts int young = __ptep_test_and_clear_young(vma, address, ptep); 11303403e56bSAlex Van Brunt 11313403e56bSAlex Van Brunt if (young) { 11323403e56bSAlex Van Brunt /* 11333403e56bSAlex Van Brunt * We can elide the trailing DSB here since the worst that can 11343403e56bSAlex Van Brunt * happen is that a CPU continues to use the young entry in its 11353403e56bSAlex Van Brunt * TLB and we mistakenly reclaim the associated page. The 11363403e56bSAlex Van Brunt * window for such an event is bounded by the next 11373403e56bSAlex Van Brunt * context-switch, which provides a DSB to complete the TLB 11383403e56bSAlex Van Brunt * invalidation. 11393403e56bSAlex Van Brunt */ 11403403e56bSAlex Van Brunt flush_tlb_page_nosync(vma, address); 11413403e56bSAlex Van Brunt } 11423403e56bSAlex Van Brunt 11433403e56bSAlex Van Brunt return young; 11443403e56bSAlex Van Brunt } 11453403e56bSAlex Van Brunt 11462f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 11472f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 11482f4b829cSCatalin Marinas static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 11492f4b829cSCatalin Marinas unsigned long address, 11502f4b829cSCatalin Marinas pmd_t *pmdp) 11512f4b829cSCatalin Marinas { 11525a00bfd6SRyan Roberts return __ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 11532f4b829cSCatalin Marinas } 11542f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 11552f4b829cSCatalin Marinas 11565a00bfd6SRyan Roberts static inline pte_t __ptep_get_and_clear(struct mm_struct *mm, 11572f4b829cSCatalin Marinas unsigned long address, pte_t *ptep) 11582f4b829cSCatalin Marinas { 115942b25471SKefeng Wang pte_t pte = __pte(xchg_relaxed(&pte_val(*ptep), 0)); 116042b25471SKefeng Wang 1161aa232204SKemeng Shi page_table_check_pte_clear(mm, pte); 116242b25471SKefeng Wang 116342b25471SKefeng Wang return pte; 11642f4b829cSCatalin Marinas } 11652f4b829cSCatalin Marinas 11666b1e4efbSRyan Roberts static inline void __clear_full_ptes(struct mm_struct *mm, unsigned long addr, 11676b1e4efbSRyan Roberts pte_t *ptep, unsigned int nr, int full) 11686b1e4efbSRyan Roberts { 11696b1e4efbSRyan Roberts for (;;) { 11706b1e4efbSRyan Roberts __ptep_get_and_clear(mm, addr, ptep); 11716b1e4efbSRyan Roberts if (--nr == 0) 11726b1e4efbSRyan Roberts break; 11736b1e4efbSRyan Roberts ptep++; 11746b1e4efbSRyan Roberts addr += PAGE_SIZE; 11756b1e4efbSRyan Roberts } 11766b1e4efbSRyan Roberts } 11776b1e4efbSRyan Roberts 11786b1e4efbSRyan Roberts static inline pte_t __get_and_clear_full_ptes(struct mm_struct *mm, 11796b1e4efbSRyan Roberts unsigned long addr, pte_t *ptep, 11806b1e4efbSRyan Roberts unsigned int nr, int full) 11816b1e4efbSRyan Roberts { 11826b1e4efbSRyan Roberts pte_t pte, tmp_pte; 11836b1e4efbSRyan Roberts 11846b1e4efbSRyan Roberts pte = __ptep_get_and_clear(mm, addr, ptep); 11856b1e4efbSRyan Roberts while (--nr) { 11866b1e4efbSRyan Roberts ptep++; 11876b1e4efbSRyan Roberts addr += PAGE_SIZE; 11886b1e4efbSRyan Roberts tmp_pte = __ptep_get_and_clear(mm, addr, ptep); 11896b1e4efbSRyan Roberts if (pte_dirty(tmp_pte)) 11906b1e4efbSRyan Roberts pte = pte_mkdirty(pte); 11916b1e4efbSRyan Roberts if (pte_young(tmp_pte)) 11926b1e4efbSRyan Roberts pte = pte_mkyoung(pte); 11936b1e4efbSRyan Roberts } 11946b1e4efbSRyan Roberts return pte; 11956b1e4efbSRyan Roberts } 11966b1e4efbSRyan Roberts 11972f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1198911f56eeSCatalin Marinas #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1199911f56eeSCatalin Marinas static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 12002f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 12012f4b829cSCatalin Marinas { 120242b25471SKefeng Wang pmd_t pmd = __pmd(xchg_relaxed(&pmd_val(*pmdp), 0)); 120342b25471SKefeng Wang 12041831414cSKemeng Shi page_table_check_pmd_clear(mm, pmd); 120542b25471SKefeng Wang 120642b25471SKefeng Wang return pmd; 12072f4b829cSCatalin Marinas } 12082f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 12092f4b829cSCatalin Marinas 1210311a6cf2SRyan Roberts static inline void ___ptep_set_wrprotect(struct mm_struct *mm, 1211311a6cf2SRyan Roberts unsigned long address, pte_t *ptep, 1212311a6cf2SRyan Roberts pte_t pte) 12132f4b829cSCatalin Marinas { 1214311a6cf2SRyan Roberts pte_t old_pte; 12152f4b829cSCatalin Marinas 12163bbf7157SCatalin Marinas do { 12173bbf7157SCatalin Marinas old_pte = pte; 12183bbf7157SCatalin Marinas pte = pte_wrprotect(pte); 12193bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 12203bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 12213bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 12222f4b829cSCatalin Marinas } 12232f4b829cSCatalin Marinas 12242f4b829cSCatalin Marinas /* 12255a00bfd6SRyan Roberts * __ptep_set_wrprotect - mark read-only while trasferring potential hardware 12262f4b829cSCatalin Marinas * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 12272f4b829cSCatalin Marinas */ 12285a00bfd6SRyan Roberts static inline void __ptep_set_wrprotect(struct mm_struct *mm, 12295a00bfd6SRyan Roberts unsigned long address, pte_t *ptep) 12302f4b829cSCatalin Marinas { 1231311a6cf2SRyan Roberts ___ptep_set_wrprotect(mm, address, ptep, __ptep_get(ptep)); 1232311a6cf2SRyan Roberts } 12332f4b829cSCatalin Marinas 1234311a6cf2SRyan Roberts static inline void __wrprotect_ptes(struct mm_struct *mm, unsigned long address, 1235311a6cf2SRyan Roberts pte_t *ptep, unsigned int nr) 1236311a6cf2SRyan Roberts { 1237311a6cf2SRyan Roberts unsigned int i; 1238311a6cf2SRyan Roberts 1239311a6cf2SRyan Roberts for (i = 0; i < nr; i++, address += PAGE_SIZE, ptep++) 1240311a6cf2SRyan Roberts __ptep_set_wrprotect(mm, address, ptep); 12412f4b829cSCatalin Marinas } 12422f4b829cSCatalin Marinas 12432f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 12442f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_SET_WRPROTECT 12452f4b829cSCatalin Marinas static inline void pmdp_set_wrprotect(struct mm_struct *mm, 12462f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 12472f4b829cSCatalin Marinas { 12485a00bfd6SRyan Roberts __ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 12492f4b829cSCatalin Marinas } 12501d78a62cSCatalin Marinas 12511d78a62cSCatalin Marinas #define pmdp_establish pmdp_establish 12521d78a62cSCatalin Marinas static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 12531d78a62cSCatalin Marinas unsigned long address, pmd_t *pmdp, pmd_t pmd) 12541d78a62cSCatalin Marinas { 1255a3b83713SKemeng Shi page_table_check_pmd_set(vma->vm_mm, pmdp, pmd); 12561d78a62cSCatalin Marinas return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 12571d78a62cSCatalin Marinas } 12582f4b829cSCatalin Marinas #endif 12592f4b829cSCatalin Marinas 12604f04d8f0SCatalin Marinas /* 12614f04d8f0SCatalin Marinas * Encode and decode a swap entry: 12623676f9efSCatalin Marinas * bits 0-1: present (must be zero) 1263570ef363SDavid Hildenbrand * bits 2: remember PG_anon_exclusive 1264*55564814SRyan Roberts * bits 6-10: swap type 1265*55564814SRyan Roberts * bit 11: PTE_PRESENT_INVALID (must be zero) 1266*55564814SRyan Roberts * bits 12-61: swap offset 12674f04d8f0SCatalin Marinas */ 1268*55564814SRyan Roberts #define __SWP_TYPE_SHIFT 6 1269570ef363SDavid Hildenbrand #define __SWP_TYPE_BITS 5 12704f04d8f0SCatalin Marinas #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 1271*55564814SRyan Roberts #define __SWP_OFFSET_SHIFT 12 1272*55564814SRyan Roberts #define __SWP_OFFSET_BITS 50 12733676f9efSCatalin Marinas #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 12744f04d8f0SCatalin Marinas 12754f04d8f0SCatalin Marinas #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 12763676f9efSCatalin Marinas #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 12774f04d8f0SCatalin Marinas #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 12784f04d8f0SCatalin Marinas 12794f04d8f0SCatalin Marinas #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 12804f04d8f0SCatalin Marinas #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 12814f04d8f0SCatalin Marinas 128253fa117bSAnshuman Khandual #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 128353fa117bSAnshuman Khandual #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 128453fa117bSAnshuman Khandual #define __swp_entry_to_pmd(swp) __pmd((swp).val) 128553fa117bSAnshuman Khandual #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 128653fa117bSAnshuman Khandual 12874f04d8f0SCatalin Marinas /* 12884f04d8f0SCatalin Marinas * Ensure that there are not more swap files than can be encoded in the kernel 1289aad9061bSGeert Uytterhoeven * PTEs. 12904f04d8f0SCatalin Marinas */ 12914f04d8f0SCatalin Marinas #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 12924f04d8f0SCatalin Marinas 129336943abaSSteven Price #ifdef CONFIG_ARM64_MTE 129436943abaSSteven Price 129536943abaSSteven Price #define __HAVE_ARCH_PREPARE_TO_SWAP 129636943abaSSteven Price static inline int arch_prepare_to_swap(struct page *page) 129736943abaSSteven Price { 129836943abaSSteven Price if (system_supports_mte()) 129936943abaSSteven Price return mte_save_tags(page); 130036943abaSSteven Price return 0; 130136943abaSSteven Price } 130236943abaSSteven Price 130336943abaSSteven Price #define __HAVE_ARCH_SWAP_INVALIDATE 130436943abaSSteven Price static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 130536943abaSSteven Price { 130636943abaSSteven Price if (system_supports_mte()) 130736943abaSSteven Price mte_invalidate_tags(type, offset); 130836943abaSSteven Price } 130936943abaSSteven Price 131036943abaSSteven Price static inline void arch_swap_invalidate_area(int type) 131136943abaSSteven Price { 131236943abaSSteven Price if (system_supports_mte()) 131336943abaSSteven Price mte_invalidate_tags_area(type); 131436943abaSSteven Price } 131536943abaSSteven Price 131636943abaSSteven Price #define __HAVE_ARCH_SWAP_RESTORE 1317da08e9b7SMatthew Wilcox (Oracle) static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio) 131836943abaSSteven Price { 1319d77e59a8SCatalin Marinas if (system_supports_mte()) 1320d77e59a8SCatalin Marinas mte_restore_tags(entry, &folio->page); 132136943abaSSteven Price } 132236943abaSSteven Price 132336943abaSSteven Price #endif /* CONFIG_ARM64_MTE */ 132436943abaSSteven Price 1325cba3574fSWill Deacon /* 13265a00bfd6SRyan Roberts * On AArch64, the cache coherency is handled via the __set_ptes() function. 1327cba3574fSWill Deacon */ 13284a169d61SMatthew Wilcox (Oracle) static inline void update_mmu_cache_range(struct vm_fault *vmf, 13294a169d61SMatthew Wilcox (Oracle) struct vm_area_struct *vma, unsigned long addr, pte_t *ptep, 13304a169d61SMatthew Wilcox (Oracle) unsigned int nr) 1331cba3574fSWill Deacon { 1332cba3574fSWill Deacon /* 1333120798d2SWill Deacon * We don't do anything here, so there's a very small chance of 1334120798d2SWill Deacon * us retaking a user fault which we just fixed up. The alternative 1335120798d2SWill Deacon * is doing a dsb(ishst), but that penalises the fastpath. 1336cba3574fSWill Deacon */ 1337cba3574fSWill Deacon } 1338cba3574fSWill Deacon 13394a169d61SMatthew Wilcox (Oracle) #define update_mmu_cache(vma, addr, ptep) \ 13404a169d61SMatthew Wilcox (Oracle) update_mmu_cache_range(NULL, vma, addr, ptep, 1) 1341cba3574fSWill Deacon #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 1342cba3574fSWill Deacon 1343529c4b05SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 1344529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 1345529c4b05SKristina Martsenko #else 1346529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (addr) 1347529c4b05SKristina Martsenko #endif 1348529c4b05SKristina Martsenko 13496af31226SJia He /* 13506af31226SJia He * On arm64 without hardware Access Flag, copying from user will fail because 13516af31226SJia He * the pte is old and cannot be marked young. So we always end up with zeroed 13526af31226SJia He * page after fork() + CoW for pfn mappings. We don't always have a 13536af31226SJia He * hardware-managed access flag on arm64. 13546af31226SJia He */ 1355e1fd09e3SYu Zhao #define arch_has_hw_pte_young cpu_has_hw_af 13560388f9c7SWill Deacon 13570388f9c7SWill Deacon /* 13580388f9c7SWill Deacon * Experimentally, it's cheap to set the access flag in hardware and we 13590388f9c7SWill Deacon * benefit from prefaulting mappings as 'old' to start with. 13600388f9c7SWill Deacon */ 1361e1fd09e3SYu Zhao #define arch_wants_old_prefaulted_pte cpu_has_hw_af 13626af31226SJia He 1363f8b46c4bSAnshuman Khandual static inline bool pud_sect_supported(void) 1364f8b46c4bSAnshuman Khandual { 1365f8b46c4bSAnshuman Khandual return PAGE_SIZE == SZ_4K; 1366f8b46c4bSAnshuman Khandual } 1367f8b46c4bSAnshuman Khandual 136818107f8aSVladimir Murzin 13695db568e7SAnshuman Khandual #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 13705db568e7SAnshuman Khandual #define ptep_modify_prot_start ptep_modify_prot_start 13715db568e7SAnshuman Khandual extern pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 13725db568e7SAnshuman Khandual unsigned long addr, pte_t *ptep); 13735db568e7SAnshuman Khandual 13745db568e7SAnshuman Khandual #define ptep_modify_prot_commit ptep_modify_prot_commit 13755db568e7SAnshuman Khandual extern void ptep_modify_prot_commit(struct vm_area_struct *vma, 13765db568e7SAnshuman Khandual unsigned long addr, pte_t *ptep, 13775db568e7SAnshuman Khandual pte_t old_pte, pte_t new_pte); 13785a00bfd6SRyan Roberts 13794602e575SRyan Roberts #ifdef CONFIG_ARM64_CONTPTE 13804602e575SRyan Roberts 13814602e575SRyan Roberts /* 13824602e575SRyan Roberts * The contpte APIs are used to transparently manage the contiguous bit in ptes 13834602e575SRyan Roberts * where it is possible and makes sense to do so. The PTE_CONT bit is considered 13844602e575SRyan Roberts * a private implementation detail of the public ptep API (see below). 13854602e575SRyan Roberts */ 1386f0c22649SRyan Roberts extern void __contpte_try_fold(struct mm_struct *mm, unsigned long addr, 1387f0c22649SRyan Roberts pte_t *ptep, pte_t pte); 13884602e575SRyan Roberts extern void __contpte_try_unfold(struct mm_struct *mm, unsigned long addr, 13894602e575SRyan Roberts pte_t *ptep, pte_t pte); 13904602e575SRyan Roberts extern pte_t contpte_ptep_get(pte_t *ptep, pte_t orig_pte); 13914602e575SRyan Roberts extern pte_t contpte_ptep_get_lockless(pte_t *orig_ptep); 13924602e575SRyan Roberts extern void contpte_set_ptes(struct mm_struct *mm, unsigned long addr, 13934602e575SRyan Roberts pte_t *ptep, pte_t pte, unsigned int nr); 13946b1e4efbSRyan Roberts extern void contpte_clear_full_ptes(struct mm_struct *mm, unsigned long addr, 13956b1e4efbSRyan Roberts pte_t *ptep, unsigned int nr, int full); 13966b1e4efbSRyan Roberts extern pte_t contpte_get_and_clear_full_ptes(struct mm_struct *mm, 13976b1e4efbSRyan Roberts unsigned long addr, pte_t *ptep, 13986b1e4efbSRyan Roberts unsigned int nr, int full); 13994602e575SRyan Roberts extern int contpte_ptep_test_and_clear_young(struct vm_area_struct *vma, 14004602e575SRyan Roberts unsigned long addr, pte_t *ptep); 14014602e575SRyan Roberts extern int contpte_ptep_clear_flush_young(struct vm_area_struct *vma, 14024602e575SRyan Roberts unsigned long addr, pte_t *ptep); 1403311a6cf2SRyan Roberts extern void contpte_wrprotect_ptes(struct mm_struct *mm, unsigned long addr, 1404311a6cf2SRyan Roberts pte_t *ptep, unsigned int nr); 14054602e575SRyan Roberts extern int contpte_ptep_set_access_flags(struct vm_area_struct *vma, 14064602e575SRyan Roberts unsigned long addr, pte_t *ptep, 14074602e575SRyan Roberts pte_t entry, int dirty); 14084602e575SRyan Roberts 1409f0c22649SRyan Roberts static __always_inline void contpte_try_fold(struct mm_struct *mm, 1410f0c22649SRyan Roberts unsigned long addr, pte_t *ptep, pte_t pte) 1411f0c22649SRyan Roberts { 1412f0c22649SRyan Roberts /* 1413f0c22649SRyan Roberts * Only bother trying if both the virtual and physical addresses are 1414f0c22649SRyan Roberts * aligned and correspond to the last entry in a contig range. The core 1415f0c22649SRyan Roberts * code mostly modifies ranges from low to high, so this is the likely 1416f0c22649SRyan Roberts * the last modification in the contig range, so a good time to fold. 1417f0c22649SRyan Roberts * We can't fold special mappings, because there is no associated folio. 1418f0c22649SRyan Roberts */ 1419f0c22649SRyan Roberts 1420f0c22649SRyan Roberts const unsigned long contmask = CONT_PTES - 1; 1421f0c22649SRyan Roberts bool valign = ((addr >> PAGE_SHIFT) & contmask) == contmask; 1422f0c22649SRyan Roberts 1423f0c22649SRyan Roberts if (unlikely(valign)) { 1424f0c22649SRyan Roberts bool palign = (pte_pfn(pte) & contmask) == contmask; 1425f0c22649SRyan Roberts 1426f0c22649SRyan Roberts if (unlikely(palign && 1427f0c22649SRyan Roberts pte_valid(pte) && !pte_cont(pte) && !pte_special(pte))) 1428f0c22649SRyan Roberts __contpte_try_fold(mm, addr, ptep, pte); 1429f0c22649SRyan Roberts } 1430f0c22649SRyan Roberts } 1431f0c22649SRyan Roberts 1432b972fc6aSRyan Roberts static __always_inline void contpte_try_unfold(struct mm_struct *mm, 1433b972fc6aSRyan Roberts unsigned long addr, pte_t *ptep, pte_t pte) 14344602e575SRyan Roberts { 14354602e575SRyan Roberts if (unlikely(pte_valid_cont(pte))) 14364602e575SRyan Roberts __contpte_try_unfold(mm, addr, ptep, pte); 14374602e575SRyan Roberts } 14384602e575SRyan Roberts 1439fb5451e5SRyan Roberts #define pte_batch_hint pte_batch_hint 1440fb5451e5SRyan Roberts static inline unsigned int pte_batch_hint(pte_t *ptep, pte_t pte) 1441fb5451e5SRyan Roberts { 1442fb5451e5SRyan Roberts if (!pte_valid_cont(pte)) 1443fb5451e5SRyan Roberts return 1; 1444fb5451e5SRyan Roberts 1445fb5451e5SRyan Roberts return CONT_PTES - (((unsigned long)ptep >> 3) & (CONT_PTES - 1)); 1446fb5451e5SRyan Roberts } 1447fb5451e5SRyan Roberts 14484602e575SRyan Roberts /* 14494602e575SRyan Roberts * The below functions constitute the public API that arm64 presents to the 14504602e575SRyan Roberts * core-mm to manipulate PTE entries within their page tables (or at least this 14514602e575SRyan Roberts * is the subset of the API that arm64 needs to implement). These public 14524602e575SRyan Roberts * versions will automatically and transparently apply the contiguous bit where 14534602e575SRyan Roberts * it makes sense to do so. Therefore any users that are contig-aware (e.g. 14544602e575SRyan Roberts * hugetlb, kernel mapper) should NOT use these APIs, but instead use the 14554602e575SRyan Roberts * private versions, which are prefixed with double underscore. All of these 14564602e575SRyan Roberts * APIs except for ptep_get_lockless() are expected to be called with the PTL 14574602e575SRyan Roberts * held. Although the contiguous bit is considered private to the 14584602e575SRyan Roberts * implementation, it is deliberately allowed to leak through the getters (e.g. 14594602e575SRyan Roberts * ptep_get()), back to core code. This is required so that pte_leaf_size() can 14604602e575SRyan Roberts * provide an accurate size for perf_get_pgtable_size(). But this leakage means 14614602e575SRyan Roberts * its possible a pte will be passed to a setter with the contiguous bit set, so 14624602e575SRyan Roberts * we explicitly clear the contiguous bit in those cases to prevent accidentally 14634602e575SRyan Roberts * setting it in the pgtable. 14644602e575SRyan Roberts */ 14654602e575SRyan Roberts 14664602e575SRyan Roberts #define ptep_get ptep_get 14674602e575SRyan Roberts static inline pte_t ptep_get(pte_t *ptep) 14684602e575SRyan Roberts { 14694602e575SRyan Roberts pte_t pte = __ptep_get(ptep); 14704602e575SRyan Roberts 14714602e575SRyan Roberts if (likely(!pte_valid_cont(pte))) 14724602e575SRyan Roberts return pte; 14734602e575SRyan Roberts 14744602e575SRyan Roberts return contpte_ptep_get(ptep, pte); 14754602e575SRyan Roberts } 14764602e575SRyan Roberts 14774602e575SRyan Roberts #define ptep_get_lockless ptep_get_lockless 14784602e575SRyan Roberts static inline pte_t ptep_get_lockless(pte_t *ptep) 14794602e575SRyan Roberts { 14804602e575SRyan Roberts pte_t pte = __ptep_get(ptep); 14814602e575SRyan Roberts 14824602e575SRyan Roberts if (likely(!pte_valid_cont(pte))) 14834602e575SRyan Roberts return pte; 14844602e575SRyan Roberts 14854602e575SRyan Roberts return contpte_ptep_get_lockless(ptep); 14864602e575SRyan Roberts } 14874602e575SRyan Roberts 14884602e575SRyan Roberts static inline void set_pte(pte_t *ptep, pte_t pte) 14894602e575SRyan Roberts { 14904602e575SRyan Roberts /* 14914602e575SRyan Roberts * We don't have the mm or vaddr so cannot unfold contig entries (since 14924602e575SRyan Roberts * it requires tlb maintenance). set_pte() is not used in core code, so 14934602e575SRyan Roberts * this should never even be called. Regardless do our best to service 14944602e575SRyan Roberts * any call and emit a warning if there is any attempt to set a pte on 14954602e575SRyan Roberts * top of an existing contig range. 14964602e575SRyan Roberts */ 14974602e575SRyan Roberts pte_t orig_pte = __ptep_get(ptep); 14984602e575SRyan Roberts 14994602e575SRyan Roberts WARN_ON_ONCE(pte_valid_cont(orig_pte)); 15004602e575SRyan Roberts __set_pte(ptep, pte_mknoncont(pte)); 15014602e575SRyan Roberts } 15024602e575SRyan Roberts 15034602e575SRyan Roberts #define set_ptes set_ptes 1504b972fc6aSRyan Roberts static __always_inline void set_ptes(struct mm_struct *mm, unsigned long addr, 15054602e575SRyan Roberts pte_t *ptep, pte_t pte, unsigned int nr) 15064602e575SRyan Roberts { 15074602e575SRyan Roberts pte = pte_mknoncont(pte); 15084602e575SRyan Roberts 15094602e575SRyan Roberts if (likely(nr == 1)) { 15104602e575SRyan Roberts contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 15114602e575SRyan Roberts __set_ptes(mm, addr, ptep, pte, 1); 1512f0c22649SRyan Roberts contpte_try_fold(mm, addr, ptep, pte); 15134602e575SRyan Roberts } else { 15144602e575SRyan Roberts contpte_set_ptes(mm, addr, ptep, pte, nr); 15154602e575SRyan Roberts } 15164602e575SRyan Roberts } 15174602e575SRyan Roberts 15184602e575SRyan Roberts static inline void pte_clear(struct mm_struct *mm, 15194602e575SRyan Roberts unsigned long addr, pte_t *ptep) 15204602e575SRyan Roberts { 15214602e575SRyan Roberts contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 15224602e575SRyan Roberts __pte_clear(mm, addr, ptep); 15234602e575SRyan Roberts } 15244602e575SRyan Roberts 15256b1e4efbSRyan Roberts #define clear_full_ptes clear_full_ptes 15266b1e4efbSRyan Roberts static inline void clear_full_ptes(struct mm_struct *mm, unsigned long addr, 15276b1e4efbSRyan Roberts pte_t *ptep, unsigned int nr, int full) 15286b1e4efbSRyan Roberts { 15296b1e4efbSRyan Roberts if (likely(nr == 1)) { 15306b1e4efbSRyan Roberts contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 15316b1e4efbSRyan Roberts __clear_full_ptes(mm, addr, ptep, nr, full); 15326b1e4efbSRyan Roberts } else { 15336b1e4efbSRyan Roberts contpte_clear_full_ptes(mm, addr, ptep, nr, full); 15346b1e4efbSRyan Roberts } 15356b1e4efbSRyan Roberts } 15366b1e4efbSRyan Roberts 15376b1e4efbSRyan Roberts #define get_and_clear_full_ptes get_and_clear_full_ptes 15386b1e4efbSRyan Roberts static inline pte_t get_and_clear_full_ptes(struct mm_struct *mm, 15396b1e4efbSRyan Roberts unsigned long addr, pte_t *ptep, 15406b1e4efbSRyan Roberts unsigned int nr, int full) 15416b1e4efbSRyan Roberts { 15426b1e4efbSRyan Roberts pte_t pte; 15436b1e4efbSRyan Roberts 15446b1e4efbSRyan Roberts if (likely(nr == 1)) { 15456b1e4efbSRyan Roberts contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 15466b1e4efbSRyan Roberts pte = __get_and_clear_full_ptes(mm, addr, ptep, nr, full); 15476b1e4efbSRyan Roberts } else { 15486b1e4efbSRyan Roberts pte = contpte_get_and_clear_full_ptes(mm, addr, ptep, nr, full); 15496b1e4efbSRyan Roberts } 15506b1e4efbSRyan Roberts 15516b1e4efbSRyan Roberts return pte; 15526b1e4efbSRyan Roberts } 15536b1e4efbSRyan Roberts 15544602e575SRyan Roberts #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 15554602e575SRyan Roberts static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 15564602e575SRyan Roberts unsigned long addr, pte_t *ptep) 15574602e575SRyan Roberts { 15584602e575SRyan Roberts contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 15594602e575SRyan Roberts return __ptep_get_and_clear(mm, addr, ptep); 15604602e575SRyan Roberts } 15614602e575SRyan Roberts 15624602e575SRyan Roberts #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 15634602e575SRyan Roberts static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 15644602e575SRyan Roberts unsigned long addr, pte_t *ptep) 15654602e575SRyan Roberts { 15664602e575SRyan Roberts pte_t orig_pte = __ptep_get(ptep); 15674602e575SRyan Roberts 15684602e575SRyan Roberts if (likely(!pte_valid_cont(orig_pte))) 15694602e575SRyan Roberts return __ptep_test_and_clear_young(vma, addr, ptep); 15704602e575SRyan Roberts 15714602e575SRyan Roberts return contpte_ptep_test_and_clear_young(vma, addr, ptep); 15724602e575SRyan Roberts } 15734602e575SRyan Roberts 15744602e575SRyan Roberts #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 15754602e575SRyan Roberts static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 15764602e575SRyan Roberts unsigned long addr, pte_t *ptep) 15774602e575SRyan Roberts { 15784602e575SRyan Roberts pte_t orig_pte = __ptep_get(ptep); 15794602e575SRyan Roberts 15804602e575SRyan Roberts if (likely(!pte_valid_cont(orig_pte))) 15814602e575SRyan Roberts return __ptep_clear_flush_young(vma, addr, ptep); 15824602e575SRyan Roberts 15834602e575SRyan Roberts return contpte_ptep_clear_flush_young(vma, addr, ptep); 15844602e575SRyan Roberts } 15854602e575SRyan Roberts 1586311a6cf2SRyan Roberts #define wrprotect_ptes wrprotect_ptes 1587b972fc6aSRyan Roberts static __always_inline void wrprotect_ptes(struct mm_struct *mm, 1588b972fc6aSRyan Roberts unsigned long addr, pte_t *ptep, unsigned int nr) 1589311a6cf2SRyan Roberts { 1590311a6cf2SRyan Roberts if (likely(nr == 1)) { 1591311a6cf2SRyan Roberts /* 1592311a6cf2SRyan Roberts * Optimization: wrprotect_ptes() can only be called for present 1593311a6cf2SRyan Roberts * ptes so we only need to check contig bit as condition for 1594311a6cf2SRyan Roberts * unfold, and we can remove the contig bit from the pte we read 1595311a6cf2SRyan Roberts * to avoid re-reading. This speeds up fork() which is sensitive 1596311a6cf2SRyan Roberts * for order-0 folios. Equivalent to contpte_try_unfold(). 1597311a6cf2SRyan Roberts */ 1598311a6cf2SRyan Roberts pte_t orig_pte = __ptep_get(ptep); 1599311a6cf2SRyan Roberts 1600311a6cf2SRyan Roberts if (unlikely(pte_cont(orig_pte))) { 1601311a6cf2SRyan Roberts __contpte_try_unfold(mm, addr, ptep, orig_pte); 1602311a6cf2SRyan Roberts orig_pte = pte_mknoncont(orig_pte); 1603311a6cf2SRyan Roberts } 1604311a6cf2SRyan Roberts ___ptep_set_wrprotect(mm, addr, ptep, orig_pte); 1605311a6cf2SRyan Roberts } else { 1606311a6cf2SRyan Roberts contpte_wrprotect_ptes(mm, addr, ptep, nr); 1607311a6cf2SRyan Roberts } 1608311a6cf2SRyan Roberts } 1609311a6cf2SRyan Roberts 16104602e575SRyan Roberts #define __HAVE_ARCH_PTEP_SET_WRPROTECT 16114602e575SRyan Roberts static inline void ptep_set_wrprotect(struct mm_struct *mm, 16124602e575SRyan Roberts unsigned long addr, pte_t *ptep) 16134602e575SRyan Roberts { 1614311a6cf2SRyan Roberts wrprotect_ptes(mm, addr, ptep, 1); 16154602e575SRyan Roberts } 16164602e575SRyan Roberts 16174602e575SRyan Roberts #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 16184602e575SRyan Roberts static inline int ptep_set_access_flags(struct vm_area_struct *vma, 16194602e575SRyan Roberts unsigned long addr, pte_t *ptep, 16204602e575SRyan Roberts pte_t entry, int dirty) 16214602e575SRyan Roberts { 16224602e575SRyan Roberts pte_t orig_pte = __ptep_get(ptep); 16234602e575SRyan Roberts 16244602e575SRyan Roberts entry = pte_mknoncont(entry); 16254602e575SRyan Roberts 16264602e575SRyan Roberts if (likely(!pte_valid_cont(orig_pte))) 16274602e575SRyan Roberts return __ptep_set_access_flags(vma, addr, ptep, entry, dirty); 16284602e575SRyan Roberts 16294602e575SRyan Roberts return contpte_ptep_set_access_flags(vma, addr, ptep, entry, dirty); 16304602e575SRyan Roberts } 16314602e575SRyan Roberts 16324602e575SRyan Roberts #else /* CONFIG_ARM64_CONTPTE */ 16334602e575SRyan Roberts 16345a00bfd6SRyan Roberts #define ptep_get __ptep_get 16355a00bfd6SRyan Roberts #define set_pte __set_pte 16365a00bfd6SRyan Roberts #define set_ptes __set_ptes 16375a00bfd6SRyan Roberts #define pte_clear __pte_clear 16386b1e4efbSRyan Roberts #define clear_full_ptes __clear_full_ptes 16396b1e4efbSRyan Roberts #define get_and_clear_full_ptes __get_and_clear_full_ptes 16405a00bfd6SRyan Roberts #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 16415a00bfd6SRyan Roberts #define ptep_get_and_clear __ptep_get_and_clear 16425a00bfd6SRyan Roberts #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 16435a00bfd6SRyan Roberts #define ptep_test_and_clear_young __ptep_test_and_clear_young 16445a00bfd6SRyan Roberts #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 16455a00bfd6SRyan Roberts #define ptep_clear_flush_young __ptep_clear_flush_young 16465a00bfd6SRyan Roberts #define __HAVE_ARCH_PTEP_SET_WRPROTECT 16475a00bfd6SRyan Roberts #define ptep_set_wrprotect __ptep_set_wrprotect 1648311a6cf2SRyan Roberts #define wrprotect_ptes __wrprotect_ptes 16495a00bfd6SRyan Roberts #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 16505a00bfd6SRyan Roberts #define ptep_set_access_flags __ptep_set_access_flags 16515a00bfd6SRyan Roberts 16524602e575SRyan Roberts #endif /* CONFIG_ARM64_CONTPTE */ 16534602e575SRyan Roberts 16544f04d8f0SCatalin Marinas #endif /* !__ASSEMBLY__ */ 16554f04d8f0SCatalin Marinas 16564f04d8f0SCatalin Marinas #endif /* __ASM_PGTABLE_H */ 1657