14f04d8f0SCatalin Marinas /* 24f04d8f0SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 34f04d8f0SCatalin Marinas * 44f04d8f0SCatalin Marinas * This program is free software; you can redistribute it and/or modify 54f04d8f0SCatalin Marinas * it under the terms of the GNU General Public License version 2 as 64f04d8f0SCatalin Marinas * published by the Free Software Foundation. 74f04d8f0SCatalin Marinas * 84f04d8f0SCatalin Marinas * This program is distributed in the hope that it will be useful, 94f04d8f0SCatalin Marinas * but WITHOUT ANY WARRANTY; without even the implied warranty of 104f04d8f0SCatalin Marinas * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 114f04d8f0SCatalin Marinas * GNU General Public License for more details. 124f04d8f0SCatalin Marinas * 134f04d8f0SCatalin Marinas * You should have received a copy of the GNU General Public License 144f04d8f0SCatalin Marinas * along with this program. If not, see <http://www.gnu.org/licenses/>. 154f04d8f0SCatalin Marinas */ 164f04d8f0SCatalin Marinas #ifndef __ASM_PGTABLE_H 174f04d8f0SCatalin Marinas #define __ASM_PGTABLE_H 184f04d8f0SCatalin Marinas 192f4b829cSCatalin Marinas #include <asm/bug.h> 204f04d8f0SCatalin Marinas #include <asm/proc-fns.h> 214f04d8f0SCatalin Marinas 224f04d8f0SCatalin Marinas #include <asm/memory.h> 234f04d8f0SCatalin Marinas #include <asm/pgtable-hwdef.h> 243eca86e7SMark Rutland #include <asm/pgtable-prot.h> 25*3403e56bSAlex Van Brunt #include <asm/tlbflush.h> 264f04d8f0SCatalin Marinas 274f04d8f0SCatalin Marinas /* 283e1907d5SArd Biesheuvel * VMALLOC range. 2908375198SCatalin Marinas * 30f9040773SArd Biesheuvel * VMALLOC_START: beginning of the kernel vmalloc space 313e1907d5SArd Biesheuvel * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space 323e1907d5SArd Biesheuvel * and fixed mappings 334f04d8f0SCatalin Marinas */ 34f9040773SArd Biesheuvel #define VMALLOC_START (MODULES_END) 3508375198SCatalin Marinas #define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K) 364f04d8f0SCatalin Marinas 373bab79edSArd Biesheuvel #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 384f04d8f0SCatalin Marinas 39d016bf7eSKirill A. Shutemov #define FIRST_USER_ADDRESS 0UL 404f04d8f0SCatalin Marinas 414f04d8f0SCatalin Marinas #ifndef __ASSEMBLY__ 422f4b829cSCatalin Marinas 433bbf7157SCatalin Marinas #include <asm/cmpxchg.h> 44961faac1SMark Rutland #include <asm/fixmap.h> 452f4b829cSCatalin Marinas #include <linux/mmdebug.h> 4686c9e812SWill Deacon #include <linux/mm_types.h> 4786c9e812SWill Deacon #include <linux/sched.h> 482f4b829cSCatalin Marinas 494f04d8f0SCatalin Marinas extern void __pte_error(const char *file, int line, unsigned long val); 504f04d8f0SCatalin Marinas extern void __pmd_error(const char *file, int line, unsigned long val); 51c79b954bSJungseok Lee extern void __pud_error(const char *file, int line, unsigned long val); 524f04d8f0SCatalin Marinas extern void __pgd_error(const char *file, int line, unsigned long val); 534f04d8f0SCatalin Marinas 544f04d8f0SCatalin Marinas /* 554f04d8f0SCatalin Marinas * ZERO_PAGE is a global shared page that is always zero: used 564f04d8f0SCatalin Marinas * for zero-mapped memory areas etc.. 574f04d8f0SCatalin Marinas */ 585227cfa7SMark Rutland extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 592077be67SLaura Abbott #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 604f04d8f0SCatalin Marinas 617078db46SCatalin Marinas #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) 627078db46SCatalin Marinas 6375387b92SKristina Martsenko /* 6475387b92SKristina Martsenko * Macros to convert between a physical address and its placement in a 6575387b92SKristina Martsenko * page table entry, taking care of 52-bit addresses. 6675387b92SKristina Martsenko */ 6775387b92SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 6875387b92SKristina Martsenko #define __pte_to_phys(pte) \ 6975387b92SKristina Martsenko ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36)) 7075387b92SKristina Martsenko #define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK) 7175387b92SKristina Martsenko #else 7275387b92SKristina Martsenko #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK) 7375387b92SKristina Martsenko #define __phys_to_pte_val(phys) (phys) 7475387b92SKristina Martsenko #endif 754f04d8f0SCatalin Marinas 7675387b92SKristina Martsenko #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 7775387b92SKristina Martsenko #define pfn_pte(pfn,prot) \ 7875387b92SKristina Martsenko __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 794f04d8f0SCatalin Marinas 804f04d8f0SCatalin Marinas #define pte_none(pte) (!pte_val(pte)) 814f04d8f0SCatalin Marinas #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 824f04d8f0SCatalin Marinas #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 837078db46SCatalin Marinas 844f04d8f0SCatalin Marinas /* 854f04d8f0SCatalin Marinas * The following only work if pte_present(). Undefined behaviour otherwise. 864f04d8f0SCatalin Marinas */ 8784fe6826SSteve Capper #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 8884fe6826SSteve Capper #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 8984fe6826SSteve Capper #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 9084fe6826SSteve Capper #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 91ec663d96SCatalin Marinas #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 9293ef666aSJeremy Linton #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 934f04d8f0SCatalin Marinas 94d27cfa1fSArd Biesheuvel #define pte_cont_addr_end(addr, end) \ 95d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 96d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 97d27cfa1fSArd Biesheuvel }) 98d27cfa1fSArd Biesheuvel 99d27cfa1fSArd Biesheuvel #define pmd_cont_addr_end(addr, end) \ 100d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 101d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 102d27cfa1fSArd Biesheuvel }) 103d27cfa1fSArd Biesheuvel 104b847415cSCatalin Marinas #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) 1052f4b829cSCatalin Marinas #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 1062f4b829cSCatalin Marinas #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 1072f4b829cSCatalin Marinas 108766ffb69SWill Deacon #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 109ec663d96SCatalin Marinas /* 110ec663d96SCatalin Marinas * Execute-only user mappings do not have the PTE_USER bit set. All valid 111ec663d96SCatalin Marinas * kernel mappings have the PTE_UXN bit set. 112ec663d96SCatalin Marinas */ 113ec663d96SCatalin Marinas #define pte_valid_not_user(pte) \ 114ec663d96SCatalin Marinas ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 11576c714beSWill Deacon #define pte_valid_young(pte) \ 11676c714beSWill Deacon ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF)) 1176218f96cSCatalin Marinas #define pte_valid_user(pte) \ 1186218f96cSCatalin Marinas ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) 11976c714beSWill Deacon 12076c714beSWill Deacon /* 12176c714beSWill Deacon * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 12276c714beSWill Deacon * so that we don't erroneously return false for pages that have been 12376c714beSWill Deacon * remapped as PROT_NONE but are yet to be flushed from the TLB. 12476c714beSWill Deacon */ 12576c714beSWill Deacon #define pte_accessible(mm, pte) \ 12676c714beSWill Deacon (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte)) 1274f04d8f0SCatalin Marinas 1286218f96cSCatalin Marinas /* 1296218f96cSCatalin Marinas * p??_access_permitted() is true for valid user mappings (subject to the 1306218f96cSCatalin Marinas * write permission check) other than user execute-only which do not have the 1316218f96cSCatalin Marinas * PTE_USER bit set. PROT_NONE mappings do not have the PTE_VALID bit set. 1326218f96cSCatalin Marinas */ 1336218f96cSCatalin Marinas #define pte_access_permitted(pte, write) \ 1346218f96cSCatalin Marinas (pte_valid_user(pte) && (!(write) || pte_write(pte))) 1356218f96cSCatalin Marinas #define pmd_access_permitted(pmd, write) \ 1366218f96cSCatalin Marinas (pte_access_permitted(pmd_pte(pmd), (write))) 1376218f96cSCatalin Marinas #define pud_access_permitted(pud, write) \ 1386218f96cSCatalin Marinas (pte_access_permitted(pud_pte(pud), (write))) 1396218f96cSCatalin Marinas 140b6d4f280SLaura Abbott static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 141b6d4f280SLaura Abbott { 142b6d4f280SLaura Abbott pte_val(pte) &= ~pgprot_val(prot); 143b6d4f280SLaura Abbott return pte; 144b6d4f280SLaura Abbott } 145b6d4f280SLaura Abbott 146b6d4f280SLaura Abbott static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 147b6d4f280SLaura Abbott { 148b6d4f280SLaura Abbott pte_val(pte) |= pgprot_val(prot); 149b6d4f280SLaura Abbott return pte; 150b6d4f280SLaura Abbott } 151b6d4f280SLaura Abbott 15244b6dfc5SSteve Capper static inline pte_t pte_wrprotect(pte_t pte) 15344b6dfc5SSteve Capper { 15473e86cb0SCatalin Marinas pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 15573e86cb0SCatalin Marinas pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 15673e86cb0SCatalin Marinas return pte; 15744b6dfc5SSteve Capper } 1584f04d8f0SCatalin Marinas 15944b6dfc5SSteve Capper static inline pte_t pte_mkwrite(pte_t pte) 16044b6dfc5SSteve Capper { 16173e86cb0SCatalin Marinas pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 16273e86cb0SCatalin Marinas pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 16373e86cb0SCatalin Marinas return pte; 16444b6dfc5SSteve Capper } 16544b6dfc5SSteve Capper 16644b6dfc5SSteve Capper static inline pte_t pte_mkclean(pte_t pte) 16744b6dfc5SSteve Capper { 1688781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 1698781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 1708781bcbcSSteve Capper 1718781bcbcSSteve Capper return pte; 17244b6dfc5SSteve Capper } 17344b6dfc5SSteve Capper 17444b6dfc5SSteve Capper static inline pte_t pte_mkdirty(pte_t pte) 17544b6dfc5SSteve Capper { 1768781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 1778781bcbcSSteve Capper 1788781bcbcSSteve Capper if (pte_write(pte)) 1798781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 1808781bcbcSSteve Capper 1818781bcbcSSteve Capper return pte; 18244b6dfc5SSteve Capper } 18344b6dfc5SSteve Capper 18444b6dfc5SSteve Capper static inline pte_t pte_mkold(pte_t pte) 18544b6dfc5SSteve Capper { 186b6d4f280SLaura Abbott return clear_pte_bit(pte, __pgprot(PTE_AF)); 18744b6dfc5SSteve Capper } 18844b6dfc5SSteve Capper 18944b6dfc5SSteve Capper static inline pte_t pte_mkyoung(pte_t pte) 19044b6dfc5SSteve Capper { 191b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_AF)); 19244b6dfc5SSteve Capper } 19344b6dfc5SSteve Capper 19444b6dfc5SSteve Capper static inline pte_t pte_mkspecial(pte_t pte) 19544b6dfc5SSteve Capper { 196b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 19744b6dfc5SSteve Capper } 1984f04d8f0SCatalin Marinas 19993ef666aSJeremy Linton static inline pte_t pte_mkcont(pte_t pte) 20093ef666aSJeremy Linton { 20166b3923aSDavid Woods pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 20266b3923aSDavid Woods return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 20393ef666aSJeremy Linton } 20493ef666aSJeremy Linton 20593ef666aSJeremy Linton static inline pte_t pte_mknoncont(pte_t pte) 20693ef666aSJeremy Linton { 20793ef666aSJeremy Linton return clear_pte_bit(pte, __pgprot(PTE_CONT)); 20893ef666aSJeremy Linton } 20993ef666aSJeremy Linton 2105ebe3a44SJames Morse static inline pte_t pte_mkpresent(pte_t pte) 2115ebe3a44SJames Morse { 2125ebe3a44SJames Morse return set_pte_bit(pte, __pgprot(PTE_VALID)); 2135ebe3a44SJames Morse } 2145ebe3a44SJames Morse 21566b3923aSDavid Woods static inline pmd_t pmd_mkcont(pmd_t pmd) 21666b3923aSDavid Woods { 21766b3923aSDavid Woods return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 21866b3923aSDavid Woods } 21966b3923aSDavid Woods 2204f04d8f0SCatalin Marinas static inline void set_pte(pte_t *ptep, pte_t pte) 2214f04d8f0SCatalin Marinas { 22220a004e7SWill Deacon WRITE_ONCE(*ptep, pte); 2237f0b1bf0SCatalin Marinas 2247f0b1bf0SCatalin Marinas /* 2257f0b1bf0SCatalin Marinas * Only if the new pte is valid and kernel, otherwise TLB maintenance 2267f0b1bf0SCatalin Marinas * or update_mmu_cache() have the necessary barriers. 2277f0b1bf0SCatalin Marinas */ 22824fe1b0eSWill Deacon if (pte_valid_not_user(pte)) 2297f0b1bf0SCatalin Marinas dsb(ishst); 2304f04d8f0SCatalin Marinas } 2314f04d8f0SCatalin Marinas 232907e21c1SShaokun Zhang extern void __sync_icache_dcache(pte_t pteval); 2334f04d8f0SCatalin Marinas 2342f4b829cSCatalin Marinas /* 2352f4b829cSCatalin Marinas * PTE bits configuration in the presence of hardware Dirty Bit Management 2362f4b829cSCatalin Marinas * (PTE_WRITE == PTE_DBM): 2372f4b829cSCatalin Marinas * 2382f4b829cSCatalin Marinas * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 2392f4b829cSCatalin Marinas * 0 0 | 1 0 0 2402f4b829cSCatalin Marinas * 0 1 | 1 1 0 2412f4b829cSCatalin Marinas * 1 0 | 1 0 1 2422f4b829cSCatalin Marinas * 1 1 | 0 1 x 2432f4b829cSCatalin Marinas * 2442f4b829cSCatalin Marinas * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 2452f4b829cSCatalin Marinas * the page fault mechanism. Checking the dirty status of a pte becomes: 2462f4b829cSCatalin Marinas * 247b847415cSCatalin Marinas * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 2482f4b829cSCatalin Marinas */ 2494f04d8f0SCatalin Marinas static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 2504f04d8f0SCatalin Marinas pte_t *ptep, pte_t pte) 2514f04d8f0SCatalin Marinas { 25220a004e7SWill Deacon pte_t old_pte; 25320a004e7SWill Deacon 25473e86cb0SCatalin Marinas if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 255907e21c1SShaokun Zhang __sync_icache_dcache(pte); 25602522463SWill Deacon 2572f4b829cSCatalin Marinas /* 2582f4b829cSCatalin Marinas * If the existing pte is valid, check for potential race with 2592f4b829cSCatalin Marinas * hardware updates of the pte (ptep_set_access_flags safely changes 2602f4b829cSCatalin Marinas * valid ptes without going through an invalid entry). 2612f4b829cSCatalin Marinas */ 26220a004e7SWill Deacon old_pte = READ_ONCE(*ptep); 26320a004e7SWill Deacon if (IS_ENABLED(CONFIG_DEBUG_VM) && pte_valid(old_pte) && pte_valid(pte) && 26486c9e812SWill Deacon (mm == current->active_mm || atomic_read(&mm->mm_users) > 1)) { 26582d34008SCatalin Marinas VM_WARN_ONCE(!pte_young(pte), 26682d34008SCatalin Marinas "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 26720a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 26820a004e7SWill Deacon VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 26982d34008SCatalin Marinas "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 27020a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 2712f4b829cSCatalin Marinas } 2722f4b829cSCatalin Marinas 2734f04d8f0SCatalin Marinas set_pte(ptep, pte); 2744f04d8f0SCatalin Marinas } 2754f04d8f0SCatalin Marinas 276747a70e6SSteve Capper #define __HAVE_ARCH_PTE_SAME 277747a70e6SSteve Capper static inline int pte_same(pte_t pte_a, pte_t pte_b) 278747a70e6SSteve Capper { 279747a70e6SSteve Capper pteval_t lhs, rhs; 280747a70e6SSteve Capper 281747a70e6SSteve Capper lhs = pte_val(pte_a); 282747a70e6SSteve Capper rhs = pte_val(pte_b); 283747a70e6SSteve Capper 284747a70e6SSteve Capper if (pte_present(pte_a)) 285747a70e6SSteve Capper lhs &= ~PTE_RDONLY; 286747a70e6SSteve Capper 287747a70e6SSteve Capper if (pte_present(pte_b)) 288747a70e6SSteve Capper rhs &= ~PTE_RDONLY; 289747a70e6SSteve Capper 290747a70e6SSteve Capper return (lhs == rhs); 291747a70e6SSteve Capper } 292747a70e6SSteve Capper 2934f04d8f0SCatalin Marinas /* 2944f04d8f0SCatalin Marinas * Huge pte definitions. 2954f04d8f0SCatalin Marinas */ 296084bd298SSteve Capper #define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT)) 297084bd298SSteve Capper #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 298084bd298SSteve Capper 299084bd298SSteve Capper /* 300084bd298SSteve Capper * Hugetlb definitions. 301084bd298SSteve Capper */ 30266b3923aSDavid Woods #define HUGE_MAX_HSTATE 4 303084bd298SSteve Capper #define HPAGE_SHIFT PMD_SHIFT 304084bd298SSteve Capper #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 305084bd298SSteve Capper #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 306084bd298SSteve Capper #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 3074f04d8f0SCatalin Marinas 30875387b92SKristina Martsenko static inline pte_t pgd_pte(pgd_t pgd) 30975387b92SKristina Martsenko { 31075387b92SKristina Martsenko return __pte(pgd_val(pgd)); 31175387b92SKristina Martsenko } 31275387b92SKristina Martsenko 31329e56940SSteve Capper static inline pte_t pud_pte(pud_t pud) 31429e56940SSteve Capper { 31529e56940SSteve Capper return __pte(pud_val(pud)); 31629e56940SSteve Capper } 31729e56940SSteve Capper 31829e56940SSteve Capper static inline pmd_t pud_pmd(pud_t pud) 31929e56940SSteve Capper { 32029e56940SSteve Capper return __pmd(pud_val(pud)); 32129e56940SSteve Capper } 32229e56940SSteve Capper 3239c7e535fSSteve Capper static inline pte_t pmd_pte(pmd_t pmd) 3249c7e535fSSteve Capper { 3259c7e535fSSteve Capper return __pte(pmd_val(pmd)); 3269c7e535fSSteve Capper } 327af074848SSteve Capper 3289c7e535fSSteve Capper static inline pmd_t pte_pmd(pte_t pte) 3299c7e535fSSteve Capper { 3309c7e535fSSteve Capper return __pmd(pte_val(pte)); 3319c7e535fSSteve Capper } 332af074848SSteve Capper 3338ce837ceSArd Biesheuvel static inline pgprot_t mk_sect_prot(pgprot_t prot) 3348ce837ceSArd Biesheuvel { 3358ce837ceSArd Biesheuvel return __pgprot(pgprot_val(prot) & ~PTE_TABLE_BIT); 3368ce837ceSArd Biesheuvel } 3378ce837ceSArd Biesheuvel 33856166230SGanapatrao Kulkarni #ifdef CONFIG_NUMA_BALANCING 33956166230SGanapatrao Kulkarni /* 34056166230SGanapatrao Kulkarni * See the comment in include/asm-generic/pgtable.h 34156166230SGanapatrao Kulkarni */ 34256166230SGanapatrao Kulkarni static inline int pte_protnone(pte_t pte) 34356166230SGanapatrao Kulkarni { 34456166230SGanapatrao Kulkarni return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; 34556166230SGanapatrao Kulkarni } 34656166230SGanapatrao Kulkarni 34756166230SGanapatrao Kulkarni static inline int pmd_protnone(pmd_t pmd) 34856166230SGanapatrao Kulkarni { 34956166230SGanapatrao Kulkarni return pte_protnone(pmd_pte(pmd)); 35056166230SGanapatrao Kulkarni } 35156166230SGanapatrao Kulkarni #endif 35256166230SGanapatrao Kulkarni 353af074848SSteve Capper /* 354af074848SSteve Capper * THP definitions. 355af074848SSteve Capper */ 356af074848SSteve Capper 357af074848SSteve Capper #ifdef CONFIG_TRANSPARENT_HUGEPAGE 358af074848SSteve Capper #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) 35929e56940SSteve Capper #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 360af074848SSteve Capper 3615bb1cc0fSCatalin Marinas #define pmd_present(pmd) pte_present(pmd_pte(pmd)) 362c164e038SKirill A. Shutemov #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 3639c7e535fSSteve Capper #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 3640795edafSWill Deacon #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 3659c7e535fSSteve Capper #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 3669c7e535fSSteve Capper #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 3679c7e535fSSteve Capper #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 36805ee26d9SMinchan Kim #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 3699c7e535fSSteve Capper #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 3709c7e535fSSteve Capper #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 3715bb1cc0fSCatalin Marinas #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_SECT_VALID)) 372af074848SSteve Capper 3730dbd3b18SSuzuki K Poulose #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 3740dbd3b18SSuzuki K Poulose 3759c7e535fSSteve Capper #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 376af074848SSteve Capper 377af074848SSteve Capper #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 378af074848SSteve Capper 37975387b92SKristina Martsenko #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 38075387b92SKristina Martsenko #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 38175387b92SKristina Martsenko #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 38275387b92SKristina Martsenko #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 383af074848SSteve Capper #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 384af074848SSteve Capper 38529e56940SSteve Capper #define pud_write(pud) pte_write(pud_pte(pud)) 38675387b92SKristina Martsenko 38775387b92SKristina Martsenko #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 38875387b92SKristina Martsenko #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 38975387b92SKristina Martsenko #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 39075387b92SKristina Martsenko #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 391af074848SSteve Capper 392ceb21835SWill Deacon #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) 393af074848SSteve Capper 39475387b92SKristina Martsenko #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 39575387b92SKristina Martsenko #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 39675387b92SKristina Martsenko 397a501e324SCatalin Marinas #define __pgprot_modify(prot,mask,bits) \ 398a501e324SCatalin Marinas __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 399a501e324SCatalin Marinas 400af074848SSteve Capper /* 4014f04d8f0SCatalin Marinas * Mark the prot value as uncacheable and unbufferable. 4024f04d8f0SCatalin Marinas */ 4034f04d8f0SCatalin Marinas #define pgprot_noncached(prot) \ 404de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 4054f04d8f0SCatalin Marinas #define pgprot_writecombine(prot) \ 406de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 407d1e6dc91SLiviu Dudau #define pgprot_device(prot) \ 408d1e6dc91SLiviu Dudau __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 4094f04d8f0SCatalin Marinas #define __HAVE_PHYS_MEM_ACCESS_PROT 4104f04d8f0SCatalin Marinas struct file; 4114f04d8f0SCatalin Marinas extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 4124f04d8f0SCatalin Marinas unsigned long size, pgprot_t vma_prot); 4134f04d8f0SCatalin Marinas 4144f04d8f0SCatalin Marinas #define pmd_none(pmd) (!pmd_val(pmd)) 4154f04d8f0SCatalin Marinas 416ab4db1f2SCatalin Marinas #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT)) 4174f04d8f0SCatalin Marinas 41836311607SMarc Zyngier #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 41936311607SMarc Zyngier PMD_TYPE_TABLE) 42036311607SMarc Zyngier #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 42136311607SMarc Zyngier PMD_TYPE_SECT) 42236311607SMarc Zyngier 423cac4b8cdSCatalin Marinas #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 424206a2a73SSteve Capper #define pud_sect(pud) (0) 425523d6e9fSzhichang.yuan #define pud_table(pud) (1) 426206a2a73SSteve Capper #else 427206a2a73SSteve Capper #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 428206a2a73SSteve Capper PUD_TYPE_SECT) 429523d6e9fSzhichang.yuan #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 430523d6e9fSzhichang.yuan PUD_TYPE_TABLE) 431206a2a73SSteve Capper #endif 43236311607SMarc Zyngier 4332330b7caSJun Yao extern pgd_t init_pg_dir[PTRS_PER_PGD]; 4342330b7caSJun Yao extern pgd_t init_pg_end[]; 4352330b7caSJun Yao extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 4362330b7caSJun Yao extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 4372330b7caSJun Yao extern pgd_t tramp_pg_dir[PTRS_PER_PGD]; 4382330b7caSJun Yao 4392330b7caSJun Yao extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 4402330b7caSJun Yao 4412330b7caSJun Yao static inline bool in_swapper_pgdir(void *addr) 4422330b7caSJun Yao { 4432330b7caSJun Yao return ((unsigned long)addr & PAGE_MASK) == 4442330b7caSJun Yao ((unsigned long)swapper_pg_dir & PAGE_MASK); 4452330b7caSJun Yao } 4462330b7caSJun Yao 4474f04d8f0SCatalin Marinas static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 4484f04d8f0SCatalin Marinas { 449e9ed821bSJames Morse #ifdef __PAGETABLE_PMD_FOLDED 450e9ed821bSJames Morse if (in_swapper_pgdir(pmdp)) { 4512330b7caSJun Yao set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 4522330b7caSJun Yao return; 4532330b7caSJun Yao } 454e9ed821bSJames Morse #endif /* __PAGETABLE_PMD_FOLDED */ 4552330b7caSJun Yao 45620a004e7SWill Deacon WRITE_ONCE(*pmdp, pmd); 4570795edafSWill Deacon 4580795edafSWill Deacon if (pmd_valid(pmd)) 45998f7685eSWill Deacon dsb(ishst); 4604f04d8f0SCatalin Marinas } 4614f04d8f0SCatalin Marinas 4624f04d8f0SCatalin Marinas static inline void pmd_clear(pmd_t *pmdp) 4634f04d8f0SCatalin Marinas { 4644f04d8f0SCatalin Marinas set_pmd(pmdp, __pmd(0)); 4654f04d8f0SCatalin Marinas } 4664f04d8f0SCatalin Marinas 467dca56dcaSMark Rutland static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 4684f04d8f0SCatalin Marinas { 46975387b92SKristina Martsenko return __pmd_to_phys(pmd); 4704f04d8f0SCatalin Marinas } 4714f04d8f0SCatalin Marinas 472053520f7SMark Rutland /* Find an entry in the third-level page table. */ 473053520f7SMark Rutland #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 474053520f7SMark Rutland 475f069fabaSWill Deacon #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 476dca56dcaSMark Rutland #define pte_offset_kernel(dir,addr) ((pte_t *)__va(pte_offset_phys((dir), (addr)))) 477053520f7SMark Rutland 478053520f7SMark Rutland #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 479053520f7SMark Rutland #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr)) 480053520f7SMark Rutland #define pte_unmap(pte) do { } while (0) 481053520f7SMark Rutland #define pte_unmap_nested(pte) do { } while (0) 482053520f7SMark Rutland 483961faac1SMark Rutland #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 484961faac1SMark Rutland #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 485961faac1SMark Rutland #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 486961faac1SMark Rutland 48775387b92SKristina Martsenko #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(__pmd_to_phys(pmd))) 4884f04d8f0SCatalin Marinas 4896533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 4906533945aSArd Biesheuvel #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 4916533945aSArd Biesheuvel 4924f04d8f0SCatalin Marinas /* 4934f04d8f0SCatalin Marinas * Conversion functions: convert a page and protection to a page entry, 4944f04d8f0SCatalin Marinas * and a page entry and page directory to the page they refer to. 4954f04d8f0SCatalin Marinas */ 4964f04d8f0SCatalin Marinas #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 4974f04d8f0SCatalin Marinas 4989f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 2 4994f04d8f0SCatalin Marinas 5007078db46SCatalin Marinas #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) 5017078db46SCatalin Marinas 5024f04d8f0SCatalin Marinas #define pud_none(pud) (!pud_val(pud)) 503ab4db1f2SCatalin Marinas #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT)) 504f02ab08aSPunit Agrawal #define pud_present(pud) pte_present(pud_pte(pud)) 5050795edafSWill Deacon #define pud_valid(pud) pte_valid(pud_pte(pud)) 5064f04d8f0SCatalin Marinas 5074f04d8f0SCatalin Marinas static inline void set_pud(pud_t *pudp, pud_t pud) 5084f04d8f0SCatalin Marinas { 509e9ed821bSJames Morse #ifdef __PAGETABLE_PUD_FOLDED 510e9ed821bSJames Morse if (in_swapper_pgdir(pudp)) { 5112330b7caSJun Yao set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 5122330b7caSJun Yao return; 5132330b7caSJun Yao } 514e9ed821bSJames Morse #endif /* __PAGETABLE_PUD_FOLDED */ 5152330b7caSJun Yao 51620a004e7SWill Deacon WRITE_ONCE(*pudp, pud); 5170795edafSWill Deacon 5180795edafSWill Deacon if (pud_valid(pud)) 51998f7685eSWill Deacon dsb(ishst); 5204f04d8f0SCatalin Marinas } 5214f04d8f0SCatalin Marinas 5224f04d8f0SCatalin Marinas static inline void pud_clear(pud_t *pudp) 5234f04d8f0SCatalin Marinas { 5244f04d8f0SCatalin Marinas set_pud(pudp, __pud(0)); 5254f04d8f0SCatalin Marinas } 5264f04d8f0SCatalin Marinas 527dca56dcaSMark Rutland static inline phys_addr_t pud_page_paddr(pud_t pud) 5284f04d8f0SCatalin Marinas { 52975387b92SKristina Martsenko return __pud_to_phys(pud); 5304f04d8f0SCatalin Marinas } 5314f04d8f0SCatalin Marinas 5327078db46SCatalin Marinas /* Find an entry in the second-level page table. */ 5337078db46SCatalin Marinas #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) 5347078db46SCatalin Marinas 53520a004e7SWill Deacon #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 536dca56dcaSMark Rutland #define pmd_offset(dir, addr) ((pmd_t *)__va(pmd_offset_phys((dir), (addr)))) 5377078db46SCatalin Marinas 538961faac1SMark Rutland #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 539961faac1SMark Rutland #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 540961faac1SMark Rutland #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 5414f04d8f0SCatalin Marinas 54275387b92SKristina Martsenko #define pud_page(pud) pfn_to_page(__phys_to_pfn(__pud_to_phys(pud))) 54329e56940SSteve Capper 5446533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 5456533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 5466533945aSArd Biesheuvel 547dca56dcaSMark Rutland #else 548dca56dcaSMark Rutland 549dca56dcaSMark Rutland #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 550dca56dcaSMark Rutland 551961faac1SMark Rutland /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 552961faac1SMark Rutland #define pmd_set_fixmap(addr) NULL 553961faac1SMark Rutland #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 554961faac1SMark Rutland #define pmd_clear_fixmap() 555961faac1SMark Rutland 5566533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 5576533945aSArd Biesheuvel 5589f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 5594f04d8f0SCatalin Marinas 5609f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 3 561c79b954bSJungseok Lee 5627078db46SCatalin Marinas #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud)) 5637078db46SCatalin Marinas 564c79b954bSJungseok Lee #define pgd_none(pgd) (!pgd_val(pgd)) 565c79b954bSJungseok Lee #define pgd_bad(pgd) (!(pgd_val(pgd) & 2)) 566c79b954bSJungseok Lee #define pgd_present(pgd) (pgd_val(pgd)) 567c79b954bSJungseok Lee 568c79b954bSJungseok Lee static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 569c79b954bSJungseok Lee { 5702330b7caSJun Yao if (in_swapper_pgdir(pgdp)) { 5712330b7caSJun Yao set_swapper_pgd(pgdp, pgd); 5722330b7caSJun Yao return; 5732330b7caSJun Yao } 5742330b7caSJun Yao 57520a004e7SWill Deacon WRITE_ONCE(*pgdp, pgd); 576c79b954bSJungseok Lee dsb(ishst); 577c79b954bSJungseok Lee } 578c79b954bSJungseok Lee 579c79b954bSJungseok Lee static inline void pgd_clear(pgd_t *pgdp) 580c79b954bSJungseok Lee { 581c79b954bSJungseok Lee set_pgd(pgdp, __pgd(0)); 582c79b954bSJungseok Lee } 583c79b954bSJungseok Lee 584dca56dcaSMark Rutland static inline phys_addr_t pgd_page_paddr(pgd_t pgd) 585c79b954bSJungseok Lee { 58675387b92SKristina Martsenko return __pgd_to_phys(pgd); 587c79b954bSJungseok Lee } 588c79b954bSJungseok Lee 5897078db46SCatalin Marinas /* Find an entry in the frst-level page table. */ 5907078db46SCatalin Marinas #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 5917078db46SCatalin Marinas 59220a004e7SWill Deacon #define pud_offset_phys(dir, addr) (pgd_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t)) 593dca56dcaSMark Rutland #define pud_offset(dir, addr) ((pud_t *)__va(pud_offset_phys((dir), (addr)))) 5947078db46SCatalin Marinas 595961faac1SMark Rutland #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) 596961faac1SMark Rutland #define pud_set_fixmap_offset(pgd, addr) pud_set_fixmap(pud_offset_phys(pgd, addr)) 597961faac1SMark Rutland #define pud_clear_fixmap() clear_fixmap(FIX_PUD) 598c79b954bSJungseok Lee 59975387b92SKristina Martsenko #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd))) 6005d96e0cbSJungseok Lee 6016533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 6026533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) 6036533945aSArd Biesheuvel 604dca56dcaSMark Rutland #else 605dca56dcaSMark Rutland 606dca56dcaSMark Rutland #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) 607dca56dcaSMark Rutland 608961faac1SMark Rutland /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 609961faac1SMark Rutland #define pud_set_fixmap(addr) NULL 610961faac1SMark Rutland #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 611961faac1SMark Rutland #define pud_clear_fixmap() 612961faac1SMark Rutland 6136533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 6146533945aSArd Biesheuvel 6159f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 616c79b954bSJungseok Lee 6177078db46SCatalin Marinas #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) 6187078db46SCatalin Marinas 6194f04d8f0SCatalin Marinas /* to find an entry in a page-table-directory */ 6204f04d8f0SCatalin Marinas #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 6214f04d8f0SCatalin Marinas 622dca56dcaSMark Rutland #define pgd_offset_raw(pgd, addr) ((pgd) + pgd_index(addr)) 623dca56dcaSMark Rutland 624dca56dcaSMark Rutland #define pgd_offset(mm, addr) (pgd_offset_raw((mm)->pgd, (addr))) 6254f04d8f0SCatalin Marinas 6264f04d8f0SCatalin Marinas /* to find an entry in a kernel page-table-directory */ 6274f04d8f0SCatalin Marinas #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) 6284f04d8f0SCatalin Marinas 629961faac1SMark Rutland #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 630961faac1SMark Rutland #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 631961faac1SMark Rutland 6324f04d8f0SCatalin Marinas static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 6334f04d8f0SCatalin Marinas { 634a6fadf7eSWill Deacon const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 6351a541b4eSSteve Capper PTE_PROT_NONE | PTE_VALID | PTE_WRITE; 6362f4b829cSCatalin Marinas /* preserve the hardware dirty information */ 6372f4b829cSCatalin Marinas if (pte_hw_dirty(pte)) 63862d96c71SCatalin Marinas pte = pte_mkdirty(pte); 6394f04d8f0SCatalin Marinas pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 6404f04d8f0SCatalin Marinas return pte; 6414f04d8f0SCatalin Marinas } 6424f04d8f0SCatalin Marinas 6439c7e535fSSteve Capper static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 6449c7e535fSSteve Capper { 6459c7e535fSSteve Capper return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 6469c7e535fSSteve Capper } 6479c7e535fSSteve Capper 64866dbd6e6SCatalin Marinas #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 64966dbd6e6SCatalin Marinas extern int ptep_set_access_flags(struct vm_area_struct *vma, 65066dbd6e6SCatalin Marinas unsigned long address, pte_t *ptep, 65166dbd6e6SCatalin Marinas pte_t entry, int dirty); 65266dbd6e6SCatalin Marinas 653282aa705SCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 654282aa705SCatalin Marinas #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 655282aa705SCatalin Marinas static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 656282aa705SCatalin Marinas unsigned long address, pmd_t *pmdp, 657282aa705SCatalin Marinas pmd_t entry, int dirty) 658282aa705SCatalin Marinas { 659282aa705SCatalin Marinas return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 660282aa705SCatalin Marinas } 661282aa705SCatalin Marinas #endif 662282aa705SCatalin Marinas 6632f4b829cSCatalin Marinas /* 6642f4b829cSCatalin Marinas * Atomic pte/pmd modifications. 6652f4b829cSCatalin Marinas */ 6662f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 66706485053SCatalin Marinas static inline int __ptep_test_and_clear_young(pte_t *ptep) 6682f4b829cSCatalin Marinas { 6693bbf7157SCatalin Marinas pte_t old_pte, pte; 6702f4b829cSCatalin Marinas 6713bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 6723bbf7157SCatalin Marinas do { 6733bbf7157SCatalin Marinas old_pte = pte; 6743bbf7157SCatalin Marinas pte = pte_mkold(pte); 6753bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 6763bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 6773bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 6782f4b829cSCatalin Marinas 6793bbf7157SCatalin Marinas return pte_young(pte); 6802f4b829cSCatalin Marinas } 6812f4b829cSCatalin Marinas 68206485053SCatalin Marinas static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 68306485053SCatalin Marinas unsigned long address, 68406485053SCatalin Marinas pte_t *ptep) 68506485053SCatalin Marinas { 68606485053SCatalin Marinas return __ptep_test_and_clear_young(ptep); 68706485053SCatalin Marinas } 68806485053SCatalin Marinas 689*3403e56bSAlex Van Brunt #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 690*3403e56bSAlex Van Brunt static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 691*3403e56bSAlex Van Brunt unsigned long address, pte_t *ptep) 692*3403e56bSAlex Van Brunt { 693*3403e56bSAlex Van Brunt int young = ptep_test_and_clear_young(vma, address, ptep); 694*3403e56bSAlex Van Brunt 695*3403e56bSAlex Van Brunt if (young) { 696*3403e56bSAlex Van Brunt /* 697*3403e56bSAlex Van Brunt * We can elide the trailing DSB here since the worst that can 698*3403e56bSAlex Van Brunt * happen is that a CPU continues to use the young entry in its 699*3403e56bSAlex Van Brunt * TLB and we mistakenly reclaim the associated page. The 700*3403e56bSAlex Van Brunt * window for such an event is bounded by the next 701*3403e56bSAlex Van Brunt * context-switch, which provides a DSB to complete the TLB 702*3403e56bSAlex Van Brunt * invalidation. 703*3403e56bSAlex Van Brunt */ 704*3403e56bSAlex Van Brunt flush_tlb_page_nosync(vma, address); 705*3403e56bSAlex Van Brunt } 706*3403e56bSAlex Van Brunt 707*3403e56bSAlex Van Brunt return young; 708*3403e56bSAlex Van Brunt } 709*3403e56bSAlex Van Brunt 7102f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 7112f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 7122f4b829cSCatalin Marinas static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 7132f4b829cSCatalin Marinas unsigned long address, 7142f4b829cSCatalin Marinas pmd_t *pmdp) 7152f4b829cSCatalin Marinas { 7162f4b829cSCatalin Marinas return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 7172f4b829cSCatalin Marinas } 7182f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 7192f4b829cSCatalin Marinas 7202f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 7212f4b829cSCatalin Marinas static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 7222f4b829cSCatalin Marinas unsigned long address, pte_t *ptep) 7232f4b829cSCatalin Marinas { 7243bbf7157SCatalin Marinas return __pte(xchg_relaxed(&pte_val(*ptep), 0)); 7252f4b829cSCatalin Marinas } 7262f4b829cSCatalin Marinas 7272f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 728911f56eeSCatalin Marinas #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 729911f56eeSCatalin Marinas static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 7302f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 7312f4b829cSCatalin Marinas { 7322f4b829cSCatalin Marinas return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); 7332f4b829cSCatalin Marinas } 7342f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 7352f4b829cSCatalin Marinas 7362f4b829cSCatalin Marinas /* 7378781bcbcSSteve Capper * ptep_set_wrprotect - mark read-only while trasferring potential hardware 7388781bcbcSSteve Capper * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 7392f4b829cSCatalin Marinas */ 7402f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_SET_WRPROTECT 7412f4b829cSCatalin Marinas static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 7422f4b829cSCatalin Marinas { 7433bbf7157SCatalin Marinas pte_t old_pte, pte; 7442f4b829cSCatalin Marinas 7453bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 7463bbf7157SCatalin Marinas do { 7473bbf7157SCatalin Marinas old_pte = pte; 7488781bcbcSSteve Capper /* 7498781bcbcSSteve Capper * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 7508781bcbcSSteve Capper * clear), set the PTE_DIRTY bit. 7518781bcbcSSteve Capper */ 7528781bcbcSSteve Capper if (pte_hw_dirty(pte)) 7538781bcbcSSteve Capper pte = pte_mkdirty(pte); 7543bbf7157SCatalin Marinas pte = pte_wrprotect(pte); 7553bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 7563bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 7573bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 7582f4b829cSCatalin Marinas } 7592f4b829cSCatalin Marinas 7602f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 7612f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_SET_WRPROTECT 7622f4b829cSCatalin Marinas static inline void pmdp_set_wrprotect(struct mm_struct *mm, 7632f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 7642f4b829cSCatalin Marinas { 7652f4b829cSCatalin Marinas ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 7662f4b829cSCatalin Marinas } 7671d78a62cSCatalin Marinas 7681d78a62cSCatalin Marinas #define pmdp_establish pmdp_establish 7691d78a62cSCatalin Marinas static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 7701d78a62cSCatalin Marinas unsigned long address, pmd_t *pmdp, pmd_t pmd) 7711d78a62cSCatalin Marinas { 7721d78a62cSCatalin Marinas return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 7731d78a62cSCatalin Marinas } 7742f4b829cSCatalin Marinas #endif 7752f4b829cSCatalin Marinas 7764f04d8f0SCatalin Marinas /* 7774f04d8f0SCatalin Marinas * Encode and decode a swap entry: 7783676f9efSCatalin Marinas * bits 0-1: present (must be zero) 7799b3e661eSKirill A. Shutemov * bits 2-7: swap type 7809b3e661eSKirill A. Shutemov * bits 8-57: swap offset 781fdc69e7dSCatalin Marinas * bit 58: PTE_PROT_NONE (must be zero) 7824f04d8f0SCatalin Marinas */ 7839b3e661eSKirill A. Shutemov #define __SWP_TYPE_SHIFT 2 7844f04d8f0SCatalin Marinas #define __SWP_TYPE_BITS 6 7859b3e661eSKirill A. Shutemov #define __SWP_OFFSET_BITS 50 7864f04d8f0SCatalin Marinas #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 7874f04d8f0SCatalin Marinas #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 7883676f9efSCatalin Marinas #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 7894f04d8f0SCatalin Marinas 7904f04d8f0SCatalin Marinas #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 7913676f9efSCatalin Marinas #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 7924f04d8f0SCatalin Marinas #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 7934f04d8f0SCatalin Marinas 7944f04d8f0SCatalin Marinas #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 7954f04d8f0SCatalin Marinas #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 7964f04d8f0SCatalin Marinas 7974f04d8f0SCatalin Marinas /* 7984f04d8f0SCatalin Marinas * Ensure that there are not more swap files than can be encoded in the kernel 799aad9061bSGeert Uytterhoeven * PTEs. 8004f04d8f0SCatalin Marinas */ 8014f04d8f0SCatalin Marinas #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 8024f04d8f0SCatalin Marinas 8034f04d8f0SCatalin Marinas extern int kern_addr_valid(unsigned long addr); 8044f04d8f0SCatalin Marinas 8054f04d8f0SCatalin Marinas #include <asm-generic/pgtable.h> 8064f04d8f0SCatalin Marinas 80739b5be9bSWill Deacon void pgd_cache_init(void); 80839b5be9bSWill Deacon #define pgtable_cache_init pgd_cache_init 8094f04d8f0SCatalin Marinas 810cba3574fSWill Deacon /* 811cba3574fSWill Deacon * On AArch64, the cache coherency is handled via the set_pte_at() function. 812cba3574fSWill Deacon */ 813cba3574fSWill Deacon static inline void update_mmu_cache(struct vm_area_struct *vma, 814cba3574fSWill Deacon unsigned long addr, pte_t *ptep) 815cba3574fSWill Deacon { 816cba3574fSWill Deacon /* 817120798d2SWill Deacon * We don't do anything here, so there's a very small chance of 818120798d2SWill Deacon * us retaking a user fault which we just fixed up. The alternative 819120798d2SWill Deacon * is doing a dsb(ishst), but that penalises the fastpath. 820cba3574fSWill Deacon */ 821cba3574fSWill Deacon } 822cba3574fSWill Deacon 823cba3574fSWill Deacon #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 824cba3574fSWill Deacon 82503875ad5Syalin wang #define kc_vaddr_to_offset(v) ((v) & ~VA_START) 82603875ad5Syalin wang #define kc_offset_to_vaddr(o) ((o) | VA_START) 8277db743c6SCatalin Marinas 828529c4b05SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 829529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 830529c4b05SKristina Martsenko #else 831529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (addr) 832529c4b05SKristina Martsenko #endif 833529c4b05SKristina Martsenko 8344f04d8f0SCatalin Marinas #endif /* !__ASSEMBLY__ */ 8354f04d8f0SCatalin Marinas 8364f04d8f0SCatalin Marinas #endif /* __ASM_PGTABLE_H */ 837