1caab277bSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 24f04d8f0SCatalin Marinas /* 34f04d8f0SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 44f04d8f0SCatalin Marinas */ 54f04d8f0SCatalin Marinas #ifndef __ASM_PGTABLE_H 64f04d8f0SCatalin Marinas #define __ASM_PGTABLE_H 74f04d8f0SCatalin Marinas 82f4b829cSCatalin Marinas #include <asm/bug.h> 94f04d8f0SCatalin Marinas #include <asm/proc-fns.h> 104f04d8f0SCatalin Marinas 114f04d8f0SCatalin Marinas #include <asm/memory.h> 1234bfeea4SCatalin Marinas #include <asm/mte.h> 134f04d8f0SCatalin Marinas #include <asm/pgtable-hwdef.h> 143eca86e7SMark Rutland #include <asm/pgtable-prot.h> 153403e56bSAlex Van Brunt #include <asm/tlbflush.h> 164f04d8f0SCatalin Marinas 174f04d8f0SCatalin Marinas /* 183e1907d5SArd Biesheuvel * VMALLOC range. 1908375198SCatalin Marinas * 20f9040773SArd Biesheuvel * VMALLOC_START: beginning of the kernel vmalloc space 21a5315819SMark Brown * VMALLOC_END: extends to the available space below vmemmap, PCI I/O space 223e1907d5SArd Biesheuvel * and fixed mappings 234f04d8f0SCatalin Marinas */ 24f9040773SArd Biesheuvel #define VMALLOC_START (MODULES_END) 259ad7c6d5SArd Biesheuvel #define VMALLOC_END (VMEMMAP_START - SZ_256M) 264f04d8f0SCatalin Marinas 277bc1a0f9SArd Biesheuvel #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 287bc1a0f9SArd Biesheuvel 294f04d8f0SCatalin Marinas #ifndef __ASSEMBLY__ 302f4b829cSCatalin Marinas 313bbf7157SCatalin Marinas #include <asm/cmpxchg.h> 32961faac1SMark Rutland #include <asm/fixmap.h> 332f4b829cSCatalin Marinas #include <linux/mmdebug.h> 3486c9e812SWill Deacon #include <linux/mm_types.h> 3586c9e812SWill Deacon #include <linux/sched.h> 3642b25471SKefeng Wang #include <linux/page_table_check.h> 372f4b829cSCatalin Marinas 38a7ac1cfaSZhenyu Ye #ifdef CONFIG_TRANSPARENT_HUGEPAGE 39a7ac1cfaSZhenyu Ye #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 40a7ac1cfaSZhenyu Ye 41a7ac1cfaSZhenyu Ye /* Set stride and tlb_level in flush_*_tlb_range */ 42a7ac1cfaSZhenyu Ye #define flush_pmd_tlb_range(vma, addr, end) \ 43a7ac1cfaSZhenyu Ye __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) 44a7ac1cfaSZhenyu Ye #define flush_pud_tlb_range(vma, addr, end) \ 45a7ac1cfaSZhenyu Ye __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) 46a7ac1cfaSZhenyu Ye #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 47a7ac1cfaSZhenyu Ye 48d0637c50SBarry Song static inline bool arch_thp_swp_supported(void) 49d0637c50SBarry Song { 50d0637c50SBarry Song return !system_supports_mte(); 51d0637c50SBarry Song } 52d0637c50SBarry Song #define arch_thp_swp_supported arch_thp_swp_supported 53d0637c50SBarry Song 544f04d8f0SCatalin Marinas /* 556a1bdb17SWill Deacon * Outside of a few very special situations (e.g. hibernation), we always 566a1bdb17SWill Deacon * use broadcast TLB invalidation instructions, therefore a spurious page 576a1bdb17SWill Deacon * fault on one CPU which has been handled concurrently by another CPU 586a1bdb17SWill Deacon * does not need to perform additional invalidation. 596a1bdb17SWill Deacon */ 6099c29133SGerald Schaefer #define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0) 616a1bdb17SWill Deacon 626a1bdb17SWill Deacon /* 634f04d8f0SCatalin Marinas * ZERO_PAGE is a global shared page that is always zero: used 644f04d8f0SCatalin Marinas * for zero-mapped memory areas etc.. 654f04d8f0SCatalin Marinas */ 665227cfa7SMark Rutland extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 672077be67SLaura Abbott #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 684f04d8f0SCatalin Marinas 692cf660ebSGavin Shan #define pte_ERROR(e) \ 702cf660ebSGavin Shan pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) 717078db46SCatalin Marinas 7275387b92SKristina Martsenko /* 7375387b92SKristina Martsenko * Macros to convert between a physical address and its placement in a 7475387b92SKristina Martsenko * page table entry, taking care of 52-bit addresses. 7575387b92SKristina Martsenko */ 7675387b92SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 77c7c386fbSArnd Bergmann static inline phys_addr_t __pte_to_phys(pte_t pte) 78c7c386fbSArnd Bergmann { 79c7c386fbSArnd Bergmann return (pte_val(pte) & PTE_ADDR_LOW) | 80a4ee2861SAnshuman Khandual ((pte_val(pte) & PTE_ADDR_HIGH) << PTE_ADDR_HIGH_SHIFT); 81c7c386fbSArnd Bergmann } 82c7c386fbSArnd Bergmann static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 83c7c386fbSArnd Bergmann { 84a4ee2861SAnshuman Khandual return (phys | (phys >> PTE_ADDR_HIGH_SHIFT)) & PTE_ADDR_MASK; 85c7c386fbSArnd Bergmann } 8675387b92SKristina Martsenko #else 8775387b92SKristina Martsenko #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK) 8875387b92SKristina Martsenko #define __phys_to_pte_val(phys) (phys) 8975387b92SKristina Martsenko #endif 904f04d8f0SCatalin Marinas 9175387b92SKristina Martsenko #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 9275387b92SKristina Martsenko #define pfn_pte(pfn,prot) \ 9375387b92SKristina Martsenko __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 944f04d8f0SCatalin Marinas 954f04d8f0SCatalin Marinas #define pte_none(pte) (!pte_val(pte)) 964f04d8f0SCatalin Marinas #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 974f04d8f0SCatalin Marinas #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 987078db46SCatalin Marinas 994f04d8f0SCatalin Marinas /* 1004f04d8f0SCatalin Marinas * The following only work if pte_present(). Undefined behaviour otherwise. 1014f04d8f0SCatalin Marinas */ 10284fe6826SSteve Capper #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 10384fe6826SSteve Capper #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 10484fe6826SSteve Capper #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 10584fe6826SSteve Capper #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 10642b25471SKefeng Wang #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) 107ec663d96SCatalin Marinas #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 10893ef666aSJeremy Linton #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 10973b20c84SRobin Murphy #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 11034bfeea4SCatalin Marinas #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \ 11134bfeea4SCatalin Marinas PTE_ATTRINDX(MT_NORMAL_TAGGED)) 1124f04d8f0SCatalin Marinas 113d27cfa1fSArd Biesheuvel #define pte_cont_addr_end(addr, end) \ 114d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 115d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 116d27cfa1fSArd Biesheuvel }) 117d27cfa1fSArd Biesheuvel 118d27cfa1fSArd Biesheuvel #define pmd_cont_addr_end(addr, end) \ 119d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 120d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 121d27cfa1fSArd Biesheuvel }) 122d27cfa1fSArd Biesheuvel 123b847415cSCatalin Marinas #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) 1242f4b829cSCatalin Marinas #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 1252f4b829cSCatalin Marinas #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 1262f4b829cSCatalin Marinas 127766ffb69SWill Deacon #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 12818107f8aSVladimir Murzin /* 12918107f8aSVladimir Murzin * Execute-only user mappings do not have the PTE_USER bit set. All valid 13018107f8aSVladimir Murzin * kernel mappings have the PTE_UXN bit set. 13118107f8aSVladimir Murzin */ 132ec663d96SCatalin Marinas #define pte_valid_not_user(pte) \ 13318107f8aSVladimir Murzin ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 13476c714beSWill Deacon /* 13576c714beSWill Deacon * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 13676c714beSWill Deacon * so that we don't erroneously return false for pages that have been 13776c714beSWill Deacon * remapped as PROT_NONE but are yet to be flushed from the TLB. 13807509e10SWill Deacon * Note that we can't make any assumptions based on the state of the access 13907509e10SWill Deacon * flag, since ptep_clear_flush_young() elides a DSB when invalidating the 14007509e10SWill Deacon * TLB. 14176c714beSWill Deacon */ 14276c714beSWill Deacon #define pte_accessible(mm, pte) \ 14307509e10SWill Deacon (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) 1444f04d8f0SCatalin Marinas 1456218f96cSCatalin Marinas /* 14618107f8aSVladimir Murzin * p??_access_permitted() is true for valid user mappings (PTE_USER 14718107f8aSVladimir Murzin * bit set, subject to the write permission check). For execute-only 14818107f8aSVladimir Murzin * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits 14918107f8aSVladimir Murzin * not set) must return false. PROT_NONE mappings do not have the 15018107f8aSVladimir Murzin * PTE_VALID bit set. 1516218f96cSCatalin Marinas */ 1526218f96cSCatalin Marinas #define pte_access_permitted(pte, write) \ 15318107f8aSVladimir Murzin (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte))) 1546218f96cSCatalin Marinas #define pmd_access_permitted(pmd, write) \ 1556218f96cSCatalin Marinas (pte_access_permitted(pmd_pte(pmd), (write))) 1566218f96cSCatalin Marinas #define pud_access_permitted(pud, write) \ 1576218f96cSCatalin Marinas (pte_access_permitted(pud_pte(pud), (write))) 1586218f96cSCatalin Marinas 159b6d4f280SLaura Abbott static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 160b6d4f280SLaura Abbott { 161b6d4f280SLaura Abbott pte_val(pte) &= ~pgprot_val(prot); 162b6d4f280SLaura Abbott return pte; 163b6d4f280SLaura Abbott } 164b6d4f280SLaura Abbott 165b6d4f280SLaura Abbott static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 166b6d4f280SLaura Abbott { 167b6d4f280SLaura Abbott pte_val(pte) |= pgprot_val(prot); 168b6d4f280SLaura Abbott return pte; 169b6d4f280SLaura Abbott } 170b6d4f280SLaura Abbott 171b65399f6SAnshuman Khandual static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 172b65399f6SAnshuman Khandual { 173b65399f6SAnshuman Khandual pmd_val(pmd) &= ~pgprot_val(prot); 174b65399f6SAnshuman Khandual return pmd; 175b65399f6SAnshuman Khandual } 176b65399f6SAnshuman Khandual 177b65399f6SAnshuman Khandual static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 178b65399f6SAnshuman Khandual { 179b65399f6SAnshuman Khandual pmd_val(pmd) |= pgprot_val(prot); 180b65399f6SAnshuman Khandual return pmd; 181b65399f6SAnshuman Khandual } 182b65399f6SAnshuman Khandual 183*2f0584f3SRick Edgecombe static inline pte_t pte_mkwrite_novma(pte_t pte) 18444b6dfc5SSteve Capper { 18573e86cb0SCatalin Marinas pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 18673e86cb0SCatalin Marinas pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 18773e86cb0SCatalin Marinas return pte; 18844b6dfc5SSteve Capper } 18944b6dfc5SSteve Capper 19044b6dfc5SSteve Capper static inline pte_t pte_mkclean(pte_t pte) 19144b6dfc5SSteve Capper { 1928781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 1938781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 1948781bcbcSSteve Capper 1958781bcbcSSteve Capper return pte; 19644b6dfc5SSteve Capper } 19744b6dfc5SSteve Capper 19844b6dfc5SSteve Capper static inline pte_t pte_mkdirty(pte_t pte) 19944b6dfc5SSteve Capper { 2008781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 2018781bcbcSSteve Capper 2028781bcbcSSteve Capper if (pte_write(pte)) 2038781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 2048781bcbcSSteve Capper 2058781bcbcSSteve Capper return pte; 20644b6dfc5SSteve Capper } 20744b6dfc5SSteve Capper 208ff1712f9SWill Deacon static inline pte_t pte_wrprotect(pte_t pte) 209ff1712f9SWill Deacon { 210ff1712f9SWill Deacon /* 211ff1712f9SWill Deacon * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 212ff1712f9SWill Deacon * clear), set the PTE_DIRTY bit. 213ff1712f9SWill Deacon */ 214ff1712f9SWill Deacon if (pte_hw_dirty(pte)) 215ff1712f9SWill Deacon pte = pte_mkdirty(pte); 216ff1712f9SWill Deacon 217ff1712f9SWill Deacon pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 218ff1712f9SWill Deacon pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 219ff1712f9SWill Deacon return pte; 220ff1712f9SWill Deacon } 221ff1712f9SWill Deacon 22244b6dfc5SSteve Capper static inline pte_t pte_mkold(pte_t pte) 22344b6dfc5SSteve Capper { 224b6d4f280SLaura Abbott return clear_pte_bit(pte, __pgprot(PTE_AF)); 22544b6dfc5SSteve Capper } 22644b6dfc5SSteve Capper 22744b6dfc5SSteve Capper static inline pte_t pte_mkyoung(pte_t pte) 22844b6dfc5SSteve Capper { 229b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_AF)); 23044b6dfc5SSteve Capper } 23144b6dfc5SSteve Capper 23244b6dfc5SSteve Capper static inline pte_t pte_mkspecial(pte_t pte) 23344b6dfc5SSteve Capper { 234b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 23544b6dfc5SSteve Capper } 2364f04d8f0SCatalin Marinas 23793ef666aSJeremy Linton static inline pte_t pte_mkcont(pte_t pte) 23893ef666aSJeremy Linton { 23966b3923aSDavid Woods pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 24066b3923aSDavid Woods return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 24193ef666aSJeremy Linton } 24293ef666aSJeremy Linton 24393ef666aSJeremy Linton static inline pte_t pte_mknoncont(pte_t pte) 24493ef666aSJeremy Linton { 24593ef666aSJeremy Linton return clear_pte_bit(pte, __pgprot(PTE_CONT)); 24693ef666aSJeremy Linton } 24793ef666aSJeremy Linton 2485ebe3a44SJames Morse static inline pte_t pte_mkpresent(pte_t pte) 2495ebe3a44SJames Morse { 2505ebe3a44SJames Morse return set_pte_bit(pte, __pgprot(PTE_VALID)); 2515ebe3a44SJames Morse } 2525ebe3a44SJames Morse 25366b3923aSDavid Woods static inline pmd_t pmd_mkcont(pmd_t pmd) 25466b3923aSDavid Woods { 25566b3923aSDavid Woods return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 25666b3923aSDavid Woods } 25766b3923aSDavid Woods 25873b20c84SRobin Murphy static inline pte_t pte_mkdevmap(pte_t pte) 25973b20c84SRobin Murphy { 26030e23538SJia He return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 26173b20c84SRobin Murphy } 26273b20c84SRobin Murphy 2634f04d8f0SCatalin Marinas static inline void set_pte(pte_t *ptep, pte_t pte) 2644f04d8f0SCatalin Marinas { 26520a004e7SWill Deacon WRITE_ONCE(*ptep, pte); 2667f0b1bf0SCatalin Marinas 2677f0b1bf0SCatalin Marinas /* 2687f0b1bf0SCatalin Marinas * Only if the new pte is valid and kernel, otherwise TLB maintenance 2697f0b1bf0SCatalin Marinas * or update_mmu_cache() have the necessary barriers. 2707f0b1bf0SCatalin Marinas */ 271d0b7a302SWill Deacon if (pte_valid_not_user(pte)) { 2727f0b1bf0SCatalin Marinas dsb(ishst); 273d0b7a302SWill Deacon isb(); 274d0b7a302SWill Deacon } 2754f04d8f0SCatalin Marinas } 2764f04d8f0SCatalin Marinas 277907e21c1SShaokun Zhang extern void __sync_icache_dcache(pte_t pteval); 278004fc58fSAnshuman Khandual bool pgattr_change_is_safe(u64 old, u64 new); 2794f04d8f0SCatalin Marinas 2802f4b829cSCatalin Marinas /* 2812f4b829cSCatalin Marinas * PTE bits configuration in the presence of hardware Dirty Bit Management 2822f4b829cSCatalin Marinas * (PTE_WRITE == PTE_DBM): 2832f4b829cSCatalin Marinas * 2842f4b829cSCatalin Marinas * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 2852f4b829cSCatalin Marinas * 0 0 | 1 0 0 2862f4b829cSCatalin Marinas * 0 1 | 1 1 0 2872f4b829cSCatalin Marinas * 1 0 | 1 0 1 2882f4b829cSCatalin Marinas * 1 1 | 0 1 x 2892f4b829cSCatalin Marinas * 2902f4b829cSCatalin Marinas * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 2912f4b829cSCatalin Marinas * the page fault mechanism. Checking the dirty status of a pte becomes: 2922f4b829cSCatalin Marinas * 293b847415cSCatalin Marinas * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 2942f4b829cSCatalin Marinas */ 2959b604722SMark Rutland 296004fc58fSAnshuman Khandual static inline void __check_safe_pte_update(struct mm_struct *mm, pte_t *ptep, 2979b604722SMark Rutland pte_t pte) 2984f04d8f0SCatalin Marinas { 29920a004e7SWill Deacon pte_t old_pte; 30020a004e7SWill Deacon 3019b604722SMark Rutland if (!IS_ENABLED(CONFIG_DEBUG_VM)) 3029b604722SMark Rutland return; 3039b604722SMark Rutland 3049b604722SMark Rutland old_pte = READ_ONCE(*ptep); 3059b604722SMark Rutland 3069b604722SMark Rutland if (!pte_valid(old_pte) || !pte_valid(pte)) 3079b604722SMark Rutland return; 3089b604722SMark Rutland if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 3099b604722SMark Rutland return; 31002522463SWill Deacon 3112f4b829cSCatalin Marinas /* 3129b604722SMark Rutland * Check for potential race with hardware updates of the pte 3139b604722SMark Rutland * (ptep_set_access_flags safely changes valid ptes without going 3149b604722SMark Rutland * through an invalid entry). 3152f4b829cSCatalin Marinas */ 31682d34008SCatalin Marinas VM_WARN_ONCE(!pte_young(pte), 31782d34008SCatalin Marinas "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 31820a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 31920a004e7SWill Deacon VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 32082d34008SCatalin Marinas "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 32120a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 322004fc58fSAnshuman Khandual VM_WARN_ONCE(!pgattr_change_is_safe(pte_val(old_pte), pte_val(pte)), 323004fc58fSAnshuman Khandual "%s: unsafe attribute change: 0x%016llx -> 0x%016llx", 324004fc58fSAnshuman Khandual __func__, pte_val(old_pte), pte_val(pte)); 3252f4b829cSCatalin Marinas } 3262f4b829cSCatalin Marinas 32742b25471SKefeng Wang static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 3289b604722SMark Rutland pte_t *ptep, pte_t pte) 3299b604722SMark Rutland { 3309b604722SMark Rutland if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 3319b604722SMark Rutland __sync_icache_dcache(pte); 3329b604722SMark Rutland 33369e3b846SSteven Price /* 33469e3b846SSteven Price * If the PTE would provide user space access to the tags associated 33569e3b846SSteven Price * with it then ensure that the MTE tags are synchronised. Although 33669e3b846SSteven Price * pte_access_permitted() returns false for exec only mappings, they 33769e3b846SSteven Price * don't expose tags (instruction fetches don't check tags). 33869e3b846SSteven Price */ 33969e3b846SSteven Price if (system_supports_mte() && pte_access_permitted(pte, false) && 34069e3b846SSteven Price !pte_special(pte)) { 34169e3b846SSteven Price pte_t old_pte = READ_ONCE(*ptep); 34269e3b846SSteven Price /* 34369e3b846SSteven Price * We only need to synchronise if the new PTE has tags enabled 34469e3b846SSteven Price * or if swapping in (in which case another mapping may have 34569e3b846SSteven Price * set tags in the past even if this PTE isn't tagged). 34669e3b846SSteven Price * (!pte_none() && !pte_present()) is an open coded version of 34769e3b846SSteven Price * is_swap_pte() 34869e3b846SSteven Price */ 34969e3b846SSteven Price if (pte_tagged(pte) || (!pte_none(old_pte) && !pte_present(old_pte))) 35069e3b846SSteven Price mte_sync_tags(old_pte, pte); 35169e3b846SSteven Price } 35234bfeea4SCatalin Marinas 353004fc58fSAnshuman Khandual __check_safe_pte_update(mm, ptep, pte); 3549b604722SMark Rutland 3554f04d8f0SCatalin Marinas set_pte(ptep, pte); 3564f04d8f0SCatalin Marinas } 3574f04d8f0SCatalin Marinas 35842b25471SKefeng Wang static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 35942b25471SKefeng Wang pte_t *ptep, pte_t pte) 36042b25471SKefeng Wang { 36142b25471SKefeng Wang page_table_check_pte_set(mm, addr, ptep, pte); 36242b25471SKefeng Wang return __set_pte_at(mm, addr, ptep, pte); 36342b25471SKefeng Wang } 36442b25471SKefeng Wang 3654f04d8f0SCatalin Marinas /* 3664f04d8f0SCatalin Marinas * Huge pte definitions. 3674f04d8f0SCatalin Marinas */ 368084bd298SSteve Capper #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 369084bd298SSteve Capper 370084bd298SSteve Capper /* 371084bd298SSteve Capper * Hugetlb definitions. 372084bd298SSteve Capper */ 37366b3923aSDavid Woods #define HUGE_MAX_HSTATE 4 374084bd298SSteve Capper #define HPAGE_SHIFT PMD_SHIFT 375084bd298SSteve Capper #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 376084bd298SSteve Capper #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 377084bd298SSteve Capper #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 3784f04d8f0SCatalin Marinas 37975387b92SKristina Martsenko static inline pte_t pgd_pte(pgd_t pgd) 38075387b92SKristina Martsenko { 38175387b92SKristina Martsenko return __pte(pgd_val(pgd)); 38275387b92SKristina Martsenko } 38375387b92SKristina Martsenko 384e9f63768SMike Rapoport static inline pte_t p4d_pte(p4d_t p4d) 385e9f63768SMike Rapoport { 386e9f63768SMike Rapoport return __pte(p4d_val(p4d)); 387e9f63768SMike Rapoport } 388e9f63768SMike Rapoport 38929e56940SSteve Capper static inline pte_t pud_pte(pud_t pud) 39029e56940SSteve Capper { 39129e56940SSteve Capper return __pte(pud_val(pud)); 39229e56940SSteve Capper } 39329e56940SSteve Capper 394eb3f0624SPunit Agrawal static inline pud_t pte_pud(pte_t pte) 395eb3f0624SPunit Agrawal { 396eb3f0624SPunit Agrawal return __pud(pte_val(pte)); 397eb3f0624SPunit Agrawal } 398eb3f0624SPunit Agrawal 39929e56940SSteve Capper static inline pmd_t pud_pmd(pud_t pud) 40029e56940SSteve Capper { 40129e56940SSteve Capper return __pmd(pud_val(pud)); 40229e56940SSteve Capper } 40329e56940SSteve Capper 4049c7e535fSSteve Capper static inline pte_t pmd_pte(pmd_t pmd) 4059c7e535fSSteve Capper { 4069c7e535fSSteve Capper return __pte(pmd_val(pmd)); 4079c7e535fSSteve Capper } 408af074848SSteve Capper 4099c7e535fSSteve Capper static inline pmd_t pte_pmd(pte_t pte) 4109c7e535fSSteve Capper { 4119c7e535fSSteve Capper return __pmd(pte_val(pte)); 4129c7e535fSSteve Capper } 413af074848SSteve Capper 414f7f0097aSAnshuman Khandual static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 4158ce837ceSArd Biesheuvel { 416f7f0097aSAnshuman Khandual return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 417f7f0097aSAnshuman Khandual } 418f7f0097aSAnshuman Khandual 419f7f0097aSAnshuman Khandual static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 420f7f0097aSAnshuman Khandual { 421f7f0097aSAnshuman Khandual return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 4228ce837ceSArd Biesheuvel } 4238ce837ceSArd Biesheuvel 424570ef363SDavid Hildenbrand static inline pte_t pte_swp_mkexclusive(pte_t pte) 425570ef363SDavid Hildenbrand { 426570ef363SDavid Hildenbrand return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 427570ef363SDavid Hildenbrand } 428570ef363SDavid Hildenbrand 429570ef363SDavid Hildenbrand static inline int pte_swp_exclusive(pte_t pte) 430570ef363SDavid Hildenbrand { 431570ef363SDavid Hildenbrand return pte_val(pte) & PTE_SWP_EXCLUSIVE; 432570ef363SDavid Hildenbrand } 433570ef363SDavid Hildenbrand 434570ef363SDavid Hildenbrand static inline pte_t pte_swp_clear_exclusive(pte_t pte) 435570ef363SDavid Hildenbrand { 436570ef363SDavid Hildenbrand return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 437570ef363SDavid Hildenbrand } 438570ef363SDavid Hildenbrand 439893dea9cSKefeng Wang /* 440893dea9cSKefeng Wang * Select all bits except the pfn 441893dea9cSKefeng Wang */ 442893dea9cSKefeng Wang static inline pgprot_t pte_pgprot(pte_t pte) 443893dea9cSKefeng Wang { 444893dea9cSKefeng Wang unsigned long pfn = pte_pfn(pte); 445893dea9cSKefeng Wang 446893dea9cSKefeng Wang return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); 447893dea9cSKefeng Wang } 448893dea9cSKefeng Wang 44956166230SGanapatrao Kulkarni #ifdef CONFIG_NUMA_BALANCING 45056166230SGanapatrao Kulkarni /* 451ca5999fdSMike Rapoport * See the comment in include/linux/pgtable.h 45256166230SGanapatrao Kulkarni */ 45356166230SGanapatrao Kulkarni static inline int pte_protnone(pte_t pte) 45456166230SGanapatrao Kulkarni { 45556166230SGanapatrao Kulkarni return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; 45656166230SGanapatrao Kulkarni } 45756166230SGanapatrao Kulkarni 45856166230SGanapatrao Kulkarni static inline int pmd_protnone(pmd_t pmd) 45956166230SGanapatrao Kulkarni { 46056166230SGanapatrao Kulkarni return pte_protnone(pmd_pte(pmd)); 46156166230SGanapatrao Kulkarni } 46256166230SGanapatrao Kulkarni #endif 46356166230SGanapatrao Kulkarni 464b65399f6SAnshuman Khandual #define pmd_present_invalid(pmd) (!!(pmd_val(pmd) & PMD_PRESENT_INVALID)) 465b65399f6SAnshuman Khandual 466b65399f6SAnshuman Khandual static inline int pmd_present(pmd_t pmd) 467b65399f6SAnshuman Khandual { 468b65399f6SAnshuman Khandual return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd); 469b65399f6SAnshuman Khandual } 470b65399f6SAnshuman Khandual 471af074848SSteve Capper /* 472af074848SSteve Capper * THP definitions. 473af074848SSteve Capper */ 474af074848SSteve Capper 475af074848SSteve Capper #ifdef CONFIG_TRANSPARENT_HUGEPAGE 476b65399f6SAnshuman Khandual static inline int pmd_trans_huge(pmd_t pmd) 477b65399f6SAnshuman Khandual { 478b65399f6SAnshuman Khandual return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT); 479b65399f6SAnshuman Khandual } 48029e56940SSteve Capper #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 481af074848SSteve Capper 482c164e038SKirill A. Shutemov #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 4839c7e535fSSteve Capper #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 4840795edafSWill Deacon #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 48542b25471SKefeng Wang #define pmd_user(pmd) pte_user(pmd_pte(pmd)) 48642b25471SKefeng Wang #define pmd_user_exec(pmd) pte_user_exec(pmd_pte(pmd)) 487d55863dbSPeter Zijlstra #define pmd_cont(pmd) pte_cont(pmd_pte(pmd)) 4889c7e535fSSteve Capper #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 4899c7e535fSSteve Capper #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 490*2f0584f3SRick Edgecombe #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))) 49105ee26d9SMinchan Kim #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 4929c7e535fSSteve Capper #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 4939c7e535fSSteve Capper #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 494b65399f6SAnshuman Khandual 495b65399f6SAnshuman Khandual static inline pmd_t pmd_mkinvalid(pmd_t pmd) 496b65399f6SAnshuman Khandual { 497b65399f6SAnshuman Khandual pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID)); 498b65399f6SAnshuman Khandual pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID)); 499b65399f6SAnshuman Khandual 500b65399f6SAnshuman Khandual return pmd; 501b65399f6SAnshuman Khandual } 502af074848SSteve Capper 5030dbd3b18SSuzuki K Poulose #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 5040dbd3b18SSuzuki K Poulose 5059c7e535fSSteve Capper #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 506af074848SSteve Capper 507af074848SSteve Capper #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 508af074848SSteve Capper 50973b20c84SRobin Murphy #ifdef CONFIG_TRANSPARENT_HUGEPAGE 51073b20c84SRobin Murphy #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 51173b20c84SRobin Murphy #endif 51230e23538SJia He static inline pmd_t pmd_mkdevmap(pmd_t pmd) 51330e23538SJia He { 51430e23538SJia He return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 51530e23538SJia He } 51673b20c84SRobin Murphy 51775387b92SKristina Martsenko #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 51875387b92SKristina Martsenko #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 51975387b92SKristina Martsenko #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 52075387b92SKristina Martsenko #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 521af074848SSteve Capper #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 522af074848SSteve Capper 52335a63966SPunit Agrawal #define pud_young(pud) pte_young(pud_pte(pud)) 524eb3f0624SPunit Agrawal #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 52529e56940SSteve Capper #define pud_write(pud) pte_write(pud_pte(pud)) 52675387b92SKristina Martsenko 527b8e0ba7cSPunit Agrawal #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 528b8e0ba7cSPunit Agrawal 52975387b92SKristina Martsenko #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 53075387b92SKristina Martsenko #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 53175387b92SKristina Martsenko #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 53275387b92SKristina Martsenko #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 533af074848SSteve Capper 53442b25471SKefeng Wang static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 53542b25471SKefeng Wang pmd_t *pmdp, pmd_t pmd) 53642b25471SKefeng Wang { 53742b25471SKefeng Wang page_table_check_pmd_set(mm, addr, pmdp, pmd); 53842b25471SKefeng Wang return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)); 53942b25471SKefeng Wang } 54042b25471SKefeng Wang 54142b25471SKefeng Wang static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 54242b25471SKefeng Wang pud_t *pudp, pud_t pud) 54342b25471SKefeng Wang { 54442b25471SKefeng Wang page_table_check_pud_set(mm, addr, pudp, pud); 54542b25471SKefeng Wang return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud)); 54642b25471SKefeng Wang } 547af074848SSteve Capper 548e9f63768SMike Rapoport #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 549e9f63768SMike Rapoport #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 550e9f63768SMike Rapoport 55175387b92SKristina Martsenko #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 55275387b92SKristina Martsenko #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 55375387b92SKristina Martsenko 554a501e324SCatalin Marinas #define __pgprot_modify(prot,mask,bits) \ 555a501e324SCatalin Marinas __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 556a501e324SCatalin Marinas 557cca98e9fSChristoph Hellwig #define pgprot_nx(prot) \ 558034aa9cdSWill Deacon __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 559cca98e9fSChristoph Hellwig 560af074848SSteve Capper /* 5614f04d8f0SCatalin Marinas * Mark the prot value as uncacheable and unbufferable. 5624f04d8f0SCatalin Marinas */ 5634f04d8f0SCatalin Marinas #define pgprot_noncached(prot) \ 564de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 5654f04d8f0SCatalin Marinas #define pgprot_writecombine(prot) \ 566de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 567d1e6dc91SLiviu Dudau #define pgprot_device(prot) \ 568d1e6dc91SLiviu Dudau __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 569d15dfd31SCatalin Marinas #define pgprot_tagged(prot) \ 570d15dfd31SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED)) 571d15dfd31SCatalin Marinas #define pgprot_mhp pgprot_tagged 5723e4e1d3fSChristoph Hellwig /* 5733e4e1d3fSChristoph Hellwig * DMA allocations for non-coherent devices use what the Arm architecture calls 5743e4e1d3fSChristoph Hellwig * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 5753e4e1d3fSChristoph Hellwig * and merging of writes. This is different from "Device-nGnR[nE]" memory which 5763e4e1d3fSChristoph Hellwig * is intended for MMIO and thus forbids speculation, preserves access size, 5773e4e1d3fSChristoph Hellwig * requires strict alignment and can also force write responses to come from the 5783e4e1d3fSChristoph Hellwig * endpoint. 5793e4e1d3fSChristoph Hellwig */ 580419e2f18SChristoph Hellwig #define pgprot_dmacoherent(prot) \ 581419e2f18SChristoph Hellwig __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 582419e2f18SChristoph Hellwig PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 583419e2f18SChristoph Hellwig 5844f04d8f0SCatalin Marinas #define __HAVE_PHYS_MEM_ACCESS_PROT 5854f04d8f0SCatalin Marinas struct file; 5864f04d8f0SCatalin Marinas extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 5874f04d8f0SCatalin Marinas unsigned long size, pgprot_t vma_prot); 5884f04d8f0SCatalin Marinas 5894f04d8f0SCatalin Marinas #define pmd_none(pmd) (!pmd_val(pmd)) 5904f04d8f0SCatalin Marinas 59136311607SMarc Zyngier #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 59236311607SMarc Zyngier PMD_TYPE_TABLE) 59336311607SMarc Zyngier #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 59436311607SMarc Zyngier PMD_TYPE_SECT) 59523bc8f69SMuchun Song #define pmd_leaf(pmd) (pmd_present(pmd) && !pmd_table(pmd)) 596e377ab82SAnshuman Khandual #define pmd_bad(pmd) (!pmd_table(pmd)) 59736311607SMarc Zyngier 598d55863dbSPeter Zijlstra #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE) 599d55863dbSPeter Zijlstra #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE) 600d55863dbSPeter Zijlstra 601cac4b8cdSCatalin Marinas #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 6027d4e2dcfSQian Cai static inline bool pud_sect(pud_t pud) { return false; } 6037d4e2dcfSQian Cai static inline bool pud_table(pud_t pud) { return true; } 604206a2a73SSteve Capper #else 605206a2a73SSteve Capper #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 606206a2a73SSteve Capper PUD_TYPE_SECT) 607523d6e9fSzhichang.yuan #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 608523d6e9fSzhichang.yuan PUD_TYPE_TABLE) 609206a2a73SSteve Capper #endif 61036311607SMarc Zyngier 6112330b7caSJun Yao extern pgd_t init_pg_dir[PTRS_PER_PGD]; 6122330b7caSJun Yao extern pgd_t init_pg_end[]; 6132330b7caSJun Yao extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 6142330b7caSJun Yao extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 6152330b7caSJun Yao extern pgd_t tramp_pg_dir[PTRS_PER_PGD]; 616833be850SMark Rutland extern pgd_t reserved_pg_dir[PTRS_PER_PGD]; 6172330b7caSJun Yao 6182330b7caSJun Yao extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 6192330b7caSJun Yao 6202330b7caSJun Yao static inline bool in_swapper_pgdir(void *addr) 6212330b7caSJun Yao { 6222330b7caSJun Yao return ((unsigned long)addr & PAGE_MASK) == 6232330b7caSJun Yao ((unsigned long)swapper_pg_dir & PAGE_MASK); 6242330b7caSJun Yao } 6252330b7caSJun Yao 6264f04d8f0SCatalin Marinas static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 6274f04d8f0SCatalin Marinas { 628e9ed821bSJames Morse #ifdef __PAGETABLE_PMD_FOLDED 629e9ed821bSJames Morse if (in_swapper_pgdir(pmdp)) { 6302330b7caSJun Yao set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 6312330b7caSJun Yao return; 6322330b7caSJun Yao } 633e9ed821bSJames Morse #endif /* __PAGETABLE_PMD_FOLDED */ 6342330b7caSJun Yao 63520a004e7SWill Deacon WRITE_ONCE(*pmdp, pmd); 6360795edafSWill Deacon 637d0b7a302SWill Deacon if (pmd_valid(pmd)) { 63898f7685eSWill Deacon dsb(ishst); 639d0b7a302SWill Deacon isb(); 640d0b7a302SWill Deacon } 6414f04d8f0SCatalin Marinas } 6424f04d8f0SCatalin Marinas 6434f04d8f0SCatalin Marinas static inline void pmd_clear(pmd_t *pmdp) 6444f04d8f0SCatalin Marinas { 6454f04d8f0SCatalin Marinas set_pmd(pmdp, __pmd(0)); 6464f04d8f0SCatalin Marinas } 6474f04d8f0SCatalin Marinas 648dca56dcaSMark Rutland static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 6494f04d8f0SCatalin Marinas { 65075387b92SKristina Martsenko return __pmd_to_phys(pmd); 6514f04d8f0SCatalin Marinas } 6524f04d8f0SCatalin Marinas 653974b9b2cSMike Rapoport static inline unsigned long pmd_page_vaddr(pmd_t pmd) 654974b9b2cSMike Rapoport { 655974b9b2cSMike Rapoport return (unsigned long)__va(pmd_page_paddr(pmd)); 656974b9b2cSMike Rapoport } 65774dd022fSQian Cai 658053520f7SMark Rutland /* Find an entry in the third-level page table. */ 659f069fabaSWill Deacon #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 660053520f7SMark Rutland 661961faac1SMark Rutland #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 662961faac1SMark Rutland #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 663961faac1SMark Rutland #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 664961faac1SMark Rutland 66568ecabd0SGavin Shan #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 6664f04d8f0SCatalin Marinas 6676533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 6686533945aSArd Biesheuvel #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 6696533945aSArd Biesheuvel 6704f04d8f0SCatalin Marinas /* 6714f04d8f0SCatalin Marinas * Conversion functions: convert a page and protection to a page entry, 6724f04d8f0SCatalin Marinas * and a page entry and page directory to the page they refer to. 6734f04d8f0SCatalin Marinas */ 6744f04d8f0SCatalin Marinas #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 6754f04d8f0SCatalin Marinas 6769f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 2 6774f04d8f0SCatalin Marinas 6782cf660ebSGavin Shan #define pmd_ERROR(e) \ 6792cf660ebSGavin Shan pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) 6807078db46SCatalin Marinas 6814f04d8f0SCatalin Marinas #define pud_none(pud) (!pud_val(pud)) 682e377ab82SAnshuman Khandual #define pud_bad(pud) (!pud_table(pud)) 683f02ab08aSPunit Agrawal #define pud_present(pud) pte_present(pud_pte(pud)) 68423bc8f69SMuchun Song #define pud_leaf(pud) (pud_present(pud) && !pud_table(pud)) 6850795edafSWill Deacon #define pud_valid(pud) pte_valid(pud_pte(pud)) 68642b25471SKefeng Wang #define pud_user(pud) pte_user(pud_pte(pud)) 687730a11f9SLiu Shixin #define pud_user_exec(pud) pte_user_exec(pud_pte(pud)) 6884f04d8f0SCatalin Marinas 6894f04d8f0SCatalin Marinas static inline void set_pud(pud_t *pudp, pud_t pud) 6904f04d8f0SCatalin Marinas { 691e9ed821bSJames Morse #ifdef __PAGETABLE_PUD_FOLDED 692e9ed821bSJames Morse if (in_swapper_pgdir(pudp)) { 6932330b7caSJun Yao set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 6942330b7caSJun Yao return; 6952330b7caSJun Yao } 696e9ed821bSJames Morse #endif /* __PAGETABLE_PUD_FOLDED */ 6972330b7caSJun Yao 69820a004e7SWill Deacon WRITE_ONCE(*pudp, pud); 6990795edafSWill Deacon 700d0b7a302SWill Deacon if (pud_valid(pud)) { 70198f7685eSWill Deacon dsb(ishst); 702d0b7a302SWill Deacon isb(); 703d0b7a302SWill Deacon } 7044f04d8f0SCatalin Marinas } 7054f04d8f0SCatalin Marinas 7064f04d8f0SCatalin Marinas static inline void pud_clear(pud_t *pudp) 7074f04d8f0SCatalin Marinas { 7084f04d8f0SCatalin Marinas set_pud(pudp, __pud(0)); 7094f04d8f0SCatalin Marinas } 7104f04d8f0SCatalin Marinas 711dca56dcaSMark Rutland static inline phys_addr_t pud_page_paddr(pud_t pud) 7124f04d8f0SCatalin Marinas { 71375387b92SKristina Martsenko return __pud_to_phys(pud); 7144f04d8f0SCatalin Marinas } 7154f04d8f0SCatalin Marinas 7169cf6fa24SAneesh Kumar K.V static inline pmd_t *pud_pgtable(pud_t pud) 717974b9b2cSMike Rapoport { 7189cf6fa24SAneesh Kumar K.V return (pmd_t *)__va(pud_page_paddr(pud)); 719974b9b2cSMike Rapoport } 7207078db46SCatalin Marinas 721974b9b2cSMike Rapoport /* Find an entry in the second-level page table. */ 72220a004e7SWill Deacon #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 7237078db46SCatalin Marinas 724961faac1SMark Rutland #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 725961faac1SMark Rutland #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 726961faac1SMark Rutland #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 7274f04d8f0SCatalin Marinas 72868ecabd0SGavin Shan #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 72929e56940SSteve Capper 7306533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 7316533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 7326533945aSArd Biesheuvel 733dca56dcaSMark Rutland #else 734dca56dcaSMark Rutland 735dca56dcaSMark Rutland #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 7364e4ff23aSWill Deacon #define pud_user_exec(pud) pud_user(pud) /* Always 0 with folding */ 737dca56dcaSMark Rutland 738961faac1SMark Rutland /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 739961faac1SMark Rutland #define pmd_set_fixmap(addr) NULL 740961faac1SMark Rutland #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 741961faac1SMark Rutland #define pmd_clear_fixmap() 742961faac1SMark Rutland 7436533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 7446533945aSArd Biesheuvel 7459f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 7464f04d8f0SCatalin Marinas 7479f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 3 748c79b954bSJungseok Lee 7492cf660ebSGavin Shan #define pud_ERROR(e) \ 7502cf660ebSGavin Shan pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) 7517078db46SCatalin Marinas 752e9f63768SMike Rapoport #define p4d_none(p4d) (!p4d_val(p4d)) 753e9f63768SMike Rapoport #define p4d_bad(p4d) (!(p4d_val(p4d) & 2)) 754e9f63768SMike Rapoport #define p4d_present(p4d) (p4d_val(p4d)) 755c79b954bSJungseok Lee 756e9f63768SMike Rapoport static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 757c79b954bSJungseok Lee { 758e9f63768SMike Rapoport if (in_swapper_pgdir(p4dp)) { 759e9f63768SMike Rapoport set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 7602330b7caSJun Yao return; 7612330b7caSJun Yao } 7622330b7caSJun Yao 763e9f63768SMike Rapoport WRITE_ONCE(*p4dp, p4d); 764c79b954bSJungseok Lee dsb(ishst); 765eb6a4dccSWill Deacon isb(); 766c79b954bSJungseok Lee } 767c79b954bSJungseok Lee 768e9f63768SMike Rapoport static inline void p4d_clear(p4d_t *p4dp) 769c79b954bSJungseok Lee { 770e9f63768SMike Rapoport set_p4d(p4dp, __p4d(0)); 771c79b954bSJungseok Lee } 772c79b954bSJungseok Lee 773e9f63768SMike Rapoport static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 774c79b954bSJungseok Lee { 775e9f63768SMike Rapoport return __p4d_to_phys(p4d); 776c79b954bSJungseok Lee } 777c79b954bSJungseok Lee 778dc4875f0SAneesh Kumar K.V static inline pud_t *p4d_pgtable(p4d_t p4d) 779974b9b2cSMike Rapoport { 780dc4875f0SAneesh Kumar K.V return (pud_t *)__va(p4d_page_paddr(p4d)); 781974b9b2cSMike Rapoport } 7827078db46SCatalin Marinas 7835845e703SXujun Leng /* Find an entry in the first-level page table. */ 784e9f63768SMike Rapoport #define pud_offset_phys(dir, addr) (p4d_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t)) 7857078db46SCatalin Marinas 786961faac1SMark Rutland #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) 787e9f63768SMike Rapoport #define pud_set_fixmap_offset(p4d, addr) pud_set_fixmap(pud_offset_phys(p4d, addr)) 788961faac1SMark Rutland #define pud_clear_fixmap() clear_fixmap(FIX_PUD) 789c79b954bSJungseok Lee 790e9f63768SMike Rapoport #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 7915d96e0cbSJungseok Lee 7926533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 7936533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) 7946533945aSArd Biesheuvel 795dca56dcaSMark Rutland #else 796dca56dcaSMark Rutland 797e9f63768SMike Rapoport #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 798dca56dcaSMark Rutland #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) 799dca56dcaSMark Rutland 800961faac1SMark Rutland /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 801961faac1SMark Rutland #define pud_set_fixmap(addr) NULL 802961faac1SMark Rutland #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 803961faac1SMark Rutland #define pud_clear_fixmap() 804961faac1SMark Rutland 8056533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 8066533945aSArd Biesheuvel 8079f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 808c79b954bSJungseok Lee 8092cf660ebSGavin Shan #define pgd_ERROR(e) \ 8102cf660ebSGavin Shan pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) 8117078db46SCatalin Marinas 812961faac1SMark Rutland #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 813961faac1SMark Rutland #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 814961faac1SMark Rutland 8154f04d8f0SCatalin Marinas static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 8164f04d8f0SCatalin Marinas { 8179f341931SCatalin Marinas /* 8189f341931SCatalin Marinas * Normal and Normal-Tagged are two different memory types and indices 8199f341931SCatalin Marinas * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK. 8209f341931SCatalin Marinas */ 821a6fadf7eSWill Deacon const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 8229f341931SCatalin Marinas PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP | 8239f341931SCatalin Marinas PTE_ATTRINDX_MASK; 8242f4b829cSCatalin Marinas /* preserve the hardware dirty information */ 8252f4b829cSCatalin Marinas if (pte_hw_dirty(pte)) 82662d96c71SCatalin Marinas pte = pte_mkdirty(pte); 8274f04d8f0SCatalin Marinas pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 8284f04d8f0SCatalin Marinas return pte; 8294f04d8f0SCatalin Marinas } 8304f04d8f0SCatalin Marinas 8319c7e535fSSteve Capper static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 8329c7e535fSSteve Capper { 8339c7e535fSSteve Capper return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 8349c7e535fSSteve Capper } 8359c7e535fSSteve Capper 83666dbd6e6SCatalin Marinas #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 83766dbd6e6SCatalin Marinas extern int ptep_set_access_flags(struct vm_area_struct *vma, 83866dbd6e6SCatalin Marinas unsigned long address, pte_t *ptep, 83966dbd6e6SCatalin Marinas pte_t entry, int dirty); 84066dbd6e6SCatalin Marinas 841282aa705SCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 842282aa705SCatalin Marinas #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 843282aa705SCatalin Marinas static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 844282aa705SCatalin Marinas unsigned long address, pmd_t *pmdp, 845282aa705SCatalin Marinas pmd_t entry, int dirty) 846282aa705SCatalin Marinas { 847282aa705SCatalin Marinas return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 848282aa705SCatalin Marinas } 84973b20c84SRobin Murphy 85073b20c84SRobin Murphy static inline int pud_devmap(pud_t pud) 85173b20c84SRobin Murphy { 85273b20c84SRobin Murphy return 0; 85373b20c84SRobin Murphy } 85473b20c84SRobin Murphy 85573b20c84SRobin Murphy static inline int pgd_devmap(pgd_t pgd) 85673b20c84SRobin Murphy { 85773b20c84SRobin Murphy return 0; 85873b20c84SRobin Murphy } 859282aa705SCatalin Marinas #endif 860282aa705SCatalin Marinas 861ed928a34STong Tiangen #ifdef CONFIG_PAGE_TABLE_CHECK 862ed928a34STong Tiangen static inline bool pte_user_accessible_page(pte_t pte) 863ed928a34STong Tiangen { 864ed928a34STong Tiangen return pte_present(pte) && (pte_user(pte) || pte_user_exec(pte)); 865ed928a34STong Tiangen } 866ed928a34STong Tiangen 867ed928a34STong Tiangen static inline bool pmd_user_accessible_page(pmd_t pmd) 868ed928a34STong Tiangen { 86974c2f810SLiu Shixin return pmd_leaf(pmd) && !pmd_present_invalid(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd)); 870ed928a34STong Tiangen } 871ed928a34STong Tiangen 872ed928a34STong Tiangen static inline bool pud_user_accessible_page(pud_t pud) 873ed928a34STong Tiangen { 874730a11f9SLiu Shixin return pud_leaf(pud) && (pud_user(pud) || pud_user_exec(pud)); 875ed928a34STong Tiangen } 876ed928a34STong Tiangen #endif 877ed928a34STong Tiangen 8782f4b829cSCatalin Marinas /* 8792f4b829cSCatalin Marinas * Atomic pte/pmd modifications. 8802f4b829cSCatalin Marinas */ 8812f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 88206485053SCatalin Marinas static inline int __ptep_test_and_clear_young(pte_t *ptep) 8832f4b829cSCatalin Marinas { 8843bbf7157SCatalin Marinas pte_t old_pte, pte; 8852f4b829cSCatalin Marinas 8863bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 8873bbf7157SCatalin Marinas do { 8883bbf7157SCatalin Marinas old_pte = pte; 8893bbf7157SCatalin Marinas pte = pte_mkold(pte); 8903bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 8913bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 8923bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 8932f4b829cSCatalin Marinas 8943bbf7157SCatalin Marinas return pte_young(pte); 8952f4b829cSCatalin Marinas } 8962f4b829cSCatalin Marinas 89706485053SCatalin Marinas static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 89806485053SCatalin Marinas unsigned long address, 89906485053SCatalin Marinas pte_t *ptep) 90006485053SCatalin Marinas { 90106485053SCatalin Marinas return __ptep_test_and_clear_young(ptep); 90206485053SCatalin Marinas } 90306485053SCatalin Marinas 9043403e56bSAlex Van Brunt #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 9053403e56bSAlex Van Brunt static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 9063403e56bSAlex Van Brunt unsigned long address, pte_t *ptep) 9073403e56bSAlex Van Brunt { 9083403e56bSAlex Van Brunt int young = ptep_test_and_clear_young(vma, address, ptep); 9093403e56bSAlex Van Brunt 9103403e56bSAlex Van Brunt if (young) { 9113403e56bSAlex Van Brunt /* 9123403e56bSAlex Van Brunt * We can elide the trailing DSB here since the worst that can 9133403e56bSAlex Van Brunt * happen is that a CPU continues to use the young entry in its 9143403e56bSAlex Van Brunt * TLB and we mistakenly reclaim the associated page. The 9153403e56bSAlex Van Brunt * window for such an event is bounded by the next 9163403e56bSAlex Van Brunt * context-switch, which provides a DSB to complete the TLB 9173403e56bSAlex Van Brunt * invalidation. 9183403e56bSAlex Van Brunt */ 9193403e56bSAlex Van Brunt flush_tlb_page_nosync(vma, address); 9203403e56bSAlex Van Brunt } 9213403e56bSAlex Van Brunt 9223403e56bSAlex Van Brunt return young; 9233403e56bSAlex Van Brunt } 9243403e56bSAlex Van Brunt 9252f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 9262f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 9272f4b829cSCatalin Marinas static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 9282f4b829cSCatalin Marinas unsigned long address, 9292f4b829cSCatalin Marinas pmd_t *pmdp) 9302f4b829cSCatalin Marinas { 9312f4b829cSCatalin Marinas return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 9322f4b829cSCatalin Marinas } 9332f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 9342f4b829cSCatalin Marinas 9352f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 9362f4b829cSCatalin Marinas static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 9372f4b829cSCatalin Marinas unsigned long address, pte_t *ptep) 9382f4b829cSCatalin Marinas { 93942b25471SKefeng Wang pte_t pte = __pte(xchg_relaxed(&pte_val(*ptep), 0)); 94042b25471SKefeng Wang 94142b25471SKefeng Wang page_table_check_pte_clear(mm, address, pte); 94242b25471SKefeng Wang 94342b25471SKefeng Wang return pte; 9442f4b829cSCatalin Marinas } 9452f4b829cSCatalin Marinas 9462f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 947911f56eeSCatalin Marinas #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 948911f56eeSCatalin Marinas static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 9492f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 9502f4b829cSCatalin Marinas { 95142b25471SKefeng Wang pmd_t pmd = __pmd(xchg_relaxed(&pmd_val(*pmdp), 0)); 95242b25471SKefeng Wang 95342b25471SKefeng Wang page_table_check_pmd_clear(mm, address, pmd); 95442b25471SKefeng Wang 95542b25471SKefeng Wang return pmd; 9562f4b829cSCatalin Marinas } 9572f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 9582f4b829cSCatalin Marinas 9592f4b829cSCatalin Marinas /* 9608781bcbcSSteve Capper * ptep_set_wrprotect - mark read-only while trasferring potential hardware 9618781bcbcSSteve Capper * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 9622f4b829cSCatalin Marinas */ 9632f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_SET_WRPROTECT 9642f4b829cSCatalin Marinas static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 9652f4b829cSCatalin Marinas { 9663bbf7157SCatalin Marinas pte_t old_pte, pte; 9672f4b829cSCatalin Marinas 9683bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 9693bbf7157SCatalin Marinas do { 9703bbf7157SCatalin Marinas old_pte = pte; 9713bbf7157SCatalin Marinas pte = pte_wrprotect(pte); 9723bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 9733bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 9743bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 9752f4b829cSCatalin Marinas } 9762f4b829cSCatalin Marinas 9772f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 9782f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_SET_WRPROTECT 9792f4b829cSCatalin Marinas static inline void pmdp_set_wrprotect(struct mm_struct *mm, 9802f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 9812f4b829cSCatalin Marinas { 9822f4b829cSCatalin Marinas ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 9832f4b829cSCatalin Marinas } 9841d78a62cSCatalin Marinas 9851d78a62cSCatalin Marinas #define pmdp_establish pmdp_establish 9861d78a62cSCatalin Marinas static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 9871d78a62cSCatalin Marinas unsigned long address, pmd_t *pmdp, pmd_t pmd) 9881d78a62cSCatalin Marinas { 98942b25471SKefeng Wang page_table_check_pmd_set(vma->vm_mm, address, pmdp, pmd); 9901d78a62cSCatalin Marinas return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 9911d78a62cSCatalin Marinas } 9922f4b829cSCatalin Marinas #endif 9932f4b829cSCatalin Marinas 9944f04d8f0SCatalin Marinas /* 9954f04d8f0SCatalin Marinas * Encode and decode a swap entry: 9963676f9efSCatalin Marinas * bits 0-1: present (must be zero) 997570ef363SDavid Hildenbrand * bits 2: remember PG_anon_exclusive 998570ef363SDavid Hildenbrand * bits 3-7: swap type 9999b3e661eSKirill A. Shutemov * bits 8-57: swap offset 1000fdc69e7dSCatalin Marinas * bit 58: PTE_PROT_NONE (must be zero) 10014f04d8f0SCatalin Marinas */ 1002570ef363SDavid Hildenbrand #define __SWP_TYPE_SHIFT 3 1003570ef363SDavid Hildenbrand #define __SWP_TYPE_BITS 5 10049b3e661eSKirill A. Shutemov #define __SWP_OFFSET_BITS 50 10054f04d8f0SCatalin Marinas #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 10064f04d8f0SCatalin Marinas #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 10073676f9efSCatalin Marinas #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 10084f04d8f0SCatalin Marinas 10094f04d8f0SCatalin Marinas #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 10103676f9efSCatalin Marinas #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 10114f04d8f0SCatalin Marinas #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 10124f04d8f0SCatalin Marinas 10134f04d8f0SCatalin Marinas #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 10144f04d8f0SCatalin Marinas #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 10154f04d8f0SCatalin Marinas 101653fa117bSAnshuman Khandual #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 101753fa117bSAnshuman Khandual #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 101853fa117bSAnshuman Khandual #define __swp_entry_to_pmd(swp) __pmd((swp).val) 101953fa117bSAnshuman Khandual #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 102053fa117bSAnshuman Khandual 10214f04d8f0SCatalin Marinas /* 10224f04d8f0SCatalin Marinas * Ensure that there are not more swap files than can be encoded in the kernel 1023aad9061bSGeert Uytterhoeven * PTEs. 10244f04d8f0SCatalin Marinas */ 10254f04d8f0SCatalin Marinas #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 10264f04d8f0SCatalin Marinas 102736943abaSSteven Price #ifdef CONFIG_ARM64_MTE 102836943abaSSteven Price 102936943abaSSteven Price #define __HAVE_ARCH_PREPARE_TO_SWAP 103036943abaSSteven Price static inline int arch_prepare_to_swap(struct page *page) 103136943abaSSteven Price { 103236943abaSSteven Price if (system_supports_mte()) 103336943abaSSteven Price return mte_save_tags(page); 103436943abaSSteven Price return 0; 103536943abaSSteven Price } 103636943abaSSteven Price 103736943abaSSteven Price #define __HAVE_ARCH_SWAP_INVALIDATE 103836943abaSSteven Price static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 103936943abaSSteven Price { 104036943abaSSteven Price if (system_supports_mte()) 104136943abaSSteven Price mte_invalidate_tags(type, offset); 104236943abaSSteven Price } 104336943abaSSteven Price 104436943abaSSteven Price static inline void arch_swap_invalidate_area(int type) 104536943abaSSteven Price { 104636943abaSSteven Price if (system_supports_mte()) 104736943abaSSteven Price mte_invalidate_tags_area(type); 104836943abaSSteven Price } 104936943abaSSteven Price 105036943abaSSteven Price #define __HAVE_ARCH_SWAP_RESTORE 1051da08e9b7SMatthew Wilcox (Oracle) static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio) 105236943abaSSteven Price { 1053d77e59a8SCatalin Marinas if (system_supports_mte()) 1054d77e59a8SCatalin Marinas mte_restore_tags(entry, &folio->page); 105536943abaSSteven Price } 105636943abaSSteven Price 105736943abaSSteven Price #endif /* CONFIG_ARM64_MTE */ 105836943abaSSteven Price 1059cba3574fSWill Deacon /* 1060cba3574fSWill Deacon * On AArch64, the cache coherency is handled via the set_pte_at() function. 1061cba3574fSWill Deacon */ 1062cba3574fSWill Deacon static inline void update_mmu_cache(struct vm_area_struct *vma, 1063cba3574fSWill Deacon unsigned long addr, pte_t *ptep) 1064cba3574fSWill Deacon { 1065cba3574fSWill Deacon /* 1066120798d2SWill Deacon * We don't do anything here, so there's a very small chance of 1067120798d2SWill Deacon * us retaking a user fault which we just fixed up. The alternative 1068120798d2SWill Deacon * is doing a dsb(ishst), but that penalises the fastpath. 1069cba3574fSWill Deacon */ 1070cba3574fSWill Deacon } 1071cba3574fSWill Deacon 1072cba3574fSWill Deacon #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 1073cba3574fSWill Deacon 1074529c4b05SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 1075529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 1076529c4b05SKristina Martsenko #else 1077529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (addr) 1078529c4b05SKristina Martsenko #endif 1079529c4b05SKristina Martsenko 10806af31226SJia He /* 10816af31226SJia He * On arm64 without hardware Access Flag, copying from user will fail because 10826af31226SJia He * the pte is old and cannot be marked young. So we always end up with zeroed 10836af31226SJia He * page after fork() + CoW for pfn mappings. We don't always have a 10846af31226SJia He * hardware-managed access flag on arm64. 10856af31226SJia He */ 1086e1fd09e3SYu Zhao #define arch_has_hw_pte_young cpu_has_hw_af 10870388f9c7SWill Deacon 10880388f9c7SWill Deacon /* 10890388f9c7SWill Deacon * Experimentally, it's cheap to set the access flag in hardware and we 10900388f9c7SWill Deacon * benefit from prefaulting mappings as 'old' to start with. 10910388f9c7SWill Deacon */ 1092e1fd09e3SYu Zhao #define arch_wants_old_prefaulted_pte cpu_has_hw_af 10936af31226SJia He 1094f8b46c4bSAnshuman Khandual static inline bool pud_sect_supported(void) 1095f8b46c4bSAnshuman Khandual { 1096f8b46c4bSAnshuman Khandual return PAGE_SIZE == SZ_4K; 1097f8b46c4bSAnshuman Khandual } 1098f8b46c4bSAnshuman Khandual 109918107f8aSVladimir Murzin 11005db568e7SAnshuman Khandual #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 11015db568e7SAnshuman Khandual #define ptep_modify_prot_start ptep_modify_prot_start 11025db568e7SAnshuman Khandual extern pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 11035db568e7SAnshuman Khandual unsigned long addr, pte_t *ptep); 11045db568e7SAnshuman Khandual 11055db568e7SAnshuman Khandual #define ptep_modify_prot_commit ptep_modify_prot_commit 11065db568e7SAnshuman Khandual extern void ptep_modify_prot_commit(struct vm_area_struct *vma, 11075db568e7SAnshuman Khandual unsigned long addr, pte_t *ptep, 11085db568e7SAnshuman Khandual pte_t old_pte, pte_t new_pte); 11094f04d8f0SCatalin Marinas #endif /* !__ASSEMBLY__ */ 11104f04d8f0SCatalin Marinas 11114f04d8f0SCatalin Marinas #endif /* __ASM_PGTABLE_H */ 1112