1caab277bSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 24f04d8f0SCatalin Marinas /* 34f04d8f0SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 44f04d8f0SCatalin Marinas */ 54f04d8f0SCatalin Marinas #ifndef __ASM_PGTABLE_H 64f04d8f0SCatalin Marinas #define __ASM_PGTABLE_H 74f04d8f0SCatalin Marinas 82f4b829cSCatalin Marinas #include <asm/bug.h> 94f04d8f0SCatalin Marinas #include <asm/proc-fns.h> 104f04d8f0SCatalin Marinas 114f04d8f0SCatalin Marinas #include <asm/memory.h> 124f04d8f0SCatalin Marinas #include <asm/pgtable-hwdef.h> 133eca86e7SMark Rutland #include <asm/pgtable-prot.h> 143403e56bSAlex Van Brunt #include <asm/tlbflush.h> 154f04d8f0SCatalin Marinas 164f04d8f0SCatalin Marinas /* 173e1907d5SArd Biesheuvel * VMALLOC range. 1808375198SCatalin Marinas * 19f9040773SArd Biesheuvel * VMALLOC_START: beginning of the kernel vmalloc space 20a5315819SMark Brown * VMALLOC_END: extends to the available space below vmemmap, PCI I/O space 213e1907d5SArd Biesheuvel * and fixed mappings 224f04d8f0SCatalin Marinas */ 23f9040773SArd Biesheuvel #define VMALLOC_START (MODULES_END) 2414c127c9SSteve Capper #define VMALLOC_END (- PUD_SIZE - VMEMMAP_SIZE - SZ_64K) 254f04d8f0SCatalin Marinas 26d016bf7eSKirill A. Shutemov #define FIRST_USER_ADDRESS 0UL 274f04d8f0SCatalin Marinas 284f04d8f0SCatalin Marinas #ifndef __ASSEMBLY__ 292f4b829cSCatalin Marinas 303bbf7157SCatalin Marinas #include <asm/cmpxchg.h> 31961faac1SMark Rutland #include <asm/fixmap.h> 322f4b829cSCatalin Marinas #include <linux/mmdebug.h> 3386c9e812SWill Deacon #include <linux/mm_types.h> 3486c9e812SWill Deacon #include <linux/sched.h> 352f4b829cSCatalin Marinas 36c8b6d2ccSSteve Capper extern struct page *vmemmap; 37c8b6d2ccSSteve Capper 38a7ac1cfaSZhenyu Ye #ifdef CONFIG_TRANSPARENT_HUGEPAGE 39a7ac1cfaSZhenyu Ye #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 40a7ac1cfaSZhenyu Ye 41a7ac1cfaSZhenyu Ye /* Set stride and tlb_level in flush_*_tlb_range */ 42a7ac1cfaSZhenyu Ye #define flush_pmd_tlb_range(vma, addr, end) \ 43a7ac1cfaSZhenyu Ye __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) 44a7ac1cfaSZhenyu Ye #define flush_pud_tlb_range(vma, addr, end) \ 45a7ac1cfaSZhenyu Ye __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) 46a7ac1cfaSZhenyu Ye #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 47a7ac1cfaSZhenyu Ye 484f04d8f0SCatalin Marinas /* 494f04d8f0SCatalin Marinas * ZERO_PAGE is a global shared page that is always zero: used 504f04d8f0SCatalin Marinas * for zero-mapped memory areas etc.. 514f04d8f0SCatalin Marinas */ 525227cfa7SMark Rutland extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 532077be67SLaura Abbott #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 544f04d8f0SCatalin Marinas 55*2cf660ebSGavin Shan #define pte_ERROR(e) \ 56*2cf660ebSGavin Shan pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) 577078db46SCatalin Marinas 5875387b92SKristina Martsenko /* 5975387b92SKristina Martsenko * Macros to convert between a physical address and its placement in a 6075387b92SKristina Martsenko * page table entry, taking care of 52-bit addresses. 6175387b92SKristina Martsenko */ 6275387b92SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 6375387b92SKristina Martsenko #define __pte_to_phys(pte) \ 6475387b92SKristina Martsenko ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36)) 6575387b92SKristina Martsenko #define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK) 6675387b92SKristina Martsenko #else 6775387b92SKristina Martsenko #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK) 6875387b92SKristina Martsenko #define __phys_to_pte_val(phys) (phys) 6975387b92SKristina Martsenko #endif 704f04d8f0SCatalin Marinas 7175387b92SKristina Martsenko #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 7275387b92SKristina Martsenko #define pfn_pte(pfn,prot) \ 7375387b92SKristina Martsenko __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 744f04d8f0SCatalin Marinas 754f04d8f0SCatalin Marinas #define pte_none(pte) (!pte_val(pte)) 764f04d8f0SCatalin Marinas #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 774f04d8f0SCatalin Marinas #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 787078db46SCatalin Marinas 794f04d8f0SCatalin Marinas /* 804f04d8f0SCatalin Marinas * The following only work if pte_present(). Undefined behaviour otherwise. 814f04d8f0SCatalin Marinas */ 8284fe6826SSteve Capper #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 8384fe6826SSteve Capper #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 8484fe6826SSteve Capper #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 8584fe6826SSteve Capper #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 86ec663d96SCatalin Marinas #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 8793ef666aSJeremy Linton #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 8873b20c84SRobin Murphy #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 894f04d8f0SCatalin Marinas 90d27cfa1fSArd Biesheuvel #define pte_cont_addr_end(addr, end) \ 91d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 92d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 93d27cfa1fSArd Biesheuvel }) 94d27cfa1fSArd Biesheuvel 95d27cfa1fSArd Biesheuvel #define pmd_cont_addr_end(addr, end) \ 96d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 97d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 98d27cfa1fSArd Biesheuvel }) 99d27cfa1fSArd Biesheuvel 100b847415cSCatalin Marinas #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) 1012f4b829cSCatalin Marinas #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 1022f4b829cSCatalin Marinas #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 1032f4b829cSCatalin Marinas 104766ffb69SWill Deacon #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 105ec663d96SCatalin Marinas #define pte_valid_not_user(pte) \ 10624cecc37SCatalin Marinas ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID) 10776c714beSWill Deacon #define pte_valid_young(pte) \ 10876c714beSWill Deacon ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF)) 1096218f96cSCatalin Marinas #define pte_valid_user(pte) \ 1106218f96cSCatalin Marinas ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) 11176c714beSWill Deacon 11276c714beSWill Deacon /* 11376c714beSWill Deacon * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 11476c714beSWill Deacon * so that we don't erroneously return false for pages that have been 11576c714beSWill Deacon * remapped as PROT_NONE but are yet to be flushed from the TLB. 11676c714beSWill Deacon */ 11776c714beSWill Deacon #define pte_accessible(mm, pte) \ 11876c714beSWill Deacon (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte)) 1194f04d8f0SCatalin Marinas 1206218f96cSCatalin Marinas /* 1216218f96cSCatalin Marinas * p??_access_permitted() is true for valid user mappings (subject to the 12224cecc37SCatalin Marinas * write permission check). PROT_NONE mappings do not have the PTE_VALID bit 12324cecc37SCatalin Marinas * set. 1246218f96cSCatalin Marinas */ 1256218f96cSCatalin Marinas #define pte_access_permitted(pte, write) \ 1266218f96cSCatalin Marinas (pte_valid_user(pte) && (!(write) || pte_write(pte))) 1276218f96cSCatalin Marinas #define pmd_access_permitted(pmd, write) \ 1286218f96cSCatalin Marinas (pte_access_permitted(pmd_pte(pmd), (write))) 1296218f96cSCatalin Marinas #define pud_access_permitted(pud, write) \ 1306218f96cSCatalin Marinas (pte_access_permitted(pud_pte(pud), (write))) 1316218f96cSCatalin Marinas 132b6d4f280SLaura Abbott static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 133b6d4f280SLaura Abbott { 134b6d4f280SLaura Abbott pte_val(pte) &= ~pgprot_val(prot); 135b6d4f280SLaura Abbott return pte; 136b6d4f280SLaura Abbott } 137b6d4f280SLaura Abbott 138b6d4f280SLaura Abbott static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 139b6d4f280SLaura Abbott { 140b6d4f280SLaura Abbott pte_val(pte) |= pgprot_val(prot); 141b6d4f280SLaura Abbott return pte; 142b6d4f280SLaura Abbott } 143b6d4f280SLaura Abbott 14444b6dfc5SSteve Capper static inline pte_t pte_wrprotect(pte_t pte) 14544b6dfc5SSteve Capper { 14673e86cb0SCatalin Marinas pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 14773e86cb0SCatalin Marinas pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 14873e86cb0SCatalin Marinas return pte; 14944b6dfc5SSteve Capper } 1504f04d8f0SCatalin Marinas 15144b6dfc5SSteve Capper static inline pte_t pte_mkwrite(pte_t pte) 15244b6dfc5SSteve Capper { 15373e86cb0SCatalin Marinas pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 15473e86cb0SCatalin Marinas pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 15573e86cb0SCatalin Marinas return pte; 15644b6dfc5SSteve Capper } 15744b6dfc5SSteve Capper 15844b6dfc5SSteve Capper static inline pte_t pte_mkclean(pte_t pte) 15944b6dfc5SSteve Capper { 1608781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 1618781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 1628781bcbcSSteve Capper 1638781bcbcSSteve Capper return pte; 16444b6dfc5SSteve Capper } 16544b6dfc5SSteve Capper 16644b6dfc5SSteve Capper static inline pte_t pte_mkdirty(pte_t pte) 16744b6dfc5SSteve Capper { 1688781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 1698781bcbcSSteve Capper 1708781bcbcSSteve Capper if (pte_write(pte)) 1718781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 1728781bcbcSSteve Capper 1738781bcbcSSteve Capper return pte; 17444b6dfc5SSteve Capper } 17544b6dfc5SSteve Capper 17644b6dfc5SSteve Capper static inline pte_t pte_mkold(pte_t pte) 17744b6dfc5SSteve Capper { 178b6d4f280SLaura Abbott return clear_pte_bit(pte, __pgprot(PTE_AF)); 17944b6dfc5SSteve Capper } 18044b6dfc5SSteve Capper 18144b6dfc5SSteve Capper static inline pte_t pte_mkyoung(pte_t pte) 18244b6dfc5SSteve Capper { 183b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_AF)); 18444b6dfc5SSteve Capper } 18544b6dfc5SSteve Capper 18644b6dfc5SSteve Capper static inline pte_t pte_mkspecial(pte_t pte) 18744b6dfc5SSteve Capper { 188b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 18944b6dfc5SSteve Capper } 1904f04d8f0SCatalin Marinas 19193ef666aSJeremy Linton static inline pte_t pte_mkcont(pte_t pte) 19293ef666aSJeremy Linton { 19366b3923aSDavid Woods pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 19466b3923aSDavid Woods return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 19593ef666aSJeremy Linton } 19693ef666aSJeremy Linton 19793ef666aSJeremy Linton static inline pte_t pte_mknoncont(pte_t pte) 19893ef666aSJeremy Linton { 19993ef666aSJeremy Linton return clear_pte_bit(pte, __pgprot(PTE_CONT)); 20093ef666aSJeremy Linton } 20193ef666aSJeremy Linton 2025ebe3a44SJames Morse static inline pte_t pte_mkpresent(pte_t pte) 2035ebe3a44SJames Morse { 2045ebe3a44SJames Morse return set_pte_bit(pte, __pgprot(PTE_VALID)); 2055ebe3a44SJames Morse } 2065ebe3a44SJames Morse 20766b3923aSDavid Woods static inline pmd_t pmd_mkcont(pmd_t pmd) 20866b3923aSDavid Woods { 20966b3923aSDavid Woods return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 21066b3923aSDavid Woods } 21166b3923aSDavid Woods 21273b20c84SRobin Murphy static inline pte_t pte_mkdevmap(pte_t pte) 21373b20c84SRobin Murphy { 21430e23538SJia He return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 21573b20c84SRobin Murphy } 21673b20c84SRobin Murphy 2174f04d8f0SCatalin Marinas static inline void set_pte(pte_t *ptep, pte_t pte) 2184f04d8f0SCatalin Marinas { 21920a004e7SWill Deacon WRITE_ONCE(*ptep, pte); 2207f0b1bf0SCatalin Marinas 2217f0b1bf0SCatalin Marinas /* 2227f0b1bf0SCatalin Marinas * Only if the new pte is valid and kernel, otherwise TLB maintenance 2237f0b1bf0SCatalin Marinas * or update_mmu_cache() have the necessary barriers. 2247f0b1bf0SCatalin Marinas */ 225d0b7a302SWill Deacon if (pte_valid_not_user(pte)) { 2267f0b1bf0SCatalin Marinas dsb(ishst); 227d0b7a302SWill Deacon isb(); 228d0b7a302SWill Deacon } 2294f04d8f0SCatalin Marinas } 2304f04d8f0SCatalin Marinas 231907e21c1SShaokun Zhang extern void __sync_icache_dcache(pte_t pteval); 2324f04d8f0SCatalin Marinas 2332f4b829cSCatalin Marinas /* 2342f4b829cSCatalin Marinas * PTE bits configuration in the presence of hardware Dirty Bit Management 2352f4b829cSCatalin Marinas * (PTE_WRITE == PTE_DBM): 2362f4b829cSCatalin Marinas * 2372f4b829cSCatalin Marinas * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 2382f4b829cSCatalin Marinas * 0 0 | 1 0 0 2392f4b829cSCatalin Marinas * 0 1 | 1 1 0 2402f4b829cSCatalin Marinas * 1 0 | 1 0 1 2412f4b829cSCatalin Marinas * 1 1 | 0 1 x 2422f4b829cSCatalin Marinas * 2432f4b829cSCatalin Marinas * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 2442f4b829cSCatalin Marinas * the page fault mechanism. Checking the dirty status of a pte becomes: 2452f4b829cSCatalin Marinas * 246b847415cSCatalin Marinas * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 2472f4b829cSCatalin Marinas */ 2489b604722SMark Rutland 2499b604722SMark Rutland static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep, 2509b604722SMark Rutland pte_t pte) 2514f04d8f0SCatalin Marinas { 25220a004e7SWill Deacon pte_t old_pte; 25320a004e7SWill Deacon 2549b604722SMark Rutland if (!IS_ENABLED(CONFIG_DEBUG_VM)) 2559b604722SMark Rutland return; 2569b604722SMark Rutland 2579b604722SMark Rutland old_pte = READ_ONCE(*ptep); 2589b604722SMark Rutland 2599b604722SMark Rutland if (!pte_valid(old_pte) || !pte_valid(pte)) 2609b604722SMark Rutland return; 2619b604722SMark Rutland if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 2629b604722SMark Rutland return; 26302522463SWill Deacon 2642f4b829cSCatalin Marinas /* 2659b604722SMark Rutland * Check for potential race with hardware updates of the pte 2669b604722SMark Rutland * (ptep_set_access_flags safely changes valid ptes without going 2679b604722SMark Rutland * through an invalid entry). 2682f4b829cSCatalin Marinas */ 26982d34008SCatalin Marinas VM_WARN_ONCE(!pte_young(pte), 27082d34008SCatalin Marinas "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 27120a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 27220a004e7SWill Deacon VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 27382d34008SCatalin Marinas "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 27420a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 2752f4b829cSCatalin Marinas } 2762f4b829cSCatalin Marinas 2779b604722SMark Rutland static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 2789b604722SMark Rutland pte_t *ptep, pte_t pte) 2799b604722SMark Rutland { 2809b604722SMark Rutland if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 2819b604722SMark Rutland __sync_icache_dcache(pte); 2829b604722SMark Rutland 2839b604722SMark Rutland __check_racy_pte_update(mm, ptep, pte); 2849b604722SMark Rutland 2854f04d8f0SCatalin Marinas set_pte(ptep, pte); 2864f04d8f0SCatalin Marinas } 2874f04d8f0SCatalin Marinas 2884f04d8f0SCatalin Marinas /* 2894f04d8f0SCatalin Marinas * Huge pte definitions. 2904f04d8f0SCatalin Marinas */ 291084bd298SSteve Capper #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 292084bd298SSteve Capper 293084bd298SSteve Capper /* 294084bd298SSteve Capper * Hugetlb definitions. 295084bd298SSteve Capper */ 29666b3923aSDavid Woods #define HUGE_MAX_HSTATE 4 297084bd298SSteve Capper #define HPAGE_SHIFT PMD_SHIFT 298084bd298SSteve Capper #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 299084bd298SSteve Capper #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 300084bd298SSteve Capper #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 3014f04d8f0SCatalin Marinas 30275387b92SKristina Martsenko static inline pte_t pgd_pte(pgd_t pgd) 30375387b92SKristina Martsenko { 30475387b92SKristina Martsenko return __pte(pgd_val(pgd)); 30575387b92SKristina Martsenko } 30675387b92SKristina Martsenko 307e9f63768SMike Rapoport static inline pte_t p4d_pte(p4d_t p4d) 308e9f63768SMike Rapoport { 309e9f63768SMike Rapoport return __pte(p4d_val(p4d)); 310e9f63768SMike Rapoport } 311e9f63768SMike Rapoport 31229e56940SSteve Capper static inline pte_t pud_pte(pud_t pud) 31329e56940SSteve Capper { 31429e56940SSteve Capper return __pte(pud_val(pud)); 31529e56940SSteve Capper } 31629e56940SSteve Capper 317eb3f0624SPunit Agrawal static inline pud_t pte_pud(pte_t pte) 318eb3f0624SPunit Agrawal { 319eb3f0624SPunit Agrawal return __pud(pte_val(pte)); 320eb3f0624SPunit Agrawal } 321eb3f0624SPunit Agrawal 32229e56940SSteve Capper static inline pmd_t pud_pmd(pud_t pud) 32329e56940SSteve Capper { 32429e56940SSteve Capper return __pmd(pud_val(pud)); 32529e56940SSteve Capper } 32629e56940SSteve Capper 3279c7e535fSSteve Capper static inline pte_t pmd_pte(pmd_t pmd) 3289c7e535fSSteve Capper { 3299c7e535fSSteve Capper return __pte(pmd_val(pmd)); 3309c7e535fSSteve Capper } 331af074848SSteve Capper 3329c7e535fSSteve Capper static inline pmd_t pte_pmd(pte_t pte) 3339c7e535fSSteve Capper { 3349c7e535fSSteve Capper return __pmd(pte_val(pte)); 3359c7e535fSSteve Capper } 336af074848SSteve Capper 337f7f0097aSAnshuman Khandual static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 3388ce837ceSArd Biesheuvel { 339f7f0097aSAnshuman Khandual return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 340f7f0097aSAnshuman Khandual } 341f7f0097aSAnshuman Khandual 342f7f0097aSAnshuman Khandual static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 343f7f0097aSAnshuman Khandual { 344f7f0097aSAnshuman Khandual return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 3458ce837ceSArd Biesheuvel } 3468ce837ceSArd Biesheuvel 34756166230SGanapatrao Kulkarni #ifdef CONFIG_NUMA_BALANCING 34856166230SGanapatrao Kulkarni /* 349ca5999fdSMike Rapoport * See the comment in include/linux/pgtable.h 35056166230SGanapatrao Kulkarni */ 35156166230SGanapatrao Kulkarni static inline int pte_protnone(pte_t pte) 35256166230SGanapatrao Kulkarni { 35356166230SGanapatrao Kulkarni return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; 35456166230SGanapatrao Kulkarni } 35556166230SGanapatrao Kulkarni 35656166230SGanapatrao Kulkarni static inline int pmd_protnone(pmd_t pmd) 35756166230SGanapatrao Kulkarni { 35856166230SGanapatrao Kulkarni return pte_protnone(pmd_pte(pmd)); 35956166230SGanapatrao Kulkarni } 36056166230SGanapatrao Kulkarni #endif 36156166230SGanapatrao Kulkarni 362af074848SSteve Capper /* 363af074848SSteve Capper * THP definitions. 364af074848SSteve Capper */ 365af074848SSteve Capper 366af074848SSteve Capper #ifdef CONFIG_TRANSPARENT_HUGEPAGE 367af074848SSteve Capper #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) 36829e56940SSteve Capper #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 369af074848SSteve Capper 3705bb1cc0fSCatalin Marinas #define pmd_present(pmd) pte_present(pmd_pte(pmd)) 371c164e038SKirill A. Shutemov #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 3729c7e535fSSteve Capper #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 3730795edafSWill Deacon #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 3749c7e535fSSteve Capper #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 3759c7e535fSSteve Capper #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 3769c7e535fSSteve Capper #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 37705ee26d9SMinchan Kim #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 3789c7e535fSSteve Capper #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 3799c7e535fSSteve Capper #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 38086ec2da0SAnshuman Khandual #define pmd_mkinvalid(pmd) (__pmd(pmd_val(pmd) & ~PMD_SECT_VALID)) 381af074848SSteve Capper 3820dbd3b18SSuzuki K Poulose #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 3830dbd3b18SSuzuki K Poulose 3849c7e535fSSteve Capper #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 385af074848SSteve Capper 386af074848SSteve Capper #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 387af074848SSteve Capper 38873b20c84SRobin Murphy #ifdef CONFIG_TRANSPARENT_HUGEPAGE 38973b20c84SRobin Murphy #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 39073b20c84SRobin Murphy #endif 39130e23538SJia He static inline pmd_t pmd_mkdevmap(pmd_t pmd) 39230e23538SJia He { 39330e23538SJia He return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 39430e23538SJia He } 39573b20c84SRobin Murphy 39675387b92SKristina Martsenko #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 39775387b92SKristina Martsenko #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 39875387b92SKristina Martsenko #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 39975387b92SKristina Martsenko #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 400af074848SSteve Capper #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 401af074848SSteve Capper 40235a63966SPunit Agrawal #define pud_young(pud) pte_young(pud_pte(pud)) 403eb3f0624SPunit Agrawal #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 40429e56940SSteve Capper #define pud_write(pud) pte_write(pud_pte(pud)) 40575387b92SKristina Martsenko 406b8e0ba7cSPunit Agrawal #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 407b8e0ba7cSPunit Agrawal 40875387b92SKristina Martsenko #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 40975387b92SKristina Martsenko #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 41075387b92SKristina Martsenko #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 41175387b92SKristina Martsenko #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 412af074848SSteve Capper 413ceb21835SWill Deacon #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) 414af074848SSteve Capper 415e9f63768SMike Rapoport #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 416e9f63768SMike Rapoport #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 417e9f63768SMike Rapoport 41875387b92SKristina Martsenko #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 41975387b92SKristina Martsenko #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 42075387b92SKristina Martsenko 421a501e324SCatalin Marinas #define __pgprot_modify(prot,mask,bits) \ 422a501e324SCatalin Marinas __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 423a501e324SCatalin Marinas 424cca98e9fSChristoph Hellwig #define pgprot_nx(prot) \ 425034aa9cdSWill Deacon __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 426cca98e9fSChristoph Hellwig 427af074848SSteve Capper /* 4284f04d8f0SCatalin Marinas * Mark the prot value as uncacheable and unbufferable. 4294f04d8f0SCatalin Marinas */ 4304f04d8f0SCatalin Marinas #define pgprot_noncached(prot) \ 431de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 4324f04d8f0SCatalin Marinas #define pgprot_writecombine(prot) \ 433de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 434d1e6dc91SLiviu Dudau #define pgprot_device(prot) \ 435d1e6dc91SLiviu Dudau __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 4363e4e1d3fSChristoph Hellwig /* 4373e4e1d3fSChristoph Hellwig * DMA allocations for non-coherent devices use what the Arm architecture calls 4383e4e1d3fSChristoph Hellwig * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 4393e4e1d3fSChristoph Hellwig * and merging of writes. This is different from "Device-nGnR[nE]" memory which 4403e4e1d3fSChristoph Hellwig * is intended for MMIO and thus forbids speculation, preserves access size, 4413e4e1d3fSChristoph Hellwig * requires strict alignment and can also force write responses to come from the 4423e4e1d3fSChristoph Hellwig * endpoint. 4433e4e1d3fSChristoph Hellwig */ 444419e2f18SChristoph Hellwig #define pgprot_dmacoherent(prot) \ 445419e2f18SChristoph Hellwig __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 446419e2f18SChristoph Hellwig PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 447419e2f18SChristoph Hellwig 4484f04d8f0SCatalin Marinas #define __HAVE_PHYS_MEM_ACCESS_PROT 4494f04d8f0SCatalin Marinas struct file; 4504f04d8f0SCatalin Marinas extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 4514f04d8f0SCatalin Marinas unsigned long size, pgprot_t vma_prot); 4524f04d8f0SCatalin Marinas 4534f04d8f0SCatalin Marinas #define pmd_none(pmd) (!pmd_val(pmd)) 4544f04d8f0SCatalin Marinas 455ab4db1f2SCatalin Marinas #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT)) 4564f04d8f0SCatalin Marinas 45736311607SMarc Zyngier #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 45836311607SMarc Zyngier PMD_TYPE_TABLE) 45936311607SMarc Zyngier #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 46036311607SMarc Zyngier PMD_TYPE_SECT) 4618aa82df3SSteven Price #define pmd_leaf(pmd) pmd_sect(pmd) 46236311607SMarc Zyngier 463cac4b8cdSCatalin Marinas #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 4647d4e2dcfSQian Cai static inline bool pud_sect(pud_t pud) { return false; } 4657d4e2dcfSQian Cai static inline bool pud_table(pud_t pud) { return true; } 466206a2a73SSteve Capper #else 467206a2a73SSteve Capper #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 468206a2a73SSteve Capper PUD_TYPE_SECT) 469523d6e9fSzhichang.yuan #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 470523d6e9fSzhichang.yuan PUD_TYPE_TABLE) 471206a2a73SSteve Capper #endif 47236311607SMarc Zyngier 4732330b7caSJun Yao extern pgd_t init_pg_dir[PTRS_PER_PGD]; 4742330b7caSJun Yao extern pgd_t init_pg_end[]; 4752330b7caSJun Yao extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 4762330b7caSJun Yao extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 4779d2d75edSGavin Shan extern pgd_t idmap_pg_end[]; 4782330b7caSJun Yao extern pgd_t tramp_pg_dir[PTRS_PER_PGD]; 4792330b7caSJun Yao 4802330b7caSJun Yao extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 4812330b7caSJun Yao 4822330b7caSJun Yao static inline bool in_swapper_pgdir(void *addr) 4832330b7caSJun Yao { 4842330b7caSJun Yao return ((unsigned long)addr & PAGE_MASK) == 4852330b7caSJun Yao ((unsigned long)swapper_pg_dir & PAGE_MASK); 4862330b7caSJun Yao } 4872330b7caSJun Yao 4884f04d8f0SCatalin Marinas static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 4894f04d8f0SCatalin Marinas { 490e9ed821bSJames Morse #ifdef __PAGETABLE_PMD_FOLDED 491e9ed821bSJames Morse if (in_swapper_pgdir(pmdp)) { 4922330b7caSJun Yao set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 4932330b7caSJun Yao return; 4942330b7caSJun Yao } 495e9ed821bSJames Morse #endif /* __PAGETABLE_PMD_FOLDED */ 4962330b7caSJun Yao 49720a004e7SWill Deacon WRITE_ONCE(*pmdp, pmd); 4980795edafSWill Deacon 499d0b7a302SWill Deacon if (pmd_valid(pmd)) { 50098f7685eSWill Deacon dsb(ishst); 501d0b7a302SWill Deacon isb(); 502d0b7a302SWill Deacon } 5034f04d8f0SCatalin Marinas } 5044f04d8f0SCatalin Marinas 5054f04d8f0SCatalin Marinas static inline void pmd_clear(pmd_t *pmdp) 5064f04d8f0SCatalin Marinas { 5074f04d8f0SCatalin Marinas set_pmd(pmdp, __pmd(0)); 5084f04d8f0SCatalin Marinas } 5094f04d8f0SCatalin Marinas 510dca56dcaSMark Rutland static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 5114f04d8f0SCatalin Marinas { 51275387b92SKristina Martsenko return __pmd_to_phys(pmd); 5134f04d8f0SCatalin Marinas } 5144f04d8f0SCatalin Marinas 515974b9b2cSMike Rapoport static inline unsigned long pmd_page_vaddr(pmd_t pmd) 516974b9b2cSMike Rapoport { 517974b9b2cSMike Rapoport return (unsigned long)__va(pmd_page_paddr(pmd)); 518974b9b2cSMike Rapoport } 51974dd022fSQian Cai 520053520f7SMark Rutland /* Find an entry in the third-level page table. */ 521f069fabaSWill Deacon #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 522053520f7SMark Rutland 523961faac1SMark Rutland #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 524961faac1SMark Rutland #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 525961faac1SMark Rutland #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 526961faac1SMark Rutland 52768ecabd0SGavin Shan #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 5284f04d8f0SCatalin Marinas 5296533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 5306533945aSArd Biesheuvel #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 5316533945aSArd Biesheuvel 5324f04d8f0SCatalin Marinas /* 5334f04d8f0SCatalin Marinas * Conversion functions: convert a page and protection to a page entry, 5344f04d8f0SCatalin Marinas * and a page entry and page directory to the page they refer to. 5354f04d8f0SCatalin Marinas */ 5364f04d8f0SCatalin Marinas #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 5374f04d8f0SCatalin Marinas 5389f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 2 5394f04d8f0SCatalin Marinas 540*2cf660ebSGavin Shan #define pmd_ERROR(e) \ 541*2cf660ebSGavin Shan pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) 5427078db46SCatalin Marinas 5434f04d8f0SCatalin Marinas #define pud_none(pud) (!pud_val(pud)) 544ab4db1f2SCatalin Marinas #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT)) 545f02ab08aSPunit Agrawal #define pud_present(pud) pte_present(pud_pte(pud)) 5468aa82df3SSteven Price #define pud_leaf(pud) pud_sect(pud) 5470795edafSWill Deacon #define pud_valid(pud) pte_valid(pud_pte(pud)) 5484f04d8f0SCatalin Marinas 5494f04d8f0SCatalin Marinas static inline void set_pud(pud_t *pudp, pud_t pud) 5504f04d8f0SCatalin Marinas { 551e9ed821bSJames Morse #ifdef __PAGETABLE_PUD_FOLDED 552e9ed821bSJames Morse if (in_swapper_pgdir(pudp)) { 5532330b7caSJun Yao set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 5542330b7caSJun Yao return; 5552330b7caSJun Yao } 556e9ed821bSJames Morse #endif /* __PAGETABLE_PUD_FOLDED */ 5572330b7caSJun Yao 55820a004e7SWill Deacon WRITE_ONCE(*pudp, pud); 5590795edafSWill Deacon 560d0b7a302SWill Deacon if (pud_valid(pud)) { 56198f7685eSWill Deacon dsb(ishst); 562d0b7a302SWill Deacon isb(); 563d0b7a302SWill Deacon } 5644f04d8f0SCatalin Marinas } 5654f04d8f0SCatalin Marinas 5664f04d8f0SCatalin Marinas static inline void pud_clear(pud_t *pudp) 5674f04d8f0SCatalin Marinas { 5684f04d8f0SCatalin Marinas set_pud(pudp, __pud(0)); 5694f04d8f0SCatalin Marinas } 5704f04d8f0SCatalin Marinas 571dca56dcaSMark Rutland static inline phys_addr_t pud_page_paddr(pud_t pud) 5724f04d8f0SCatalin Marinas { 57375387b92SKristina Martsenko return __pud_to_phys(pud); 5744f04d8f0SCatalin Marinas } 5754f04d8f0SCatalin Marinas 576974b9b2cSMike Rapoport static inline unsigned long pud_page_vaddr(pud_t pud) 577974b9b2cSMike Rapoport { 578974b9b2cSMike Rapoport return (unsigned long)__va(pud_page_paddr(pud)); 579974b9b2cSMike Rapoport } 5807078db46SCatalin Marinas 581974b9b2cSMike Rapoport /* Find an entry in the second-level page table. */ 58220a004e7SWill Deacon #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 5837078db46SCatalin Marinas 584961faac1SMark Rutland #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 585961faac1SMark Rutland #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 586961faac1SMark Rutland #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 5874f04d8f0SCatalin Marinas 58868ecabd0SGavin Shan #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 58929e56940SSteve Capper 5906533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 5916533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 5926533945aSArd Biesheuvel 593dca56dcaSMark Rutland #else 594dca56dcaSMark Rutland 595dca56dcaSMark Rutland #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 596dca56dcaSMark Rutland 597961faac1SMark Rutland /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 598961faac1SMark Rutland #define pmd_set_fixmap(addr) NULL 599961faac1SMark Rutland #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 600961faac1SMark Rutland #define pmd_clear_fixmap() 601961faac1SMark Rutland 6026533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 6036533945aSArd Biesheuvel 6049f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 6054f04d8f0SCatalin Marinas 6069f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 3 607c79b954bSJungseok Lee 608*2cf660ebSGavin Shan #define pud_ERROR(e) \ 609*2cf660ebSGavin Shan pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) 6107078db46SCatalin Marinas 611e9f63768SMike Rapoport #define p4d_none(p4d) (!p4d_val(p4d)) 612e9f63768SMike Rapoport #define p4d_bad(p4d) (!(p4d_val(p4d) & 2)) 613e9f63768SMike Rapoport #define p4d_present(p4d) (p4d_val(p4d)) 614c79b954bSJungseok Lee 615e9f63768SMike Rapoport static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 616c79b954bSJungseok Lee { 617e9f63768SMike Rapoport if (in_swapper_pgdir(p4dp)) { 618e9f63768SMike Rapoport set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 6192330b7caSJun Yao return; 6202330b7caSJun Yao } 6212330b7caSJun Yao 622e9f63768SMike Rapoport WRITE_ONCE(*p4dp, p4d); 623c79b954bSJungseok Lee dsb(ishst); 624eb6a4dccSWill Deacon isb(); 625c79b954bSJungseok Lee } 626c79b954bSJungseok Lee 627e9f63768SMike Rapoport static inline void p4d_clear(p4d_t *p4dp) 628c79b954bSJungseok Lee { 629e9f63768SMike Rapoport set_p4d(p4dp, __p4d(0)); 630c79b954bSJungseok Lee } 631c79b954bSJungseok Lee 632e9f63768SMike Rapoport static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 633c79b954bSJungseok Lee { 634e9f63768SMike Rapoport return __p4d_to_phys(p4d); 635c79b954bSJungseok Lee } 636c79b954bSJungseok Lee 637974b9b2cSMike Rapoport static inline unsigned long p4d_page_vaddr(p4d_t p4d) 638974b9b2cSMike Rapoport { 639974b9b2cSMike Rapoport return (unsigned long)__va(p4d_page_paddr(p4d)); 640974b9b2cSMike Rapoport } 6417078db46SCatalin Marinas 642974b9b2cSMike Rapoport /* Find an entry in the frst-level page table. */ 643e9f63768SMike Rapoport #define pud_offset_phys(dir, addr) (p4d_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t)) 6447078db46SCatalin Marinas 645961faac1SMark Rutland #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) 646e9f63768SMike Rapoport #define pud_set_fixmap_offset(p4d, addr) pud_set_fixmap(pud_offset_phys(p4d, addr)) 647961faac1SMark Rutland #define pud_clear_fixmap() clear_fixmap(FIX_PUD) 648c79b954bSJungseok Lee 649e9f63768SMike Rapoport #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 6505d96e0cbSJungseok Lee 6516533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 6526533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) 6536533945aSArd Biesheuvel 654dca56dcaSMark Rutland #else 655dca56dcaSMark Rutland 656e9f63768SMike Rapoport #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 657dca56dcaSMark Rutland #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) 658dca56dcaSMark Rutland 659961faac1SMark Rutland /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 660961faac1SMark Rutland #define pud_set_fixmap(addr) NULL 661961faac1SMark Rutland #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 662961faac1SMark Rutland #define pud_clear_fixmap() 663961faac1SMark Rutland 6646533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 6656533945aSArd Biesheuvel 6669f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 667c79b954bSJungseok Lee 668*2cf660ebSGavin Shan #define pgd_ERROR(e) \ 669*2cf660ebSGavin Shan pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) 6707078db46SCatalin Marinas 671961faac1SMark Rutland #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 672961faac1SMark Rutland #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 673961faac1SMark Rutland 6744f04d8f0SCatalin Marinas static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 6754f04d8f0SCatalin Marinas { 676a6fadf7eSWill Deacon const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 6778ef8f360SDave Martin PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP; 6782f4b829cSCatalin Marinas /* preserve the hardware dirty information */ 6792f4b829cSCatalin Marinas if (pte_hw_dirty(pte)) 68062d96c71SCatalin Marinas pte = pte_mkdirty(pte); 6814f04d8f0SCatalin Marinas pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 6824f04d8f0SCatalin Marinas return pte; 6834f04d8f0SCatalin Marinas } 6844f04d8f0SCatalin Marinas 6859c7e535fSSteve Capper static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 6869c7e535fSSteve Capper { 6879c7e535fSSteve Capper return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 6889c7e535fSSteve Capper } 6899c7e535fSSteve Capper 69066dbd6e6SCatalin Marinas #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 69166dbd6e6SCatalin Marinas extern int ptep_set_access_flags(struct vm_area_struct *vma, 69266dbd6e6SCatalin Marinas unsigned long address, pte_t *ptep, 69366dbd6e6SCatalin Marinas pte_t entry, int dirty); 69466dbd6e6SCatalin Marinas 695282aa705SCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 696282aa705SCatalin Marinas #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 697282aa705SCatalin Marinas static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 698282aa705SCatalin Marinas unsigned long address, pmd_t *pmdp, 699282aa705SCatalin Marinas pmd_t entry, int dirty) 700282aa705SCatalin Marinas { 701282aa705SCatalin Marinas return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 702282aa705SCatalin Marinas } 70373b20c84SRobin Murphy 70473b20c84SRobin Murphy static inline int pud_devmap(pud_t pud) 70573b20c84SRobin Murphy { 70673b20c84SRobin Murphy return 0; 70773b20c84SRobin Murphy } 70873b20c84SRobin Murphy 70973b20c84SRobin Murphy static inline int pgd_devmap(pgd_t pgd) 71073b20c84SRobin Murphy { 71173b20c84SRobin Murphy return 0; 71273b20c84SRobin Murphy } 713282aa705SCatalin Marinas #endif 714282aa705SCatalin Marinas 7152f4b829cSCatalin Marinas /* 7162f4b829cSCatalin Marinas * Atomic pte/pmd modifications. 7172f4b829cSCatalin Marinas */ 7182f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 71906485053SCatalin Marinas static inline int __ptep_test_and_clear_young(pte_t *ptep) 7202f4b829cSCatalin Marinas { 7213bbf7157SCatalin Marinas pte_t old_pte, pte; 7222f4b829cSCatalin Marinas 7233bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 7243bbf7157SCatalin Marinas do { 7253bbf7157SCatalin Marinas old_pte = pte; 7263bbf7157SCatalin Marinas pte = pte_mkold(pte); 7273bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 7283bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 7293bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 7302f4b829cSCatalin Marinas 7313bbf7157SCatalin Marinas return pte_young(pte); 7322f4b829cSCatalin Marinas } 7332f4b829cSCatalin Marinas 73406485053SCatalin Marinas static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 73506485053SCatalin Marinas unsigned long address, 73606485053SCatalin Marinas pte_t *ptep) 73706485053SCatalin Marinas { 73806485053SCatalin Marinas return __ptep_test_and_clear_young(ptep); 73906485053SCatalin Marinas } 74006485053SCatalin Marinas 7413403e56bSAlex Van Brunt #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 7423403e56bSAlex Van Brunt static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 7433403e56bSAlex Van Brunt unsigned long address, pte_t *ptep) 7443403e56bSAlex Van Brunt { 7453403e56bSAlex Van Brunt int young = ptep_test_and_clear_young(vma, address, ptep); 7463403e56bSAlex Van Brunt 7473403e56bSAlex Van Brunt if (young) { 7483403e56bSAlex Van Brunt /* 7493403e56bSAlex Van Brunt * We can elide the trailing DSB here since the worst that can 7503403e56bSAlex Van Brunt * happen is that a CPU continues to use the young entry in its 7513403e56bSAlex Van Brunt * TLB and we mistakenly reclaim the associated page. The 7523403e56bSAlex Van Brunt * window for such an event is bounded by the next 7533403e56bSAlex Van Brunt * context-switch, which provides a DSB to complete the TLB 7543403e56bSAlex Van Brunt * invalidation. 7553403e56bSAlex Van Brunt */ 7563403e56bSAlex Van Brunt flush_tlb_page_nosync(vma, address); 7573403e56bSAlex Van Brunt } 7583403e56bSAlex Van Brunt 7593403e56bSAlex Van Brunt return young; 7603403e56bSAlex Van Brunt } 7613403e56bSAlex Van Brunt 7622f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 7632f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 7642f4b829cSCatalin Marinas static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 7652f4b829cSCatalin Marinas unsigned long address, 7662f4b829cSCatalin Marinas pmd_t *pmdp) 7672f4b829cSCatalin Marinas { 7682f4b829cSCatalin Marinas return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 7692f4b829cSCatalin Marinas } 7702f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 7712f4b829cSCatalin Marinas 7722f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 7732f4b829cSCatalin Marinas static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 7742f4b829cSCatalin Marinas unsigned long address, pte_t *ptep) 7752f4b829cSCatalin Marinas { 7763bbf7157SCatalin Marinas return __pte(xchg_relaxed(&pte_val(*ptep), 0)); 7772f4b829cSCatalin Marinas } 7782f4b829cSCatalin Marinas 7792f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 780911f56eeSCatalin Marinas #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 781911f56eeSCatalin Marinas static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 7822f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 7832f4b829cSCatalin Marinas { 7842f4b829cSCatalin Marinas return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); 7852f4b829cSCatalin Marinas } 7862f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 7872f4b829cSCatalin Marinas 7882f4b829cSCatalin Marinas /* 7898781bcbcSSteve Capper * ptep_set_wrprotect - mark read-only while trasferring potential hardware 7908781bcbcSSteve Capper * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 7912f4b829cSCatalin Marinas */ 7922f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_SET_WRPROTECT 7932f4b829cSCatalin Marinas static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 7942f4b829cSCatalin Marinas { 7953bbf7157SCatalin Marinas pte_t old_pte, pte; 7962f4b829cSCatalin Marinas 7973bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 7983bbf7157SCatalin Marinas do { 7993bbf7157SCatalin Marinas old_pte = pte; 8008781bcbcSSteve Capper /* 8018781bcbcSSteve Capper * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 8028781bcbcSSteve Capper * clear), set the PTE_DIRTY bit. 8038781bcbcSSteve Capper */ 8048781bcbcSSteve Capper if (pte_hw_dirty(pte)) 8058781bcbcSSteve Capper pte = pte_mkdirty(pte); 8063bbf7157SCatalin Marinas pte = pte_wrprotect(pte); 8073bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 8083bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 8093bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 8102f4b829cSCatalin Marinas } 8112f4b829cSCatalin Marinas 8122f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 8132f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_SET_WRPROTECT 8142f4b829cSCatalin Marinas static inline void pmdp_set_wrprotect(struct mm_struct *mm, 8152f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 8162f4b829cSCatalin Marinas { 8172f4b829cSCatalin Marinas ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 8182f4b829cSCatalin Marinas } 8191d78a62cSCatalin Marinas 8201d78a62cSCatalin Marinas #define pmdp_establish pmdp_establish 8211d78a62cSCatalin Marinas static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 8221d78a62cSCatalin Marinas unsigned long address, pmd_t *pmdp, pmd_t pmd) 8231d78a62cSCatalin Marinas { 8241d78a62cSCatalin Marinas return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 8251d78a62cSCatalin Marinas } 8262f4b829cSCatalin Marinas #endif 8272f4b829cSCatalin Marinas 8284f04d8f0SCatalin Marinas /* 8294f04d8f0SCatalin Marinas * Encode and decode a swap entry: 8303676f9efSCatalin Marinas * bits 0-1: present (must be zero) 8319b3e661eSKirill A. Shutemov * bits 2-7: swap type 8329b3e661eSKirill A. Shutemov * bits 8-57: swap offset 833fdc69e7dSCatalin Marinas * bit 58: PTE_PROT_NONE (must be zero) 8344f04d8f0SCatalin Marinas */ 8359b3e661eSKirill A. Shutemov #define __SWP_TYPE_SHIFT 2 8364f04d8f0SCatalin Marinas #define __SWP_TYPE_BITS 6 8379b3e661eSKirill A. Shutemov #define __SWP_OFFSET_BITS 50 8384f04d8f0SCatalin Marinas #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 8394f04d8f0SCatalin Marinas #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 8403676f9efSCatalin Marinas #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 8414f04d8f0SCatalin Marinas 8424f04d8f0SCatalin Marinas #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 8433676f9efSCatalin Marinas #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 8444f04d8f0SCatalin Marinas #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 8454f04d8f0SCatalin Marinas 8464f04d8f0SCatalin Marinas #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 8474f04d8f0SCatalin Marinas #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 8484f04d8f0SCatalin Marinas 8494f04d8f0SCatalin Marinas /* 8504f04d8f0SCatalin Marinas * Ensure that there are not more swap files than can be encoded in the kernel 851aad9061bSGeert Uytterhoeven * PTEs. 8524f04d8f0SCatalin Marinas */ 8534f04d8f0SCatalin Marinas #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 8544f04d8f0SCatalin Marinas 8554f04d8f0SCatalin Marinas extern int kern_addr_valid(unsigned long addr); 8564f04d8f0SCatalin Marinas 857cba3574fSWill Deacon /* 858cba3574fSWill Deacon * On AArch64, the cache coherency is handled via the set_pte_at() function. 859cba3574fSWill Deacon */ 860cba3574fSWill Deacon static inline void update_mmu_cache(struct vm_area_struct *vma, 861cba3574fSWill Deacon unsigned long addr, pte_t *ptep) 862cba3574fSWill Deacon { 863cba3574fSWill Deacon /* 864120798d2SWill Deacon * We don't do anything here, so there's a very small chance of 865120798d2SWill Deacon * us retaking a user fault which we just fixed up. The alternative 866120798d2SWill Deacon * is doing a dsb(ishst), but that penalises the fastpath. 867cba3574fSWill Deacon */ 868cba3574fSWill Deacon } 869cba3574fSWill Deacon 870cba3574fSWill Deacon #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 871cba3574fSWill Deacon 872529c4b05SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 873529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 874529c4b05SKristina Martsenko #else 875529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (addr) 876529c4b05SKristina Martsenko #endif 877529c4b05SKristina Martsenko 8786af31226SJia He /* 8796af31226SJia He * On arm64 without hardware Access Flag, copying from user will fail because 8806af31226SJia He * the pte is old and cannot be marked young. So we always end up with zeroed 8816af31226SJia He * page after fork() + CoW for pfn mappings. We don't always have a 8826af31226SJia He * hardware-managed access flag on arm64. 8836af31226SJia He */ 8846af31226SJia He static inline bool arch_faults_on_old_pte(void) 8856af31226SJia He { 8866af31226SJia He WARN_ON(preemptible()); 8876af31226SJia He 8886af31226SJia He return !cpu_has_hw_af(); 8896af31226SJia He } 8906af31226SJia He #define arch_faults_on_old_pte arch_faults_on_old_pte 8916af31226SJia He 8924f04d8f0SCatalin Marinas #endif /* !__ASSEMBLY__ */ 8934f04d8f0SCatalin Marinas 8944f04d8f0SCatalin Marinas #endif /* __ASM_PGTABLE_H */ 895