14f04d8f0SCatalin Marinas /* 24f04d8f0SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 34f04d8f0SCatalin Marinas * 44f04d8f0SCatalin Marinas * This program is free software; you can redistribute it and/or modify 54f04d8f0SCatalin Marinas * it under the terms of the GNU General Public License version 2 as 64f04d8f0SCatalin Marinas * published by the Free Software Foundation. 74f04d8f0SCatalin Marinas * 84f04d8f0SCatalin Marinas * This program is distributed in the hope that it will be useful, 94f04d8f0SCatalin Marinas * but WITHOUT ANY WARRANTY; without even the implied warranty of 104f04d8f0SCatalin Marinas * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 114f04d8f0SCatalin Marinas * GNU General Public License for more details. 124f04d8f0SCatalin Marinas * 134f04d8f0SCatalin Marinas * You should have received a copy of the GNU General Public License 144f04d8f0SCatalin Marinas * along with this program. If not, see <http://www.gnu.org/licenses/>. 154f04d8f0SCatalin Marinas */ 164f04d8f0SCatalin Marinas #ifndef __ASM_PGTABLE_H 174f04d8f0SCatalin Marinas #define __ASM_PGTABLE_H 184f04d8f0SCatalin Marinas 192f4b829cSCatalin Marinas #include <asm/bug.h> 204f04d8f0SCatalin Marinas #include <asm/proc-fns.h> 214f04d8f0SCatalin Marinas 224f04d8f0SCatalin Marinas #include <asm/memory.h> 234f04d8f0SCatalin Marinas #include <asm/pgtable-hwdef.h> 243eca86e7SMark Rutland #include <asm/pgtable-prot.h> 254f04d8f0SCatalin Marinas 264f04d8f0SCatalin Marinas /* 273e1907d5SArd Biesheuvel * VMALLOC range. 2808375198SCatalin Marinas * 29f9040773SArd Biesheuvel * VMALLOC_START: beginning of the kernel vmalloc space 303e1907d5SArd Biesheuvel * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space 313e1907d5SArd Biesheuvel * and fixed mappings 324f04d8f0SCatalin Marinas */ 33f9040773SArd Biesheuvel #define VMALLOC_START (MODULES_END) 3408375198SCatalin Marinas #define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K) 354f04d8f0SCatalin Marinas 363bab79edSArd Biesheuvel #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 374f04d8f0SCatalin Marinas 38d016bf7eSKirill A. Shutemov #define FIRST_USER_ADDRESS 0UL 394f04d8f0SCatalin Marinas 404f04d8f0SCatalin Marinas #ifndef __ASSEMBLY__ 412f4b829cSCatalin Marinas 423bbf7157SCatalin Marinas #include <asm/cmpxchg.h> 43961faac1SMark Rutland #include <asm/fixmap.h> 442f4b829cSCatalin Marinas #include <linux/mmdebug.h> 4586c9e812SWill Deacon #include <linux/mm_types.h> 4686c9e812SWill Deacon #include <linux/sched.h> 472f4b829cSCatalin Marinas 484f04d8f0SCatalin Marinas extern void __pte_error(const char *file, int line, unsigned long val); 494f04d8f0SCatalin Marinas extern void __pmd_error(const char *file, int line, unsigned long val); 50c79b954bSJungseok Lee extern void __pud_error(const char *file, int line, unsigned long val); 514f04d8f0SCatalin Marinas extern void __pgd_error(const char *file, int line, unsigned long val); 524f04d8f0SCatalin Marinas 534f04d8f0SCatalin Marinas /* 544f04d8f0SCatalin Marinas * ZERO_PAGE is a global shared page that is always zero: used 554f04d8f0SCatalin Marinas * for zero-mapped memory areas etc.. 564f04d8f0SCatalin Marinas */ 575227cfa7SMark Rutland extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 582077be67SLaura Abbott #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 594f04d8f0SCatalin Marinas 607078db46SCatalin Marinas #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) 617078db46SCatalin Marinas 6275387b92SKristina Martsenko /* 6375387b92SKristina Martsenko * Macros to convert between a physical address and its placement in a 6475387b92SKristina Martsenko * page table entry, taking care of 52-bit addresses. 6575387b92SKristina Martsenko */ 6675387b92SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 6775387b92SKristina Martsenko #define __pte_to_phys(pte) \ 6875387b92SKristina Martsenko ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36)) 6975387b92SKristina Martsenko #define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK) 7075387b92SKristina Martsenko #else 7175387b92SKristina Martsenko #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK) 7275387b92SKristina Martsenko #define __phys_to_pte_val(phys) (phys) 7375387b92SKristina Martsenko #endif 744f04d8f0SCatalin Marinas 7575387b92SKristina Martsenko #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 7675387b92SKristina Martsenko #define pfn_pte(pfn,prot) \ 7775387b92SKristina Martsenko __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 784f04d8f0SCatalin Marinas 794f04d8f0SCatalin Marinas #define pte_none(pte) (!pte_val(pte)) 804f04d8f0SCatalin Marinas #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 814f04d8f0SCatalin Marinas #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 827078db46SCatalin Marinas 834f04d8f0SCatalin Marinas /* 844f04d8f0SCatalin Marinas * The following only work if pte_present(). Undefined behaviour otherwise. 854f04d8f0SCatalin Marinas */ 8684fe6826SSteve Capper #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 8784fe6826SSteve Capper #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 8884fe6826SSteve Capper #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 8984fe6826SSteve Capper #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 90ec663d96SCatalin Marinas #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 9193ef666aSJeremy Linton #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 924f04d8f0SCatalin Marinas 93d27cfa1fSArd Biesheuvel #define pte_cont_addr_end(addr, end) \ 94d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 95d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 96d27cfa1fSArd Biesheuvel }) 97d27cfa1fSArd Biesheuvel 98d27cfa1fSArd Biesheuvel #define pmd_cont_addr_end(addr, end) \ 99d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 100d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 101d27cfa1fSArd Biesheuvel }) 102d27cfa1fSArd Biesheuvel 103b847415cSCatalin Marinas #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) 1042f4b829cSCatalin Marinas #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 1052f4b829cSCatalin Marinas #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 1062f4b829cSCatalin Marinas 107766ffb69SWill Deacon #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 108ec663d96SCatalin Marinas /* 109ec663d96SCatalin Marinas * Execute-only user mappings do not have the PTE_USER bit set. All valid 110ec663d96SCatalin Marinas * kernel mappings have the PTE_UXN bit set. 111ec663d96SCatalin Marinas */ 112ec663d96SCatalin Marinas #define pte_valid_not_user(pte) \ 113ec663d96SCatalin Marinas ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 11476c714beSWill Deacon #define pte_valid_young(pte) \ 11576c714beSWill Deacon ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF)) 1166218f96cSCatalin Marinas #define pte_valid_user(pte) \ 1176218f96cSCatalin Marinas ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) 11876c714beSWill Deacon 11976c714beSWill Deacon /* 12076c714beSWill Deacon * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 12176c714beSWill Deacon * so that we don't erroneously return false for pages that have been 12276c714beSWill Deacon * remapped as PROT_NONE but are yet to be flushed from the TLB. 12376c714beSWill Deacon */ 12476c714beSWill Deacon #define pte_accessible(mm, pte) \ 12576c714beSWill Deacon (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte)) 1264f04d8f0SCatalin Marinas 1276218f96cSCatalin Marinas /* 1286218f96cSCatalin Marinas * p??_access_permitted() is true for valid user mappings (subject to the 1296218f96cSCatalin Marinas * write permission check) other than user execute-only which do not have the 1306218f96cSCatalin Marinas * PTE_USER bit set. PROT_NONE mappings do not have the PTE_VALID bit set. 1316218f96cSCatalin Marinas */ 1326218f96cSCatalin Marinas #define pte_access_permitted(pte, write) \ 1336218f96cSCatalin Marinas (pte_valid_user(pte) && (!(write) || pte_write(pte))) 1346218f96cSCatalin Marinas #define pmd_access_permitted(pmd, write) \ 1356218f96cSCatalin Marinas (pte_access_permitted(pmd_pte(pmd), (write))) 1366218f96cSCatalin Marinas #define pud_access_permitted(pud, write) \ 1376218f96cSCatalin Marinas (pte_access_permitted(pud_pte(pud), (write))) 1386218f96cSCatalin Marinas 139b6d4f280SLaura Abbott static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 140b6d4f280SLaura Abbott { 141b6d4f280SLaura Abbott pte_val(pte) &= ~pgprot_val(prot); 142b6d4f280SLaura Abbott return pte; 143b6d4f280SLaura Abbott } 144b6d4f280SLaura Abbott 145b6d4f280SLaura Abbott static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 146b6d4f280SLaura Abbott { 147b6d4f280SLaura Abbott pte_val(pte) |= pgprot_val(prot); 148b6d4f280SLaura Abbott return pte; 149b6d4f280SLaura Abbott } 150b6d4f280SLaura Abbott 15144b6dfc5SSteve Capper static inline pte_t pte_wrprotect(pte_t pte) 15244b6dfc5SSteve Capper { 15373e86cb0SCatalin Marinas pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 15473e86cb0SCatalin Marinas pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 15573e86cb0SCatalin Marinas return pte; 15644b6dfc5SSteve Capper } 1574f04d8f0SCatalin Marinas 15844b6dfc5SSteve Capper static inline pte_t pte_mkwrite(pte_t pte) 15944b6dfc5SSteve Capper { 16073e86cb0SCatalin Marinas pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 16173e86cb0SCatalin Marinas pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 16273e86cb0SCatalin Marinas return pte; 16344b6dfc5SSteve Capper } 16444b6dfc5SSteve Capper 16544b6dfc5SSteve Capper static inline pte_t pte_mkclean(pte_t pte) 16644b6dfc5SSteve Capper { 1678781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 1688781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 1698781bcbcSSteve Capper 1708781bcbcSSteve Capper return pte; 17144b6dfc5SSteve Capper } 17244b6dfc5SSteve Capper 17344b6dfc5SSteve Capper static inline pte_t pte_mkdirty(pte_t pte) 17444b6dfc5SSteve Capper { 1758781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 1768781bcbcSSteve Capper 1778781bcbcSSteve Capper if (pte_write(pte)) 1788781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 1798781bcbcSSteve Capper 1808781bcbcSSteve Capper return pte; 18144b6dfc5SSteve Capper } 18244b6dfc5SSteve Capper 18344b6dfc5SSteve Capper static inline pte_t pte_mkold(pte_t pte) 18444b6dfc5SSteve Capper { 185b6d4f280SLaura Abbott return clear_pte_bit(pte, __pgprot(PTE_AF)); 18644b6dfc5SSteve Capper } 18744b6dfc5SSteve Capper 18844b6dfc5SSteve Capper static inline pte_t pte_mkyoung(pte_t pte) 18944b6dfc5SSteve Capper { 190b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_AF)); 19144b6dfc5SSteve Capper } 19244b6dfc5SSteve Capper 19344b6dfc5SSteve Capper static inline pte_t pte_mkspecial(pte_t pte) 19444b6dfc5SSteve Capper { 195b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 19644b6dfc5SSteve Capper } 1974f04d8f0SCatalin Marinas 19893ef666aSJeremy Linton static inline pte_t pte_mkcont(pte_t pte) 19993ef666aSJeremy Linton { 20066b3923aSDavid Woods pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 20166b3923aSDavid Woods return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 20293ef666aSJeremy Linton } 20393ef666aSJeremy Linton 20493ef666aSJeremy Linton static inline pte_t pte_mknoncont(pte_t pte) 20593ef666aSJeremy Linton { 20693ef666aSJeremy Linton return clear_pte_bit(pte, __pgprot(PTE_CONT)); 20793ef666aSJeremy Linton } 20893ef666aSJeremy Linton 2095ebe3a44SJames Morse static inline pte_t pte_mkpresent(pte_t pte) 2105ebe3a44SJames Morse { 2115ebe3a44SJames Morse return set_pte_bit(pte, __pgprot(PTE_VALID)); 2125ebe3a44SJames Morse } 2135ebe3a44SJames Morse 21466b3923aSDavid Woods static inline pmd_t pmd_mkcont(pmd_t pmd) 21566b3923aSDavid Woods { 21666b3923aSDavid Woods return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 21766b3923aSDavid Woods } 21866b3923aSDavid Woods 2194f04d8f0SCatalin Marinas static inline void set_pte(pte_t *ptep, pte_t pte) 2204f04d8f0SCatalin Marinas { 221*20a004e7SWill Deacon WRITE_ONCE(*ptep, pte); 2227f0b1bf0SCatalin Marinas 2237f0b1bf0SCatalin Marinas /* 2247f0b1bf0SCatalin Marinas * Only if the new pte is valid and kernel, otherwise TLB maintenance 2257f0b1bf0SCatalin Marinas * or update_mmu_cache() have the necessary barriers. 2267f0b1bf0SCatalin Marinas */ 227ec663d96SCatalin Marinas if (pte_valid_not_user(pte)) { 2287f0b1bf0SCatalin Marinas dsb(ishst); 2297f0b1bf0SCatalin Marinas isb(); 2307f0b1bf0SCatalin Marinas } 2314f04d8f0SCatalin Marinas } 2324f04d8f0SCatalin Marinas 2334f04d8f0SCatalin Marinas extern void __sync_icache_dcache(pte_t pteval, unsigned long addr); 2344f04d8f0SCatalin Marinas 2352f4b829cSCatalin Marinas /* 2362f4b829cSCatalin Marinas * PTE bits configuration in the presence of hardware Dirty Bit Management 2372f4b829cSCatalin Marinas * (PTE_WRITE == PTE_DBM): 2382f4b829cSCatalin Marinas * 2392f4b829cSCatalin Marinas * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 2402f4b829cSCatalin Marinas * 0 0 | 1 0 0 2412f4b829cSCatalin Marinas * 0 1 | 1 1 0 2422f4b829cSCatalin Marinas * 1 0 | 1 0 1 2432f4b829cSCatalin Marinas * 1 1 | 0 1 x 2442f4b829cSCatalin Marinas * 2452f4b829cSCatalin Marinas * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 2462f4b829cSCatalin Marinas * the page fault mechanism. Checking the dirty status of a pte becomes: 2472f4b829cSCatalin Marinas * 248b847415cSCatalin Marinas * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 2492f4b829cSCatalin Marinas */ 2504f04d8f0SCatalin Marinas static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 2514f04d8f0SCatalin Marinas pte_t *ptep, pte_t pte) 2524f04d8f0SCatalin Marinas { 253*20a004e7SWill Deacon pte_t old_pte; 254*20a004e7SWill Deacon 25573e86cb0SCatalin Marinas if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 256ac15bd63SCatalin Marinas __sync_icache_dcache(pte, addr); 25702522463SWill Deacon 2582f4b829cSCatalin Marinas /* 2592f4b829cSCatalin Marinas * If the existing pte is valid, check for potential race with 2602f4b829cSCatalin Marinas * hardware updates of the pte (ptep_set_access_flags safely changes 2612f4b829cSCatalin Marinas * valid ptes without going through an invalid entry). 2622f4b829cSCatalin Marinas */ 263*20a004e7SWill Deacon old_pte = READ_ONCE(*ptep); 264*20a004e7SWill Deacon if (IS_ENABLED(CONFIG_DEBUG_VM) && pte_valid(old_pte) && pte_valid(pte) && 26586c9e812SWill Deacon (mm == current->active_mm || atomic_read(&mm->mm_users) > 1)) { 26682d34008SCatalin Marinas VM_WARN_ONCE(!pte_young(pte), 26782d34008SCatalin Marinas "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 268*20a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 269*20a004e7SWill Deacon VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 27082d34008SCatalin Marinas "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 271*20a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 2722f4b829cSCatalin Marinas } 2732f4b829cSCatalin Marinas 2744f04d8f0SCatalin Marinas set_pte(ptep, pte); 2754f04d8f0SCatalin Marinas } 2764f04d8f0SCatalin Marinas 277747a70e6SSteve Capper #define __HAVE_ARCH_PTE_SAME 278747a70e6SSteve Capper static inline int pte_same(pte_t pte_a, pte_t pte_b) 279747a70e6SSteve Capper { 280747a70e6SSteve Capper pteval_t lhs, rhs; 281747a70e6SSteve Capper 282747a70e6SSteve Capper lhs = pte_val(pte_a); 283747a70e6SSteve Capper rhs = pte_val(pte_b); 284747a70e6SSteve Capper 285747a70e6SSteve Capper if (pte_present(pte_a)) 286747a70e6SSteve Capper lhs &= ~PTE_RDONLY; 287747a70e6SSteve Capper 288747a70e6SSteve Capper if (pte_present(pte_b)) 289747a70e6SSteve Capper rhs &= ~PTE_RDONLY; 290747a70e6SSteve Capper 291747a70e6SSteve Capper return (lhs == rhs); 292747a70e6SSteve Capper } 293747a70e6SSteve Capper 2944f04d8f0SCatalin Marinas /* 2954f04d8f0SCatalin Marinas * Huge pte definitions. 2964f04d8f0SCatalin Marinas */ 297084bd298SSteve Capper #define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT)) 298084bd298SSteve Capper #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 299084bd298SSteve Capper 300084bd298SSteve Capper /* 301084bd298SSteve Capper * Hugetlb definitions. 302084bd298SSteve Capper */ 30366b3923aSDavid Woods #define HUGE_MAX_HSTATE 4 304084bd298SSteve Capper #define HPAGE_SHIFT PMD_SHIFT 305084bd298SSteve Capper #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 306084bd298SSteve Capper #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 307084bd298SSteve Capper #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 3084f04d8f0SCatalin Marinas 3094f04d8f0SCatalin Marinas #define __HAVE_ARCH_PTE_SPECIAL 3104f04d8f0SCatalin Marinas 31175387b92SKristina Martsenko static inline pte_t pgd_pte(pgd_t pgd) 31275387b92SKristina Martsenko { 31375387b92SKristina Martsenko return __pte(pgd_val(pgd)); 31475387b92SKristina Martsenko } 31575387b92SKristina Martsenko 31629e56940SSteve Capper static inline pte_t pud_pte(pud_t pud) 31729e56940SSteve Capper { 31829e56940SSteve Capper return __pte(pud_val(pud)); 31929e56940SSteve Capper } 32029e56940SSteve Capper 32129e56940SSteve Capper static inline pmd_t pud_pmd(pud_t pud) 32229e56940SSteve Capper { 32329e56940SSteve Capper return __pmd(pud_val(pud)); 32429e56940SSteve Capper } 32529e56940SSteve Capper 3269c7e535fSSteve Capper static inline pte_t pmd_pte(pmd_t pmd) 3279c7e535fSSteve Capper { 3289c7e535fSSteve Capper return __pte(pmd_val(pmd)); 3299c7e535fSSteve Capper } 330af074848SSteve Capper 3319c7e535fSSteve Capper static inline pmd_t pte_pmd(pte_t pte) 3329c7e535fSSteve Capper { 3339c7e535fSSteve Capper return __pmd(pte_val(pte)); 3349c7e535fSSteve Capper } 335af074848SSteve Capper 3368ce837ceSArd Biesheuvel static inline pgprot_t mk_sect_prot(pgprot_t prot) 3378ce837ceSArd Biesheuvel { 3388ce837ceSArd Biesheuvel return __pgprot(pgprot_val(prot) & ~PTE_TABLE_BIT); 3398ce837ceSArd Biesheuvel } 3408ce837ceSArd Biesheuvel 34156166230SGanapatrao Kulkarni #ifdef CONFIG_NUMA_BALANCING 34256166230SGanapatrao Kulkarni /* 34356166230SGanapatrao Kulkarni * See the comment in include/asm-generic/pgtable.h 34456166230SGanapatrao Kulkarni */ 34556166230SGanapatrao Kulkarni static inline int pte_protnone(pte_t pte) 34656166230SGanapatrao Kulkarni { 34756166230SGanapatrao Kulkarni return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; 34856166230SGanapatrao Kulkarni } 34956166230SGanapatrao Kulkarni 35056166230SGanapatrao Kulkarni static inline int pmd_protnone(pmd_t pmd) 35156166230SGanapatrao Kulkarni { 35256166230SGanapatrao Kulkarni return pte_protnone(pmd_pte(pmd)); 35356166230SGanapatrao Kulkarni } 35456166230SGanapatrao Kulkarni #endif 35556166230SGanapatrao Kulkarni 356af074848SSteve Capper /* 357af074848SSteve Capper * THP definitions. 358af074848SSteve Capper */ 359af074848SSteve Capper 360af074848SSteve Capper #ifdef CONFIG_TRANSPARENT_HUGEPAGE 361af074848SSteve Capper #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) 36229e56940SSteve Capper #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 363af074848SSteve Capper 3645bb1cc0fSCatalin Marinas #define pmd_present(pmd) pte_present(pmd_pte(pmd)) 365c164e038SKirill A. Shutemov #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 3669c7e535fSSteve Capper #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 3679c7e535fSSteve Capper #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 3689c7e535fSSteve Capper #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 3699c7e535fSSteve Capper #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 37005ee26d9SMinchan Kim #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 3719c7e535fSSteve Capper #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 3729c7e535fSSteve Capper #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 3735bb1cc0fSCatalin Marinas #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_SECT_VALID)) 374af074848SSteve Capper 3750dbd3b18SSuzuki K Poulose #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 3760dbd3b18SSuzuki K Poulose 3779c7e535fSSteve Capper #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 378af074848SSteve Capper 379af074848SSteve Capper #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 380af074848SSteve Capper 38175387b92SKristina Martsenko #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 38275387b92SKristina Martsenko #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 38375387b92SKristina Martsenko #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 38475387b92SKristina Martsenko #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 385af074848SSteve Capper #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 386af074848SSteve Capper 38729e56940SSteve Capper #define pud_write(pud) pte_write(pud_pte(pud)) 38875387b92SKristina Martsenko 38975387b92SKristina Martsenko #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 39075387b92SKristina Martsenko #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 39175387b92SKristina Martsenko #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 39275387b92SKristina Martsenko #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 393af074848SSteve Capper 394ceb21835SWill Deacon #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) 395af074848SSteve Capper 39675387b92SKristina Martsenko #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 39775387b92SKristina Martsenko #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 39875387b92SKristina Martsenko 399a501e324SCatalin Marinas #define __pgprot_modify(prot,mask,bits) \ 400a501e324SCatalin Marinas __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 401a501e324SCatalin Marinas 402af074848SSteve Capper /* 4034f04d8f0SCatalin Marinas * Mark the prot value as uncacheable and unbufferable. 4044f04d8f0SCatalin Marinas */ 4054f04d8f0SCatalin Marinas #define pgprot_noncached(prot) \ 406de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 4074f04d8f0SCatalin Marinas #define pgprot_writecombine(prot) \ 408de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 409d1e6dc91SLiviu Dudau #define pgprot_device(prot) \ 410d1e6dc91SLiviu Dudau __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 4114f04d8f0SCatalin Marinas #define __HAVE_PHYS_MEM_ACCESS_PROT 4124f04d8f0SCatalin Marinas struct file; 4134f04d8f0SCatalin Marinas extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 4144f04d8f0SCatalin Marinas unsigned long size, pgprot_t vma_prot); 4154f04d8f0SCatalin Marinas 4164f04d8f0SCatalin Marinas #define pmd_none(pmd) (!pmd_val(pmd)) 4174f04d8f0SCatalin Marinas 418ab4db1f2SCatalin Marinas #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT)) 4194f04d8f0SCatalin Marinas 42036311607SMarc Zyngier #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 42136311607SMarc Zyngier PMD_TYPE_TABLE) 42236311607SMarc Zyngier #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 42336311607SMarc Zyngier PMD_TYPE_SECT) 42436311607SMarc Zyngier 425cac4b8cdSCatalin Marinas #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 426206a2a73SSteve Capper #define pud_sect(pud) (0) 427523d6e9fSzhichang.yuan #define pud_table(pud) (1) 428206a2a73SSteve Capper #else 429206a2a73SSteve Capper #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 430206a2a73SSteve Capper PUD_TYPE_SECT) 431523d6e9fSzhichang.yuan #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 432523d6e9fSzhichang.yuan PUD_TYPE_TABLE) 433206a2a73SSteve Capper #endif 43436311607SMarc Zyngier 4354f04d8f0SCatalin Marinas static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 4364f04d8f0SCatalin Marinas { 437*20a004e7SWill Deacon WRITE_ONCE(*pmdp, pmd); 43898f7685eSWill Deacon dsb(ishst); 4397f0b1bf0SCatalin Marinas isb(); 4404f04d8f0SCatalin Marinas } 4414f04d8f0SCatalin Marinas 4424f04d8f0SCatalin Marinas static inline void pmd_clear(pmd_t *pmdp) 4434f04d8f0SCatalin Marinas { 4444f04d8f0SCatalin Marinas set_pmd(pmdp, __pmd(0)); 4454f04d8f0SCatalin Marinas } 4464f04d8f0SCatalin Marinas 447dca56dcaSMark Rutland static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 4484f04d8f0SCatalin Marinas { 44975387b92SKristina Martsenko return __pmd_to_phys(pmd); 4504f04d8f0SCatalin Marinas } 4514f04d8f0SCatalin Marinas 452053520f7SMark Rutland /* Find an entry in the third-level page table. */ 453053520f7SMark Rutland #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 454053520f7SMark Rutland 455f069fabaSWill Deacon #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 456dca56dcaSMark Rutland #define pte_offset_kernel(dir,addr) ((pte_t *)__va(pte_offset_phys((dir), (addr)))) 457053520f7SMark Rutland 458053520f7SMark Rutland #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 459053520f7SMark Rutland #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr)) 460053520f7SMark Rutland #define pte_unmap(pte) do { } while (0) 461053520f7SMark Rutland #define pte_unmap_nested(pte) do { } while (0) 462053520f7SMark Rutland 463961faac1SMark Rutland #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 464961faac1SMark Rutland #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 465961faac1SMark Rutland #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 466961faac1SMark Rutland 46775387b92SKristina Martsenko #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(__pmd_to_phys(pmd))) 4684f04d8f0SCatalin Marinas 4696533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 4706533945aSArd Biesheuvel #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 4716533945aSArd Biesheuvel 4724f04d8f0SCatalin Marinas /* 4734f04d8f0SCatalin Marinas * Conversion functions: convert a page and protection to a page entry, 4744f04d8f0SCatalin Marinas * and a page entry and page directory to the page they refer to. 4754f04d8f0SCatalin Marinas */ 4764f04d8f0SCatalin Marinas #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 4774f04d8f0SCatalin Marinas 4789f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 2 4794f04d8f0SCatalin Marinas 4807078db46SCatalin Marinas #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) 4817078db46SCatalin Marinas 4824f04d8f0SCatalin Marinas #define pud_none(pud) (!pud_val(pud)) 483ab4db1f2SCatalin Marinas #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT)) 484f02ab08aSPunit Agrawal #define pud_present(pud) pte_present(pud_pte(pud)) 4854f04d8f0SCatalin Marinas 4864f04d8f0SCatalin Marinas static inline void set_pud(pud_t *pudp, pud_t pud) 4874f04d8f0SCatalin Marinas { 488*20a004e7SWill Deacon WRITE_ONCE(*pudp, pud); 48998f7685eSWill Deacon dsb(ishst); 4907f0b1bf0SCatalin Marinas isb(); 4914f04d8f0SCatalin Marinas } 4924f04d8f0SCatalin Marinas 4934f04d8f0SCatalin Marinas static inline void pud_clear(pud_t *pudp) 4944f04d8f0SCatalin Marinas { 4954f04d8f0SCatalin Marinas set_pud(pudp, __pud(0)); 4964f04d8f0SCatalin Marinas } 4974f04d8f0SCatalin Marinas 498dca56dcaSMark Rutland static inline phys_addr_t pud_page_paddr(pud_t pud) 4994f04d8f0SCatalin Marinas { 50075387b92SKristina Martsenko return __pud_to_phys(pud); 5014f04d8f0SCatalin Marinas } 5024f04d8f0SCatalin Marinas 5037078db46SCatalin Marinas /* Find an entry in the second-level page table. */ 5047078db46SCatalin Marinas #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) 5057078db46SCatalin Marinas 506*20a004e7SWill Deacon #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 507dca56dcaSMark Rutland #define pmd_offset(dir, addr) ((pmd_t *)__va(pmd_offset_phys((dir), (addr)))) 5087078db46SCatalin Marinas 509961faac1SMark Rutland #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 510961faac1SMark Rutland #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 511961faac1SMark Rutland #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 5124f04d8f0SCatalin Marinas 51375387b92SKristina Martsenko #define pud_page(pud) pfn_to_page(__phys_to_pfn(__pud_to_phys(pud))) 51429e56940SSteve Capper 5156533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 5166533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 5176533945aSArd Biesheuvel 518dca56dcaSMark Rutland #else 519dca56dcaSMark Rutland 520dca56dcaSMark Rutland #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 521dca56dcaSMark Rutland 522961faac1SMark Rutland /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 523961faac1SMark Rutland #define pmd_set_fixmap(addr) NULL 524961faac1SMark Rutland #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 525961faac1SMark Rutland #define pmd_clear_fixmap() 526961faac1SMark Rutland 5276533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 5286533945aSArd Biesheuvel 5299f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 5304f04d8f0SCatalin Marinas 5319f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 3 532c79b954bSJungseok Lee 5337078db46SCatalin Marinas #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud)) 5347078db46SCatalin Marinas 535c79b954bSJungseok Lee #define pgd_none(pgd) (!pgd_val(pgd)) 536c79b954bSJungseok Lee #define pgd_bad(pgd) (!(pgd_val(pgd) & 2)) 537c79b954bSJungseok Lee #define pgd_present(pgd) (pgd_val(pgd)) 538c79b954bSJungseok Lee 539c79b954bSJungseok Lee static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 540c79b954bSJungseok Lee { 541*20a004e7SWill Deacon WRITE_ONCE(*pgdp, pgd); 542c79b954bSJungseok Lee dsb(ishst); 543c79b954bSJungseok Lee } 544c79b954bSJungseok Lee 545c79b954bSJungseok Lee static inline void pgd_clear(pgd_t *pgdp) 546c79b954bSJungseok Lee { 547c79b954bSJungseok Lee set_pgd(pgdp, __pgd(0)); 548c79b954bSJungseok Lee } 549c79b954bSJungseok Lee 550dca56dcaSMark Rutland static inline phys_addr_t pgd_page_paddr(pgd_t pgd) 551c79b954bSJungseok Lee { 55275387b92SKristina Martsenko return __pgd_to_phys(pgd); 553c79b954bSJungseok Lee } 554c79b954bSJungseok Lee 5557078db46SCatalin Marinas /* Find an entry in the frst-level page table. */ 5567078db46SCatalin Marinas #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 5577078db46SCatalin Marinas 558*20a004e7SWill Deacon #define pud_offset_phys(dir, addr) (pgd_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t)) 559dca56dcaSMark Rutland #define pud_offset(dir, addr) ((pud_t *)__va(pud_offset_phys((dir), (addr)))) 5607078db46SCatalin Marinas 561961faac1SMark Rutland #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) 562961faac1SMark Rutland #define pud_set_fixmap_offset(pgd, addr) pud_set_fixmap(pud_offset_phys(pgd, addr)) 563961faac1SMark Rutland #define pud_clear_fixmap() clear_fixmap(FIX_PUD) 564c79b954bSJungseok Lee 56575387b92SKristina Martsenko #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd))) 5665d96e0cbSJungseok Lee 5676533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 5686533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) 5696533945aSArd Biesheuvel 570dca56dcaSMark Rutland #else 571dca56dcaSMark Rutland 572dca56dcaSMark Rutland #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) 573dca56dcaSMark Rutland 574961faac1SMark Rutland /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 575961faac1SMark Rutland #define pud_set_fixmap(addr) NULL 576961faac1SMark Rutland #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 577961faac1SMark Rutland #define pud_clear_fixmap() 578961faac1SMark Rutland 5796533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 5806533945aSArd Biesheuvel 5819f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 582c79b954bSJungseok Lee 5837078db46SCatalin Marinas #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) 5847078db46SCatalin Marinas 5854f04d8f0SCatalin Marinas /* to find an entry in a page-table-directory */ 5864f04d8f0SCatalin Marinas #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 5874f04d8f0SCatalin Marinas 588dca56dcaSMark Rutland #define pgd_offset_raw(pgd, addr) ((pgd) + pgd_index(addr)) 589dca56dcaSMark Rutland 590dca56dcaSMark Rutland #define pgd_offset(mm, addr) (pgd_offset_raw((mm)->pgd, (addr))) 5914f04d8f0SCatalin Marinas 5924f04d8f0SCatalin Marinas /* to find an entry in a kernel page-table-directory */ 5934f04d8f0SCatalin Marinas #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) 5944f04d8f0SCatalin Marinas 595961faac1SMark Rutland #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 596961faac1SMark Rutland #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 597961faac1SMark Rutland 5984f04d8f0SCatalin Marinas static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 5994f04d8f0SCatalin Marinas { 600a6fadf7eSWill Deacon const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 6011a541b4eSSteve Capper PTE_PROT_NONE | PTE_VALID | PTE_WRITE; 6022f4b829cSCatalin Marinas /* preserve the hardware dirty information */ 6032f4b829cSCatalin Marinas if (pte_hw_dirty(pte)) 60462d96c71SCatalin Marinas pte = pte_mkdirty(pte); 6054f04d8f0SCatalin Marinas pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 6064f04d8f0SCatalin Marinas return pte; 6074f04d8f0SCatalin Marinas } 6084f04d8f0SCatalin Marinas 6099c7e535fSSteve Capper static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 6109c7e535fSSteve Capper { 6119c7e535fSSteve Capper return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 6129c7e535fSSteve Capper } 6139c7e535fSSteve Capper 61466dbd6e6SCatalin Marinas #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 61566dbd6e6SCatalin Marinas extern int ptep_set_access_flags(struct vm_area_struct *vma, 61666dbd6e6SCatalin Marinas unsigned long address, pte_t *ptep, 61766dbd6e6SCatalin Marinas pte_t entry, int dirty); 61866dbd6e6SCatalin Marinas 619282aa705SCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 620282aa705SCatalin Marinas #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 621282aa705SCatalin Marinas static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 622282aa705SCatalin Marinas unsigned long address, pmd_t *pmdp, 623282aa705SCatalin Marinas pmd_t entry, int dirty) 624282aa705SCatalin Marinas { 625282aa705SCatalin Marinas return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 626282aa705SCatalin Marinas } 627282aa705SCatalin Marinas #endif 628282aa705SCatalin Marinas 6292f4b829cSCatalin Marinas /* 6302f4b829cSCatalin Marinas * Atomic pte/pmd modifications. 6312f4b829cSCatalin Marinas */ 6322f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 63306485053SCatalin Marinas static inline int __ptep_test_and_clear_young(pte_t *ptep) 6342f4b829cSCatalin Marinas { 6353bbf7157SCatalin Marinas pte_t old_pte, pte; 6362f4b829cSCatalin Marinas 6373bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 6383bbf7157SCatalin Marinas do { 6393bbf7157SCatalin Marinas old_pte = pte; 6403bbf7157SCatalin Marinas pte = pte_mkold(pte); 6413bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 6423bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 6433bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 6442f4b829cSCatalin Marinas 6453bbf7157SCatalin Marinas return pte_young(pte); 6462f4b829cSCatalin Marinas } 6472f4b829cSCatalin Marinas 64806485053SCatalin Marinas static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 64906485053SCatalin Marinas unsigned long address, 65006485053SCatalin Marinas pte_t *ptep) 65106485053SCatalin Marinas { 65206485053SCatalin Marinas return __ptep_test_and_clear_young(ptep); 65306485053SCatalin Marinas } 65406485053SCatalin Marinas 6552f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 6562f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 6572f4b829cSCatalin Marinas static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 6582f4b829cSCatalin Marinas unsigned long address, 6592f4b829cSCatalin Marinas pmd_t *pmdp) 6602f4b829cSCatalin Marinas { 6612f4b829cSCatalin Marinas return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 6622f4b829cSCatalin Marinas } 6632f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 6642f4b829cSCatalin Marinas 6652f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 6662f4b829cSCatalin Marinas static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 6672f4b829cSCatalin Marinas unsigned long address, pte_t *ptep) 6682f4b829cSCatalin Marinas { 6693bbf7157SCatalin Marinas return __pte(xchg_relaxed(&pte_val(*ptep), 0)); 6702f4b829cSCatalin Marinas } 6712f4b829cSCatalin Marinas 6722f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 673911f56eeSCatalin Marinas #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 674911f56eeSCatalin Marinas static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 6752f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 6762f4b829cSCatalin Marinas { 6772f4b829cSCatalin Marinas return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); 6782f4b829cSCatalin Marinas } 6792f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 6802f4b829cSCatalin Marinas 6812f4b829cSCatalin Marinas /* 6828781bcbcSSteve Capper * ptep_set_wrprotect - mark read-only while trasferring potential hardware 6838781bcbcSSteve Capper * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 6842f4b829cSCatalin Marinas */ 6852f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_SET_WRPROTECT 6862f4b829cSCatalin Marinas static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 6872f4b829cSCatalin Marinas { 6883bbf7157SCatalin Marinas pte_t old_pte, pte; 6892f4b829cSCatalin Marinas 6903bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 6913bbf7157SCatalin Marinas do { 6923bbf7157SCatalin Marinas old_pte = pte; 6938781bcbcSSteve Capper /* 6948781bcbcSSteve Capper * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 6958781bcbcSSteve Capper * clear), set the PTE_DIRTY bit. 6968781bcbcSSteve Capper */ 6978781bcbcSSteve Capper if (pte_hw_dirty(pte)) 6988781bcbcSSteve Capper pte = pte_mkdirty(pte); 6993bbf7157SCatalin Marinas pte = pte_wrprotect(pte); 7003bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 7013bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 7023bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 7032f4b829cSCatalin Marinas } 7042f4b829cSCatalin Marinas 7052f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 7062f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_SET_WRPROTECT 7072f4b829cSCatalin Marinas static inline void pmdp_set_wrprotect(struct mm_struct *mm, 7082f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 7092f4b829cSCatalin Marinas { 7102f4b829cSCatalin Marinas ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 7112f4b829cSCatalin Marinas } 7121d78a62cSCatalin Marinas 7131d78a62cSCatalin Marinas #define pmdp_establish pmdp_establish 7141d78a62cSCatalin Marinas static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 7151d78a62cSCatalin Marinas unsigned long address, pmd_t *pmdp, pmd_t pmd) 7161d78a62cSCatalin Marinas { 7171d78a62cSCatalin Marinas return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 7181d78a62cSCatalin Marinas } 7192f4b829cSCatalin Marinas #endif 7202f4b829cSCatalin Marinas 7214f04d8f0SCatalin Marinas extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 7220370b31eSSteve Capper extern pgd_t swapper_pg_end[]; 7234f04d8f0SCatalin Marinas extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 72451a0048bSWill Deacon extern pgd_t tramp_pg_dir[PTRS_PER_PGD]; 7254f04d8f0SCatalin Marinas 7264f04d8f0SCatalin Marinas /* 7274f04d8f0SCatalin Marinas * Encode and decode a swap entry: 7283676f9efSCatalin Marinas * bits 0-1: present (must be zero) 7299b3e661eSKirill A. Shutemov * bits 2-7: swap type 7309b3e661eSKirill A. Shutemov * bits 8-57: swap offset 731fdc69e7dSCatalin Marinas * bit 58: PTE_PROT_NONE (must be zero) 7324f04d8f0SCatalin Marinas */ 7339b3e661eSKirill A. Shutemov #define __SWP_TYPE_SHIFT 2 7344f04d8f0SCatalin Marinas #define __SWP_TYPE_BITS 6 7359b3e661eSKirill A. Shutemov #define __SWP_OFFSET_BITS 50 7364f04d8f0SCatalin Marinas #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 7374f04d8f0SCatalin Marinas #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 7383676f9efSCatalin Marinas #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 7394f04d8f0SCatalin Marinas 7404f04d8f0SCatalin Marinas #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 7413676f9efSCatalin Marinas #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 7424f04d8f0SCatalin Marinas #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 7434f04d8f0SCatalin Marinas 7444f04d8f0SCatalin Marinas #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 7454f04d8f0SCatalin Marinas #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 7464f04d8f0SCatalin Marinas 7474f04d8f0SCatalin Marinas /* 7484f04d8f0SCatalin Marinas * Ensure that there are not more swap files than can be encoded in the kernel 749aad9061bSGeert Uytterhoeven * PTEs. 7504f04d8f0SCatalin Marinas */ 7514f04d8f0SCatalin Marinas #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 7524f04d8f0SCatalin Marinas 7534f04d8f0SCatalin Marinas extern int kern_addr_valid(unsigned long addr); 7544f04d8f0SCatalin Marinas 7554f04d8f0SCatalin Marinas #include <asm-generic/pgtable.h> 7564f04d8f0SCatalin Marinas 75739b5be9bSWill Deacon void pgd_cache_init(void); 75839b5be9bSWill Deacon #define pgtable_cache_init pgd_cache_init 7594f04d8f0SCatalin Marinas 760cba3574fSWill Deacon /* 761cba3574fSWill Deacon * On AArch64, the cache coherency is handled via the set_pte_at() function. 762cba3574fSWill Deacon */ 763cba3574fSWill Deacon static inline void update_mmu_cache(struct vm_area_struct *vma, 764cba3574fSWill Deacon unsigned long addr, pte_t *ptep) 765cba3574fSWill Deacon { 766cba3574fSWill Deacon /* 767120798d2SWill Deacon * We don't do anything here, so there's a very small chance of 768120798d2SWill Deacon * us retaking a user fault which we just fixed up. The alternative 769120798d2SWill Deacon * is doing a dsb(ishst), but that penalises the fastpath. 770cba3574fSWill Deacon */ 771cba3574fSWill Deacon } 772cba3574fSWill Deacon 773cba3574fSWill Deacon #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 774cba3574fSWill Deacon 77503875ad5Syalin wang #define kc_vaddr_to_offset(v) ((v) & ~VA_START) 77603875ad5Syalin wang #define kc_offset_to_vaddr(o) ((o) | VA_START) 7777db743c6SCatalin Marinas 778529c4b05SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 779529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 780529c4b05SKristina Martsenko #else 781529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (addr) 782529c4b05SKristina Martsenko #endif 783529c4b05SKristina Martsenko 7844f04d8f0SCatalin Marinas #endif /* !__ASSEMBLY__ */ 7854f04d8f0SCatalin Marinas 7864f04d8f0SCatalin Marinas #endif /* __ASM_PGTABLE_H */ 787