1caab277bSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 24f04d8f0SCatalin Marinas /* 34f04d8f0SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 44f04d8f0SCatalin Marinas */ 54f04d8f0SCatalin Marinas #ifndef __ASM_PGTABLE_H 64f04d8f0SCatalin Marinas #define __ASM_PGTABLE_H 74f04d8f0SCatalin Marinas 82f4b829cSCatalin Marinas #include <asm/bug.h> 94f04d8f0SCatalin Marinas #include <asm/proc-fns.h> 104f04d8f0SCatalin Marinas 114f04d8f0SCatalin Marinas #include <asm/memory.h> 1234bfeea4SCatalin Marinas #include <asm/mte.h> 134f04d8f0SCatalin Marinas #include <asm/pgtable-hwdef.h> 143eca86e7SMark Rutland #include <asm/pgtable-prot.h> 153403e56bSAlex Van Brunt #include <asm/tlbflush.h> 164f04d8f0SCatalin Marinas 174f04d8f0SCatalin Marinas /* 183e1907d5SArd Biesheuvel * VMALLOC range. 1908375198SCatalin Marinas * 20f9040773SArd Biesheuvel * VMALLOC_START: beginning of the kernel vmalloc space 21d432b8d5SArd Biesheuvel * VMALLOC_END: extends to the available space below vmemmap 224f04d8f0SCatalin Marinas */ 23f9040773SArd Biesheuvel #define VMALLOC_START (MODULES_END) 24d432b8d5SArd Biesheuvel #if VA_BITS == VA_BITS_MIN 25b730b0f2SArd Biesheuvel #define VMALLOC_END (VMEMMAP_START - SZ_8M) 26d432b8d5SArd Biesheuvel #else 27d432b8d5SArd Biesheuvel #define VMEMMAP_UNUSED_NPAGES ((_PAGE_OFFSET(vabits_actual) - PAGE_OFFSET) >> PAGE_SHIFT) 28d432b8d5SArd Biesheuvel #define VMALLOC_END (VMEMMAP_START + VMEMMAP_UNUSED_NPAGES * sizeof(struct page) - SZ_8M) 29d432b8d5SArd Biesheuvel #endif 304f04d8f0SCatalin Marinas 317bc1a0f9SArd Biesheuvel #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 327bc1a0f9SArd Biesheuvel 334f04d8f0SCatalin Marinas #ifndef __ASSEMBLY__ 342f4b829cSCatalin Marinas 353bbf7157SCatalin Marinas #include <asm/cmpxchg.h> 36961faac1SMark Rutland #include <asm/fixmap.h> 372f4b829cSCatalin Marinas #include <linux/mmdebug.h> 3886c9e812SWill Deacon #include <linux/mm_types.h> 3986c9e812SWill Deacon #include <linux/sched.h> 4042b25471SKefeng Wang #include <linux/page_table_check.h> 412f4b829cSCatalin Marinas 42a7ac1cfaSZhenyu Ye #ifdef CONFIG_TRANSPARENT_HUGEPAGE 43a7ac1cfaSZhenyu Ye #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 44a7ac1cfaSZhenyu Ye 45a7ac1cfaSZhenyu Ye /* Set stride and tlb_level in flush_*_tlb_range */ 46a7ac1cfaSZhenyu Ye #define flush_pmd_tlb_range(vma, addr, end) \ 47a7ac1cfaSZhenyu Ye __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) 48a7ac1cfaSZhenyu Ye #define flush_pud_tlb_range(vma, addr, end) \ 49a7ac1cfaSZhenyu Ye __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) 50a7ac1cfaSZhenyu Ye #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 51a7ac1cfaSZhenyu Ye 52d0637c50SBarry Song static inline bool arch_thp_swp_supported(void) 53d0637c50SBarry Song { 54d0637c50SBarry Song return !system_supports_mte(); 55d0637c50SBarry Song } 56d0637c50SBarry Song #define arch_thp_swp_supported arch_thp_swp_supported 57d0637c50SBarry Song 584f04d8f0SCatalin Marinas /* 596a1bdb17SWill Deacon * Outside of a few very special situations (e.g. hibernation), we always 606a1bdb17SWill Deacon * use broadcast TLB invalidation instructions, therefore a spurious page 616a1bdb17SWill Deacon * fault on one CPU which has been handled concurrently by another CPU 626a1bdb17SWill Deacon * does not need to perform additional invalidation. 636a1bdb17SWill Deacon */ 6499c29133SGerald Schaefer #define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0) 656a1bdb17SWill Deacon 666a1bdb17SWill Deacon /* 674f04d8f0SCatalin Marinas * ZERO_PAGE is a global shared page that is always zero: used 684f04d8f0SCatalin Marinas * for zero-mapped memory areas etc.. 694f04d8f0SCatalin Marinas */ 705227cfa7SMark Rutland extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 712077be67SLaura Abbott #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 724f04d8f0SCatalin Marinas 732cf660ebSGavin Shan #define pte_ERROR(e) \ 742cf660ebSGavin Shan pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) 757078db46SCatalin Marinas 7675387b92SKristina Martsenko /* 7775387b92SKristina Martsenko * Macros to convert between a physical address and its placement in a 7875387b92SKristina Martsenko * page table entry, taking care of 52-bit addresses. 7975387b92SKristina Martsenko */ 8075387b92SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 81c7c386fbSArnd Bergmann static inline phys_addr_t __pte_to_phys(pte_t pte) 82c7c386fbSArnd Bergmann { 83925a0eb4SArd Biesheuvel pte_val(pte) &= ~PTE_MAYBE_SHARED; 84c7c386fbSArnd Bergmann return (pte_val(pte) & PTE_ADDR_LOW) | 85a4ee2861SAnshuman Khandual ((pte_val(pte) & PTE_ADDR_HIGH) << PTE_ADDR_HIGH_SHIFT); 86c7c386fbSArnd Bergmann } 87c7c386fbSArnd Bergmann static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 88c7c386fbSArnd Bergmann { 89925a0eb4SArd Biesheuvel return (phys | (phys >> PTE_ADDR_HIGH_SHIFT)) & PHYS_TO_PTE_ADDR_MASK; 90c7c386fbSArnd Bergmann } 9175387b92SKristina Martsenko #else 92925a0eb4SArd Biesheuvel #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_LOW) 9375387b92SKristina Martsenko #define __phys_to_pte_val(phys) (phys) 9475387b92SKristina Martsenko #endif 954f04d8f0SCatalin Marinas 9675387b92SKristina Martsenko #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 9775387b92SKristina Martsenko #define pfn_pte(pfn,prot) \ 9875387b92SKristina Martsenko __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 994f04d8f0SCatalin Marinas 1004f04d8f0SCatalin Marinas #define pte_none(pte) (!pte_val(pte)) 1015a00bfd6SRyan Roberts #define __pte_clear(mm, addr, ptep) \ 1025a00bfd6SRyan Roberts __set_pte(ptep, __pte(0)) 1034f04d8f0SCatalin Marinas #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 1047078db46SCatalin Marinas 1054f04d8f0SCatalin Marinas /* 1064f04d8f0SCatalin Marinas * The following only work if pte_present(). Undefined behaviour otherwise. 1074f04d8f0SCatalin Marinas */ 10884fe6826SSteve Capper #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 10984fe6826SSteve Capper #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 11084fe6826SSteve Capper #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 11184fe6826SSteve Capper #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 112d0ba9612SAnshuman Khandual #define pte_rdonly(pte) (!!(pte_val(pte) & PTE_RDONLY)) 11342b25471SKefeng Wang #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) 114ec663d96SCatalin Marinas #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 11593ef666aSJeremy Linton #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 11673b20c84SRobin Murphy #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 11734bfeea4SCatalin Marinas #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \ 11834bfeea4SCatalin Marinas PTE_ATTRINDX(MT_NORMAL_TAGGED)) 1194f04d8f0SCatalin Marinas 120d27cfa1fSArd Biesheuvel #define pte_cont_addr_end(addr, end) \ 121d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 122d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 123d27cfa1fSArd Biesheuvel }) 124d27cfa1fSArd Biesheuvel 125d27cfa1fSArd Biesheuvel #define pmd_cont_addr_end(addr, end) \ 126d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 127d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 128d27cfa1fSArd Biesheuvel }) 129d27cfa1fSArd Biesheuvel 130d0ba9612SAnshuman Khandual #define pte_hw_dirty(pte) (pte_write(pte) && !pte_rdonly(pte)) 1312f4b829cSCatalin Marinas #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 1322f4b829cSCatalin Marinas #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 1332f4b829cSCatalin Marinas 134766ffb69SWill Deacon #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 13518107f8aSVladimir Murzin /* 13618107f8aSVladimir Murzin * Execute-only user mappings do not have the PTE_USER bit set. All valid 13718107f8aSVladimir Murzin * kernel mappings have the PTE_UXN bit set. 13818107f8aSVladimir Murzin */ 139ec663d96SCatalin Marinas #define pte_valid_not_user(pte) \ 14018107f8aSVladimir Murzin ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 14176c714beSWill Deacon /* 1424602e575SRyan Roberts * Returns true if the pte is valid and has the contiguous bit set. 1434602e575SRyan Roberts */ 1444602e575SRyan Roberts #define pte_valid_cont(pte) (pte_valid(pte) && pte_cont(pte)) 1454602e575SRyan Roberts /* 14676c714beSWill Deacon * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 14776c714beSWill Deacon * so that we don't erroneously return false for pages that have been 14876c714beSWill Deacon * remapped as PROT_NONE but are yet to be flushed from the TLB. 14907509e10SWill Deacon * Note that we can't make any assumptions based on the state of the access 1505a00bfd6SRyan Roberts * flag, since __ptep_clear_flush_young() elides a DSB when invalidating the 15107509e10SWill Deacon * TLB. 15276c714beSWill Deacon */ 15376c714beSWill Deacon #define pte_accessible(mm, pte) \ 15407509e10SWill Deacon (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) 1554f04d8f0SCatalin Marinas 1566218f96cSCatalin Marinas /* 15718107f8aSVladimir Murzin * p??_access_permitted() is true for valid user mappings (PTE_USER 15818107f8aSVladimir Murzin * bit set, subject to the write permission check). For execute-only 15918107f8aSVladimir Murzin * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits 16018107f8aSVladimir Murzin * not set) must return false. PROT_NONE mappings do not have the 16118107f8aSVladimir Murzin * PTE_VALID bit set. 1626218f96cSCatalin Marinas */ 1636218f96cSCatalin Marinas #define pte_access_permitted(pte, write) \ 16418107f8aSVladimir Murzin (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte))) 1656218f96cSCatalin Marinas #define pmd_access_permitted(pmd, write) \ 1666218f96cSCatalin Marinas (pte_access_permitted(pmd_pte(pmd), (write))) 1676218f96cSCatalin Marinas #define pud_access_permitted(pud, write) \ 1686218f96cSCatalin Marinas (pte_access_permitted(pud_pte(pud), (write))) 1696218f96cSCatalin Marinas 170b6d4f280SLaura Abbott static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 171b6d4f280SLaura Abbott { 172b6d4f280SLaura Abbott pte_val(pte) &= ~pgprot_val(prot); 173b6d4f280SLaura Abbott return pte; 174b6d4f280SLaura Abbott } 175b6d4f280SLaura Abbott 176b6d4f280SLaura Abbott static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 177b6d4f280SLaura Abbott { 178b6d4f280SLaura Abbott pte_val(pte) |= pgprot_val(prot); 179b6d4f280SLaura Abbott return pte; 180b6d4f280SLaura Abbott } 181b6d4f280SLaura Abbott 182b65399f6SAnshuman Khandual static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 183b65399f6SAnshuman Khandual { 184b65399f6SAnshuman Khandual pmd_val(pmd) &= ~pgprot_val(prot); 185b65399f6SAnshuman Khandual return pmd; 186b65399f6SAnshuman Khandual } 187b65399f6SAnshuman Khandual 188b65399f6SAnshuman Khandual static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 189b65399f6SAnshuman Khandual { 190b65399f6SAnshuman Khandual pmd_val(pmd) |= pgprot_val(prot); 191b65399f6SAnshuman Khandual return pmd; 192b65399f6SAnshuman Khandual } 193b65399f6SAnshuman Khandual 1942f0584f3SRick Edgecombe static inline pte_t pte_mkwrite_novma(pte_t pte) 19544b6dfc5SSteve Capper { 19673e86cb0SCatalin Marinas pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 19773e86cb0SCatalin Marinas pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 19873e86cb0SCatalin Marinas return pte; 19944b6dfc5SSteve Capper } 20044b6dfc5SSteve Capper 20144b6dfc5SSteve Capper static inline pte_t pte_mkclean(pte_t pte) 20244b6dfc5SSteve Capper { 2038781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 2048781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 2058781bcbcSSteve Capper 2068781bcbcSSteve Capper return pte; 20744b6dfc5SSteve Capper } 20844b6dfc5SSteve Capper 20944b6dfc5SSteve Capper static inline pte_t pte_mkdirty(pte_t pte) 21044b6dfc5SSteve Capper { 2118781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 2128781bcbcSSteve Capper 2138781bcbcSSteve Capper if (pte_write(pte)) 2148781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 2158781bcbcSSteve Capper 2168781bcbcSSteve Capper return pte; 21744b6dfc5SSteve Capper } 21844b6dfc5SSteve Capper 219ff1712f9SWill Deacon static inline pte_t pte_wrprotect(pte_t pte) 220ff1712f9SWill Deacon { 221ff1712f9SWill Deacon /* 222ff1712f9SWill Deacon * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 223ff1712f9SWill Deacon * clear), set the PTE_DIRTY bit. 224ff1712f9SWill Deacon */ 225ff1712f9SWill Deacon if (pte_hw_dirty(pte)) 2266477c388SAnshuman Khandual pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 227ff1712f9SWill Deacon 228ff1712f9SWill Deacon pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 229ff1712f9SWill Deacon pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 230ff1712f9SWill Deacon return pte; 231ff1712f9SWill Deacon } 232ff1712f9SWill Deacon 23344b6dfc5SSteve Capper static inline pte_t pte_mkold(pte_t pte) 23444b6dfc5SSteve Capper { 235b6d4f280SLaura Abbott return clear_pte_bit(pte, __pgprot(PTE_AF)); 23644b6dfc5SSteve Capper } 23744b6dfc5SSteve Capper 23844b6dfc5SSteve Capper static inline pte_t pte_mkyoung(pte_t pte) 23944b6dfc5SSteve Capper { 240b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_AF)); 24144b6dfc5SSteve Capper } 24244b6dfc5SSteve Capper 24344b6dfc5SSteve Capper static inline pte_t pte_mkspecial(pte_t pte) 24444b6dfc5SSteve Capper { 245b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 24644b6dfc5SSteve Capper } 2474f04d8f0SCatalin Marinas 24893ef666aSJeremy Linton static inline pte_t pte_mkcont(pte_t pte) 24993ef666aSJeremy Linton { 25066b3923aSDavid Woods pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 25166b3923aSDavid Woods return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 25293ef666aSJeremy Linton } 25393ef666aSJeremy Linton 25493ef666aSJeremy Linton static inline pte_t pte_mknoncont(pte_t pte) 25593ef666aSJeremy Linton { 25693ef666aSJeremy Linton return clear_pte_bit(pte, __pgprot(PTE_CONT)); 25793ef666aSJeremy Linton } 25893ef666aSJeremy Linton 2595ebe3a44SJames Morse static inline pte_t pte_mkpresent(pte_t pte) 2605ebe3a44SJames Morse { 2615ebe3a44SJames Morse return set_pte_bit(pte, __pgprot(PTE_VALID)); 2625ebe3a44SJames Morse } 2635ebe3a44SJames Morse 26466b3923aSDavid Woods static inline pmd_t pmd_mkcont(pmd_t pmd) 26566b3923aSDavid Woods { 26666b3923aSDavid Woods return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 26766b3923aSDavid Woods } 26866b3923aSDavid Woods 26973b20c84SRobin Murphy static inline pte_t pte_mkdevmap(pte_t pte) 27073b20c84SRobin Murphy { 27130e23538SJia He return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 27273b20c84SRobin Murphy } 27373b20c84SRobin Murphy 2741fcb7ceaSRyan Roberts static inline void __set_pte_nosync(pte_t *ptep, pte_t pte) 2754f04d8f0SCatalin Marinas { 27620a004e7SWill Deacon WRITE_ONCE(*ptep, pte); 2771fcb7ceaSRyan Roberts } 2781fcb7ceaSRyan Roberts 2791fcb7ceaSRyan Roberts static inline void __set_pte(pte_t *ptep, pte_t pte) 2801fcb7ceaSRyan Roberts { 2811fcb7ceaSRyan Roberts __set_pte_nosync(ptep, pte); 2827f0b1bf0SCatalin Marinas 2837f0b1bf0SCatalin Marinas /* 2847f0b1bf0SCatalin Marinas * Only if the new pte is valid and kernel, otherwise TLB maintenance 2857f0b1bf0SCatalin Marinas * or update_mmu_cache() have the necessary barriers. 2867f0b1bf0SCatalin Marinas */ 287d0b7a302SWill Deacon if (pte_valid_not_user(pte)) { 2887f0b1bf0SCatalin Marinas dsb(ishst); 289d0b7a302SWill Deacon isb(); 290d0b7a302SWill Deacon } 2914f04d8f0SCatalin Marinas } 2924f04d8f0SCatalin Marinas 2935a00bfd6SRyan Roberts static inline pte_t __ptep_get(pte_t *ptep) 29453273655SRyan Roberts { 29553273655SRyan Roberts return READ_ONCE(*ptep); 29653273655SRyan Roberts } 29753273655SRyan Roberts 298907e21c1SShaokun Zhang extern void __sync_icache_dcache(pte_t pteval); 299004fc58fSAnshuman Khandual bool pgattr_change_is_safe(u64 old, u64 new); 3004f04d8f0SCatalin Marinas 3012f4b829cSCatalin Marinas /* 3022f4b829cSCatalin Marinas * PTE bits configuration in the presence of hardware Dirty Bit Management 3032f4b829cSCatalin Marinas * (PTE_WRITE == PTE_DBM): 3042f4b829cSCatalin Marinas * 3052f4b829cSCatalin Marinas * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 3062f4b829cSCatalin Marinas * 0 0 | 1 0 0 3072f4b829cSCatalin Marinas * 0 1 | 1 1 0 3082f4b829cSCatalin Marinas * 1 0 | 1 0 1 3092f4b829cSCatalin Marinas * 1 1 | 0 1 x 3102f4b829cSCatalin Marinas * 3112f4b829cSCatalin Marinas * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 3122f4b829cSCatalin Marinas * the page fault mechanism. Checking the dirty status of a pte becomes: 3132f4b829cSCatalin Marinas * 314b847415cSCatalin Marinas * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 3152f4b829cSCatalin Marinas */ 3169b604722SMark Rutland 317004fc58fSAnshuman Khandual static inline void __check_safe_pte_update(struct mm_struct *mm, pte_t *ptep, 3189b604722SMark Rutland pte_t pte) 3194f04d8f0SCatalin Marinas { 32020a004e7SWill Deacon pte_t old_pte; 32120a004e7SWill Deacon 3229b604722SMark Rutland if (!IS_ENABLED(CONFIG_DEBUG_VM)) 3239b604722SMark Rutland return; 3249b604722SMark Rutland 3255a00bfd6SRyan Roberts old_pte = __ptep_get(ptep); 3269b604722SMark Rutland 3279b604722SMark Rutland if (!pte_valid(old_pte) || !pte_valid(pte)) 3289b604722SMark Rutland return; 3299b604722SMark Rutland if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 3309b604722SMark Rutland return; 33102522463SWill Deacon 3322f4b829cSCatalin Marinas /* 3339b604722SMark Rutland * Check for potential race with hardware updates of the pte 3345a00bfd6SRyan Roberts * (__ptep_set_access_flags safely changes valid ptes without going 3359b604722SMark Rutland * through an invalid entry). 3362f4b829cSCatalin Marinas */ 33782d34008SCatalin Marinas VM_WARN_ONCE(!pte_young(pte), 33882d34008SCatalin Marinas "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 33920a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 34020a004e7SWill Deacon VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 34182d34008SCatalin Marinas "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 34220a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 343004fc58fSAnshuman Khandual VM_WARN_ONCE(!pgattr_change_is_safe(pte_val(old_pte), pte_val(pte)), 344004fc58fSAnshuman Khandual "%s: unsafe attribute change: 0x%016llx -> 0x%016llx", 345004fc58fSAnshuman Khandual __func__, pte_val(old_pte), pte_val(pte)); 3462f4b829cSCatalin Marinas } 3472f4b829cSCatalin Marinas 3483425cec4SRyan Roberts static inline void __sync_cache_and_tags(pte_t pte, unsigned int nr_pages) 3499b604722SMark Rutland { 3509b604722SMark Rutland if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 3519b604722SMark Rutland __sync_icache_dcache(pte); 3529b604722SMark Rutland 35369e3b846SSteven Price /* 35469e3b846SSteven Price * If the PTE would provide user space access to the tags associated 35569e3b846SSteven Price * with it then ensure that the MTE tags are synchronised. Although 35669e3b846SSteven Price * pte_access_permitted() returns false for exec only mappings, they 35769e3b846SSteven Price * don't expose tags (instruction fetches don't check tags). 35869e3b846SSteven Price */ 35969e3b846SSteven Price if (system_supports_mte() && pte_access_permitted(pte, false) && 360332c151cSPeter Collingbourne !pte_special(pte) && pte_tagged(pte)) 3613425cec4SRyan Roberts mte_sync_tags(pte, nr_pages); 3624f04d8f0SCatalin Marinas } 3634f04d8f0SCatalin Marinas 3646e8f5887SRyan Roberts /* 3656e8f5887SRyan Roberts * Select all bits except the pfn 3666e8f5887SRyan Roberts */ 3676e8f5887SRyan Roberts static inline pgprot_t pte_pgprot(pte_t pte) 3686e8f5887SRyan Roberts { 3696e8f5887SRyan Roberts unsigned long pfn = pte_pfn(pte); 3706e8f5887SRyan Roberts 3716e8f5887SRyan Roberts return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); 3726e8f5887SRyan Roberts } 3736e8f5887SRyan Roberts 374c1bd2b40SRyan Roberts #define pte_advance_pfn pte_advance_pfn 375c1bd2b40SRyan Roberts static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr) 3766e8f5887SRyan Roberts { 377c1bd2b40SRyan Roberts return pfn_pte(pte_pfn(pte) + nr, pte_pgprot(pte)); 3786e8f5887SRyan Roberts } 3796e8f5887SRyan Roberts 3805a00bfd6SRyan Roberts static inline void __set_ptes(struct mm_struct *mm, 381dba2ff49SCatalin Marinas unsigned long __always_unused addr, 3824a169d61SMatthew Wilcox (Oracle) pte_t *ptep, pte_t pte, unsigned int nr) 38342b25471SKefeng Wang { 3844a169d61SMatthew Wilcox (Oracle) page_table_check_ptes_set(mm, ptep, pte, nr); 3853425cec4SRyan Roberts __sync_cache_and_tags(pte, nr); 3864a169d61SMatthew Wilcox (Oracle) 3874a169d61SMatthew Wilcox (Oracle) for (;;) { 3883425cec4SRyan Roberts __check_safe_pte_update(mm, ptep, pte); 3895a00bfd6SRyan Roberts __set_pte(ptep, pte); 3904a169d61SMatthew Wilcox (Oracle) if (--nr == 0) 3914a169d61SMatthew Wilcox (Oracle) break; 3924a169d61SMatthew Wilcox (Oracle) ptep++; 393c1bd2b40SRyan Roberts pte = pte_advance_pfn(pte, 1); 39442b25471SKefeng Wang } 3954a169d61SMatthew Wilcox (Oracle) } 39642b25471SKefeng Wang 3974f04d8f0SCatalin Marinas /* 3984f04d8f0SCatalin Marinas * Huge pte definitions. 3994f04d8f0SCatalin Marinas */ 400084bd298SSteve Capper #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 401084bd298SSteve Capper 402084bd298SSteve Capper /* 403084bd298SSteve Capper * Hugetlb definitions. 404084bd298SSteve Capper */ 40566b3923aSDavid Woods #define HUGE_MAX_HSTATE 4 406084bd298SSteve Capper #define HPAGE_SHIFT PMD_SHIFT 407084bd298SSteve Capper #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 408084bd298SSteve Capper #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 409084bd298SSteve Capper #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 4104f04d8f0SCatalin Marinas 41175387b92SKristina Martsenko static inline pte_t pgd_pte(pgd_t pgd) 41275387b92SKristina Martsenko { 41375387b92SKristina Martsenko return __pte(pgd_val(pgd)); 41475387b92SKristina Martsenko } 41575387b92SKristina Martsenko 416e9f63768SMike Rapoport static inline pte_t p4d_pte(p4d_t p4d) 417e9f63768SMike Rapoport { 418e9f63768SMike Rapoport return __pte(p4d_val(p4d)); 419e9f63768SMike Rapoport } 420e9f63768SMike Rapoport 42129e56940SSteve Capper static inline pte_t pud_pte(pud_t pud) 42229e56940SSteve Capper { 42329e56940SSteve Capper return __pte(pud_val(pud)); 42429e56940SSteve Capper } 42529e56940SSteve Capper 426eb3f0624SPunit Agrawal static inline pud_t pte_pud(pte_t pte) 427eb3f0624SPunit Agrawal { 428eb3f0624SPunit Agrawal return __pud(pte_val(pte)); 429eb3f0624SPunit Agrawal } 430eb3f0624SPunit Agrawal 43129e56940SSteve Capper static inline pmd_t pud_pmd(pud_t pud) 43229e56940SSteve Capper { 43329e56940SSteve Capper return __pmd(pud_val(pud)); 43429e56940SSteve Capper } 43529e56940SSteve Capper 4369c7e535fSSteve Capper static inline pte_t pmd_pte(pmd_t pmd) 4379c7e535fSSteve Capper { 4389c7e535fSSteve Capper return __pte(pmd_val(pmd)); 4399c7e535fSSteve Capper } 440af074848SSteve Capper 4419c7e535fSSteve Capper static inline pmd_t pte_pmd(pte_t pte) 4429c7e535fSSteve Capper { 4439c7e535fSSteve Capper return __pmd(pte_val(pte)); 4449c7e535fSSteve Capper } 445af074848SSteve Capper 446f7f0097aSAnshuman Khandual static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 4478ce837ceSArd Biesheuvel { 448f7f0097aSAnshuman Khandual return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 449f7f0097aSAnshuman Khandual } 450f7f0097aSAnshuman Khandual 451f7f0097aSAnshuman Khandual static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 452f7f0097aSAnshuman Khandual { 453f7f0097aSAnshuman Khandual return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 4548ce837ceSArd Biesheuvel } 4558ce837ceSArd Biesheuvel 456570ef363SDavid Hildenbrand static inline pte_t pte_swp_mkexclusive(pte_t pte) 457570ef363SDavid Hildenbrand { 458570ef363SDavid Hildenbrand return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 459570ef363SDavid Hildenbrand } 460570ef363SDavid Hildenbrand 461570ef363SDavid Hildenbrand static inline int pte_swp_exclusive(pte_t pte) 462570ef363SDavid Hildenbrand { 463570ef363SDavid Hildenbrand return pte_val(pte) & PTE_SWP_EXCLUSIVE; 464570ef363SDavid Hildenbrand } 465570ef363SDavid Hildenbrand 466570ef363SDavid Hildenbrand static inline pte_t pte_swp_clear_exclusive(pte_t pte) 467570ef363SDavid Hildenbrand { 468570ef363SDavid Hildenbrand return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 469570ef363SDavid Hildenbrand } 470570ef363SDavid Hildenbrand 47156166230SGanapatrao Kulkarni #ifdef CONFIG_NUMA_BALANCING 47256166230SGanapatrao Kulkarni /* 473ca5999fdSMike Rapoport * See the comment in include/linux/pgtable.h 47456166230SGanapatrao Kulkarni */ 47556166230SGanapatrao Kulkarni static inline int pte_protnone(pte_t pte) 47656166230SGanapatrao Kulkarni { 47756166230SGanapatrao Kulkarni return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; 47856166230SGanapatrao Kulkarni } 47956166230SGanapatrao Kulkarni 48056166230SGanapatrao Kulkarni static inline int pmd_protnone(pmd_t pmd) 48156166230SGanapatrao Kulkarni { 48256166230SGanapatrao Kulkarni return pte_protnone(pmd_pte(pmd)); 48356166230SGanapatrao Kulkarni } 48456166230SGanapatrao Kulkarni #endif 48556166230SGanapatrao Kulkarni 486b65399f6SAnshuman Khandual #define pmd_present_invalid(pmd) (!!(pmd_val(pmd) & PMD_PRESENT_INVALID)) 487b65399f6SAnshuman Khandual 488b65399f6SAnshuman Khandual static inline int pmd_present(pmd_t pmd) 489b65399f6SAnshuman Khandual { 490b65399f6SAnshuman Khandual return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd); 491b65399f6SAnshuman Khandual } 492b65399f6SAnshuman Khandual 493af074848SSteve Capper /* 494af074848SSteve Capper * THP definitions. 495af074848SSteve Capper */ 496af074848SSteve Capper 497af074848SSteve Capper #ifdef CONFIG_TRANSPARENT_HUGEPAGE 498b65399f6SAnshuman Khandual static inline int pmd_trans_huge(pmd_t pmd) 499b65399f6SAnshuman Khandual { 500b65399f6SAnshuman Khandual return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT); 501b65399f6SAnshuman Khandual } 50229e56940SSteve Capper #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 503af074848SSteve Capper 504c164e038SKirill A. Shutemov #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 5059c7e535fSSteve Capper #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 5060795edafSWill Deacon #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 50742b25471SKefeng Wang #define pmd_user(pmd) pte_user(pmd_pte(pmd)) 50842b25471SKefeng Wang #define pmd_user_exec(pmd) pte_user_exec(pmd_pte(pmd)) 509d55863dbSPeter Zijlstra #define pmd_cont(pmd) pte_cont(pmd_pte(pmd)) 5109c7e535fSSteve Capper #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 5119c7e535fSSteve Capper #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 5122f0584f3SRick Edgecombe #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))) 51305ee26d9SMinchan Kim #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 5149c7e535fSSteve Capper #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 5159c7e535fSSteve Capper #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 516b65399f6SAnshuman Khandual 517b65399f6SAnshuman Khandual static inline pmd_t pmd_mkinvalid(pmd_t pmd) 518b65399f6SAnshuman Khandual { 519b65399f6SAnshuman Khandual pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID)); 520b65399f6SAnshuman Khandual pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID)); 521b65399f6SAnshuman Khandual 522b65399f6SAnshuman Khandual return pmd; 523b65399f6SAnshuman Khandual } 524af074848SSteve Capper 5250dbd3b18SSuzuki K Poulose #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 5260dbd3b18SSuzuki K Poulose 5279c7e535fSSteve Capper #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 528af074848SSteve Capper 529af074848SSteve Capper #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 530af074848SSteve Capper 53173b20c84SRobin Murphy #ifdef CONFIG_TRANSPARENT_HUGEPAGE 53273b20c84SRobin Murphy #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 53373b20c84SRobin Murphy #endif 53430e23538SJia He static inline pmd_t pmd_mkdevmap(pmd_t pmd) 53530e23538SJia He { 53630e23538SJia He return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 53730e23538SJia He } 53873b20c84SRobin Murphy 53975387b92SKristina Martsenko #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 54075387b92SKristina Martsenko #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 54175387b92SKristina Martsenko #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 54275387b92SKristina Martsenko #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 543af074848SSteve Capper #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 544af074848SSteve Capper 54535a63966SPunit Agrawal #define pud_young(pud) pte_young(pud_pte(pud)) 546eb3f0624SPunit Agrawal #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 54729e56940SSteve Capper #define pud_write(pud) pte_write(pud_pte(pud)) 54875387b92SKristina Martsenko 549b8e0ba7cSPunit Agrawal #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 550b8e0ba7cSPunit Agrawal 55175387b92SKristina Martsenko #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 55275387b92SKristina Martsenko #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 55375387b92SKristina Martsenko #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 55475387b92SKristina Martsenko #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 555af074848SSteve Capper 556dba2ff49SCatalin Marinas static inline void __set_pte_at(struct mm_struct *mm, 557dba2ff49SCatalin Marinas unsigned long __always_unused addr, 5583425cec4SRyan Roberts pte_t *ptep, pte_t pte, unsigned int nr) 5593425cec4SRyan Roberts { 5603425cec4SRyan Roberts __sync_cache_and_tags(pte, nr); 5613425cec4SRyan Roberts __check_safe_pte_update(mm, ptep, pte); 5625a00bfd6SRyan Roberts __set_pte(ptep, pte); 5633425cec4SRyan Roberts } 5643425cec4SRyan Roberts 56542b25471SKefeng Wang static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 56642b25471SKefeng Wang pmd_t *pmdp, pmd_t pmd) 56742b25471SKefeng Wang { 568a3b83713SKemeng Shi page_table_check_pmd_set(mm, pmdp, pmd); 5693425cec4SRyan Roberts return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd), 5703425cec4SRyan Roberts PMD_SIZE >> PAGE_SHIFT); 57142b25471SKefeng Wang } 57242b25471SKefeng Wang 57342b25471SKefeng Wang static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 57442b25471SKefeng Wang pud_t *pudp, pud_t pud) 57542b25471SKefeng Wang { 5766d144436SKemeng Shi page_table_check_pud_set(mm, pudp, pud); 5773425cec4SRyan Roberts return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud), 5783425cec4SRyan Roberts PUD_SIZE >> PAGE_SHIFT); 57942b25471SKefeng Wang } 580af074848SSteve Capper 581e9f63768SMike Rapoport #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 582e9f63768SMike Rapoport #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 583e9f63768SMike Rapoport 58475387b92SKristina Martsenko #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 58575387b92SKristina Martsenko #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 58675387b92SKristina Martsenko 587a501e324SCatalin Marinas #define __pgprot_modify(prot,mask,bits) \ 588a501e324SCatalin Marinas __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 589a501e324SCatalin Marinas 590cca98e9fSChristoph Hellwig #define pgprot_nx(prot) \ 591034aa9cdSWill Deacon __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 592cca98e9fSChristoph Hellwig 593af074848SSteve Capper /* 5944f04d8f0SCatalin Marinas * Mark the prot value as uncacheable and unbufferable. 5954f04d8f0SCatalin Marinas */ 5964f04d8f0SCatalin Marinas #define pgprot_noncached(prot) \ 597de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 5984f04d8f0SCatalin Marinas #define pgprot_writecombine(prot) \ 599de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 600d1e6dc91SLiviu Dudau #define pgprot_device(prot) \ 601d1e6dc91SLiviu Dudau __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 602d15dfd31SCatalin Marinas #define pgprot_tagged(prot) \ 603d15dfd31SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED)) 604d15dfd31SCatalin Marinas #define pgprot_mhp pgprot_tagged 6053e4e1d3fSChristoph Hellwig /* 6063e4e1d3fSChristoph Hellwig * DMA allocations for non-coherent devices use what the Arm architecture calls 6073e4e1d3fSChristoph Hellwig * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 6083e4e1d3fSChristoph Hellwig * and merging of writes. This is different from "Device-nGnR[nE]" memory which 6093e4e1d3fSChristoph Hellwig * is intended for MMIO and thus forbids speculation, preserves access size, 6103e4e1d3fSChristoph Hellwig * requires strict alignment and can also force write responses to come from the 6113e4e1d3fSChristoph Hellwig * endpoint. 6123e4e1d3fSChristoph Hellwig */ 613419e2f18SChristoph Hellwig #define pgprot_dmacoherent(prot) \ 614419e2f18SChristoph Hellwig __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 615419e2f18SChristoph Hellwig PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 616419e2f18SChristoph Hellwig 6174f04d8f0SCatalin Marinas #define __HAVE_PHYS_MEM_ACCESS_PROT 6184f04d8f0SCatalin Marinas struct file; 6194f04d8f0SCatalin Marinas extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 6204f04d8f0SCatalin Marinas unsigned long size, pgprot_t vma_prot); 6214f04d8f0SCatalin Marinas 6224f04d8f0SCatalin Marinas #define pmd_none(pmd) (!pmd_val(pmd)) 6234f04d8f0SCatalin Marinas 62436311607SMarc Zyngier #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 62536311607SMarc Zyngier PMD_TYPE_TABLE) 62636311607SMarc Zyngier #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 62736311607SMarc Zyngier PMD_TYPE_SECT) 62823bc8f69SMuchun Song #define pmd_leaf(pmd) (pmd_present(pmd) && !pmd_table(pmd)) 629e377ab82SAnshuman Khandual #define pmd_bad(pmd) (!pmd_table(pmd)) 63036311607SMarc Zyngier 631d55863dbSPeter Zijlstra #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE) 632d55863dbSPeter Zijlstra #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE) 633d55863dbSPeter Zijlstra 634cac4b8cdSCatalin Marinas #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 6357d4e2dcfSQian Cai static inline bool pud_sect(pud_t pud) { return false; } 6367d4e2dcfSQian Cai static inline bool pud_table(pud_t pud) { return true; } 637206a2a73SSteve Capper #else 638206a2a73SSteve Capper #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 639206a2a73SSteve Capper PUD_TYPE_SECT) 640523d6e9fSzhichang.yuan #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 641523d6e9fSzhichang.yuan PUD_TYPE_TABLE) 642206a2a73SSteve Capper #endif 64336311607SMarc Zyngier 6446ed8a3a0SArd Biesheuvel extern pgd_t init_pg_dir[]; 6452330b7caSJun Yao extern pgd_t init_pg_end[]; 6466ed8a3a0SArd Biesheuvel extern pgd_t swapper_pg_dir[]; 6476ed8a3a0SArd Biesheuvel extern pgd_t idmap_pg_dir[]; 6486ed8a3a0SArd Biesheuvel extern pgd_t tramp_pg_dir[]; 6496ed8a3a0SArd Biesheuvel extern pgd_t reserved_pg_dir[]; 6502330b7caSJun Yao 6512330b7caSJun Yao extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 6522330b7caSJun Yao 6532330b7caSJun Yao static inline bool in_swapper_pgdir(void *addr) 6542330b7caSJun Yao { 6552330b7caSJun Yao return ((unsigned long)addr & PAGE_MASK) == 6562330b7caSJun Yao ((unsigned long)swapper_pg_dir & PAGE_MASK); 6572330b7caSJun Yao } 6582330b7caSJun Yao 6594f04d8f0SCatalin Marinas static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 6604f04d8f0SCatalin Marinas { 661e9ed821bSJames Morse #ifdef __PAGETABLE_PMD_FOLDED 662e9ed821bSJames Morse if (in_swapper_pgdir(pmdp)) { 6632330b7caSJun Yao set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 6642330b7caSJun Yao return; 6652330b7caSJun Yao } 666e9ed821bSJames Morse #endif /* __PAGETABLE_PMD_FOLDED */ 6672330b7caSJun Yao 66820a004e7SWill Deacon WRITE_ONCE(*pmdp, pmd); 6690795edafSWill Deacon 670d0b7a302SWill Deacon if (pmd_valid(pmd)) { 67198f7685eSWill Deacon dsb(ishst); 672d0b7a302SWill Deacon isb(); 673d0b7a302SWill Deacon } 6744f04d8f0SCatalin Marinas } 6754f04d8f0SCatalin Marinas 6764f04d8f0SCatalin Marinas static inline void pmd_clear(pmd_t *pmdp) 6774f04d8f0SCatalin Marinas { 6784f04d8f0SCatalin Marinas set_pmd(pmdp, __pmd(0)); 6794f04d8f0SCatalin Marinas } 6804f04d8f0SCatalin Marinas 681dca56dcaSMark Rutland static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 6824f04d8f0SCatalin Marinas { 68375387b92SKristina Martsenko return __pmd_to_phys(pmd); 6844f04d8f0SCatalin Marinas } 6854f04d8f0SCatalin Marinas 686974b9b2cSMike Rapoport static inline unsigned long pmd_page_vaddr(pmd_t pmd) 687974b9b2cSMike Rapoport { 688974b9b2cSMike Rapoport return (unsigned long)__va(pmd_page_paddr(pmd)); 689974b9b2cSMike Rapoport } 69074dd022fSQian Cai 691053520f7SMark Rutland /* Find an entry in the third-level page table. */ 692f069fabaSWill Deacon #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 693053520f7SMark Rutland 694961faac1SMark Rutland #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 695961faac1SMark Rutland #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 696961faac1SMark Rutland #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 697961faac1SMark Rutland 69868ecabd0SGavin Shan #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 6994f04d8f0SCatalin Marinas 7006533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 7016533945aSArd Biesheuvel #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 7026533945aSArd Biesheuvel 7034f04d8f0SCatalin Marinas /* 7044f04d8f0SCatalin Marinas * Conversion functions: convert a page and protection to a page entry, 7054f04d8f0SCatalin Marinas * and a page entry and page directory to the page they refer to. 7064f04d8f0SCatalin Marinas */ 7074f04d8f0SCatalin Marinas #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 7084f04d8f0SCatalin Marinas 7099f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 2 7104f04d8f0SCatalin Marinas 7112cf660ebSGavin Shan #define pmd_ERROR(e) \ 7122cf660ebSGavin Shan pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) 7137078db46SCatalin Marinas 7144f04d8f0SCatalin Marinas #define pud_none(pud) (!pud_val(pud)) 715e377ab82SAnshuman Khandual #define pud_bad(pud) (!pud_table(pud)) 716f02ab08aSPunit Agrawal #define pud_present(pud) pte_present(pud_pte(pud)) 71723bc8f69SMuchun Song #define pud_leaf(pud) (pud_present(pud) && !pud_table(pud)) 7180795edafSWill Deacon #define pud_valid(pud) pte_valid(pud_pte(pud)) 71942b25471SKefeng Wang #define pud_user(pud) pte_user(pud_pte(pud)) 720730a11f9SLiu Shixin #define pud_user_exec(pud) pte_user_exec(pud_pte(pud)) 7214f04d8f0SCatalin Marinas 72290e636f6SArd Biesheuvel static inline bool pgtable_l4_enabled(void); 72390e636f6SArd Biesheuvel 7244f04d8f0SCatalin Marinas static inline void set_pud(pud_t *pudp, pud_t pud) 7254f04d8f0SCatalin Marinas { 72690e636f6SArd Biesheuvel if (!pgtable_l4_enabled() && in_swapper_pgdir(pudp)) { 7272330b7caSJun Yao set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 7282330b7caSJun Yao return; 7292330b7caSJun Yao } 7302330b7caSJun Yao 73120a004e7SWill Deacon WRITE_ONCE(*pudp, pud); 7320795edafSWill Deacon 733d0b7a302SWill Deacon if (pud_valid(pud)) { 73498f7685eSWill Deacon dsb(ishst); 735d0b7a302SWill Deacon isb(); 736d0b7a302SWill Deacon } 7374f04d8f0SCatalin Marinas } 7384f04d8f0SCatalin Marinas 7394f04d8f0SCatalin Marinas static inline void pud_clear(pud_t *pudp) 7404f04d8f0SCatalin Marinas { 7414f04d8f0SCatalin Marinas set_pud(pudp, __pud(0)); 7424f04d8f0SCatalin Marinas } 7434f04d8f0SCatalin Marinas 744dca56dcaSMark Rutland static inline phys_addr_t pud_page_paddr(pud_t pud) 7454f04d8f0SCatalin Marinas { 74675387b92SKristina Martsenko return __pud_to_phys(pud); 7474f04d8f0SCatalin Marinas } 7484f04d8f0SCatalin Marinas 7499cf6fa24SAneesh Kumar K.V static inline pmd_t *pud_pgtable(pud_t pud) 750974b9b2cSMike Rapoport { 7519cf6fa24SAneesh Kumar K.V return (pmd_t *)__va(pud_page_paddr(pud)); 752974b9b2cSMike Rapoport } 7537078db46SCatalin Marinas 754974b9b2cSMike Rapoport /* Find an entry in the second-level page table. */ 75520a004e7SWill Deacon #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 7567078db46SCatalin Marinas 757961faac1SMark Rutland #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 758961faac1SMark Rutland #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 759961faac1SMark Rutland #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 7604f04d8f0SCatalin Marinas 76168ecabd0SGavin Shan #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 76229e56940SSteve Capper 7636533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 7646533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 7656533945aSArd Biesheuvel 766dca56dcaSMark Rutland #else 767dca56dcaSMark Rutland 768dca56dcaSMark Rutland #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 7694e4ff23aSWill Deacon #define pud_user_exec(pud) pud_user(pud) /* Always 0 with folding */ 770dca56dcaSMark Rutland 771961faac1SMark Rutland /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 772961faac1SMark Rutland #define pmd_set_fixmap(addr) NULL 773961faac1SMark Rutland #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 774961faac1SMark Rutland #define pmd_clear_fixmap() 775961faac1SMark Rutland 7766533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 7776533945aSArd Biesheuvel 7789f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 7794f04d8f0SCatalin Marinas 7809f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 3 781c79b954bSJungseok Lee 7820dd4f60aSArd Biesheuvel static __always_inline bool pgtable_l4_enabled(void) 7830dd4f60aSArd Biesheuvel { 7840dd4f60aSArd Biesheuvel if (CONFIG_PGTABLE_LEVELS > 4 || !IS_ENABLED(CONFIG_ARM64_LPA2)) 7850dd4f60aSArd Biesheuvel return true; 7860dd4f60aSArd Biesheuvel if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 7870dd4f60aSArd Biesheuvel return vabits_actual == VA_BITS; 7880dd4f60aSArd Biesheuvel return alternative_has_cap_unlikely(ARM64_HAS_VA52); 7890dd4f60aSArd Biesheuvel } 7900dd4f60aSArd Biesheuvel 7910dd4f60aSArd Biesheuvel static inline bool mm_pud_folded(const struct mm_struct *mm) 7920dd4f60aSArd Biesheuvel { 7930dd4f60aSArd Biesheuvel return !pgtable_l4_enabled(); 7940dd4f60aSArd Biesheuvel } 7950dd4f60aSArd Biesheuvel #define mm_pud_folded mm_pud_folded 7960dd4f60aSArd Biesheuvel 7972cf660ebSGavin Shan #define pud_ERROR(e) \ 7982cf660ebSGavin Shan pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) 7997078db46SCatalin Marinas 8000dd4f60aSArd Biesheuvel #define p4d_none(p4d) (pgtable_l4_enabled() && !p4d_val(p4d)) 8010dd4f60aSArd Biesheuvel #define p4d_bad(p4d) (pgtable_l4_enabled() && !(p4d_val(p4d) & 2)) 8020dd4f60aSArd Biesheuvel #define p4d_present(p4d) (!p4d_none(p4d)) 803c79b954bSJungseok Lee 804e9f63768SMike Rapoport static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 805c79b954bSJungseok Lee { 806e9f63768SMike Rapoport if (in_swapper_pgdir(p4dp)) { 807e9f63768SMike Rapoport set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 8082330b7caSJun Yao return; 8092330b7caSJun Yao } 8102330b7caSJun Yao 811e9f63768SMike Rapoport WRITE_ONCE(*p4dp, p4d); 812c79b954bSJungseok Lee dsb(ishst); 813eb6a4dccSWill Deacon isb(); 814c79b954bSJungseok Lee } 815c79b954bSJungseok Lee 816e9f63768SMike Rapoport static inline void p4d_clear(p4d_t *p4dp) 817c79b954bSJungseok Lee { 8180dd4f60aSArd Biesheuvel if (pgtable_l4_enabled()) 819e9f63768SMike Rapoport set_p4d(p4dp, __p4d(0)); 820c79b954bSJungseok Lee } 821c79b954bSJungseok Lee 822e9f63768SMike Rapoport static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 823c79b954bSJungseok Lee { 824e9f63768SMike Rapoport return __p4d_to_phys(p4d); 825c79b954bSJungseok Lee } 826c79b954bSJungseok Lee 8270dd4f60aSArd Biesheuvel #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 8280dd4f60aSArd Biesheuvel 8290dd4f60aSArd Biesheuvel static inline pud_t *p4d_to_folded_pud(p4d_t *p4dp, unsigned long addr) 8300dd4f60aSArd Biesheuvel { 8310dd4f60aSArd Biesheuvel return (pud_t *)PTR_ALIGN_DOWN(p4dp, PAGE_SIZE) + pud_index(addr); 8320dd4f60aSArd Biesheuvel } 8330dd4f60aSArd Biesheuvel 834dc4875f0SAneesh Kumar K.V static inline pud_t *p4d_pgtable(p4d_t p4d) 835974b9b2cSMike Rapoport { 836dc4875f0SAneesh Kumar K.V return (pud_t *)__va(p4d_page_paddr(p4d)); 837974b9b2cSMike Rapoport } 8387078db46SCatalin Marinas 8390dd4f60aSArd Biesheuvel static inline phys_addr_t pud_offset_phys(p4d_t *p4dp, unsigned long addr) 8400dd4f60aSArd Biesheuvel { 8410dd4f60aSArd Biesheuvel BUG_ON(!pgtable_l4_enabled()); 8427078db46SCatalin Marinas 8430dd4f60aSArd Biesheuvel return p4d_page_paddr(READ_ONCE(*p4dp)) + pud_index(addr) * sizeof(pud_t); 8440dd4f60aSArd Biesheuvel } 8450dd4f60aSArd Biesheuvel 8460dd4f60aSArd Biesheuvel static inline 8470dd4f60aSArd Biesheuvel pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long addr) 8480dd4f60aSArd Biesheuvel { 8490dd4f60aSArd Biesheuvel if (!pgtable_l4_enabled()) 8500dd4f60aSArd Biesheuvel return p4d_to_folded_pud(p4dp, addr); 8510dd4f60aSArd Biesheuvel return (pud_t *)__va(p4d_page_paddr(p4d)) + pud_index(addr); 8520dd4f60aSArd Biesheuvel } 8530dd4f60aSArd Biesheuvel #define pud_offset_lockless pud_offset_lockless 8540dd4f60aSArd Biesheuvel 8550dd4f60aSArd Biesheuvel static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long addr) 8560dd4f60aSArd Biesheuvel { 8570dd4f60aSArd Biesheuvel return pud_offset_lockless(p4dp, READ_ONCE(*p4dp), addr); 8580dd4f60aSArd Biesheuvel } 8590dd4f60aSArd Biesheuvel #define pud_offset pud_offset 8600dd4f60aSArd Biesheuvel 8610dd4f60aSArd Biesheuvel static inline pud_t *pud_set_fixmap(unsigned long addr) 8620dd4f60aSArd Biesheuvel { 8630dd4f60aSArd Biesheuvel if (!pgtable_l4_enabled()) 8640dd4f60aSArd Biesheuvel return NULL; 8650dd4f60aSArd Biesheuvel return (pud_t *)set_fixmap_offset(FIX_PUD, addr); 8660dd4f60aSArd Biesheuvel } 8670dd4f60aSArd Biesheuvel 8680dd4f60aSArd Biesheuvel static inline pud_t *pud_set_fixmap_offset(p4d_t *p4dp, unsigned long addr) 8690dd4f60aSArd Biesheuvel { 8700dd4f60aSArd Biesheuvel if (!pgtable_l4_enabled()) 8710dd4f60aSArd Biesheuvel return p4d_to_folded_pud(p4dp, addr); 8720dd4f60aSArd Biesheuvel return pud_set_fixmap(pud_offset_phys(p4dp, addr)); 8730dd4f60aSArd Biesheuvel } 8740dd4f60aSArd Biesheuvel 8750dd4f60aSArd Biesheuvel static inline void pud_clear_fixmap(void) 8760dd4f60aSArd Biesheuvel { 8770dd4f60aSArd Biesheuvel if (pgtable_l4_enabled()) 8780dd4f60aSArd Biesheuvel clear_fixmap(FIX_PUD); 8790dd4f60aSArd Biesheuvel } 8800dd4f60aSArd Biesheuvel 8810dd4f60aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 8820dd4f60aSArd Biesheuvel static inline pud_t *pud_offset_kimg(p4d_t *p4dp, u64 addr) 8830dd4f60aSArd Biesheuvel { 8840dd4f60aSArd Biesheuvel if (!pgtable_l4_enabled()) 8850dd4f60aSArd Biesheuvel return p4d_to_folded_pud(p4dp, addr); 8860dd4f60aSArd Biesheuvel return (pud_t *)__phys_to_kimg(pud_offset_phys(p4dp, addr)); 8870dd4f60aSArd Biesheuvel } 888c79b954bSJungseok Lee 889e9f63768SMike Rapoport #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 8905d96e0cbSJungseok Lee 891dca56dcaSMark Rutland #else 892dca56dcaSMark Rutland 8930dd4f60aSArd Biesheuvel static inline bool pgtable_l4_enabled(void) { return false; } 8940dd4f60aSArd Biesheuvel 895e9f63768SMike Rapoport #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 896dca56dcaSMark Rutland 897961faac1SMark Rutland /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 898961faac1SMark Rutland #define pud_set_fixmap(addr) NULL 899961faac1SMark Rutland #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 900961faac1SMark Rutland #define pud_clear_fixmap() 901961faac1SMark Rutland 9026533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 9036533945aSArd Biesheuvel 9049f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 905c79b954bSJungseok Lee 906a6bbf5d4SArd Biesheuvel #if CONFIG_PGTABLE_LEVELS > 4 907a6bbf5d4SArd Biesheuvel 908a6bbf5d4SArd Biesheuvel static __always_inline bool pgtable_l5_enabled(void) 909a6bbf5d4SArd Biesheuvel { 910a6bbf5d4SArd Biesheuvel if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 911a6bbf5d4SArd Biesheuvel return vabits_actual == VA_BITS; 912a6bbf5d4SArd Biesheuvel return alternative_has_cap_unlikely(ARM64_HAS_VA52); 913a6bbf5d4SArd Biesheuvel } 914a6bbf5d4SArd Biesheuvel 915a6bbf5d4SArd Biesheuvel static inline bool mm_p4d_folded(const struct mm_struct *mm) 916a6bbf5d4SArd Biesheuvel { 917a6bbf5d4SArd Biesheuvel return !pgtable_l5_enabled(); 918a6bbf5d4SArd Biesheuvel } 919a6bbf5d4SArd Biesheuvel #define mm_p4d_folded mm_p4d_folded 920a6bbf5d4SArd Biesheuvel 921a6bbf5d4SArd Biesheuvel #define p4d_ERROR(e) \ 922a6bbf5d4SArd Biesheuvel pr_err("%s:%d: bad p4d %016llx.\n", __FILE__, __LINE__, p4d_val(e)) 923a6bbf5d4SArd Biesheuvel 924a6bbf5d4SArd Biesheuvel #define pgd_none(pgd) (pgtable_l5_enabled() && !pgd_val(pgd)) 925a6bbf5d4SArd Biesheuvel #define pgd_bad(pgd) (pgtable_l5_enabled() && !(pgd_val(pgd) & 2)) 926a6bbf5d4SArd Biesheuvel #define pgd_present(pgd) (!pgd_none(pgd)) 927a6bbf5d4SArd Biesheuvel 928a6bbf5d4SArd Biesheuvel static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 929a6bbf5d4SArd Biesheuvel { 930a6bbf5d4SArd Biesheuvel if (in_swapper_pgdir(pgdp)) { 931a6bbf5d4SArd Biesheuvel set_swapper_pgd(pgdp, __pgd(pgd_val(pgd))); 932a6bbf5d4SArd Biesheuvel return; 933a6bbf5d4SArd Biesheuvel } 934a6bbf5d4SArd Biesheuvel 935a6bbf5d4SArd Biesheuvel WRITE_ONCE(*pgdp, pgd); 936a6bbf5d4SArd Biesheuvel dsb(ishst); 937a6bbf5d4SArd Biesheuvel isb(); 938a6bbf5d4SArd Biesheuvel } 939a6bbf5d4SArd Biesheuvel 940a6bbf5d4SArd Biesheuvel static inline void pgd_clear(pgd_t *pgdp) 941a6bbf5d4SArd Biesheuvel { 942a6bbf5d4SArd Biesheuvel if (pgtable_l5_enabled()) 943a6bbf5d4SArd Biesheuvel set_pgd(pgdp, __pgd(0)); 944a6bbf5d4SArd Biesheuvel } 945a6bbf5d4SArd Biesheuvel 946a6bbf5d4SArd Biesheuvel static inline phys_addr_t pgd_page_paddr(pgd_t pgd) 947a6bbf5d4SArd Biesheuvel { 948a6bbf5d4SArd Biesheuvel return __pgd_to_phys(pgd); 949a6bbf5d4SArd Biesheuvel } 950a6bbf5d4SArd Biesheuvel 951a6bbf5d4SArd Biesheuvel #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 952a6bbf5d4SArd Biesheuvel 953a6bbf5d4SArd Biesheuvel static inline p4d_t *pgd_to_folded_p4d(pgd_t *pgdp, unsigned long addr) 954a6bbf5d4SArd Biesheuvel { 955a6bbf5d4SArd Biesheuvel return (p4d_t *)PTR_ALIGN_DOWN(pgdp, PAGE_SIZE) + p4d_index(addr); 956a6bbf5d4SArd Biesheuvel } 957a6bbf5d4SArd Biesheuvel 958a6bbf5d4SArd Biesheuvel static inline phys_addr_t p4d_offset_phys(pgd_t *pgdp, unsigned long addr) 959a6bbf5d4SArd Biesheuvel { 960a6bbf5d4SArd Biesheuvel BUG_ON(!pgtable_l5_enabled()); 961a6bbf5d4SArd Biesheuvel 962a6bbf5d4SArd Biesheuvel return pgd_page_paddr(READ_ONCE(*pgdp)) + p4d_index(addr) * sizeof(p4d_t); 963a6bbf5d4SArd Biesheuvel } 964a6bbf5d4SArd Biesheuvel 965a6bbf5d4SArd Biesheuvel static inline 966a6bbf5d4SArd Biesheuvel p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long addr) 967a6bbf5d4SArd Biesheuvel { 968a6bbf5d4SArd Biesheuvel if (!pgtable_l5_enabled()) 969a6bbf5d4SArd Biesheuvel return pgd_to_folded_p4d(pgdp, addr); 970a6bbf5d4SArd Biesheuvel return (p4d_t *)__va(pgd_page_paddr(pgd)) + p4d_index(addr); 971a6bbf5d4SArd Biesheuvel } 972a6bbf5d4SArd Biesheuvel #define p4d_offset_lockless p4d_offset_lockless 973a6bbf5d4SArd Biesheuvel 974a6bbf5d4SArd Biesheuvel static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long addr) 975a6bbf5d4SArd Biesheuvel { 976a6bbf5d4SArd Biesheuvel return p4d_offset_lockless(pgdp, READ_ONCE(*pgdp), addr); 977a6bbf5d4SArd Biesheuvel } 978a6bbf5d4SArd Biesheuvel 9796ed8a3a0SArd Biesheuvel static inline p4d_t *p4d_set_fixmap(unsigned long addr) 9806ed8a3a0SArd Biesheuvel { 9816ed8a3a0SArd Biesheuvel if (!pgtable_l5_enabled()) 9826ed8a3a0SArd Biesheuvel return NULL; 9836ed8a3a0SArd Biesheuvel return (p4d_t *)set_fixmap_offset(FIX_P4D, addr); 9846ed8a3a0SArd Biesheuvel } 9856ed8a3a0SArd Biesheuvel 9866ed8a3a0SArd Biesheuvel static inline p4d_t *p4d_set_fixmap_offset(pgd_t *pgdp, unsigned long addr) 9876ed8a3a0SArd Biesheuvel { 9886ed8a3a0SArd Biesheuvel if (!pgtable_l5_enabled()) 9896ed8a3a0SArd Biesheuvel return pgd_to_folded_p4d(pgdp, addr); 9906ed8a3a0SArd Biesheuvel return p4d_set_fixmap(p4d_offset_phys(pgdp, addr)); 9916ed8a3a0SArd Biesheuvel } 9926ed8a3a0SArd Biesheuvel 9936ed8a3a0SArd Biesheuvel static inline void p4d_clear_fixmap(void) 9946ed8a3a0SArd Biesheuvel { 9956ed8a3a0SArd Biesheuvel if (pgtable_l5_enabled()) 9966ed8a3a0SArd Biesheuvel clear_fixmap(FIX_P4D); 9976ed8a3a0SArd Biesheuvel } 9986ed8a3a0SArd Biesheuvel 9996ed8a3a0SArd Biesheuvel /* use ONLY for statically allocated translation tables */ 10006ed8a3a0SArd Biesheuvel static inline p4d_t *p4d_offset_kimg(pgd_t *pgdp, u64 addr) 10016ed8a3a0SArd Biesheuvel { 10026ed8a3a0SArd Biesheuvel if (!pgtable_l5_enabled()) 10036ed8a3a0SArd Biesheuvel return pgd_to_folded_p4d(pgdp, addr); 10046ed8a3a0SArd Biesheuvel return (p4d_t *)__phys_to_kimg(p4d_offset_phys(pgdp, addr)); 10056ed8a3a0SArd Biesheuvel } 10066ed8a3a0SArd Biesheuvel 1007a6bbf5d4SArd Biesheuvel #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd))) 1008a6bbf5d4SArd Biesheuvel 1009a6bbf5d4SArd Biesheuvel #else 1010a6bbf5d4SArd Biesheuvel 1011a6bbf5d4SArd Biesheuvel static inline bool pgtable_l5_enabled(void) { return false; } 1012a6bbf5d4SArd Biesheuvel 1013*0e9df1c9SRyan Roberts #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 1014*0e9df1c9SRyan Roberts 10156ed8a3a0SArd Biesheuvel /* Match p4d_offset folding in <asm/generic/pgtable-nop4d.h> */ 10166ed8a3a0SArd Biesheuvel #define p4d_set_fixmap(addr) NULL 10176ed8a3a0SArd Biesheuvel #define p4d_set_fixmap_offset(p4dp, addr) ((p4d_t *)p4dp) 10186ed8a3a0SArd Biesheuvel #define p4d_clear_fixmap() 10196ed8a3a0SArd Biesheuvel 10206ed8a3a0SArd Biesheuvel #define p4d_offset_kimg(dir,addr) ((p4d_t *)dir) 10216ed8a3a0SArd Biesheuvel 1022a6bbf5d4SArd Biesheuvel #endif /* CONFIG_PGTABLE_LEVELS > 4 */ 1023a6bbf5d4SArd Biesheuvel 10242cf660ebSGavin Shan #define pgd_ERROR(e) \ 10252cf660ebSGavin Shan pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) 10267078db46SCatalin Marinas 1027961faac1SMark Rutland #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 1028961faac1SMark Rutland #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 1029961faac1SMark Rutland 10304f04d8f0SCatalin Marinas static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 10314f04d8f0SCatalin Marinas { 10329f341931SCatalin Marinas /* 10339f341931SCatalin Marinas * Normal and Normal-Tagged are two different memory types and indices 10349f341931SCatalin Marinas * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK. 10359f341931SCatalin Marinas */ 1036a6fadf7eSWill Deacon const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 10379f341931SCatalin Marinas PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP | 10389f341931SCatalin Marinas PTE_ATTRINDX_MASK; 10392f4b829cSCatalin Marinas /* preserve the hardware dirty information */ 10402f4b829cSCatalin Marinas if (pte_hw_dirty(pte)) 10416477c388SAnshuman Khandual pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 10426477c388SAnshuman Khandual 10434f04d8f0SCatalin Marinas pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 10443c069607SJames Houghton /* 10453c069607SJames Houghton * If we end up clearing hw dirtiness for a sw-dirty PTE, set hardware 10463c069607SJames Houghton * dirtiness again. 10473c069607SJames Houghton */ 10483c069607SJames Houghton if (pte_sw_dirty(pte)) 10493c069607SJames Houghton pte = pte_mkdirty(pte); 10504f04d8f0SCatalin Marinas return pte; 10514f04d8f0SCatalin Marinas } 10524f04d8f0SCatalin Marinas 10539c7e535fSSteve Capper static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 10549c7e535fSSteve Capper { 10559c7e535fSSteve Capper return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 10569c7e535fSSteve Capper } 10579c7e535fSSteve Capper 10585a00bfd6SRyan Roberts extern int __ptep_set_access_flags(struct vm_area_struct *vma, 105966dbd6e6SCatalin Marinas unsigned long address, pte_t *ptep, 106066dbd6e6SCatalin Marinas pte_t entry, int dirty); 106166dbd6e6SCatalin Marinas 1062282aa705SCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1063282aa705SCatalin Marinas #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1064282aa705SCatalin Marinas static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1065282aa705SCatalin Marinas unsigned long address, pmd_t *pmdp, 1066282aa705SCatalin Marinas pmd_t entry, int dirty) 1067282aa705SCatalin Marinas { 10685a00bfd6SRyan Roberts return __ptep_set_access_flags(vma, address, (pte_t *)pmdp, 10695a00bfd6SRyan Roberts pmd_pte(entry), dirty); 1070282aa705SCatalin Marinas } 107173b20c84SRobin Murphy 107273b20c84SRobin Murphy static inline int pud_devmap(pud_t pud) 107373b20c84SRobin Murphy { 107473b20c84SRobin Murphy return 0; 107573b20c84SRobin Murphy } 107673b20c84SRobin Murphy 107773b20c84SRobin Murphy static inline int pgd_devmap(pgd_t pgd) 107873b20c84SRobin Murphy { 107973b20c84SRobin Murphy return 0; 108073b20c84SRobin Murphy } 1081282aa705SCatalin Marinas #endif 1082282aa705SCatalin Marinas 1083ed928a34STong Tiangen #ifdef CONFIG_PAGE_TABLE_CHECK 1084ed928a34STong Tiangen static inline bool pte_user_accessible_page(pte_t pte) 1085ed928a34STong Tiangen { 1086ed928a34STong Tiangen return pte_present(pte) && (pte_user(pte) || pte_user_exec(pte)); 1087ed928a34STong Tiangen } 1088ed928a34STong Tiangen 1089ed928a34STong Tiangen static inline bool pmd_user_accessible_page(pmd_t pmd) 1090ed928a34STong Tiangen { 109174c2f810SLiu Shixin return pmd_leaf(pmd) && !pmd_present_invalid(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd)); 1092ed928a34STong Tiangen } 1093ed928a34STong Tiangen 1094ed928a34STong Tiangen static inline bool pud_user_accessible_page(pud_t pud) 1095ed928a34STong Tiangen { 1096730a11f9SLiu Shixin return pud_leaf(pud) && (pud_user(pud) || pud_user_exec(pud)); 1097ed928a34STong Tiangen } 1098ed928a34STong Tiangen #endif 1099ed928a34STong Tiangen 11002f4b829cSCatalin Marinas /* 11012f4b829cSCatalin Marinas * Atomic pte/pmd modifications. 11022f4b829cSCatalin Marinas */ 11035a00bfd6SRyan Roberts static inline int __ptep_test_and_clear_young(struct vm_area_struct *vma, 11045a00bfd6SRyan Roberts unsigned long address, 11055a00bfd6SRyan Roberts pte_t *ptep) 11062f4b829cSCatalin Marinas { 11073bbf7157SCatalin Marinas pte_t old_pte, pte; 11082f4b829cSCatalin Marinas 11095a00bfd6SRyan Roberts pte = __ptep_get(ptep); 11103bbf7157SCatalin Marinas do { 11113bbf7157SCatalin Marinas old_pte = pte; 11123bbf7157SCatalin Marinas pte = pte_mkold(pte); 11133bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 11143bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 11153bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 11162f4b829cSCatalin Marinas 11173bbf7157SCatalin Marinas return pte_young(pte); 11182f4b829cSCatalin Marinas } 11192f4b829cSCatalin Marinas 11205a00bfd6SRyan Roberts static inline int __ptep_clear_flush_young(struct vm_area_struct *vma, 11213403e56bSAlex Van Brunt unsigned long address, pte_t *ptep) 11223403e56bSAlex Van Brunt { 11235a00bfd6SRyan Roberts int young = __ptep_test_and_clear_young(vma, address, ptep); 11243403e56bSAlex Van Brunt 11253403e56bSAlex Van Brunt if (young) { 11263403e56bSAlex Van Brunt /* 11273403e56bSAlex Van Brunt * We can elide the trailing DSB here since the worst that can 11283403e56bSAlex Van Brunt * happen is that a CPU continues to use the young entry in its 11293403e56bSAlex Van Brunt * TLB and we mistakenly reclaim the associated page. The 11303403e56bSAlex Van Brunt * window for such an event is bounded by the next 11313403e56bSAlex Van Brunt * context-switch, which provides a DSB to complete the TLB 11323403e56bSAlex Van Brunt * invalidation. 11333403e56bSAlex Van Brunt */ 11343403e56bSAlex Van Brunt flush_tlb_page_nosync(vma, address); 11353403e56bSAlex Van Brunt } 11363403e56bSAlex Van Brunt 11373403e56bSAlex Van Brunt return young; 11383403e56bSAlex Van Brunt } 11393403e56bSAlex Van Brunt 11402f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 11412f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 11422f4b829cSCatalin Marinas static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 11432f4b829cSCatalin Marinas unsigned long address, 11442f4b829cSCatalin Marinas pmd_t *pmdp) 11452f4b829cSCatalin Marinas { 11465a00bfd6SRyan Roberts return __ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 11472f4b829cSCatalin Marinas } 11482f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 11492f4b829cSCatalin Marinas 11505a00bfd6SRyan Roberts static inline pte_t __ptep_get_and_clear(struct mm_struct *mm, 11512f4b829cSCatalin Marinas unsigned long address, pte_t *ptep) 11522f4b829cSCatalin Marinas { 115342b25471SKefeng Wang pte_t pte = __pte(xchg_relaxed(&pte_val(*ptep), 0)); 115442b25471SKefeng Wang 1155aa232204SKemeng Shi page_table_check_pte_clear(mm, pte); 115642b25471SKefeng Wang 115742b25471SKefeng Wang return pte; 11582f4b829cSCatalin Marinas } 11592f4b829cSCatalin Marinas 11606b1e4efbSRyan Roberts static inline void __clear_full_ptes(struct mm_struct *mm, unsigned long addr, 11616b1e4efbSRyan Roberts pte_t *ptep, unsigned int nr, int full) 11626b1e4efbSRyan Roberts { 11636b1e4efbSRyan Roberts for (;;) { 11646b1e4efbSRyan Roberts __ptep_get_and_clear(mm, addr, ptep); 11656b1e4efbSRyan Roberts if (--nr == 0) 11666b1e4efbSRyan Roberts break; 11676b1e4efbSRyan Roberts ptep++; 11686b1e4efbSRyan Roberts addr += PAGE_SIZE; 11696b1e4efbSRyan Roberts } 11706b1e4efbSRyan Roberts } 11716b1e4efbSRyan Roberts 11726b1e4efbSRyan Roberts static inline pte_t __get_and_clear_full_ptes(struct mm_struct *mm, 11736b1e4efbSRyan Roberts unsigned long addr, pte_t *ptep, 11746b1e4efbSRyan Roberts unsigned int nr, int full) 11756b1e4efbSRyan Roberts { 11766b1e4efbSRyan Roberts pte_t pte, tmp_pte; 11776b1e4efbSRyan Roberts 11786b1e4efbSRyan Roberts pte = __ptep_get_and_clear(mm, addr, ptep); 11796b1e4efbSRyan Roberts while (--nr) { 11806b1e4efbSRyan Roberts ptep++; 11816b1e4efbSRyan Roberts addr += PAGE_SIZE; 11826b1e4efbSRyan Roberts tmp_pte = __ptep_get_and_clear(mm, addr, ptep); 11836b1e4efbSRyan Roberts if (pte_dirty(tmp_pte)) 11846b1e4efbSRyan Roberts pte = pte_mkdirty(pte); 11856b1e4efbSRyan Roberts if (pte_young(tmp_pte)) 11866b1e4efbSRyan Roberts pte = pte_mkyoung(pte); 11876b1e4efbSRyan Roberts } 11886b1e4efbSRyan Roberts return pte; 11896b1e4efbSRyan Roberts } 11906b1e4efbSRyan Roberts 11912f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1192911f56eeSCatalin Marinas #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1193911f56eeSCatalin Marinas static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 11942f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 11952f4b829cSCatalin Marinas { 119642b25471SKefeng Wang pmd_t pmd = __pmd(xchg_relaxed(&pmd_val(*pmdp), 0)); 119742b25471SKefeng Wang 11981831414cSKemeng Shi page_table_check_pmd_clear(mm, pmd); 119942b25471SKefeng Wang 120042b25471SKefeng Wang return pmd; 12012f4b829cSCatalin Marinas } 12022f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 12032f4b829cSCatalin Marinas 1204311a6cf2SRyan Roberts static inline void ___ptep_set_wrprotect(struct mm_struct *mm, 1205311a6cf2SRyan Roberts unsigned long address, pte_t *ptep, 1206311a6cf2SRyan Roberts pte_t pte) 12072f4b829cSCatalin Marinas { 1208311a6cf2SRyan Roberts pte_t old_pte; 12092f4b829cSCatalin Marinas 12103bbf7157SCatalin Marinas do { 12113bbf7157SCatalin Marinas old_pte = pte; 12123bbf7157SCatalin Marinas pte = pte_wrprotect(pte); 12133bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 12143bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 12153bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 12162f4b829cSCatalin Marinas } 12172f4b829cSCatalin Marinas 12182f4b829cSCatalin Marinas /* 12195a00bfd6SRyan Roberts * __ptep_set_wrprotect - mark read-only while trasferring potential hardware 12202f4b829cSCatalin Marinas * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 12212f4b829cSCatalin Marinas */ 12225a00bfd6SRyan Roberts static inline void __ptep_set_wrprotect(struct mm_struct *mm, 12235a00bfd6SRyan Roberts unsigned long address, pte_t *ptep) 12242f4b829cSCatalin Marinas { 1225311a6cf2SRyan Roberts ___ptep_set_wrprotect(mm, address, ptep, __ptep_get(ptep)); 1226311a6cf2SRyan Roberts } 12272f4b829cSCatalin Marinas 1228311a6cf2SRyan Roberts static inline void __wrprotect_ptes(struct mm_struct *mm, unsigned long address, 1229311a6cf2SRyan Roberts pte_t *ptep, unsigned int nr) 1230311a6cf2SRyan Roberts { 1231311a6cf2SRyan Roberts unsigned int i; 1232311a6cf2SRyan Roberts 1233311a6cf2SRyan Roberts for (i = 0; i < nr; i++, address += PAGE_SIZE, ptep++) 1234311a6cf2SRyan Roberts __ptep_set_wrprotect(mm, address, ptep); 12352f4b829cSCatalin Marinas } 12362f4b829cSCatalin Marinas 12372f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 12382f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_SET_WRPROTECT 12392f4b829cSCatalin Marinas static inline void pmdp_set_wrprotect(struct mm_struct *mm, 12402f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 12412f4b829cSCatalin Marinas { 12425a00bfd6SRyan Roberts __ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 12432f4b829cSCatalin Marinas } 12441d78a62cSCatalin Marinas 12451d78a62cSCatalin Marinas #define pmdp_establish pmdp_establish 12461d78a62cSCatalin Marinas static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 12471d78a62cSCatalin Marinas unsigned long address, pmd_t *pmdp, pmd_t pmd) 12481d78a62cSCatalin Marinas { 1249a3b83713SKemeng Shi page_table_check_pmd_set(vma->vm_mm, pmdp, pmd); 12501d78a62cSCatalin Marinas return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 12511d78a62cSCatalin Marinas } 12522f4b829cSCatalin Marinas #endif 12532f4b829cSCatalin Marinas 12544f04d8f0SCatalin Marinas /* 12554f04d8f0SCatalin Marinas * Encode and decode a swap entry: 12563676f9efSCatalin Marinas * bits 0-1: present (must be zero) 1257570ef363SDavid Hildenbrand * bits 2: remember PG_anon_exclusive 1258570ef363SDavid Hildenbrand * bits 3-7: swap type 12599b3e661eSKirill A. Shutemov * bits 8-57: swap offset 1260fdc69e7dSCatalin Marinas * bit 58: PTE_PROT_NONE (must be zero) 12614f04d8f0SCatalin Marinas */ 1262570ef363SDavid Hildenbrand #define __SWP_TYPE_SHIFT 3 1263570ef363SDavid Hildenbrand #define __SWP_TYPE_BITS 5 12649b3e661eSKirill A. Shutemov #define __SWP_OFFSET_BITS 50 12654f04d8f0SCatalin Marinas #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 12664f04d8f0SCatalin Marinas #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 12673676f9efSCatalin Marinas #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 12684f04d8f0SCatalin Marinas 12694f04d8f0SCatalin Marinas #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 12703676f9efSCatalin Marinas #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 12714f04d8f0SCatalin Marinas #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 12724f04d8f0SCatalin Marinas 12734f04d8f0SCatalin Marinas #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 12744f04d8f0SCatalin Marinas #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 12754f04d8f0SCatalin Marinas 127653fa117bSAnshuman Khandual #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 127753fa117bSAnshuman Khandual #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 127853fa117bSAnshuman Khandual #define __swp_entry_to_pmd(swp) __pmd((swp).val) 127953fa117bSAnshuman Khandual #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 128053fa117bSAnshuman Khandual 12814f04d8f0SCatalin Marinas /* 12824f04d8f0SCatalin Marinas * Ensure that there are not more swap files than can be encoded in the kernel 1283aad9061bSGeert Uytterhoeven * PTEs. 12844f04d8f0SCatalin Marinas */ 12854f04d8f0SCatalin Marinas #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 12864f04d8f0SCatalin Marinas 128736943abaSSteven Price #ifdef CONFIG_ARM64_MTE 128836943abaSSteven Price 128936943abaSSteven Price #define __HAVE_ARCH_PREPARE_TO_SWAP 129036943abaSSteven Price static inline int arch_prepare_to_swap(struct page *page) 129136943abaSSteven Price { 129236943abaSSteven Price if (system_supports_mte()) 129336943abaSSteven Price return mte_save_tags(page); 129436943abaSSteven Price return 0; 129536943abaSSteven Price } 129636943abaSSteven Price 129736943abaSSteven Price #define __HAVE_ARCH_SWAP_INVALIDATE 129836943abaSSteven Price static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 129936943abaSSteven Price { 130036943abaSSteven Price if (system_supports_mte()) 130136943abaSSteven Price mte_invalidate_tags(type, offset); 130236943abaSSteven Price } 130336943abaSSteven Price 130436943abaSSteven Price static inline void arch_swap_invalidate_area(int type) 130536943abaSSteven Price { 130636943abaSSteven Price if (system_supports_mte()) 130736943abaSSteven Price mte_invalidate_tags_area(type); 130836943abaSSteven Price } 130936943abaSSteven Price 131036943abaSSteven Price #define __HAVE_ARCH_SWAP_RESTORE 1311da08e9b7SMatthew Wilcox (Oracle) static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio) 131236943abaSSteven Price { 1313d77e59a8SCatalin Marinas if (system_supports_mte()) 1314d77e59a8SCatalin Marinas mte_restore_tags(entry, &folio->page); 131536943abaSSteven Price } 131636943abaSSteven Price 131736943abaSSteven Price #endif /* CONFIG_ARM64_MTE */ 131836943abaSSteven Price 1319cba3574fSWill Deacon /* 13205a00bfd6SRyan Roberts * On AArch64, the cache coherency is handled via the __set_ptes() function. 1321cba3574fSWill Deacon */ 13224a169d61SMatthew Wilcox (Oracle) static inline void update_mmu_cache_range(struct vm_fault *vmf, 13234a169d61SMatthew Wilcox (Oracle) struct vm_area_struct *vma, unsigned long addr, pte_t *ptep, 13244a169d61SMatthew Wilcox (Oracle) unsigned int nr) 1325cba3574fSWill Deacon { 1326cba3574fSWill Deacon /* 1327120798d2SWill Deacon * We don't do anything here, so there's a very small chance of 1328120798d2SWill Deacon * us retaking a user fault which we just fixed up. The alternative 1329120798d2SWill Deacon * is doing a dsb(ishst), but that penalises the fastpath. 1330cba3574fSWill Deacon */ 1331cba3574fSWill Deacon } 1332cba3574fSWill Deacon 13334a169d61SMatthew Wilcox (Oracle) #define update_mmu_cache(vma, addr, ptep) \ 13344a169d61SMatthew Wilcox (Oracle) update_mmu_cache_range(NULL, vma, addr, ptep, 1) 1335cba3574fSWill Deacon #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 1336cba3574fSWill Deacon 1337529c4b05SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 1338529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 1339529c4b05SKristina Martsenko #else 1340529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (addr) 1341529c4b05SKristina Martsenko #endif 1342529c4b05SKristina Martsenko 13436af31226SJia He /* 13446af31226SJia He * On arm64 without hardware Access Flag, copying from user will fail because 13456af31226SJia He * the pte is old and cannot be marked young. So we always end up with zeroed 13466af31226SJia He * page after fork() + CoW for pfn mappings. We don't always have a 13476af31226SJia He * hardware-managed access flag on arm64. 13486af31226SJia He */ 1349e1fd09e3SYu Zhao #define arch_has_hw_pte_young cpu_has_hw_af 13500388f9c7SWill Deacon 13510388f9c7SWill Deacon /* 13520388f9c7SWill Deacon * Experimentally, it's cheap to set the access flag in hardware and we 13530388f9c7SWill Deacon * benefit from prefaulting mappings as 'old' to start with. 13540388f9c7SWill Deacon */ 1355e1fd09e3SYu Zhao #define arch_wants_old_prefaulted_pte cpu_has_hw_af 13566af31226SJia He 1357f8b46c4bSAnshuman Khandual static inline bool pud_sect_supported(void) 1358f8b46c4bSAnshuman Khandual { 1359f8b46c4bSAnshuman Khandual return PAGE_SIZE == SZ_4K; 1360f8b46c4bSAnshuman Khandual } 1361f8b46c4bSAnshuman Khandual 136218107f8aSVladimir Murzin 13635db568e7SAnshuman Khandual #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 13645db568e7SAnshuman Khandual #define ptep_modify_prot_start ptep_modify_prot_start 13655db568e7SAnshuman Khandual extern pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 13665db568e7SAnshuman Khandual unsigned long addr, pte_t *ptep); 13675db568e7SAnshuman Khandual 13685db568e7SAnshuman Khandual #define ptep_modify_prot_commit ptep_modify_prot_commit 13695db568e7SAnshuman Khandual extern void ptep_modify_prot_commit(struct vm_area_struct *vma, 13705db568e7SAnshuman Khandual unsigned long addr, pte_t *ptep, 13715db568e7SAnshuman Khandual pte_t old_pte, pte_t new_pte); 13725a00bfd6SRyan Roberts 13734602e575SRyan Roberts #ifdef CONFIG_ARM64_CONTPTE 13744602e575SRyan Roberts 13754602e575SRyan Roberts /* 13764602e575SRyan Roberts * The contpte APIs are used to transparently manage the contiguous bit in ptes 13774602e575SRyan Roberts * where it is possible and makes sense to do so. The PTE_CONT bit is considered 13784602e575SRyan Roberts * a private implementation detail of the public ptep API (see below). 13794602e575SRyan Roberts */ 1380f0c22649SRyan Roberts extern void __contpte_try_fold(struct mm_struct *mm, unsigned long addr, 1381f0c22649SRyan Roberts pte_t *ptep, pte_t pte); 13824602e575SRyan Roberts extern void __contpte_try_unfold(struct mm_struct *mm, unsigned long addr, 13834602e575SRyan Roberts pte_t *ptep, pte_t pte); 13844602e575SRyan Roberts extern pte_t contpte_ptep_get(pte_t *ptep, pte_t orig_pte); 13854602e575SRyan Roberts extern pte_t contpte_ptep_get_lockless(pte_t *orig_ptep); 13864602e575SRyan Roberts extern void contpte_set_ptes(struct mm_struct *mm, unsigned long addr, 13874602e575SRyan Roberts pte_t *ptep, pte_t pte, unsigned int nr); 13886b1e4efbSRyan Roberts extern void contpte_clear_full_ptes(struct mm_struct *mm, unsigned long addr, 13896b1e4efbSRyan Roberts pte_t *ptep, unsigned int nr, int full); 13906b1e4efbSRyan Roberts extern pte_t contpte_get_and_clear_full_ptes(struct mm_struct *mm, 13916b1e4efbSRyan Roberts unsigned long addr, pte_t *ptep, 13926b1e4efbSRyan Roberts unsigned int nr, int full); 13934602e575SRyan Roberts extern int contpte_ptep_test_and_clear_young(struct vm_area_struct *vma, 13944602e575SRyan Roberts unsigned long addr, pte_t *ptep); 13954602e575SRyan Roberts extern int contpte_ptep_clear_flush_young(struct vm_area_struct *vma, 13964602e575SRyan Roberts unsigned long addr, pte_t *ptep); 1397311a6cf2SRyan Roberts extern void contpte_wrprotect_ptes(struct mm_struct *mm, unsigned long addr, 1398311a6cf2SRyan Roberts pte_t *ptep, unsigned int nr); 13994602e575SRyan Roberts extern int contpte_ptep_set_access_flags(struct vm_area_struct *vma, 14004602e575SRyan Roberts unsigned long addr, pte_t *ptep, 14014602e575SRyan Roberts pte_t entry, int dirty); 14024602e575SRyan Roberts 1403f0c22649SRyan Roberts static __always_inline void contpte_try_fold(struct mm_struct *mm, 1404f0c22649SRyan Roberts unsigned long addr, pte_t *ptep, pte_t pte) 1405f0c22649SRyan Roberts { 1406f0c22649SRyan Roberts /* 1407f0c22649SRyan Roberts * Only bother trying if both the virtual and physical addresses are 1408f0c22649SRyan Roberts * aligned and correspond to the last entry in a contig range. The core 1409f0c22649SRyan Roberts * code mostly modifies ranges from low to high, so this is the likely 1410f0c22649SRyan Roberts * the last modification in the contig range, so a good time to fold. 1411f0c22649SRyan Roberts * We can't fold special mappings, because there is no associated folio. 1412f0c22649SRyan Roberts */ 1413f0c22649SRyan Roberts 1414f0c22649SRyan Roberts const unsigned long contmask = CONT_PTES - 1; 1415f0c22649SRyan Roberts bool valign = ((addr >> PAGE_SHIFT) & contmask) == contmask; 1416f0c22649SRyan Roberts 1417f0c22649SRyan Roberts if (unlikely(valign)) { 1418f0c22649SRyan Roberts bool palign = (pte_pfn(pte) & contmask) == contmask; 1419f0c22649SRyan Roberts 1420f0c22649SRyan Roberts if (unlikely(palign && 1421f0c22649SRyan Roberts pte_valid(pte) && !pte_cont(pte) && !pte_special(pte))) 1422f0c22649SRyan Roberts __contpte_try_fold(mm, addr, ptep, pte); 1423f0c22649SRyan Roberts } 1424f0c22649SRyan Roberts } 1425f0c22649SRyan Roberts 1426b972fc6aSRyan Roberts static __always_inline void contpte_try_unfold(struct mm_struct *mm, 1427b972fc6aSRyan Roberts unsigned long addr, pte_t *ptep, pte_t pte) 14284602e575SRyan Roberts { 14294602e575SRyan Roberts if (unlikely(pte_valid_cont(pte))) 14304602e575SRyan Roberts __contpte_try_unfold(mm, addr, ptep, pte); 14314602e575SRyan Roberts } 14324602e575SRyan Roberts 1433fb5451e5SRyan Roberts #define pte_batch_hint pte_batch_hint 1434fb5451e5SRyan Roberts static inline unsigned int pte_batch_hint(pte_t *ptep, pte_t pte) 1435fb5451e5SRyan Roberts { 1436fb5451e5SRyan Roberts if (!pte_valid_cont(pte)) 1437fb5451e5SRyan Roberts return 1; 1438fb5451e5SRyan Roberts 1439fb5451e5SRyan Roberts return CONT_PTES - (((unsigned long)ptep >> 3) & (CONT_PTES - 1)); 1440fb5451e5SRyan Roberts } 1441fb5451e5SRyan Roberts 14424602e575SRyan Roberts /* 14434602e575SRyan Roberts * The below functions constitute the public API that arm64 presents to the 14444602e575SRyan Roberts * core-mm to manipulate PTE entries within their page tables (or at least this 14454602e575SRyan Roberts * is the subset of the API that arm64 needs to implement). These public 14464602e575SRyan Roberts * versions will automatically and transparently apply the contiguous bit where 14474602e575SRyan Roberts * it makes sense to do so. Therefore any users that are contig-aware (e.g. 14484602e575SRyan Roberts * hugetlb, kernel mapper) should NOT use these APIs, but instead use the 14494602e575SRyan Roberts * private versions, which are prefixed with double underscore. All of these 14504602e575SRyan Roberts * APIs except for ptep_get_lockless() are expected to be called with the PTL 14514602e575SRyan Roberts * held. Although the contiguous bit is considered private to the 14524602e575SRyan Roberts * implementation, it is deliberately allowed to leak through the getters (e.g. 14534602e575SRyan Roberts * ptep_get()), back to core code. This is required so that pte_leaf_size() can 14544602e575SRyan Roberts * provide an accurate size for perf_get_pgtable_size(). But this leakage means 14554602e575SRyan Roberts * its possible a pte will be passed to a setter with the contiguous bit set, so 14564602e575SRyan Roberts * we explicitly clear the contiguous bit in those cases to prevent accidentally 14574602e575SRyan Roberts * setting it in the pgtable. 14584602e575SRyan Roberts */ 14594602e575SRyan Roberts 14604602e575SRyan Roberts #define ptep_get ptep_get 14614602e575SRyan Roberts static inline pte_t ptep_get(pte_t *ptep) 14624602e575SRyan Roberts { 14634602e575SRyan Roberts pte_t pte = __ptep_get(ptep); 14644602e575SRyan Roberts 14654602e575SRyan Roberts if (likely(!pte_valid_cont(pte))) 14664602e575SRyan Roberts return pte; 14674602e575SRyan Roberts 14684602e575SRyan Roberts return contpte_ptep_get(ptep, pte); 14694602e575SRyan Roberts } 14704602e575SRyan Roberts 14714602e575SRyan Roberts #define ptep_get_lockless ptep_get_lockless 14724602e575SRyan Roberts static inline pte_t ptep_get_lockless(pte_t *ptep) 14734602e575SRyan Roberts { 14744602e575SRyan Roberts pte_t pte = __ptep_get(ptep); 14754602e575SRyan Roberts 14764602e575SRyan Roberts if (likely(!pte_valid_cont(pte))) 14774602e575SRyan Roberts return pte; 14784602e575SRyan Roberts 14794602e575SRyan Roberts return contpte_ptep_get_lockless(ptep); 14804602e575SRyan Roberts } 14814602e575SRyan Roberts 14824602e575SRyan Roberts static inline void set_pte(pte_t *ptep, pte_t pte) 14834602e575SRyan Roberts { 14844602e575SRyan Roberts /* 14854602e575SRyan Roberts * We don't have the mm or vaddr so cannot unfold contig entries (since 14864602e575SRyan Roberts * it requires tlb maintenance). set_pte() is not used in core code, so 14874602e575SRyan Roberts * this should never even be called. Regardless do our best to service 14884602e575SRyan Roberts * any call and emit a warning if there is any attempt to set a pte on 14894602e575SRyan Roberts * top of an existing contig range. 14904602e575SRyan Roberts */ 14914602e575SRyan Roberts pte_t orig_pte = __ptep_get(ptep); 14924602e575SRyan Roberts 14934602e575SRyan Roberts WARN_ON_ONCE(pte_valid_cont(orig_pte)); 14944602e575SRyan Roberts __set_pte(ptep, pte_mknoncont(pte)); 14954602e575SRyan Roberts } 14964602e575SRyan Roberts 14974602e575SRyan Roberts #define set_ptes set_ptes 1498b972fc6aSRyan Roberts static __always_inline void set_ptes(struct mm_struct *mm, unsigned long addr, 14994602e575SRyan Roberts pte_t *ptep, pte_t pte, unsigned int nr) 15004602e575SRyan Roberts { 15014602e575SRyan Roberts pte = pte_mknoncont(pte); 15024602e575SRyan Roberts 15034602e575SRyan Roberts if (likely(nr == 1)) { 15044602e575SRyan Roberts contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 15054602e575SRyan Roberts __set_ptes(mm, addr, ptep, pte, 1); 1506f0c22649SRyan Roberts contpte_try_fold(mm, addr, ptep, pte); 15074602e575SRyan Roberts } else { 15084602e575SRyan Roberts contpte_set_ptes(mm, addr, ptep, pte, nr); 15094602e575SRyan Roberts } 15104602e575SRyan Roberts } 15114602e575SRyan Roberts 15124602e575SRyan Roberts static inline void pte_clear(struct mm_struct *mm, 15134602e575SRyan Roberts unsigned long addr, pte_t *ptep) 15144602e575SRyan Roberts { 15154602e575SRyan Roberts contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 15164602e575SRyan Roberts __pte_clear(mm, addr, ptep); 15174602e575SRyan Roberts } 15184602e575SRyan Roberts 15196b1e4efbSRyan Roberts #define clear_full_ptes clear_full_ptes 15206b1e4efbSRyan Roberts static inline void clear_full_ptes(struct mm_struct *mm, unsigned long addr, 15216b1e4efbSRyan Roberts pte_t *ptep, unsigned int nr, int full) 15226b1e4efbSRyan Roberts { 15236b1e4efbSRyan Roberts if (likely(nr == 1)) { 15246b1e4efbSRyan Roberts contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 15256b1e4efbSRyan Roberts __clear_full_ptes(mm, addr, ptep, nr, full); 15266b1e4efbSRyan Roberts } else { 15276b1e4efbSRyan Roberts contpte_clear_full_ptes(mm, addr, ptep, nr, full); 15286b1e4efbSRyan Roberts } 15296b1e4efbSRyan Roberts } 15306b1e4efbSRyan Roberts 15316b1e4efbSRyan Roberts #define get_and_clear_full_ptes get_and_clear_full_ptes 15326b1e4efbSRyan Roberts static inline pte_t get_and_clear_full_ptes(struct mm_struct *mm, 15336b1e4efbSRyan Roberts unsigned long addr, pte_t *ptep, 15346b1e4efbSRyan Roberts unsigned int nr, int full) 15356b1e4efbSRyan Roberts { 15366b1e4efbSRyan Roberts pte_t pte; 15376b1e4efbSRyan Roberts 15386b1e4efbSRyan Roberts if (likely(nr == 1)) { 15396b1e4efbSRyan Roberts contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 15406b1e4efbSRyan Roberts pte = __get_and_clear_full_ptes(mm, addr, ptep, nr, full); 15416b1e4efbSRyan Roberts } else { 15426b1e4efbSRyan Roberts pte = contpte_get_and_clear_full_ptes(mm, addr, ptep, nr, full); 15436b1e4efbSRyan Roberts } 15446b1e4efbSRyan Roberts 15456b1e4efbSRyan Roberts return pte; 15466b1e4efbSRyan Roberts } 15476b1e4efbSRyan Roberts 15484602e575SRyan Roberts #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 15494602e575SRyan Roberts static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 15504602e575SRyan Roberts unsigned long addr, pte_t *ptep) 15514602e575SRyan Roberts { 15524602e575SRyan Roberts contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 15534602e575SRyan Roberts return __ptep_get_and_clear(mm, addr, ptep); 15544602e575SRyan Roberts } 15554602e575SRyan Roberts 15564602e575SRyan Roberts #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 15574602e575SRyan Roberts static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 15584602e575SRyan Roberts unsigned long addr, pte_t *ptep) 15594602e575SRyan Roberts { 15604602e575SRyan Roberts pte_t orig_pte = __ptep_get(ptep); 15614602e575SRyan Roberts 15624602e575SRyan Roberts if (likely(!pte_valid_cont(orig_pte))) 15634602e575SRyan Roberts return __ptep_test_and_clear_young(vma, addr, ptep); 15644602e575SRyan Roberts 15654602e575SRyan Roberts return contpte_ptep_test_and_clear_young(vma, addr, ptep); 15664602e575SRyan Roberts } 15674602e575SRyan Roberts 15684602e575SRyan Roberts #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 15694602e575SRyan Roberts static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 15704602e575SRyan Roberts unsigned long addr, pte_t *ptep) 15714602e575SRyan Roberts { 15724602e575SRyan Roberts pte_t orig_pte = __ptep_get(ptep); 15734602e575SRyan Roberts 15744602e575SRyan Roberts if (likely(!pte_valid_cont(orig_pte))) 15754602e575SRyan Roberts return __ptep_clear_flush_young(vma, addr, ptep); 15764602e575SRyan Roberts 15774602e575SRyan Roberts return contpte_ptep_clear_flush_young(vma, addr, ptep); 15784602e575SRyan Roberts } 15794602e575SRyan Roberts 1580311a6cf2SRyan Roberts #define wrprotect_ptes wrprotect_ptes 1581b972fc6aSRyan Roberts static __always_inline void wrprotect_ptes(struct mm_struct *mm, 1582b972fc6aSRyan Roberts unsigned long addr, pte_t *ptep, unsigned int nr) 1583311a6cf2SRyan Roberts { 1584311a6cf2SRyan Roberts if (likely(nr == 1)) { 1585311a6cf2SRyan Roberts /* 1586311a6cf2SRyan Roberts * Optimization: wrprotect_ptes() can only be called for present 1587311a6cf2SRyan Roberts * ptes so we only need to check contig bit as condition for 1588311a6cf2SRyan Roberts * unfold, and we can remove the contig bit from the pte we read 1589311a6cf2SRyan Roberts * to avoid re-reading. This speeds up fork() which is sensitive 1590311a6cf2SRyan Roberts * for order-0 folios. Equivalent to contpte_try_unfold(). 1591311a6cf2SRyan Roberts */ 1592311a6cf2SRyan Roberts pte_t orig_pte = __ptep_get(ptep); 1593311a6cf2SRyan Roberts 1594311a6cf2SRyan Roberts if (unlikely(pte_cont(orig_pte))) { 1595311a6cf2SRyan Roberts __contpte_try_unfold(mm, addr, ptep, orig_pte); 1596311a6cf2SRyan Roberts orig_pte = pte_mknoncont(orig_pte); 1597311a6cf2SRyan Roberts } 1598311a6cf2SRyan Roberts ___ptep_set_wrprotect(mm, addr, ptep, orig_pte); 1599311a6cf2SRyan Roberts } else { 1600311a6cf2SRyan Roberts contpte_wrprotect_ptes(mm, addr, ptep, nr); 1601311a6cf2SRyan Roberts } 1602311a6cf2SRyan Roberts } 1603311a6cf2SRyan Roberts 16044602e575SRyan Roberts #define __HAVE_ARCH_PTEP_SET_WRPROTECT 16054602e575SRyan Roberts static inline void ptep_set_wrprotect(struct mm_struct *mm, 16064602e575SRyan Roberts unsigned long addr, pte_t *ptep) 16074602e575SRyan Roberts { 1608311a6cf2SRyan Roberts wrprotect_ptes(mm, addr, ptep, 1); 16094602e575SRyan Roberts } 16104602e575SRyan Roberts 16114602e575SRyan Roberts #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 16124602e575SRyan Roberts static inline int ptep_set_access_flags(struct vm_area_struct *vma, 16134602e575SRyan Roberts unsigned long addr, pte_t *ptep, 16144602e575SRyan Roberts pte_t entry, int dirty) 16154602e575SRyan Roberts { 16164602e575SRyan Roberts pte_t orig_pte = __ptep_get(ptep); 16174602e575SRyan Roberts 16184602e575SRyan Roberts entry = pte_mknoncont(entry); 16194602e575SRyan Roberts 16204602e575SRyan Roberts if (likely(!pte_valid_cont(orig_pte))) 16214602e575SRyan Roberts return __ptep_set_access_flags(vma, addr, ptep, entry, dirty); 16224602e575SRyan Roberts 16234602e575SRyan Roberts return contpte_ptep_set_access_flags(vma, addr, ptep, entry, dirty); 16244602e575SRyan Roberts } 16254602e575SRyan Roberts 16264602e575SRyan Roberts #else /* CONFIG_ARM64_CONTPTE */ 16274602e575SRyan Roberts 16285a00bfd6SRyan Roberts #define ptep_get __ptep_get 16295a00bfd6SRyan Roberts #define set_pte __set_pte 16305a00bfd6SRyan Roberts #define set_ptes __set_ptes 16315a00bfd6SRyan Roberts #define pte_clear __pte_clear 16326b1e4efbSRyan Roberts #define clear_full_ptes __clear_full_ptes 16336b1e4efbSRyan Roberts #define get_and_clear_full_ptes __get_and_clear_full_ptes 16345a00bfd6SRyan Roberts #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 16355a00bfd6SRyan Roberts #define ptep_get_and_clear __ptep_get_and_clear 16365a00bfd6SRyan Roberts #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 16375a00bfd6SRyan Roberts #define ptep_test_and_clear_young __ptep_test_and_clear_young 16385a00bfd6SRyan Roberts #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 16395a00bfd6SRyan Roberts #define ptep_clear_flush_young __ptep_clear_flush_young 16405a00bfd6SRyan Roberts #define __HAVE_ARCH_PTEP_SET_WRPROTECT 16415a00bfd6SRyan Roberts #define ptep_set_wrprotect __ptep_set_wrprotect 1642311a6cf2SRyan Roberts #define wrprotect_ptes __wrprotect_ptes 16435a00bfd6SRyan Roberts #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 16445a00bfd6SRyan Roberts #define ptep_set_access_flags __ptep_set_access_flags 16455a00bfd6SRyan Roberts 16464602e575SRyan Roberts #endif /* CONFIG_ARM64_CONTPTE */ 16474602e575SRyan Roberts 16484f04d8f0SCatalin Marinas #endif /* !__ASSEMBLY__ */ 16494f04d8f0SCatalin Marinas 16504f04d8f0SCatalin Marinas #endif /* __ASM_PGTABLE_H */ 1651