14f04d8f0SCatalin Marinas /* 24f04d8f0SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 34f04d8f0SCatalin Marinas * 44f04d8f0SCatalin Marinas * This program is free software; you can redistribute it and/or modify 54f04d8f0SCatalin Marinas * it under the terms of the GNU General Public License version 2 as 64f04d8f0SCatalin Marinas * published by the Free Software Foundation. 74f04d8f0SCatalin Marinas * 84f04d8f0SCatalin Marinas * This program is distributed in the hope that it will be useful, 94f04d8f0SCatalin Marinas * but WITHOUT ANY WARRANTY; without even the implied warranty of 104f04d8f0SCatalin Marinas * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 114f04d8f0SCatalin Marinas * GNU General Public License for more details. 124f04d8f0SCatalin Marinas * 134f04d8f0SCatalin Marinas * You should have received a copy of the GNU General Public License 144f04d8f0SCatalin Marinas * along with this program. If not, see <http://www.gnu.org/licenses/>. 154f04d8f0SCatalin Marinas */ 164f04d8f0SCatalin Marinas #ifndef __ASM_PGTABLE_H 174f04d8f0SCatalin Marinas #define __ASM_PGTABLE_H 184f04d8f0SCatalin Marinas 192f4b829cSCatalin Marinas #include <asm/bug.h> 204f04d8f0SCatalin Marinas #include <asm/proc-fns.h> 214f04d8f0SCatalin Marinas 224f04d8f0SCatalin Marinas #include <asm/memory.h> 234f04d8f0SCatalin Marinas #include <asm/pgtable-hwdef.h> 244f04d8f0SCatalin Marinas 254f04d8f0SCatalin Marinas /* 264f04d8f0SCatalin Marinas * Software defined PTE bits definition. 274f04d8f0SCatalin Marinas */ 28a6fadf7eSWill Deacon #define PTE_VALID (_AT(pteval_t, 1) << 0) 29bf950040SWill Deacon #define PTE_WRITE (PTE_DBM) /* same as DBM (51) */ 304f04d8f0SCatalin Marinas #define PTE_DIRTY (_AT(pteval_t, 1) << 55) 314f04d8f0SCatalin Marinas #define PTE_SPECIAL (_AT(pteval_t, 1) << 56) 323676f9efSCatalin Marinas #define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */ 334f04d8f0SCatalin Marinas 344f04d8f0SCatalin Marinas /* 354f04d8f0SCatalin Marinas * VMALLOC and SPARSEMEM_VMEMMAP ranges. 3608375198SCatalin Marinas * 3708375198SCatalin Marinas * VMEMAP_SIZE: allows the whole VA space to be covered by a struct page array 3808375198SCatalin Marinas * (rounded up to PUD_SIZE). 3908375198SCatalin Marinas * VMALLOC_START: beginning of the kernel VA space 4008375198SCatalin Marinas * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space, 4108375198SCatalin Marinas * fixed mappings and modules 424f04d8f0SCatalin Marinas */ 4308375198SCatalin Marinas #define VMEMMAP_SIZE ALIGN((1UL << (VA_BITS - PAGE_SHIFT)) * sizeof(struct page), PUD_SIZE) 4439d114ddSAndrey Ryabinin 4539d114ddSAndrey Ryabinin #ifndef CONFIG_KASAN 46127db024SAndrey Ryabinin #define VMALLOC_START (VA_START) 4739d114ddSAndrey Ryabinin #else 4839d114ddSAndrey Ryabinin #include <asm/kasan.h> 4939d114ddSAndrey Ryabinin #define VMALLOC_START (KASAN_SHADOW_END + SZ_64K) 5039d114ddSAndrey Ryabinin #endif 5139d114ddSAndrey Ryabinin 5208375198SCatalin Marinas #define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K) 534f04d8f0SCatalin Marinas 544f04d8f0SCatalin Marinas #define vmemmap ((struct page *)(VMALLOC_END + SZ_64K)) 554f04d8f0SCatalin Marinas 56d016bf7eSKirill A. Shutemov #define FIRST_USER_ADDRESS 0UL 574f04d8f0SCatalin Marinas 584f04d8f0SCatalin Marinas #ifndef __ASSEMBLY__ 592f4b829cSCatalin Marinas 602f4b829cSCatalin Marinas #include <linux/mmdebug.h> 612f4b829cSCatalin Marinas 624f04d8f0SCatalin Marinas extern void __pte_error(const char *file, int line, unsigned long val); 634f04d8f0SCatalin Marinas extern void __pmd_error(const char *file, int line, unsigned long val); 64c79b954bSJungseok Lee extern void __pud_error(const char *file, int line, unsigned long val); 654f04d8f0SCatalin Marinas extern void __pgd_error(const char *file, int line, unsigned long val); 664f04d8f0SCatalin Marinas 67a501e324SCatalin Marinas #define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED) 68a501e324SCatalin Marinas #define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S) 694f04d8f0SCatalin Marinas 70ac15bd63SCatalin Marinas #define PROT_DEVICE_nGnRnE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE)) 71ac15bd63SCatalin Marinas #define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE)) 72ac15bd63SCatalin Marinas #define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC)) 73ac15bd63SCatalin Marinas #define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT)) 74ac15bd63SCatalin Marinas #define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL)) 754f04d8f0SCatalin Marinas 76a501e324SCatalin Marinas #define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE)) 77a501e324SCatalin Marinas #define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL)) 78a501e324SCatalin Marinas #define PROT_SECT_NORMAL_EXEC (PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL)) 794f04d8f0SCatalin Marinas 80a501e324SCatalin Marinas #define _PAGE_DEFAULT (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL)) 81a6fadf7eSWill Deacon 82a501e324SCatalin Marinas #define PAGE_KERNEL __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE) 83fb226c3dSArd Biesheuvel #define PAGE_KERNEL_RO __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_RDONLY) 840b2aa5b8SLaura Abbott #define PAGE_KERNEL_ROX __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_RDONLY) 85a501e324SCatalin Marinas #define PAGE_KERNEL_EXEC __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE) 8606f90d25SJeremy Linton #define PAGE_KERNEL_EXEC_CONT __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_CONT) 874f04d8f0SCatalin Marinas 88a501e324SCatalin Marinas #define PAGE_HYP __pgprot(_PAGE_DEFAULT | PTE_HYP) 8936311607SMarc Zyngier #define PAGE_HYP_DEVICE __pgprot(PROT_DEVICE_nGnRE | PTE_HYP) 9036311607SMarc Zyngier 91a501e324SCatalin Marinas #define PAGE_S2 __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY) 924a513fb0SArd Biesheuvel #define PAGE_S2_DEVICE __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_UXN) 9336311607SMarc Zyngier 941a541b4eSSteve Capper #define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_PXN | PTE_UXN) 95a501e324SCatalin Marinas #define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE) 96a501e324SCatalin Marinas #define PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE) 97a501e324SCatalin Marinas #define PAGE_COPY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN) 98a501e324SCatalin Marinas #define PAGE_COPY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN) 99a501e324SCatalin Marinas #define PAGE_READONLY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN) 100a501e324SCatalin Marinas #define PAGE_READONLY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN) 1014f04d8f0SCatalin Marinas 102a501e324SCatalin Marinas #define __P000 PAGE_NONE 103a501e324SCatalin Marinas #define __P001 PAGE_READONLY 104a501e324SCatalin Marinas #define __P010 PAGE_COPY 105a501e324SCatalin Marinas #define __P011 PAGE_COPY 1065a0fdfadSCatalin Marinas #define __P100 PAGE_READONLY_EXEC 107a501e324SCatalin Marinas #define __P101 PAGE_READONLY_EXEC 108a501e324SCatalin Marinas #define __P110 PAGE_COPY_EXEC 109a501e324SCatalin Marinas #define __P111 PAGE_COPY_EXEC 1104f04d8f0SCatalin Marinas 111a501e324SCatalin Marinas #define __S000 PAGE_NONE 112a501e324SCatalin Marinas #define __S001 PAGE_READONLY 113a501e324SCatalin Marinas #define __S010 PAGE_SHARED 114a501e324SCatalin Marinas #define __S011 PAGE_SHARED 1155a0fdfadSCatalin Marinas #define __S100 PAGE_READONLY_EXEC 116a501e324SCatalin Marinas #define __S101 PAGE_READONLY_EXEC 117a501e324SCatalin Marinas #define __S110 PAGE_SHARED_EXEC 118a501e324SCatalin Marinas #define __S111 PAGE_SHARED_EXEC 1194f04d8f0SCatalin Marinas 1204f04d8f0SCatalin Marinas /* 1214f04d8f0SCatalin Marinas * ZERO_PAGE is a global shared page that is always zero: used 1224f04d8f0SCatalin Marinas * for zero-mapped memory areas etc.. 1234f04d8f0SCatalin Marinas */ 1245227cfa7SMark Rutland extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 1255227cfa7SMark Rutland #define ZERO_PAGE(vaddr) virt_to_page(empty_zero_page) 1264f04d8f0SCatalin Marinas 1277078db46SCatalin Marinas #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) 1287078db46SCatalin Marinas 1294f04d8f0SCatalin Marinas #define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT) 1304f04d8f0SCatalin Marinas 1314f04d8f0SCatalin Marinas #define pfn_pte(pfn,prot) (__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) 1324f04d8f0SCatalin Marinas 1334f04d8f0SCatalin Marinas #define pte_none(pte) (!pte_val(pte)) 1344f04d8f0SCatalin Marinas #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 1354f04d8f0SCatalin Marinas #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 1367078db46SCatalin Marinas 1374f04d8f0SCatalin Marinas /* 1384f04d8f0SCatalin Marinas * The following only work if pte_present(). Undefined behaviour otherwise. 1394f04d8f0SCatalin Marinas */ 14084fe6826SSteve Capper #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 14184fe6826SSteve Capper #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 14284fe6826SSteve Capper #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 14384fe6826SSteve Capper #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 1448e620b04SCatalin Marinas #define pte_exec(pte) (!(pte_val(pte) & PTE_UXN)) 14593ef666aSJeremy Linton #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 146ac15bd63SCatalin Marinas #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) 1474f04d8f0SCatalin Marinas 1482f4b829cSCatalin Marinas #ifdef CONFIG_ARM64_HW_AFDBM 149b847415cSCatalin Marinas #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) 1502f4b829cSCatalin Marinas #else 1512f4b829cSCatalin Marinas #define pte_hw_dirty(pte) (0) 1522f4b829cSCatalin Marinas #endif 1532f4b829cSCatalin Marinas #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 1542f4b829cSCatalin Marinas #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 1552f4b829cSCatalin Marinas 156766ffb69SWill Deacon #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 1577f0b1bf0SCatalin Marinas #define pte_valid_not_user(pte) \ 1587f0b1bf0SCatalin Marinas ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID) 15976c714beSWill Deacon #define pte_valid_young(pte) \ 16076c714beSWill Deacon ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF)) 16176c714beSWill Deacon 16276c714beSWill Deacon /* 16376c714beSWill Deacon * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 16476c714beSWill Deacon * so that we don't erroneously return false for pages that have been 16576c714beSWill Deacon * remapped as PROT_NONE but are yet to be flushed from the TLB. 16676c714beSWill Deacon */ 16776c714beSWill Deacon #define pte_accessible(mm, pte) \ 16876c714beSWill Deacon (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte)) 1694f04d8f0SCatalin Marinas 170b6d4f280SLaura Abbott static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 171b6d4f280SLaura Abbott { 172b6d4f280SLaura Abbott pte_val(pte) &= ~pgprot_val(prot); 173b6d4f280SLaura Abbott return pte; 174b6d4f280SLaura Abbott } 175b6d4f280SLaura Abbott 176b6d4f280SLaura Abbott static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 177b6d4f280SLaura Abbott { 178b6d4f280SLaura Abbott pte_val(pte) |= pgprot_val(prot); 179b6d4f280SLaura Abbott return pte; 180b6d4f280SLaura Abbott } 181b6d4f280SLaura Abbott 18244b6dfc5SSteve Capper static inline pte_t pte_wrprotect(pte_t pte) 18344b6dfc5SSteve Capper { 184b6d4f280SLaura Abbott return clear_pte_bit(pte, __pgprot(PTE_WRITE)); 18544b6dfc5SSteve Capper } 1864f04d8f0SCatalin Marinas 18744b6dfc5SSteve Capper static inline pte_t pte_mkwrite(pte_t pte) 18844b6dfc5SSteve Capper { 189b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_WRITE)); 19044b6dfc5SSteve Capper } 19144b6dfc5SSteve Capper 19244b6dfc5SSteve Capper static inline pte_t pte_mkclean(pte_t pte) 19344b6dfc5SSteve Capper { 194b6d4f280SLaura Abbott return clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 19544b6dfc5SSteve Capper } 19644b6dfc5SSteve Capper 19744b6dfc5SSteve Capper static inline pte_t pte_mkdirty(pte_t pte) 19844b6dfc5SSteve Capper { 199b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_DIRTY)); 20044b6dfc5SSteve Capper } 20144b6dfc5SSteve Capper 20244b6dfc5SSteve Capper static inline pte_t pte_mkold(pte_t pte) 20344b6dfc5SSteve Capper { 204b6d4f280SLaura Abbott return clear_pte_bit(pte, __pgprot(PTE_AF)); 20544b6dfc5SSteve Capper } 20644b6dfc5SSteve Capper 20744b6dfc5SSteve Capper static inline pte_t pte_mkyoung(pte_t pte) 20844b6dfc5SSteve Capper { 209b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_AF)); 21044b6dfc5SSteve Capper } 21144b6dfc5SSteve Capper 21244b6dfc5SSteve Capper static inline pte_t pte_mkspecial(pte_t pte) 21344b6dfc5SSteve Capper { 214b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 21544b6dfc5SSteve Capper } 2164f04d8f0SCatalin Marinas 21793ef666aSJeremy Linton static inline pte_t pte_mkcont(pte_t pte) 21893ef666aSJeremy Linton { 21966b3923aSDavid Woods pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 22066b3923aSDavid Woods return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 22193ef666aSJeremy Linton } 22293ef666aSJeremy Linton 22393ef666aSJeremy Linton static inline pte_t pte_mknoncont(pte_t pte) 22493ef666aSJeremy Linton { 22593ef666aSJeremy Linton return clear_pte_bit(pte, __pgprot(PTE_CONT)); 22693ef666aSJeremy Linton } 22793ef666aSJeremy Linton 22866b3923aSDavid Woods static inline pmd_t pmd_mkcont(pmd_t pmd) 22966b3923aSDavid Woods { 23066b3923aSDavid Woods return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 23166b3923aSDavid Woods } 23266b3923aSDavid Woods 2334f04d8f0SCatalin Marinas static inline void set_pte(pte_t *ptep, pte_t pte) 2344f04d8f0SCatalin Marinas { 2354f04d8f0SCatalin Marinas *ptep = pte; 2367f0b1bf0SCatalin Marinas 2377f0b1bf0SCatalin Marinas /* 2387f0b1bf0SCatalin Marinas * Only if the new pte is valid and kernel, otherwise TLB maintenance 2397f0b1bf0SCatalin Marinas * or update_mmu_cache() have the necessary barriers. 2407f0b1bf0SCatalin Marinas */ 2417f0b1bf0SCatalin Marinas if (pte_valid_not_user(pte)) { 2427f0b1bf0SCatalin Marinas dsb(ishst); 2437f0b1bf0SCatalin Marinas isb(); 2447f0b1bf0SCatalin Marinas } 2454f04d8f0SCatalin Marinas } 2464f04d8f0SCatalin Marinas 2472f4b829cSCatalin Marinas struct mm_struct; 2482f4b829cSCatalin Marinas struct vm_area_struct; 2492f4b829cSCatalin Marinas 2504f04d8f0SCatalin Marinas extern void __sync_icache_dcache(pte_t pteval, unsigned long addr); 2514f04d8f0SCatalin Marinas 2522f4b829cSCatalin Marinas /* 2532f4b829cSCatalin Marinas * PTE bits configuration in the presence of hardware Dirty Bit Management 2542f4b829cSCatalin Marinas * (PTE_WRITE == PTE_DBM): 2552f4b829cSCatalin Marinas * 2562f4b829cSCatalin Marinas * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 2572f4b829cSCatalin Marinas * 0 0 | 1 0 0 2582f4b829cSCatalin Marinas * 0 1 | 1 1 0 2592f4b829cSCatalin Marinas * 1 0 | 1 0 1 2602f4b829cSCatalin Marinas * 1 1 | 0 1 x 2612f4b829cSCatalin Marinas * 2622f4b829cSCatalin Marinas * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 2632f4b829cSCatalin Marinas * the page fault mechanism. Checking the dirty status of a pte becomes: 2642f4b829cSCatalin Marinas * 265b847415cSCatalin Marinas * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 2662f4b829cSCatalin Marinas */ 2674f04d8f0SCatalin Marinas static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 2684f04d8f0SCatalin Marinas pte_t *ptep, pte_t pte) 2694f04d8f0SCatalin Marinas { 270ac15bd63SCatalin Marinas if (pte_valid(pte)) { 2712f4b829cSCatalin Marinas if (pte_sw_dirty(pte) && pte_write(pte)) 272c2c93e5bSSteve Capper pte_val(pte) &= ~PTE_RDONLY; 273c2c93e5bSSteve Capper else 274c2c93e5bSSteve Capper pte_val(pte) |= PTE_RDONLY; 275ac15bd63SCatalin Marinas if (pte_user(pte) && pte_exec(pte) && !pte_special(pte)) 276ac15bd63SCatalin Marinas __sync_icache_dcache(pte, addr); 27702522463SWill Deacon } 27802522463SWill Deacon 2792f4b829cSCatalin Marinas /* 2802f4b829cSCatalin Marinas * If the existing pte is valid, check for potential race with 2812f4b829cSCatalin Marinas * hardware updates of the pte (ptep_set_access_flags safely changes 2822f4b829cSCatalin Marinas * valid ptes without going through an invalid entry). 2832f4b829cSCatalin Marinas */ 28482d34008SCatalin Marinas if (IS_ENABLED(CONFIG_ARM64_HW_AFDBM) && 28582d34008SCatalin Marinas pte_valid(*ptep) && pte_valid(pte)) { 28682d34008SCatalin Marinas VM_WARN_ONCE(!pte_young(pte), 28782d34008SCatalin Marinas "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 28882d34008SCatalin Marinas __func__, pte_val(*ptep), pte_val(pte)); 28982d34008SCatalin Marinas VM_WARN_ONCE(pte_write(*ptep) && !pte_dirty(pte), 29082d34008SCatalin Marinas "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 29182d34008SCatalin Marinas __func__, pte_val(*ptep), pte_val(pte)); 2922f4b829cSCatalin Marinas } 2932f4b829cSCatalin Marinas 2944f04d8f0SCatalin Marinas set_pte(ptep, pte); 2954f04d8f0SCatalin Marinas } 2964f04d8f0SCatalin Marinas 2974f04d8f0SCatalin Marinas /* 2984f04d8f0SCatalin Marinas * Huge pte definitions. 2994f04d8f0SCatalin Marinas */ 300084bd298SSteve Capper #define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT)) 301084bd298SSteve Capper #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 302084bd298SSteve Capper 303084bd298SSteve Capper /* 304084bd298SSteve Capper * Hugetlb definitions. 305084bd298SSteve Capper */ 30666b3923aSDavid Woods #define HUGE_MAX_HSTATE 4 307084bd298SSteve Capper #define HPAGE_SHIFT PMD_SHIFT 308084bd298SSteve Capper #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 309084bd298SSteve Capper #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 310084bd298SSteve Capper #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 3114f04d8f0SCatalin Marinas 3124f04d8f0SCatalin Marinas #define __HAVE_ARCH_PTE_SPECIAL 3134f04d8f0SCatalin Marinas 31429e56940SSteve Capper static inline pte_t pud_pte(pud_t pud) 31529e56940SSteve Capper { 31629e56940SSteve Capper return __pte(pud_val(pud)); 31729e56940SSteve Capper } 31829e56940SSteve Capper 31929e56940SSteve Capper static inline pmd_t pud_pmd(pud_t pud) 32029e56940SSteve Capper { 32129e56940SSteve Capper return __pmd(pud_val(pud)); 32229e56940SSteve Capper } 32329e56940SSteve Capper 3249c7e535fSSteve Capper static inline pte_t pmd_pte(pmd_t pmd) 3259c7e535fSSteve Capper { 3269c7e535fSSteve Capper return __pte(pmd_val(pmd)); 3279c7e535fSSteve Capper } 328af074848SSteve Capper 3299c7e535fSSteve Capper static inline pmd_t pte_pmd(pte_t pte) 3309c7e535fSSteve Capper { 3319c7e535fSSteve Capper return __pmd(pte_val(pte)); 3329c7e535fSSteve Capper } 333af074848SSteve Capper 3348ce837ceSArd Biesheuvel static inline pgprot_t mk_sect_prot(pgprot_t prot) 3358ce837ceSArd Biesheuvel { 3368ce837ceSArd Biesheuvel return __pgprot(pgprot_val(prot) & ~PTE_TABLE_BIT); 3378ce837ceSArd Biesheuvel } 3388ce837ceSArd Biesheuvel 339af074848SSteve Capper /* 340af074848SSteve Capper * THP definitions. 341af074848SSteve Capper */ 342af074848SSteve Capper 343af074848SSteve Capper #ifdef CONFIG_TRANSPARENT_HUGEPAGE 344af074848SSteve Capper #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) 34529e56940SSteve Capper #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 346af074848SSteve Capper 347c164e038SKirill A. Shutemov #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 3489c7e535fSSteve Capper #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 3499c7e535fSSteve Capper #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 3509c7e535fSSteve Capper #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 3519c7e535fSSteve Capper #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 35205ee26d9SMinchan Kim #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 3539c7e535fSSteve Capper #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 3549c7e535fSSteve Capper #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 355e3a920afSWill Deacon #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_TYPE_MASK)) 356af074848SSteve Capper 3579c7e535fSSteve Capper #define __HAVE_ARCH_PMD_WRITE 3589c7e535fSSteve Capper #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 359af074848SSteve Capper 360af074848SSteve Capper #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 361af074848SSteve Capper 362af074848SSteve Capper #define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT) 363af074848SSteve Capper #define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) 364af074848SSteve Capper #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 365af074848SSteve Capper 36629e56940SSteve Capper #define pud_write(pud) pte_write(pud_pte(pud)) 367206a2a73SSteve Capper #define pud_pfn(pud) (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT) 368af074848SSteve Capper 369ceb21835SWill Deacon #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) 370af074848SSteve Capper 371af074848SSteve Capper static inline int has_transparent_hugepage(void) 372af074848SSteve Capper { 373af074848SSteve Capper return 1; 374af074848SSteve Capper } 375af074848SSteve Capper 376a501e324SCatalin Marinas #define __pgprot_modify(prot,mask,bits) \ 377a501e324SCatalin Marinas __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 378a501e324SCatalin Marinas 379af074848SSteve Capper /* 3804f04d8f0SCatalin Marinas * Mark the prot value as uncacheable and unbufferable. 3814f04d8f0SCatalin Marinas */ 3824f04d8f0SCatalin Marinas #define pgprot_noncached(prot) \ 383de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 3844f04d8f0SCatalin Marinas #define pgprot_writecombine(prot) \ 385de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 386d1e6dc91SLiviu Dudau #define pgprot_device(prot) \ 387d1e6dc91SLiviu Dudau __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 3884f04d8f0SCatalin Marinas #define __HAVE_PHYS_MEM_ACCESS_PROT 3894f04d8f0SCatalin Marinas struct file; 3904f04d8f0SCatalin Marinas extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 3914f04d8f0SCatalin Marinas unsigned long size, pgprot_t vma_prot); 3924f04d8f0SCatalin Marinas 3934f04d8f0SCatalin Marinas #define pmd_none(pmd) (!pmd_val(pmd)) 3944f04d8f0SCatalin Marinas #define pmd_present(pmd) (pmd_val(pmd)) 3954f04d8f0SCatalin Marinas 3964f04d8f0SCatalin Marinas #define pmd_bad(pmd) (!(pmd_val(pmd) & 2)) 3974f04d8f0SCatalin Marinas 39836311607SMarc Zyngier #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 39936311607SMarc Zyngier PMD_TYPE_TABLE) 40036311607SMarc Zyngier #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 40136311607SMarc Zyngier PMD_TYPE_SECT) 40236311607SMarc Zyngier 403f3b766a2SSteve Capper #ifdef CONFIG_ARM64_64K_PAGES 404206a2a73SSteve Capper #define pud_sect(pud) (0) 405523d6e9fSzhichang.yuan #define pud_table(pud) (1) 406206a2a73SSteve Capper #else 407206a2a73SSteve Capper #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 408206a2a73SSteve Capper PUD_TYPE_SECT) 409523d6e9fSzhichang.yuan #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 410523d6e9fSzhichang.yuan PUD_TYPE_TABLE) 411206a2a73SSteve Capper #endif 41236311607SMarc Zyngier 4134f04d8f0SCatalin Marinas static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 4144f04d8f0SCatalin Marinas { 4154f04d8f0SCatalin Marinas *pmdp = pmd; 41698f7685eSWill Deacon dsb(ishst); 4177f0b1bf0SCatalin Marinas isb(); 4184f04d8f0SCatalin Marinas } 4194f04d8f0SCatalin Marinas 4204f04d8f0SCatalin Marinas static inline void pmd_clear(pmd_t *pmdp) 4214f04d8f0SCatalin Marinas { 4224f04d8f0SCatalin Marinas set_pmd(pmdp, __pmd(0)); 4234f04d8f0SCatalin Marinas } 4244f04d8f0SCatalin Marinas 4254f04d8f0SCatalin Marinas static inline pte_t *pmd_page_vaddr(pmd_t pmd) 4264f04d8f0SCatalin Marinas { 4274f04d8f0SCatalin Marinas return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK); 4284f04d8f0SCatalin Marinas } 4294f04d8f0SCatalin Marinas 430*053520f7SMark Rutland /* Find an entry in the third-level page table. */ 431*053520f7SMark Rutland #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 432*053520f7SMark Rutland 433*053520f7SMark Rutland #define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + pte_index(addr)) 434*053520f7SMark Rutland 435*053520f7SMark Rutland #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 436*053520f7SMark Rutland #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr)) 437*053520f7SMark Rutland #define pte_unmap(pte) do { } while (0) 438*053520f7SMark Rutland #define pte_unmap_nested(pte) do { } while (0) 439*053520f7SMark Rutland 4404f04d8f0SCatalin Marinas #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK)) 4414f04d8f0SCatalin Marinas 4424f04d8f0SCatalin Marinas /* 4434f04d8f0SCatalin Marinas * Conversion functions: convert a page and protection to a page entry, 4444f04d8f0SCatalin Marinas * and a page entry and page directory to the page they refer to. 4454f04d8f0SCatalin Marinas */ 4464f04d8f0SCatalin Marinas #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 4474f04d8f0SCatalin Marinas 4489f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 2 4494f04d8f0SCatalin Marinas 4507078db46SCatalin Marinas #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) 4517078db46SCatalin Marinas 4524f04d8f0SCatalin Marinas #define pud_none(pud) (!pud_val(pud)) 4534f04d8f0SCatalin Marinas #define pud_bad(pud) (!(pud_val(pud) & 2)) 4544f04d8f0SCatalin Marinas #define pud_present(pud) (pud_val(pud)) 4554f04d8f0SCatalin Marinas 4564f04d8f0SCatalin Marinas static inline void set_pud(pud_t *pudp, pud_t pud) 4574f04d8f0SCatalin Marinas { 4584f04d8f0SCatalin Marinas *pudp = pud; 45998f7685eSWill Deacon dsb(ishst); 4607f0b1bf0SCatalin Marinas isb(); 4614f04d8f0SCatalin Marinas } 4624f04d8f0SCatalin Marinas 4634f04d8f0SCatalin Marinas static inline void pud_clear(pud_t *pudp) 4644f04d8f0SCatalin Marinas { 4654f04d8f0SCatalin Marinas set_pud(pudp, __pud(0)); 4664f04d8f0SCatalin Marinas } 4674f04d8f0SCatalin Marinas 4684f04d8f0SCatalin Marinas static inline pmd_t *pud_page_vaddr(pud_t pud) 4694f04d8f0SCatalin Marinas { 4704f04d8f0SCatalin Marinas return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK); 4714f04d8f0SCatalin Marinas } 4724f04d8f0SCatalin Marinas 4737078db46SCatalin Marinas /* Find an entry in the second-level page table. */ 4747078db46SCatalin Marinas #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) 4757078db46SCatalin Marinas 4767078db46SCatalin Marinas static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr) 4777078db46SCatalin Marinas { 4787078db46SCatalin Marinas return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr); 4797078db46SCatalin Marinas } 4807078db46SCatalin Marinas 4815d96e0cbSJungseok Lee #define pud_page(pud) pfn_to_page(__phys_to_pfn(pud_val(pud) & PHYS_MASK)) 48229e56940SSteve Capper 4839f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 4844f04d8f0SCatalin Marinas 4859f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 3 486c79b954bSJungseok Lee 4877078db46SCatalin Marinas #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud)) 4887078db46SCatalin Marinas 489c79b954bSJungseok Lee #define pgd_none(pgd) (!pgd_val(pgd)) 490c79b954bSJungseok Lee #define pgd_bad(pgd) (!(pgd_val(pgd) & 2)) 491c79b954bSJungseok Lee #define pgd_present(pgd) (pgd_val(pgd)) 492c79b954bSJungseok Lee 493c79b954bSJungseok Lee static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 494c79b954bSJungseok Lee { 495c79b954bSJungseok Lee *pgdp = pgd; 496c79b954bSJungseok Lee dsb(ishst); 497c79b954bSJungseok Lee } 498c79b954bSJungseok Lee 499c79b954bSJungseok Lee static inline void pgd_clear(pgd_t *pgdp) 500c79b954bSJungseok Lee { 501c79b954bSJungseok Lee set_pgd(pgdp, __pgd(0)); 502c79b954bSJungseok Lee } 503c79b954bSJungseok Lee 504c79b954bSJungseok Lee static inline pud_t *pgd_page_vaddr(pgd_t pgd) 505c79b954bSJungseok Lee { 506c79b954bSJungseok Lee return __va(pgd_val(pgd) & PHYS_MASK & (s32)PAGE_MASK); 507c79b954bSJungseok Lee } 508c79b954bSJungseok Lee 5097078db46SCatalin Marinas /* Find an entry in the frst-level page table. */ 5107078db46SCatalin Marinas #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 5117078db46SCatalin Marinas 5127078db46SCatalin Marinas static inline pud_t *pud_offset(pgd_t *pgd, unsigned long addr) 5137078db46SCatalin Marinas { 5147078db46SCatalin Marinas return (pud_t *)pgd_page_vaddr(*pgd) + pud_index(addr); 5157078db46SCatalin Marinas } 5167078db46SCatalin Marinas 5175d96e0cbSJungseok Lee #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(pgd_val(pgd) & PHYS_MASK)) 5185d96e0cbSJungseok Lee 5199f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 520c79b954bSJungseok Lee 5217078db46SCatalin Marinas #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) 5227078db46SCatalin Marinas 5234f04d8f0SCatalin Marinas /* to find an entry in a page-table-directory */ 5244f04d8f0SCatalin Marinas #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 5254f04d8f0SCatalin Marinas 5264f04d8f0SCatalin Marinas #define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr)) 5274f04d8f0SCatalin Marinas 5284f04d8f0SCatalin Marinas /* to find an entry in a kernel page-table-directory */ 5294f04d8f0SCatalin Marinas #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) 5304f04d8f0SCatalin Marinas 5314f04d8f0SCatalin Marinas static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 5324f04d8f0SCatalin Marinas { 533a6fadf7eSWill Deacon const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 5341a541b4eSSteve Capper PTE_PROT_NONE | PTE_VALID | PTE_WRITE; 5352f4b829cSCatalin Marinas /* preserve the hardware dirty information */ 5362f4b829cSCatalin Marinas if (pte_hw_dirty(pte)) 53762d96c71SCatalin Marinas pte = pte_mkdirty(pte); 5384f04d8f0SCatalin Marinas pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 5394f04d8f0SCatalin Marinas return pte; 5404f04d8f0SCatalin Marinas } 5414f04d8f0SCatalin Marinas 5429c7e535fSSteve Capper static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 5439c7e535fSSteve Capper { 5449c7e535fSSteve Capper return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 5459c7e535fSSteve Capper } 5469c7e535fSSteve Capper 5472f4b829cSCatalin Marinas #ifdef CONFIG_ARM64_HW_AFDBM 5482f4b829cSCatalin Marinas /* 5492f4b829cSCatalin Marinas * Atomic pte/pmd modifications. 5502f4b829cSCatalin Marinas */ 5512f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 5522f4b829cSCatalin Marinas static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 5532f4b829cSCatalin Marinas unsigned long address, 5542f4b829cSCatalin Marinas pte_t *ptep) 5552f4b829cSCatalin Marinas { 5562f4b829cSCatalin Marinas pteval_t pteval; 5572f4b829cSCatalin Marinas unsigned int tmp, res; 5582f4b829cSCatalin Marinas 5592f4b829cSCatalin Marinas asm volatile("// ptep_test_and_clear_young\n" 5602f4b829cSCatalin Marinas " prfm pstl1strm, %2\n" 5612f4b829cSCatalin Marinas "1: ldxr %0, %2\n" 5622f4b829cSCatalin Marinas " ubfx %w3, %w0, %5, #1 // extract PTE_AF (young)\n" 5632f4b829cSCatalin Marinas " and %0, %0, %4 // clear PTE_AF\n" 5642f4b829cSCatalin Marinas " stxr %w1, %0, %2\n" 5652f4b829cSCatalin Marinas " cbnz %w1, 1b\n" 5662f4b829cSCatalin Marinas : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)), "=&r" (res) 5672f4b829cSCatalin Marinas : "L" (~PTE_AF), "I" (ilog2(PTE_AF))); 5682f4b829cSCatalin Marinas 5692f4b829cSCatalin Marinas return res; 5702f4b829cSCatalin Marinas } 5712f4b829cSCatalin Marinas 5722f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 5732f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 5742f4b829cSCatalin Marinas static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 5752f4b829cSCatalin Marinas unsigned long address, 5762f4b829cSCatalin Marinas pmd_t *pmdp) 5772f4b829cSCatalin Marinas { 5782f4b829cSCatalin Marinas return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 5792f4b829cSCatalin Marinas } 5802f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 5812f4b829cSCatalin Marinas 5822f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 5832f4b829cSCatalin Marinas static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 5842f4b829cSCatalin Marinas unsigned long address, pte_t *ptep) 5852f4b829cSCatalin Marinas { 5862f4b829cSCatalin Marinas pteval_t old_pteval; 5872f4b829cSCatalin Marinas unsigned int tmp; 5882f4b829cSCatalin Marinas 5892f4b829cSCatalin Marinas asm volatile("// ptep_get_and_clear\n" 5902f4b829cSCatalin Marinas " prfm pstl1strm, %2\n" 5912f4b829cSCatalin Marinas "1: ldxr %0, %2\n" 5922f4b829cSCatalin Marinas " stxr %w1, xzr, %2\n" 5932f4b829cSCatalin Marinas " cbnz %w1, 1b\n" 5942f4b829cSCatalin Marinas : "=&r" (old_pteval), "=&r" (tmp), "+Q" (pte_val(*ptep))); 5952f4b829cSCatalin Marinas 5962f4b829cSCatalin Marinas return __pte(old_pteval); 5972f4b829cSCatalin Marinas } 5982f4b829cSCatalin Marinas 5992f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 6002f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_GET_AND_CLEAR 6012f4b829cSCatalin Marinas static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm, 6022f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 6032f4b829cSCatalin Marinas { 6042f4b829cSCatalin Marinas return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); 6052f4b829cSCatalin Marinas } 6062f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 6072f4b829cSCatalin Marinas 6082f4b829cSCatalin Marinas /* 6092f4b829cSCatalin Marinas * ptep_set_wrprotect - mark read-only while trasferring potential hardware 6102f4b829cSCatalin Marinas * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 6112f4b829cSCatalin Marinas */ 6122f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_SET_WRPROTECT 6132f4b829cSCatalin Marinas static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 6142f4b829cSCatalin Marinas { 6152f4b829cSCatalin Marinas pteval_t pteval; 6162f4b829cSCatalin Marinas unsigned long tmp; 6172f4b829cSCatalin Marinas 6182f4b829cSCatalin Marinas asm volatile("// ptep_set_wrprotect\n" 6192f4b829cSCatalin Marinas " prfm pstl1strm, %2\n" 6202f4b829cSCatalin Marinas "1: ldxr %0, %2\n" 6212f4b829cSCatalin Marinas " tst %0, %4 // check for hw dirty (!PTE_RDONLY)\n" 6222f4b829cSCatalin Marinas " csel %1, %3, xzr, eq // set PTE_DIRTY|PTE_RDONLY if dirty\n" 6232f4b829cSCatalin Marinas " orr %0, %0, %1 // if !dirty, PTE_RDONLY is already set\n" 6242f4b829cSCatalin Marinas " and %0, %0, %5 // clear PTE_WRITE/PTE_DBM\n" 6252f4b829cSCatalin Marinas " stxr %w1, %0, %2\n" 6262f4b829cSCatalin Marinas " cbnz %w1, 1b\n" 6272f4b829cSCatalin Marinas : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)) 6282f4b829cSCatalin Marinas : "r" (PTE_DIRTY|PTE_RDONLY), "L" (PTE_RDONLY), "L" (~PTE_WRITE) 6292f4b829cSCatalin Marinas : "cc"); 6302f4b829cSCatalin Marinas } 6312f4b829cSCatalin Marinas 6322f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 6332f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_SET_WRPROTECT 6342f4b829cSCatalin Marinas static inline void pmdp_set_wrprotect(struct mm_struct *mm, 6352f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 6362f4b829cSCatalin Marinas { 6372f4b829cSCatalin Marinas ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 6382f4b829cSCatalin Marinas } 6392f4b829cSCatalin Marinas #endif 6402f4b829cSCatalin Marinas #endif /* CONFIG_ARM64_HW_AFDBM */ 6412f4b829cSCatalin Marinas 6424f04d8f0SCatalin Marinas extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 6434f04d8f0SCatalin Marinas extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 6444f04d8f0SCatalin Marinas 6454f04d8f0SCatalin Marinas /* 6464f04d8f0SCatalin Marinas * Encode and decode a swap entry: 6473676f9efSCatalin Marinas * bits 0-1: present (must be zero) 6489b3e661eSKirill A. Shutemov * bits 2-7: swap type 6499b3e661eSKirill A. Shutemov * bits 8-57: swap offset 6504f04d8f0SCatalin Marinas */ 6519b3e661eSKirill A. Shutemov #define __SWP_TYPE_SHIFT 2 6524f04d8f0SCatalin Marinas #define __SWP_TYPE_BITS 6 6539b3e661eSKirill A. Shutemov #define __SWP_OFFSET_BITS 50 6544f04d8f0SCatalin Marinas #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 6554f04d8f0SCatalin Marinas #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 6563676f9efSCatalin Marinas #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 6574f04d8f0SCatalin Marinas 6584f04d8f0SCatalin Marinas #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 6593676f9efSCatalin Marinas #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 6604f04d8f0SCatalin Marinas #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 6614f04d8f0SCatalin Marinas 6624f04d8f0SCatalin Marinas #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 6634f04d8f0SCatalin Marinas #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 6644f04d8f0SCatalin Marinas 6654f04d8f0SCatalin Marinas /* 6664f04d8f0SCatalin Marinas * Ensure that there are not more swap files than can be encoded in the kernel 667aad9061bSGeert Uytterhoeven * PTEs. 6684f04d8f0SCatalin Marinas */ 6694f04d8f0SCatalin Marinas #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 6704f04d8f0SCatalin Marinas 6714f04d8f0SCatalin Marinas extern int kern_addr_valid(unsigned long addr); 6724f04d8f0SCatalin Marinas 6734f04d8f0SCatalin Marinas #include <asm-generic/pgtable.h> 6744f04d8f0SCatalin Marinas 67539b5be9bSWill Deacon void pgd_cache_init(void); 67639b5be9bSWill Deacon #define pgtable_cache_init pgd_cache_init 6774f04d8f0SCatalin Marinas 678cba3574fSWill Deacon /* 679cba3574fSWill Deacon * On AArch64, the cache coherency is handled via the set_pte_at() function. 680cba3574fSWill Deacon */ 681cba3574fSWill Deacon static inline void update_mmu_cache(struct vm_area_struct *vma, 682cba3574fSWill Deacon unsigned long addr, pte_t *ptep) 683cba3574fSWill Deacon { 684cba3574fSWill Deacon /* 685120798d2SWill Deacon * We don't do anything here, so there's a very small chance of 686120798d2SWill Deacon * us retaking a user fault which we just fixed up. The alternative 687120798d2SWill Deacon * is doing a dsb(ishst), but that penalises the fastpath. 688cba3574fSWill Deacon */ 689cba3574fSWill Deacon } 690cba3574fSWill Deacon 691cba3574fSWill Deacon #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 692cba3574fSWill Deacon 69303875ad5Syalin wang #define kc_vaddr_to_offset(v) ((v) & ~VA_START) 69403875ad5Syalin wang #define kc_offset_to_vaddr(o) ((o) | VA_START) 6957db743c6SCatalin Marinas 6964f04d8f0SCatalin Marinas #endif /* !__ASSEMBLY__ */ 6974f04d8f0SCatalin Marinas 6984f04d8f0SCatalin Marinas #endif /* __ASM_PGTABLE_H */ 699