1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2022, Xilinx, Inc. 4 * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. 5 */ 6 7 #ifndef _XLNX_VERSAL_NET_CLK_H 8 #define _XLNX_VERSAL_NET_CLK_H 9 10 #include "xlnx-versal-clk.h" 11 12 #define CAN0_REF_2X 0x9e 13 #define CAN1_REF_2X 0xac 14 #define FPD_WWDT0 0xb5 15 #define FPD_WWDT1 0xb6 16 #define FPD_WWDT2 0xb7 17 #define FPD_WWDT3 0xb8 18 #define LPD_WWDT0 0xb9 19 #define LPD_WWDT1 0xba 20 #define ACPU_0 0x98 21 #define ACPU_1 0x9b 22 #define ACPU_2 0x9a 23 #define ACPU_3 0x99 24 #define I3C0_REF 0x9d 25 #define I3C1_REF 0x9f 26 #define USB1_BUS_REF 0xae 27 #define LPD_WWDT 0xad 28 29 /* Remove Versal specific node IDs */ 30 #undef APU_PLL 31 #undef RPU_PLL 32 #undef CPM_PLL 33 #undef APU_PRESRC 34 #undef APU_POSTCLK 35 #undef APU_PLL_OUT 36 #undef APLL 37 #undef RPU_PRESRC 38 #undef RPU_POSTCLK 39 #undef RPU_PLL_OUT 40 #undef RPLL 41 #undef CPM_PRESRC 42 #undef CPM_POSTCLK 43 #undef CPM_PLL_OUT 44 #undef CPLL 45 #undef APLL_TO_XPD 46 #undef RPLL_TO_XPD 47 #undef RCLK_PMC 48 #undef RCLK_LPD 49 #undef WDT 50 #undef MUXED_IRO_DIV2 51 #undef MUXED_IRO_DIV4 52 #undef PSM_REF 53 #undef CPM_CORE_REF 54 #undef CPM_LSBUS_REF 55 #undef CPM_DBG_REF 56 #undef CPM_AUX0_REF 57 #undef CPM_AUX1_REF 58 #undef CPU_R5 59 #undef CPU_R5_CORE 60 #undef CPU_R5_OCM 61 #undef CPU_R5_OCM2 62 #undef CAN0_REF 63 #undef CAN1_REF 64 #undef I2C0_REF 65 #undef I2C1_REF 66 #undef CPM_TOPSW_REF 67 #undef USB3_DUAL_REF 68 #undef MUXED_IRO 69 #undef PL_EXT 70 #undef PL_LB 71 #undef MIO_50_OR_51 72 #undef MIO_24_OR_25 73 74 #endif 75