1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/** 3 * Device Tree Source for enabling IPC using TI SDK firmware on J784S4/J742S2 SoCs 4 * 5 * Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&reserved_memory { 9 mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { 10 compatible = "shared-dma-pool"; 11 reg = <0x00 0xa1000000 0x00 0x100000>; 12 no-map; 13 }; 14 15 mcu_r5fss0_core1_memory_region: memory@a1100000 { 16 compatible = "shared-dma-pool"; 17 reg = <0x00 0xa1100000 0x00 0xf00000>; 18 no-map; 19 }; 20 21 main_r5fss0_core0_dma_memory_region: memory@a2000000 { 22 compatible = "shared-dma-pool"; 23 reg = <0x00 0xa2000000 0x00 0x100000>; 24 no-map; 25 }; 26 27 main_r5fss0_core0_memory_region: memory@a2100000 { 28 compatible = "shared-dma-pool"; 29 reg = <0x00 0xa2100000 0x00 0xf00000>; 30 no-map; 31 }; 32 33 main_r5fss0_core1_dma_memory_region: memory@a3000000 { 34 compatible = "shared-dma-pool"; 35 reg = <0x00 0xa3000000 0x00 0x100000>; 36 no-map; 37 }; 38 39 main_r5fss0_core1_memory_region: memory@a3100000 { 40 compatible = "shared-dma-pool"; 41 reg = <0x00 0xa3100000 0x00 0xf00000>; 42 no-map; 43 }; 44 45 main_r5fss1_core0_dma_memory_region: memory@a4000000 { 46 compatible = "shared-dma-pool"; 47 reg = <0x00 0xa4000000 0x00 0x100000>; 48 no-map; 49 }; 50 51 main_r5fss1_core0_memory_region: memory@a4100000 { 52 compatible = "shared-dma-pool"; 53 reg = <0x00 0xa4100000 0x00 0xf00000>; 54 no-map; 55 }; 56 57 main_r5fss1_core1_dma_memory_region: memory@a5000000 { 58 compatible = "shared-dma-pool"; 59 reg = <0x00 0xa5000000 0x00 0x100000>; 60 no-map; 61 }; 62 63 main_r5fss1_core1_memory_region: memory@a5100000 { 64 compatible = "shared-dma-pool"; 65 reg = <0x00 0xa5100000 0x00 0xf00000>; 66 no-map; 67 }; 68 69 main_r5fss2_core0_dma_memory_region: memory@a6000000 { 70 compatible = "shared-dma-pool"; 71 reg = <0x00 0xa6000000 0x00 0x100000>; 72 no-map; 73 }; 74 75 main_r5fss2_core0_memory_region: memory@a6100000 { 76 compatible = "shared-dma-pool"; 77 reg = <0x00 0xa6100000 0x00 0xf00000>; 78 no-map; 79 }; 80 81 main_r5fss2_core1_dma_memory_region: memory@a7000000 { 82 compatible = "shared-dma-pool"; 83 reg = <0x00 0xa7000000 0x00 0x100000>; 84 no-map; 85 }; 86 87 main_r5fss2_core1_memory_region: memory@a7100000 { 88 compatible = "shared-dma-pool"; 89 reg = <0x00 0xa7100000 0x00 0xf00000>; 90 no-map; 91 }; 92 93 c71_0_dma_memory_region: memory@a8000000 { 94 compatible = "shared-dma-pool"; 95 reg = <0x00 0xa8000000 0x00 0x100000>; 96 no-map; 97 }; 98 99 c71_0_memory_region: memory@a8100000 { 100 compatible = "shared-dma-pool"; 101 reg = <0x00 0xa8100000 0x00 0xf00000>; 102 no-map; 103 }; 104 105 c71_1_dma_memory_region: memory@a9000000 { 106 compatible = "shared-dma-pool"; 107 reg = <0x00 0xa9000000 0x00 0x100000>; 108 no-map; 109 }; 110 111 c71_1_memory_region: memory@a9100000 { 112 compatible = "shared-dma-pool"; 113 reg = <0x00 0xa9100000 0x00 0xf00000>; 114 no-map; 115 }; 116 117 c71_2_dma_memory_region: memory@aa000000 { 118 compatible = "shared-dma-pool"; 119 reg = <0x00 0xaa000000 0x00 0x100000>; 120 no-map; 121 }; 122 123 c71_2_memory_region: memory@aa100000 { 124 compatible = "shared-dma-pool"; 125 reg = <0x00 0xaa100000 0x00 0xf00000>; 126 no-map; 127 }; 128}; 129 130&mailbox0_cluster0 { 131 status = "okay"; 132 interrupts = <436>; 133 134 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 135 ti,mbox-rx = <0 0 0>; 136 ti,mbox-tx = <1 0 0>; 137 }; 138 139 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 140 ti,mbox-rx = <2 0 0>; 141 ti,mbox-tx = <3 0 0>; 142 }; 143}; 144 145&mailbox0_cluster1 { 146 status = "okay"; 147 interrupts = <432>; 148 149 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 150 ti,mbox-rx = <0 0 0>; 151 ti,mbox-tx = <1 0 0>; 152 }; 153 154 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 155 ti,mbox-rx = <2 0 0>; 156 ti,mbox-tx = <3 0 0>; 157 }; 158}; 159 160&mailbox0_cluster2 { 161 status = "okay"; 162 interrupts = <428>; 163 164 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 165 ti,mbox-rx = <0 0 0>; 166 ti,mbox-tx = <1 0 0>; 167 }; 168 169 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 170 ti,mbox-rx = <2 0 0>; 171 ti,mbox-tx = <3 0 0>; 172 }; 173}; 174 175&mailbox0_cluster3 { 176 status = "okay"; 177 interrupts = <424>; 178 179 mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { 180 ti,mbox-rx = <0 0 0>; 181 ti,mbox-tx = <1 0 0>; 182 }; 183 184 mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { 185 ti,mbox-rx = <2 0 0>; 186 ti,mbox-tx = <3 0 0>; 187 }; 188}; 189 190&mailbox0_cluster4 { 191 status = "okay"; 192 interrupts = <420>; 193 194 mbox_c71_0: mbox-c71-0 { 195 ti,mbox-rx = <0 0 0>; 196 ti,mbox-tx = <1 0 0>; 197 }; 198 199 mbox_c71_1: mbox-c71-1 { 200 ti,mbox-rx = <2 0 0>; 201 ti,mbox-tx = <3 0 0>; 202 }; 203}; 204 205&mailbox0_cluster5 { 206 status = "okay"; 207 interrupts = <416>; 208 209 mbox_c71_2: mbox-c71-2 { 210 ti,mbox-rx = <0 0 0>; 211 ti,mbox-tx = <1 0 0>; 212 }; 213}; 214 215/* Timers are used by Remoteproc firmware */ 216&main_timer0 { 217 status = "reserved"; 218}; 219 220&main_timer1 { 221 status = "reserved"; 222}; 223 224&main_timer2 { 225 status = "reserved"; 226}; 227 228&main_timer3 { 229 status = "reserved"; 230}; 231 232&main_timer4 { 233 status = "reserved"; 234}; 235 236&main_timer5 { 237 status = "reserved"; 238}; 239 240&main_timer6 { 241 status = "reserved"; 242}; 243 244&main_timer7 { 245 status = "reserved"; 246}; 247 248&main_timer8 { 249 status = "reserved"; 250}; 251 252&main_timer9 { 253 status = "reserved"; 254}; 255 256&mcu_r5fss0 { 257 status = "okay"; 258}; 259 260&mcu_r5fss0_core0 { 261 status = "okay"; 262 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 263 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 264 <&mcu_r5fss0_core0_memory_region>; 265}; 266 267&mcu_r5fss0_core1 { 268 status = "okay"; 269 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 270 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 271 <&mcu_r5fss0_core1_memory_region>; 272}; 273 274&main_r5fss0 { 275 ti,cluster-mode = <0>; 276 status = "okay"; 277}; 278 279&main_r5fss0_core0 { 280 status = "okay"; 281 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 282 memory-region = <&main_r5fss0_core0_dma_memory_region>, 283 <&main_r5fss0_core0_memory_region>; 284}; 285 286&main_r5fss0_core1 { 287 status = "okay"; 288 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 289 memory-region = <&main_r5fss0_core1_dma_memory_region>, 290 <&main_r5fss0_core1_memory_region>; 291}; 292 293&main_r5fss1 { 294 ti,cluster-mode = <0>; 295 status = "okay"; 296}; 297 298&main_r5fss1_core0 { 299 status = "okay"; 300 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 301 memory-region = <&main_r5fss1_core0_dma_memory_region>, 302 <&main_r5fss1_core0_memory_region>; 303}; 304 305&main_r5fss1_core1 { 306 status = "okay"; 307 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 308 memory-region = <&main_r5fss1_core1_dma_memory_region>, 309 <&main_r5fss1_core1_memory_region>; 310}; 311 312&main_r5fss2 { 313 ti,cluster-mode = <0>; 314 status = "okay"; 315}; 316 317&main_r5fss2_core0 { 318 status = "okay"; 319 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; 320 memory-region = <&main_r5fss2_core0_dma_memory_region>, 321 <&main_r5fss2_core0_memory_region>; 322}; 323 324&main_r5fss2_core1 { 325 status = "okay"; 326 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; 327 memory-region = <&main_r5fss2_core1_dma_memory_region>, 328 <&main_r5fss2_core1_memory_region>; 329}; 330 331&c71_0 { 332 status = "okay"; 333 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 334 memory-region = <&c71_0_dma_memory_region>, 335 <&c71_0_memory_region>; 336}; 337 338&c71_1 { 339 status = "okay"; 340 mboxes = <&mailbox0_cluster4 &mbox_c71_1>; 341 memory-region = <&c71_1_dma_memory_region>, 342 <&c71_1_memory_region>; 343}; 344 345&c71_2 { 346 status = "okay"; 347 mboxes = <&mailbox0_cluster5 &mbox_c71_2>; 348 memory-region = <&c71_2_dma_memory_region>, 349 <&c71_2_memory_region>; 350}; 351