1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Kontron SMARC-sAM67 module 4 * 5 * Copyright (c) 2025 Kontron Europe GmbH 6 */ 7 8/dts-v1/; 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/phy/phy.h> 13#include "k3-j722s.dtsi" 14#include "k3-serdes.h" 15 16/ { 17 compatible = "kontron,sa67", "ti,j722s"; 18 model = "Kontron SMARC-sAM67"; 19 20 aliases { 21 serial0 = &mcu_uart0; 22 serial1 = &main_uart0; 23 serial2 = &main_uart5; 24 serial3 = &wkup_uart0; 25 mmc0 = &sdhci0; 26 mmc1 = &sdhci1; 27 rtc0 = &wkup_rtc0; 28 }; 29 30 lcd0_backlight: backlight-1 { 31 compatible = "pwm-backlight"; 32 pinctrl-names = "default"; 33 pinctrl-0 = <&lcd0_backlight_pins_default>; 34 pwms = <&epwm1 0 50000 0>; 35 brightness-levels = <0 32 64 96 128 160 192 224 255>; 36 default-brightness-level = <8>; 37 enable-gpios = <&main_gpio0 29 GPIO_ACTIVE_HIGH>; 38 status = "disabled"; 39 }; 40 41 lcd1_backlight: backlight-2 { 42 compatible = "pwm-backlight"; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&lcd1_backlight_pins_default>; 45 pwms = <&epwm1 1 50000 0>; 46 brightness-levels = <0 32 64 96 128 160 192 224 255>; 47 default-brightness-level = <8>; 48 enable-gpios = <&main_gpio1 18 GPIO_ACTIVE_HIGH>; 49 status = "disabled"; 50 }; 51 52 chosen { 53 stdout-path = "serial1:115200n8"; 54 }; 55 56 connector-1 { 57 compatible = "gpio-usb-b-connector", "usb-b-connector"; 58 pinctrl-names = "default"; 59 pinctrl-0 = <&usb0_connector_pins_default>; 60 type = "micro"; 61 id-gpios = <&main_gpio0 34 GPIO_ACTIVE_HIGH>; 62 vbus-supply = <&vcc_usb0_vbus>; 63 64 port { 65 usb0_connector: endpoint { 66 remote-endpoint = <&usb0_hc>; 67 }; 68 }; 69 70 }; 71 72 memory@80000000 { 73 /* Filled in by bootloader */ 74 reg = <0x00000000 0x00000000 0x00000000 0x00000000>, 75 <0x00000000 0x00000000 0x00000000 0x00000000>; 76 device_type = "memory"; 77 bootph-pre-ram; 78 }; 79 80 reserved_memory: reserved-memory { 81 #address-cells = <2>; 82 #size-cells = <2>; 83 ranges; 84 85 linux,cma { 86 compatible = "shared-dma-pool"; 87 reusable; 88 size = <0x10000000>; 89 alignment = <0x2000>; 90 linux,cma-default; 91 }; 92 93 secure_tfa_ddr: tfa@9e780000 { 94 reg = <0x00 0x9e780000 0x00 0x80000>; 95 no-map; 96 }; 97 98 secure_ddr: optee@9e800000 { 99 reg = <0x00 0x9e800000 0x00 0x01800000>; 100 no-map; 101 }; 102 103 wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { 104 compatible = "shared-dma-pool"; 105 reg = <0x00 0xa0100000 0x00 0xf00000>; 106 no-map; 107 }; 108 }; 109 110 vin_5p0: regulator-1 { 111 compatible = "regulator-fixed"; 112 regulator-name = "V_3V0_5V25_IN"; 113 regulator-min-microvolt = <5000000>; 114 regulator-max-microvolt = <5000000>; 115 regulator-always-on; 116 regulator-boot-on; 117 bootph-all; 118 }; 119 120 vcc_3p3_s5: regulator-2 { 121 compatible = "regulator-fixed"; 122 regulator-name = "V_3V3_S5"; 123 regulator-min-microvolt = <3300000>; 124 regulator-max-microvolt = <3300000>; 125 vin-supply = <&vin_5p0>; 126 regulator-always-on; 127 regulator-boot-on; 128 bootph-all; 129 }; 130 131 vcc_1p8_s5: regulator-3 { 132 compatible = "regulator-fixed"; 133 regulator-name = "V_1V8_S5"; 134 regulator-min-microvolt = <1800000>; 135 regulator-max-microvolt = <1800000>; 136 vin-supply = <&vin_5p0>; 137 regulator-always-on; 138 regulator-boot-on; 139 bootph-all; 140 }; 141 142 vcc_3p3_s0: regulator-4 { 143 compatible = "regulator-fixed"; 144 regulator-name = "V_3V3_S0"; 145 regulator-min-microvolt = <3300000>; 146 regulator-max-microvolt = <3300000>; 147 vin-supply = <&vcc_3p3_s5>; 148 regulator-always-on; 149 regulator-boot-on; 150 enable-active-high; 151 gpios = <&tps652g1 1 GPIO_ACTIVE_HIGH>; 152 bootph-all; 153 }; 154 155 vcc_3p3_sd_s0: regulator-5 { 156 compatible = "regulator-fixed"; 157 regulator-name = "SDIO_PWR_EN"; 158 pinctrl-names = "default"; 159 pinctrl-0 = <&vcc_3p3_sd_s0_pins_default>; 160 regulator-min-microvolt = <3300000>; 161 regulator-max-microvolt = <3300000>; 162 regulator-boot-on; 163 enable-active-high; 164 gpios = <&main_gpio0 7 GPIO_ACTIVE_HIGH>; 165 bootph-all; 166 }; 167 168 vcc_3p3_sd_vio_s0: regulator-6 { 169 compatible = "regulator-gpio"; 170 regulator-name = "V_3V3_1V8_SD_S0"; 171 pinctrl-names = "default"; 172 pinctrl-0 = <&vcc_3p3_sd_vio_s0_pins_default>; 173 regulator-min-microvolt = <1800000>; 174 regulator-max-microvolt = <3300000>; 175 vin-supply = <&vcc_3p3_s0>; 176 regulator-boot-on; 177 enable-gpios = <&main_gpio0 7 GPIO_ACTIVE_HIGH>; 178 gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; 179 states = <3300000 0x0>, 180 <1800000 0x1>; 181 bootph-all; 182 }; 183 184 vcc_3p3_cam_s0: regulator-7 { 185 compatible = "regulator-fixed"; 186 regulator-name = "V_3V3_CAM_S0"; 187 pinctrl-names = "default"; 188 pinctrl-0 = <&vcc_3p3_cam_s0_pins_default>; 189 regulator-min-microvolt = <3300000>; 190 regulator-max-microvolt = <3300000>; 191 vin-supply = <&vcc_3p3_s5>; 192 enable-active-high; 193 interrupts-extended = <&main_gpio1 30 IRQ_TYPE_EDGE_FALLING>; 194 bootph-all; 195 }; 196 197 vcc_1p1_s0: regulator-8 { 198 compatible = "regulator-fixed"; 199 regulator-name = "V_1V1_S0"; 200 regulator-min-microvolt = <1100000>; 201 regulator-max-microvolt = <1100000>; 202 vin-supply = <&vcc_1p1_s3>; 203 regulator-always-on; 204 regulator-boot-on; 205 enable-active-high; 206 /* shared with V_0V75_0V85_CORE_S0 */ 207 gpios = <&tps652g1 4 GPIO_ACTIVE_HIGH>; 208 bootph-all; 209 }; 210 211 vcc_0p85_vcore_s0: regulator-9 { 212 compatible = "regulator-fixed"; 213 regulator-name = "V_0V75_0V85_CORE_S0"; 214 regulator-min-microvolt = <850000>; 215 regulator-max-microvolt = <850000>; 216 vin-supply = <&vin_5p0>; 217 regulator-always-on; 218 regulator-boot-on; 219 enable-active-high; 220 gpios = <&tps652g1 4 GPIO_ACTIVE_HIGH>; 221 bootph-all; 222 }; 223 224 vcc_lcd0_panel: regulator-10 { 225 compatible = "regulator-fixed"; 226 regulator-name = "LCD0_VDD_EN"; 227 pinctrl-names = "default"; 228 pinctrl-0 = <&vcc_lcd0_panel_pins_default>; 229 enable-active-high; 230 gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>; 231 }; 232 233 vcc_lcd1_panel: regulator-11 { 234 compatible = "regulator-fixed"; 235 regulator-name = "LCD1_VDD_EN"; 236 pinctrl-names = "default"; 237 pinctrl-0 = <&vcc_lcd1_panel_pins_default>; 238 enable-active-high; 239 gpios = <&main_gpio1 19 GPIO_ACTIVE_HIGH>; 240 }; 241 242 vcc_usb0_vbus: regulator-12 { 243 compatible = "regulator-fixed"; 244 regulator-name = "USB0_EN_OC#"; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&vcc_usb0_vbus_pins_default>; 247 regulator-min-microvolt = <5000000>; 248 regulator-max-microvolt = <5000000>; 249 enable-active-high; 250 gpios = <&main_gpio1 50 GPIO_ACTIVE_HIGH>; 251 }; 252}; 253 254&audio_refclk0 { 255 pinctrl-names = "default"; 256 pinctrl-0 = <&audio_refclk0_pins_default>; 257 status = "disabled"; 258}; 259 260&audio_refclk1 { 261 pinctrl-names = "default"; 262 pinctrl-0 = <&audio_refclk1_pins_default>; 263 status = "disabled"; 264}; 265 266&cpsw3g { 267 pinctrl-names = "default"; 268 pinctrl-0 = <&cpsw3g_pins_default>, <&rgmii1_pins_default>, 269 <&rgmii2_pins_default>; 270 status = "okay"; 271}; 272 273&cpsw3g_mdio { 274 pinctrl-names = "default"; 275 pinctrl-0 = <&cpsw3g_mdio_pins_default>; 276 status = "okay"; 277 278 phy0: ethernet-phy@0 { 279 reg = <0>; 280 }; 281 282 phy1: ethernet-phy@1 { 283 reg = <1>; 284 }; 285}; 286 287&cpsw_port1 { 288 phy-connection-type = "rgmii-id"; 289 phy-handle = <&phy0>; 290 nvmem-cells = <&base_mac_address 0>; 291 nvmem-cell-names = "mac-address"; 292 status = "okay"; 293}; 294 295&main_gpio0 { 296 gpio-line-names = 297 "", "", "", "", "", "", "", "SOC_SDIO_PWR_EN", "VSD_SEL", 298 "RESET_OUT#", "I2C_MUX_RST#", "SPI_FLASH_CS#", "QPSI_CS0#", 299 "QSPI_CS1#", "BOOT_SEL1", "BRDCFG0", "BRDCFG1", "BRDCFG2", 300 "BRDCFG3", "BRDCFG4", "", "BRDREV0", "BRDREV1", "", "", "", "", 301 "", "", "LCD0_BKLT_EN", "LCD0_VDD_EN", "GBE_INT#", "DSI0_TE", 302 "CHARGING#", "USB0_OTG_ID", "PMIC_INT#", "RTC_INT#", 303 "EDP_BRIDGE_EN", "EDP_BRIDGE_IRQ#", "", "CHARGER_PRSNT#", "", 304 "", "", "", "BOOT_SEL2#", "CAM2_RST#", "CAM2_PWR#", "", 305 "CAM3_RST#", "CAM3_PWR#", "GPIO0", "GPIO1", "", "", "", "", "", 306 "", "", "", "", "", "", "", "", "", "", "", "GPIO10", "GPIO11", 307 "SLEEP#", "LID#"; 308 309 bootph-all; 310 status = "okay"; 311}; 312 313&main_gpio1 { 314 gpio-line-names = 315 "", "", "", "", "", "", "", "GPIO6", "GPIO7", "", "", "", "", 316 "GPIO8", "GPIO9", "PCIE_A_RST#", "", "BATLOW#", "LCD1_BKLT_EN", 317 "LCD1_VDD_EN", "", "", "", "", "GPIO2", "GPIO3", "", "", 318 "GPIO4", "GPIO5", "CAM_S0_FAULT#", "BOOT_SEL0#", "", "", "", "", 319 "", "", "", "", "", "", "", "", "", "", "", "", "SDIO_CD#", "", 320 "USB0_DRVVBUS", "USB1_DRVVBUS"; 321 322 bootph-all; 323 status = "okay"; 324}; 325 326/* I2C_LOCAL */ 327&main_i2c0 { 328 pinctrl-names = "default"; 329 pinctrl-0 = <&main_i2c0_pins_default>; 330 clock-frequency = <100000>; 331 bootph-all; 332 status = "okay"; 333 334 tps652g1: pmic@44 { 335 compatible = "ti,tps652g1"; 336 reg = <0x44>; 337 ti,primary-pmic; 338 system-power-controller; 339 340 gpio-controller; 341 #gpio-cells = <2>; 342 gpio-line-names = 343 "LPM_EN#", "EN_3V3_S0", "POWER_BTN#", "CARRIER_STBY#", 344 "EN_0V75_0V85_VCORE_S0", "PMIC_WAKEUP"; 345 346 pinctrl-names = "default"; 347 pinctrl-0 = <&pmic_irq_pins_default>; 348 interrupts-extended = <&main_gpio0 35 IRQ_TYPE_EDGE_FALLING>; 349 350 buck1-supply = <&vin_5p0>; 351 buck2-supply = <&vin_5p0>; 352 buck3-supply = <&vin_5p0>; 353 buck4-supply = <&vin_5p0>; 354 ldo1-supply = <&vin_5p0>; 355 ldo2-supply = <&vin_5p0>; 356 ldo3-supply = <&vin_5p0>; 357 358 bootph-all; 359 360 regulators { 361 vcc_0p85_s0: buck1 { 362 regulator-name = "V_0V85_S0"; 363 regulator-min-microvolt = <850000>; 364 regulator-max-microvolt = <850000>; 365 regulator-boot-on; 366 regulator-always-on; 367 }; 368 369 vcc_1p1_s3: buck2 { 370 regulator-name = "V_1V1_S3"; 371 regulator-min-microvolt = <1100000>; 372 regulator-max-microvolt = <1100000>; 373 regulator-boot-on; 374 regulator-always-on; 375 }; 376 377 vcc_1p8_s0: buck3 { 378 regulator-name = "V_1V8_S0"; 379 regulator-min-microvolt = <1800000>; 380 regulator-max-microvolt = <1800000>; 381 regulator-boot-on; 382 regulator-always-on; 383 }; 384 385 vcc_1p2_s0: buck4 { 386 regulator-name = "V_1V2_S0"; 387 regulator-min-microvolt = <1200000>; 388 regulator-max-microvolt = <1200000>; 389 regulator-boot-on; 390 regulator-always-on; 391 }; 392 393 vcc_1p8_vda_pll_s0: ldo1 { 394 regulator-name = "V_1V8_VDA_PLL_S0"; 395 regulator-min-microvolt = <1800000>; 396 regulator-max-microvolt = <1800000>; 397 regulator-boot-on; 398 regulator-always-on; 399 }; 400 401 vcc_1p8_s3: ldo2 { 402 regulator-name = "V_1V8_S3"; 403 regulator-min-microvolt = <1800000>; 404 regulator-max-microvolt = <1800000>; 405 regulator-boot-on; 406 regulator-always-on; 407 }; 408 409 vcc_1p8_ret_s5: ldo3 { 410 regulator-name = "V_1V8_RET_S5"; 411 regulator-min-microvolt = <1800000>; 412 regulator-max-microvolt = <1800000>; 413 regulator-boot-on; 414 regulator-always-on; 415 }; 416 }; 417 }; 418 419 system-controller@4a { 420 compatible = "kontron,sa67mcu", "kontron,sl28cpld"; 421 reg = <0x4a>; 422 #address-cells = <1>; 423 #size-cells = <0>; 424 425 watchdog@4 { 426 compatible = "kontron,sa67mcu-wdt", "kontron,sl28cpld-wdt"; 427 reg = <0x4>; 428 kontron,assert-wdt-timeout-pin; 429 }; 430 431 hwmon@8 { 432 compatible = "kontron,sa67mcu-hwmon"; 433 reg = <0x8>; 434 }; 435 }; 436}; 437 438/* I2C_CAM */ 439&main_i2c2 { 440 pinctrl-names = "default"; 441 pinctrl-0 = <&main_i2c2_pins_default>; 442 clock-frequency = <100000>; 443 status = "okay"; 444 445 i2c-mux@70 { 446 compatible = "nxp,pca9546"; 447 reg = <0x70>; 448 #address-cells = <1>; 449 #size-cells = <0>; 450 451 pinctrl-names = "default"; 452 pinctrl-0 = <&i2c_mux_pins_default>; 453 454 vdd-supply = <&vcc_1p8_s0>; 455 reset-gpios = <&main_gpio0 10 GPIO_ACTIVE_LOW>; 456 457 i2c_cam0: i2c@0 { 458 #address-cells = <1>; 459 #size-cells = <0>; 460 reg = <0>; 461 }; 462 463 i2c_cam1: i2c@1 { 464 #address-cells = <1>; 465 #size-cells = <0>; 466 reg = <1>; 467 }; 468 469 i2c_cam2: i2c@2 { 470 #address-cells = <1>; 471 #size-cells = <0>; 472 reg = <2>; 473 }; 474 475 i2c_cam3: i2c@3 { 476 #address-cells = <1>; 477 #size-cells = <0>; 478 reg = <3>; 479 }; 480 }; 481}; 482 483/* I2C_LCD */ 484&main_i2c3 { 485 pinctrl-names = "default"; 486 pinctrl-0 = <&main_i2c3_pins_default>; 487 clock-frequency = <100000>; 488 status = "okay"; 489}; 490 491&main_pmx0 { 492 audio_refclk0_pins_default: audio-refclk0-default-pins { 493 pinctrl-single,pins = < 494 J722S_IOPAD(0x0c4, PIN_OUTPUT, 5) /* (W23) VOUT0_DATA3.AUDIO_EXT_REFCLK0 */ 495 >; 496 }; 497 498 audio_refclk1_pins_default: audio-refclk1-default-pins { 499 pinctrl-single,pins = < 500 J722S_IOPAD(0x0a0, PIN_OUTPUT, 1) /* (N24) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ 501 >; 502 }; 503 504 cpsw3g_mdio_pins_default: cpsw3g-mdio-default-pins { 505 pinctrl-single,pins = < 506 J722S_IOPAD(0x160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */ 507 J722S_IOPAD(0x15c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */ 508 >; 509 }; 510 511 cpsw3g_pins_default: cpsw3g-default-pins { 512 pinctrl-single,pins = < 513 J722S_IOPAD(0x1b8, PIN_OUTPUT, 1) /* (C20) SPI0_CS1.CP_GEMAC_CPTS0_TS_COMP */ 514 >; 515 }; 516 517 edp_bridge_pins_default: edp-bridge-default-pins { 518 pinctrl-single,pins = < 519 J722S_IOPAD(0x098, PIN_OUTPUT, 7) /* (V21) GPMC0_WAIT0.GPIO0_37 */ 520 J722S_IOPAD(0x09c, PIN_INPUT, 7) /* (W26) GPMC0_WAIT1.GPIO0_38 */ 521 >; 522 }; 523 524 i2c_mux_pins_default: i2c-mux-default-pins { 525 pinctrl-single,pins = < 526 J722S_IOPAD(0x028, PIN_OUTPUT, 7) /* (M27) OSPI0_D7.GPIO0_10 */ 527 >; 528 }; 529 530 lcd0_backlight_pins_default: lcd0-backlight-default-pins { 531 pinctrl-single,pins = < 532 J722S_IOPAD(0x074, PIN_OUTPUT, 7) /* (V22) GPMC0_AD14.GPIO0_29 */ 533 J722S_IOPAD(0x110, PIN_OUTPUT, 4) /* (G27) MMC2_DAT1.EHRPWM1_A */ 534 >; 535 }; 536 537 lcd1_backlight_pins_default: lcd1-backlight-default-pins { 538 pinctrl-single,pins = < 539 J722S_IOPAD(0x1c0, PIN_OUTPUT, 7) /* (E19) SPI0_D0.GPIO1_18 */ 540 J722S_IOPAD(0x114, PIN_OUTPUT, 4) /* (G26) MMC2_DAT0.EHRPWM1_B */ 541 >; 542 }; 543 544 main_i2c0_pins_default: main-i2c0-default-pins { 545 pinctrl-single,pins = < 546 J722S_IOPAD(0x1e0, PIN_INPUT, 0) /* (D23) I2C0_SCL */ 547 J722S_IOPAD(0x1e4, PIN_INPUT, 0) /* (B22) I2C0_SDA */ 548 >; 549 bootph-all; 550 }; 551 552 main_i2c2_pins_default: main-i2c2-default-pins { 553 pinctrl-single,pins = < 554 J722S_IOPAD(0x0b0, PIN_INPUT, 1) /* (P22) GPMC0_CSn2.I2C2_SCL */ 555 J722S_IOPAD(0x0b4, PIN_INPUT, 1) /* (P23) GPMC0_CSn3.I2C2_SDA */ 556 >; 557 }; 558 559 main_i2c3_pins_default: main-i2c3-default-pins { 560 pinctrl-single,pins = < 561 J722S_IOPAD(0x1d0, PIN_INPUT, 2) /* (E22) UART0_CTSn.I2C3_SCL */ 562 J722S_IOPAD(0x1d4, PIN_INPUT, 2) /* (B21) UART0_RTSn.I2C3_SDA */ 563 >; 564 }; 565 566 main_i2c4_pins_default: main-i2c4-default-pins { 567 pinctrl-single,pins = < 568 J722S_IOPAD(0x0a8, PIN_INPUT, 1) /* (R27) GPMC0_CSn0.I2C4_SCL */ 569 J722S_IOPAD(0x0ac, PIN_INPUT, 1) /* (P21) GPMC0_CSn1.I2C4_SDA */ 570 >; 571 }; 572 573 main_uart0_pins_default: main-uart0-default-pins { 574 pinctrl-single,pins = < 575 J722S_IOPAD(0x1c8, PIN_INPUT, 0) /* (F19) UART0_RXD */ 576 J722S_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (F20) UART0_TXD */ 577 >; 578 bootph-all; 579 }; 580 581 main_uart5_pins_default: main-uart5-default-pins { 582 pinctrl-single,pins = < 583 J722S_IOPAD(0x108, PIN_INPUT, 3) /* (J27) MMC2_DAT3.UART5_RXD */ 584 J722S_IOPAD(0x10c, PIN_OUTPUT, 3) /* (H27) MMC2_DAT2.UART5_TXD */ 585 J722S_IOPAD(0x008, PIN_INPUT, 5) /* (L22) OSPI0_DQS.UART5_CTSn */ 586 J722S_IOPAD(0x004, PIN_OUTPUT, 5) /* (L23) OSPI0_LBCLKO.UART5_RTSn */ 587 >; 588 }; 589 590 mcasp0_pins_default: mcasp0-default-pins { 591 pinctrl-single,pins = < 592 J722S_IOPAD(0x1a4, PIN_INPUT, 0) /* (D25) MCASP0_ACLKX */ 593 J722S_IOPAD(0x1a8, PIN_INPUT, 0) /* (C26) MCASP0_AFSX */ 594 J722S_IOPAD(0x1a0, PIN_INPUT, 0) /* (F23) MCASP0_AXR0 */ 595 J722S_IOPAD(0x19c, PIN_OUTPUT, 0) /* (B25) MCASP0_AXR1 */ 596 >; 597 }; 598 599 mcasp2_pins_default: mcasp2-default-pins { 600 pinctrl-single,pins = < 601 J722S_IOPAD(0x070, PIN_INPUT, 3) /* (V24) GPMC0_AD13.MCASP2_ACLKX */ 602 J722S_IOPAD(0x06c, PIN_INPUT, 3) /* (V26) GPMC0_AD12.MCASP2_AFSX */ 603 J722S_IOPAD(0x05c, PIN_INPUT, 3) /* (U27) GPMC0_AD8.MCASP2_AXR0 */ 604 J722S_IOPAD(0x060, PIN_OUTPUT, 3) /* (U26) GPMC0_AD9.MCASP2_AXR1 */ 605 >; 606 }; 607 608 oldi0_pins_default: oldi0-default-pins { 609 pinctrl-single,pins = < 610 J722S_IOPAD(0x260, PIN_OUTPUT, 0) /* (AF23) OLDI0_A0N */ 611 J722S_IOPAD(0x25c, PIN_OUTPUT, 0) /* (AG24) OLDI0_A0P */ 612 J722S_IOPAD(0x268, PIN_OUTPUT, 0) /* (AG22) OLDI0_A1N */ 613 J722S_IOPAD(0x264, PIN_OUTPUT, 0) /* (AG23) OLDI0_A1P */ 614 J722S_IOPAD(0x270, PIN_OUTPUT, 0) /* (AB20) OLDI0_A2N */ 615 J722S_IOPAD(0x26c, PIN_OUTPUT, 0) /* (AB21) OLDI0_A2P */ 616 J722S_IOPAD(0x278, PIN_OUTPUT, 0) /* (AG20) OLDI0_A3N */ 617 J722S_IOPAD(0x274, PIN_OUTPUT, 0) /* (AG21) OLDI0_A3P */ 618 J722S_IOPAD(0x2a0, PIN_OUTPUT, 0) /* (AF21) OLDI0_CLK0N */ 619 J722S_IOPAD(0x29c, PIN_OUTPUT, 0) /* (AE20) OLDI0_CLK0P */ 620 >; 621 }; 622 623 oldi1_pins_default: oldi1-default-pins { 624 pinctrl-single,pins = < 625 J722S_IOPAD(0x280, PIN_OUTPUT, 0) /* (AD21) OLDI0_A4N */ 626 J722S_IOPAD(0x27c, PIN_OUTPUT, 0) /* (AC21) OLDI0_A4P */ 627 J722S_IOPAD(0x288, PIN_OUTPUT, 0) /* (AF19) OLDI0_A5N */ 628 J722S_IOPAD(0x284, PIN_OUTPUT, 0) /* (AF18) OLDI0_A5P */ 629 J722S_IOPAD(0x290, PIN_OUTPUT, 0) /* (AG17) OLDI0_A6N */ 630 J722S_IOPAD(0x28c, PIN_OUTPUT, 0) /* (AG18) OLDI0_A6P */ 631 J722S_IOPAD(0x298, PIN_OUTPUT, 0) /* (AB19) OLDI0_A7N */ 632 J722S_IOPAD(0x294, PIN_OUTPUT, 0) /* (AA20) OLDI0_A7P */ 633 J722S_IOPAD(0x2a8, PIN_OUTPUT, 0) /* (AD20) OLDI0_CLK1N */ 634 J722S_IOPAD(0x2a4, PIN_OUTPUT, 0) /* (AE19) OLDI0_CLK1P */ 635 >; 636 }; 637 638 ospi0_pins_default: ospi0-default-pins { 639 pinctrl-single,pins = < 640 J722S_IOPAD(0x000, PIN_OUTPUT, 0) /* (L24) OSPI0_CLK */ 641 J722S_IOPAD(0x02c, PIN_OUTPUT, 0) /* (K26) OSPI0_CSn0 */ 642 J722S_IOPAD(0x030, PIN_OUTPUT, 0) /* (K23) OSPI0_CSn1 */ 643 J722S_IOPAD(0x034, PIN_OUTPUT, 0) /* (K22) OSPI0_CSn2 */ 644 J722S_IOPAD(0x00c, PIN_INPUT, 0) /* (K27) OSPI0_D0 */ 645 J722S_IOPAD(0x010, PIN_INPUT, 0) /* (L27) OSPI0_D1 */ 646 J722S_IOPAD(0x014, PIN_INPUT, 0) /* (L26) OSPI0_D2 */ 647 J722S_IOPAD(0x018, PIN_INPUT, 0) /* (L25) OSPI0_D3 */ 648 >; 649 bootph-all; 650 }; 651 652 pcie0_rc_pins_default: pcie0-rc-default-pins { 653 pinctrl-single,pins = < 654 J722S_IOPAD(0x2ac, PIN_OUTPUT, 0) /* (F25) PCIE0_CLKREQn */ 655 J722S_IOPAD(0x1b4, PIN_OUTPUT, 7) /* (B20) SPI0_CS0.GPIO1_15 */ 656 >; 657 }; 658 659 pmic_irq_pins_default: pmic-irq-default-pins { 660 pinctrl-single,pins = < 661 J722S_IOPAD(0x090, PIN_INPUT, 7) /* (P27) GPMC0_BE0n_CLE.GPIO0_35 */ 662 >; 663 }; 664 665 rgmii1_pins_default: rgmii1-default-pins { 666 pinctrl-single,pins = < 667 J722S_IOPAD(0x14c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */ 668 J722S_IOPAD(0x150, PIN_INPUT, 0) /* (AD27) RGMII1_RD1 */ 669 J722S_IOPAD(0x154, PIN_INPUT, 0) /* (AE24) RGMII1_RD2 */ 670 J722S_IOPAD(0x158, PIN_INPUT, 0) /* (AE26) RGMII1_RD3 */ 671 J722S_IOPAD(0x148, PIN_INPUT, 0) /* (AE27) RGMII1_RXC */ 672 J722S_IOPAD(0x144, PIN_INPUT, 0) /* (AD23) RGMII1_RX_CTL */ 673 J722S_IOPAD(0x134, PIN_OUTPUT, 0) /* (AF27) RGMII1_TD0 */ 674 J722S_IOPAD(0x138, PIN_OUTPUT, 0) /* (AE23) RGMII1_TD1 */ 675 J722S_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AG25) RGMII1_TD2 */ 676 J722S_IOPAD(0x140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3 */ 677 J722S_IOPAD(0x130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */ 678 J722S_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ 679 >; 680 }; 681 682 rgmii2_pins_default: rgmii2-default-pins { 683 pinctrl-single,pins = < 684 J722S_IOPAD(0x0f8, PIN_INPUT, 2) /* (AB24) VOUT0_HSYNC.RGMII2_RD0 */ 685 J722S_IOPAD(0x0fc, PIN_INPUT, 2) /* (AC27) VOUT0_DE.RGMII2_RD1 */ 686 J722S_IOPAD(0x100, PIN_INPUT, 2) /* (AB23) VOUT0_VSYNC.RGMII2_RD2 */ 687 J722S_IOPAD(0x104, PIN_INPUT, 2) /* (AC26) VOUT0_PCLK.RGMII2_RD3 */ 688 J722S_IOPAD(0x0f4, PIN_INPUT, 2) /* (AB27) VOUT0_DATA15.RGMII2_RXC */ 689 J722S_IOPAD(0x0f0, PIN_INPUT, 2) /* (AB26) VOUT0_DATA14.RGMII2_RX_CTL */ 690 J722S_IOPAD(0x0e0, PIN_OUTPUT, 2) /* (AA25) VOUT0_DATA10.RGMII2_TD0 */ 691 J722S_IOPAD(0x0e4, PIN_OUTPUT, 2) /* (AB25) VOUT0_DATA11.RGMII2_TD1 */ 692 J722S_IOPAD(0x0e8, PIN_OUTPUT, 2) /* (AA23) VOUT0_DATA12.RGMII2_TD2 */ 693 J722S_IOPAD(0x0ec, PIN_OUTPUT, 2) /* (AA22) VOUT0_DATA13.RGMII2_TD3 */ 694 J722S_IOPAD(0x0dc, PIN_OUTPUT, 2) /* (AA27) VOUT0_DATA9.RGMII2_TXC */ 695 J722S_IOPAD(0x0d8, PIN_OUTPUT, 2) /* (AA24) VOUT0_DATA8.RGMII2_TX_CTL */ 696 >; 697 }; 698 699 rtc_pins_default: rtc-default-pins { 700 pinctrl-single,pins = < 701 J722S_IOPAD(0x094, PIN_INPUT, 7) /* (P26) GPMC0_BE1n.GPIO0_36 */ 702 >; 703 }; 704 705 sdhci1_pins_default: sdhci1-default-pins { 706 pinctrl-single,pins = < 707 J722S_IOPAD(0x23c, PIN_INPUT, 0) /* (H22) MMC1_CMD */ 708 J722S_IOPAD(0x234, PIN_OUTPUT, 0) /* (H24) MMC1_CLK */ 709 J722S_IOPAD(0x230, PIN_INPUT, 0) /* (H23) MMC1_DAT0 */ 710 J722S_IOPAD(0x22c, PIN_INPUT, 0) /* (H20) MMC1_DAT1 */ 711 J722S_IOPAD(0x228, PIN_INPUT, 0) /* (J23) MMC1_DAT2 */ 712 J722S_IOPAD(0x224, PIN_INPUT, 0) /* (H25) MMC1_DAT3 */ 713 J722S_IOPAD(0x240, PIN_INPUT, 0) /* (B24) MMC1_SDCD */ 714 J722S_IOPAD(0x244, PIN_INPUT, 0) /* (A24) MMC1_SDWP */ 715 >; 716 bootph-all; 717 }; 718 719 usb0_connector_pins_default: usb0-connector-default-pins { 720 pinctrl-single,pins = < 721 J722S_IOPAD(0x08c, PIN_INPUT_PULLUP, 7) /* (N23) GPMC0_WEn.GPIO0_34 */ 722 >; 723 }; 724 725 usb1_pins_default: usb1-default-pins { 726 pinctrl-single,pins = < 727 J722S_IOPAD(0x258, PIN_OUTPUT, 0) /* (B27) USB1_DRVVBUS */ 728 >; 729 }; 730 731 vcc_3p3_sd_s0_pins_default: vcc-3p3-sd-s0-default-pins { 732 pinctrl-single,pins = < 733 J722S_IOPAD(0x01c, PIN_OUTPUT, 7) /* (L21) OSPI0_D4.GPIO0_7 */ 734 >; 735 bootph-all; 736 }; 737 738 vcc_3p3_sd_vio_s0_pins_default: vcc-3p3-sd-vio-s0-default-pins { 739 pinctrl-single,pins = < 740 J722S_IOPAD(0x020, PIN_OUTPUT, 7) /* (M26) OSPI0_D5.GPIO0_8 */ 741 >; 742 bootph-all; 743 }; 744 745 vcc_3p3_cam_s0_pins_default: vcc-3p3-cam-s0-default-pins { 746 pinctrl-single,pins = < 747 J722S_IOPAD(0x1f0, PIN_OUTPUT, 7) /* (A23) EXT_REFCLK1.GPIO1_30 */ 748 >; 749 }; 750 751 vcc_lcd0_panel_pins_default: vcc-lcd0-panel-default-pins { 752 pinctrl-single,pins = < 753 J722S_IOPAD(0x078, PIN_OUTPUT, 7) /* (V23) GPMC0_AD15.GPIO0_30 */ 754 >; 755 }; 756 757 vcc_lcd1_panel_pins_default: vcc-lcd1-panel-default-pins { 758 pinctrl-single,pins = < 759 J722S_IOPAD(0x1c4, PIN_OUTPUT, 7) /* (E20) SPI0_D1.GPIO1_19 */ 760 >; 761 }; 762 763 vcc_usb0_vbus_pins_default: vcc-usb0-vbus-default-pins { 764 pinctrl-single,pins = < 765 J722S_IOPAD(0x254, PIN_OUTPUT, 7) /* (E25) USB0_DRVVBUS.GPIO1_50 */ 766 >; 767 }; 768}; 769 770/* SER1 */ 771&main_uart0 { 772 pinctrl-names = "default"; 773 pinctrl-0 = <&main_uart0_pins_default>; 774 bootph-all; 775 status = "okay"; 776}; 777 778/* SER2 */ 779&main_uart5 { 780 pinctrl-names = "default"; 781 pinctrl-0 = <&main_uart5_pins_default>; 782 bootph-all; 783 status = "okay"; 784}; 785 786/* I2S0 */ 787&mcasp0 { 788 #sound-dai-cells = <0>; 789 pinctrl-names = "default"; 790 pinctrl-0 = <&mcasp0_pins_default>; 791 op-mode = <0>; /* I2S */ 792 tdm-slots = <2>; 793 serial-dir = <2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; 794}; 795 796/* I2S2 */ 797&mcasp2 { 798 #sound-dai-cells = <0>; 799 pinctrl-names = "default"; 800 pinctrl-0 = <&mcasp2_pins_default>; 801 op-mode = <0>; /* I2S */ 802 tdm-slots = <2>; 803 serial-dir = <2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; 804}; 805 806/* CAN0 */ 807&mcu_mcan0 { 808 pinctrl-names = "default"; 809 pinctrl-0 = <&mcu_mcan0_pins_default>; 810 status = "okay"; 811}; 812 813/* CAN1 */ 814&mcu_mcan1 { 815 pinctrl-names = "default"; 816 pinctrl-0 = <&mcu_mcan1_pins_default>; 817 status = "okay"; 818}; 819 820&mcu_gpio0 { 821 gpio-line-names = 822 "", "", "", "", "", "", "", "", "", "", "", /* 10 */ "GPIO12", 823 "MCU_INT#", "", "", "", "", "", "", "", "", "", "", "GPIO13"; 824}; 825 826/* I2C_GP */ 827&mcu_i2c0 { 828 pinctrl-names = "default"; 829 pinctrl-0 = <&mcu_i2c0_pins_default>; 830 clock-frequency = <100000>; 831 status = "okay"; 832 833 /* SMARC Module EEPROM */ 834 eeprom@50 { 835 compatible = "atmel,24c32"; 836 reg = <0x50>; 837 pagesize = <32>; 838 vcc-supply = <&vcc_1p8_s0>; 839 }; 840}; 841 842&mcu_pmx0 { 843 mcu_i2c0_pins_default: mcu-i2c0-default-pins { 844 pinctrl-single,pins = < 845 J722S_MCU_IOPAD(0x044, PIN_INPUT, 0) /* (B13) MCU_I2C0_SCL */ 846 J722S_MCU_IOPAD(0x048, PIN_INPUT, 0) /* (E11) MCU_I2C0_SDA */ 847 >; 848 }; 849 mcu_mcan0_pins_default: mcu-mcan0-default-pins { 850 pinctrl-single,pins = < 851 J722S_MCU_IOPAD(0x038, PIN_INPUT, 0) /* (D8) MCU_MCAN0_RX */ 852 J722S_MCU_IOPAD(0x034, PIN_OUTPUT, 0) /* (B2) MCU_MCAN0_TX */ 853 >; 854 }; 855 856 mcu_mcan1_pins_default: mcu-mcan1-default-pins { 857 pinctrl-single,pins = < 858 J722S_MCU_IOPAD(0x040, PIN_INPUT, 0) /* (B1) MCU_MCAN1_RX */ 859 J722S_MCU_IOPAD(0x03c, PIN_OUTPUT, 0) /* (C1) MCU_MCAN1_TX */ 860 >; 861 }; 862 863 mcu_uart0_pins_default: mcu-uart0-default-pins { 864 pinctrl-single,pins = < 865 J722S_MCU_IOPAD(0x014, PIN_INPUT, 0) /* (B8) MCU_UART0_RXD */ 866 J722S_MCU_IOPAD(0x018, PIN_OUTPUT, 0) /* (B4) MCU_UART0_TXD */ 867 J722S_MCU_IOPAD(0x01c, PIN_INPUT, 0) /* (B5) MCU_UART0_CTSn */ 868 J722S_MCU_IOPAD(0x020, PIN_OUTPUT, 0) /* (C5) MCU_UART0_RTSn */ 869 >; 870 bootph-all; 871 }; 872 873 mcu_spi0_pins_default: mcu-spi0-default-pins { 874 pinctrl-single,pins = < 875 J722S_MCU_IOPAD(0x008, PIN_OUTPUT, 0) /* (A9) MCU_SPI0_CLK */ 876 J722S_MCU_IOPAD(0x000, PIN_OUTPUT, 0) /* (C12) MCU_SPI0_CS0 */ 877 J722S_MCU_IOPAD(0x004, PIN_OUTPUT, 0) /* (A10) MCU_SPI0_CS1 */ 878 J722S_MCU_IOPAD(0x00c, PIN_INPUT, 0) /* (B12) MCU_SPI0_D0 */ 879 J722S_MCU_IOPAD(0x010, PIN_OUTPUT, 0) /* (C11) MCU_SPI0_D1 */ 880 >; 881 }; 882 883 wkup_uart0_pins_default: wkup-uart0-default-pins { 884 pinctrl-single,pins = < 885 J722S_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B3) WKUP_UART0_RXD */ 886 J722S_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_TXD */ 887 >; 888 bootph-all; 889 }; 890 891 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 892 pinctrl-single,pins = < 893 J722S_MCU_IOPAD(0x04c, PIN_INPUT, 0) /* (B9) WKUP_I2C0_SCL */ 894 J722S_MCU_IOPAD(0x050, PIN_INPUT, 0) /* (D11) WKUP_I2C0_SDA */ 895 >; 896 }; 897}; 898 899/* SPI0 */ 900&mcu_spi0 { 901 pinctrl-names = "default"; 902 pinctrl-0 = <&mcu_spi0_pins_default>; 903}; 904 905/* SER0 */ 906&mcu_uart0 { 907 pinctrl-names = "default"; 908 pinctrl-0 = <&mcu_uart0_pins_default>; 909 bootph-all; 910 status = "okay"; 911}; 912 913/* QSPI0 */ 914&ospi0 { 915 pinctrl-0 = <&ospi0_pins_default>; 916 pinctrl-names = "default"; 917 status = "okay"; 918 919 flash@0 { 920 compatible = "jedec,spi-nor"; 921 reg = <0>; 922 spi-max-frequency = <104000000>; 923 spi-rx-bus-width = <2>; 924 spi-tx-bus-width = <2>; 925 m25p,fast-read; 926 cdns,tshsl-ns = <60>; 927 cdns,tsd2d-ns = <60>; 928 cdns,tchsh-ns = <60>; 929 cdns,tslch-ns = <60>; 930 cdns,read-delay = <3>; 931 vcc-supply = <&vcc_1p8_s0>; 932 bootph-all; 933 934 partitions { 935 compatible = "fixed-partitions"; 936 #address-cells = <1>; 937 #size-cells = <1>; 938 939 partition@0 { 940 reg = <0x000000 0x400000>; 941 label = "failsafe bootloader"; 942 read-only; 943 }; 944 }; 945 946 otp-1 { 947 compatible = "user-otp"; 948 949 nvmem-layout { 950 compatible = "kontron,sa67-vpd", "kontron,sl28-vpd"; 951 952 serial_number: serial-number { 953 }; 954 955 base_mac_address: base-mac-address { 956 #nvmem-cell-cells = <1>; 957 }; 958 }; 959 }; 960 }; 961}; 962 963&pcie0_rc { 964 pinctrl-names = "default"; 965 pinctrl-0 = <&pcie0_rc_pins_default>; 966 967 /* 968 * This is low active, but the driver itself is broken and already 969 * inverts the logic. 970 */ 971 reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>; 972 phys = <&serdes1_pcie>; 973 phy-names = "pcie-phy"; 974 status = "okay"; 975}; 976 977&sdhci0 { 978 disable-wp; 979 bootph-all; 980 ti,driver-strength-ohm = <50>; 981 status = "okay"; 982}; 983 984/* SDIO */ 985&sdhci1 { 986 pinctrl-names = "default"; 987 pinctrl-0 = <&sdhci1_pins_default>; 988 vmmc-supply = <&vcc_3p3_sd_s0>; 989 vqmmc-supply = <&vcc_3p3_sd_vio_s0>; 990 bootph-all; 991 cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>; 992 cd-debounce-delay-ms = <100>; 993 ti,fails-without-test-cd; 994 ti,driver-strength-ohm = <50>; 995 status = "okay"; 996}; 997 998&serdes_ln_ctrl { 999 idle-states = <J722S_SERDES0_LANE0_USB>, 1000 <J722S_SERDES1_LANE0_PCIE0_LANE0>; 1001}; 1002 1003&serdes_wiz0 { 1004 status = "okay"; 1005}; 1006 1007&serdes_wiz1 { 1008 status = "okay"; 1009}; 1010 1011&serdes0 { 1012 serdes0_usb3: phy@0 { 1013 reg = <0>; 1014 #phy-cells = <0>; 1015 resets = <&serdes_wiz0 1>; 1016 cdns,num-lanes = <1>; 1017 cdns,phy-type = <PHY_TYPE_USB3>; 1018 }; 1019}; 1020 1021&serdes1 { 1022 serdes1_pcie: phy@0 { 1023 reg = <0>; 1024 #phy-cells = <0>; 1025 resets = <&serdes_wiz1 1>; 1026 cdns,num-lanes = <1>; 1027 cdns,phy-type = <PHY_TYPE_PCIE>; 1028 }; 1029}; 1030 1031&usb0 { 1032 /* dual role is implemented but not a full featured OTG */ 1033 adp-disable; 1034 hnp-disable; 1035 srp-disable; 1036 dr_mode = "otg"; 1037 usb-role-switch; 1038 role-switch-default-mode = "peripheral"; 1039 status = "okay"; 1040 1041 port { 1042 usb0_hc: endpoint { 1043 remote-endpoint = <&usb0_connector>; 1044 }; 1045 }; 1046}; 1047 1048&usb0_phy_ctrl { 1049 /* 1050 * Keep this node in the SPL to be able to use the USB controller to 1051 * boot via DFU. 1052 */ 1053 bootph-all; 1054}; 1055 1056&usb1 { 1057 pinctrl-names = "default"; 1058 pinctrl-0 = <&usb1_pins_default>; 1059 1060 dr_mode = "host"; 1061 maximum-speed = "super-speed"; 1062 phys = <&serdes0_usb3>; 1063 phy-names = "cdns3,usb3-phy"; 1064}; 1065 1066&usbss0 { 1067 ti,vbus-divider; 1068 status = "okay"; 1069}; 1070 1071&usbss1 { 1072 ti,vbus-divider; 1073 status = "okay"; 1074}; 1075 1076/* I2C_PM */ 1077&wkup_i2c0 { 1078 pinctrl-names = "default"; 1079 pinctrl-0 = <&wkup_i2c0_pins_default>; 1080 clock-frequency = <100000>; 1081 status = "okay"; 1082}; 1083 1084/* SER3 */ 1085&wkup_uart0 { 1086 /* WKUP UART0 is used by Device Manager firmware */ 1087 pinctrl-names = "default"; 1088 pinctrl-0 = <&wkup_uart0_pins_default>; 1089 bootph-all; 1090 status = "reserved"; 1091}; 1092