1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) Siemens AG, 2018-2023 4 * 5 * Authors: 6 * Chao Zeng <chao.zeng@siemens.com> 7 * Jan Kiszka <jan.kiszka@siemens.com> 8 * 9 * AM6548-based (quad-core) IOT2050 M.2 variant (based on Advanced Product 10 * Generation 2), 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30 11 * 12 * Product homepage: 13 * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html 14 */ 15 16#include "k3-am6548-iot2050-advanced-common.dtsi" 17#include "k3-am65-iot2050-common-pg2.dtsi" 18#include "k3-am65-iot2050-arduino-connector.dtsi" 19#include "k3-am65-iot2050-dp.dtsi" 20 21/ { 22 compatible = "siemens,iot2050-advanced-m2", "ti,am654"; 23 model = "SIMATIC IOT2050 Advanced M2"; 24}; 25 26&main_pmx0 { 27 main_bkey_pcie_reset: main-bkey-pcie-reset-default-pins { 28 pinctrl-single,pins = < 29 AM65X_IOPAD(0x01bc, PIN_OUTPUT_PULLUP, 7) /* (AG13) GPIO1_15 */ 30 >; 31 }; 32 33 main_pmx0_m2_config_pins_default: main-pmx0-m2-config-default-pins { 34 pinctrl-single,pins = < 35 AM65X_IOPAD(0x01c8, PIN_INPUT_PULLUP, 7) /* (AE13) GPIO1_18 */ 36 AM65X_IOPAD(0x01cc, PIN_INPUT_PULLUP, 7) /* (AD13) GPIO1_19 */ 37 >; 38 }; 39 40 main_m2_pcie_mux_control: main-m2-pcie-mux-control-default-pins { 41 pinctrl-single,pins = < 42 AM65X_IOPAD(0x0148, PIN_INPUT_PULLUP, 7) /* (AG22) GPIO0_82 */ 43 AM65X_IOPAD(0x0160, PIN_INPUT_PULLUP, 7) /* (AE20) GPIO0_88 */ 44 AM65X_IOPAD(0x0164, PIN_INPUT_PULLUP, 7) /* (AF19) GPIO0_89 */ 45 >; 46 }; 47}; 48 49&main_pmx1 { 50 main_pmx1_m2_config_pins_default: main-pmx1-m2-config-default-pins { 51 pinctrl-single,pins = < 52 AM65X_IOPAD(0x0018, PIN_INPUT_PULLUP, 7) /* (B22) GPIO1_88 */ 53 AM65X_IOPAD(0x001c, PIN_INPUT_PULLUP, 7) /* (C23) GPIO1_89 */ 54 >; 55 }; 56}; 57 58&main_gpio0 { 59 pinctrl-names = "default"; 60 pinctrl-0 = <&main_m2_pcie_mux_control>; 61}; 62 63&main_gpio1 { 64 pinctrl-names = "default"; 65 pinctrl-0 = 66 <&main_pcie_enable_pins_default>, 67 <&main_pmx0_m2_config_pins_default>, 68 <&main_pmx1_m2_config_pins_default>, 69 <&cp2102n_reset_pin_default>; 70}; 71 72/* 73 * Base configuration for B-key slot with PCIe x2, E-key with USB 2.0 only. 74 * Firmware switches to other modes via device tree overlays. 75 */ 76 77&serdes0 { 78 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; 79 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; 80}; 81 82&pcie0_rc { 83 pinctrl-names = "default"; 84 pinctrl-0 = <&main_bkey_pcie_reset>; 85 86 num-lanes = <2>; 87 phys = <&serdes0 PHY_TYPE_PCIE 1>, <&serdes1 PHY_TYPE_PCIE 1>; 88 phy-names = "pcie-phy0","pcie-phy1"; 89 reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>; 90 status = "okay"; 91}; 92 93&pcie1_rc { 94 status = "disabled"; 95}; 96