1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Common dtsi for Variscite VAR-SOM-AM62P 4 * 5 * Link: https://www.variscite.com/product/system-on-module-som/cortex-a53-krait/var-som-am62p-ti-sitara-am62px/ 6 * 7 * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/ 8 * 9 */ 10 11/dts-v1/; 12 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/input/input.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/leds/common.h> 17#include <dt-bindings/pwm/pwm.h> 18#include "k3-am62p5.dtsi" 19 20/ { 21 compatible = "variscite,var-som-am62p", "ti,am62p5"; 22 23 wifi_pwrseq: wifi-pwrseq { 24 compatible = "mmc-pwrseq-simple"; 25 post-power-on-delay-ms = <100>; 26 power-off-delay-us = <10000>; 27 reset-gpios = <&main_gpio0 54 GPIO_ACTIVE_LOW>, /* WIFI_PWR_EN */ 28 <&main_gpio0 59 GPIO_ACTIVE_LOW>; /* WIFI_EN */ 29 }; 30 31 mmc_pwrseq: mmc-pwrseq { 32 compatible = "mmc-pwrseq-emmc"; 33 pinctrl-names = "default"; 34 pinctrl-0 = <&pinctrl_mmc_pwrseq>; 35 reset-gpios = <&main_gpio0 49 GPIO_ACTIVE_LOW>; 36 }; 37 38 memory@80000000 { 39 /* 8G RAM */ 40 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 41 <0x00000008 0x80000000 0x00000001 0x80000000>; 42 device_type = "memory"; 43 bootph-pre-ram; 44 }; 45 46 opp-table { 47 /* Add 1.4GHz OPP for am62p5-sk board. Requires VDD_CORE at 0v85 */ 48 opp-1400000000 { 49 opp-hz = /bits/ 64 <1400000000>; 50 opp-supported-hw = <0x01 0x0004>; 51 clock-latency-ns = <6000000>; 52 }; 53 }; 54 55 reserved_memory: reserved-memory { 56 #address-cells = <2>; 57 #size-cells = <2>; 58 ranges; 59 60 rtos_ipc_memory_region: rtos-ipc-memory@9b500000 { 61 compatible = "shared-dma-pool"; 62 reg = <0x00 0x9b500000 0x00 0x00300000>; 63 no-map; 64 }; 65 66 mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000 { 67 compatible = "shared-dma-pool"; 68 reg = <0x00 0x9b800000 0x00 0x00100000>; 69 no-map; 70 }; 71 72 mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 { 73 compatible = "shared-dma-pool"; 74 reg = <0x00 0x9b900000 0x00 0x00f00000>; 75 no-map; 76 }; 77 78 wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { 79 compatible = "shared-dma-pool"; 80 reg = <0x00 0x9c800000 0x00 0x00100000>; 81 no-map; 82 }; 83 84 wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 { 85 compatible = "shared-dma-pool"; 86 reg = <0x00 0x9c900000 0x00 0x01e00000>; 87 no-map; 88 }; 89 90 secure_tfa_ddr: tfa@9e780000 { 91 reg = <0x00 0x9e780000 0x00 0x80000>; 92 no-map; 93 }; 94 95 secure_ddr: optee@9e800000 { 96 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 97 no-map; 98 }; 99 }; 100 101 reg_3v3: regulator-3v3 { 102 compatible = "regulator-fixed"; 103 regulator-name = "On-module +V3.3"; 104 regulator-min-microvolt = <3300000>; 105 regulator-max-microvolt = <3300000>; 106 regulator-always-on; 107 regulator-boot-on; 108 }; 109 110 reg_1v8: regulator-1v8 { 111 compatible = "regulator-fixed"; 112 regulator-name = "On-module +V1.8"; 113 regulator-min-microvolt = <1800000>; 114 regulator-max-microvolt = <1800000>; 115 vin-supply = <®_3v3>; 116 regulator-always-on; 117 regulator-boot-on; 118 }; 119 120 reg_3v3_phy: regulator-3v3-phy { 121 compatible = "regulator-fixed"; 122 regulator-name = "On-module +V3.3_PHY"; 123 gpios = <&main_gpio0 45 GPIO_ACTIVE_HIGH>; 124 enable-active-high; 125 regulator-always-on; 126 }; 127}; 128 129&cpsw3g { 130 pinctrl-names = "default"; 131 pinctrl-0 = <&pinctrl_rgmii1>; 132}; 133 134&cpsw3g_mdio { 135 pinctrl-names = "default"; 136 pinctrl-0 = <&pinctrl_mdio1>; 137 status = "okay"; 138 139 cpsw3g_phy0: ethernet-phy@4 { 140 compatible = "ethernet-phy-id0283.bc30"; 141 reg = <4>; 142 reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>; 143 reset-assert-us = <10000>; 144 reset-deassert-us = <100000>; 145 }; 146}; 147 148&cpsw_port1 { 149 /* 150 * The required RGMII TX and RX 2ns delays are implemented directly 151 * in hardware via passive delay elements on the SOM PCB. 152 * No delay configuration is needed in software via PHY driver. 153 */ 154 phy-mode = "rgmii"; 155 phy-handle = <&cpsw3g_phy0>; 156 status = "okay"; 157}; 158 159&main_i2c2 { 160 pinctrl-names = "default"; 161 pinctrl-0 = <&pinctrl_i2c2>; 162 clock-frequency = <400000>; 163 status = "okay"; 164}; 165 166&main_i2c3 { 167 pinctrl-names = "default"; 168 pinctrl-0 = <&pinctrl_i2c3>; 169 clock-frequency = <400000>; 170 status = "okay"; 171}; 172 173&main_pmx0 { 174 pinctrl_mmc_pwrseq: main-emmc-pwrseq-pins { 175 pinctrl-single,pins = < 176 AM62PX_IOPAD(0x00c8, PIN_OUTPUT, 7) /* (AB23) VOUT0_DATA4.GPIO0_49 */ 177 >; 178 }; 179 180 pinctrl_i2c2: main-i2c2-default-pins { 181 pinctrl-single,pins = < 182 AM62PX_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (T22) GPMC0_CSn2.I2C2_SCL */ 183 AM62PX_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (U25) GPMC0_CSn3.I2C2_SDA */ 184 >; 185 }; 186 187 pinctrl_i2c3: main-i2c3-default-pins { 188 pinctrl-single,pins = < 189 AM62PX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A23) UART0_CTSn.I2C3_SCL */ 190 AM62PX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (C22) UART0_RTSn.I2C3_SDA */ 191 >; 192 }; 193 194 pinctrl_mdio1: main-mdio1-default-pins { 195 pinctrl-single,pins = < 196 AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */ 197 AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */ 198 >; 199 }; 200 201 pinctrl_mmc2: main-mmc2-default-pins { 202 pinctrl-single,pins = < 203 AM62PX_IOPAD(0x0120, PIN_INPUT_PULLUP, 0) /* (K24) MMC2_CMD */ 204 AM62PX_IOPAD(0x0118, PIN_INPUT_PULLDOWN, 0) /* (K21) MMC2_CLK */ 205 AM62PX_IOPAD(0x011c, PIN_INPUT_PULLUP, 0) /* () MMC2_CLKLB */ 206 AM62PX_IOPAD(0x0114, PIN_INPUT_PULLUP, 0) /* (K23) MMC2_DAT0 */ 207 AM62PX_IOPAD(0x0110, PIN_INPUT_PULLUP, 0) /* (K22) MMC2_DAT1 */ 208 AM62PX_IOPAD(0x010c, PIN_INPUT_PULLUP, 0) /* (L20) MMC2_DAT2 */ 209 AM62PX_IOPAD(0x0108, PIN_INPUT_PULLUP, 0) /* (L21) MMC2_DAT3 */ 210 >; 211 }; 212 213 pinctrl_rgmii1: main-rgmii1-default-pins { 214 pinctrl-single,pins = < 215 AM62PX_IOPAD(0x014c, PIN_INPUT, 0) /* (B15) RGMII1_RD0 */ 216 AM62PX_IOPAD(0x0150, PIN_INPUT, 0) /* (B16) RGMII1_RD1 */ 217 AM62PX_IOPAD(0x0154, PIN_INPUT, 0) /* (A14) RGMII1_RD2 */ 218 AM62PX_IOPAD(0x0158, PIN_INPUT, 0) /* (B14) RGMII1_RD3 */ 219 AM62PX_IOPAD(0x0148, PIN_INPUT, 0) /* (A16) RGMII1_RXC */ 220 AM62PX_IOPAD(0x0144, PIN_INPUT, 0) /* (A15) RGMII1_RX_CTL */ 221 AM62PX_IOPAD(0x0134, PIN_INPUT, 0) /* (A18) RGMII1_TD0 */ 222 AM62PX_IOPAD(0x0138, PIN_INPUT, 0) /* (C17) RGMII1_TD1 */ 223 AM62PX_IOPAD(0x013c, PIN_INPUT, 0) /* (A17) RGMII1_TD2 */ 224 AM62PX_IOPAD(0x0140, PIN_INPUT, 0) /* (C16) RGMII1_TD3 */ 225 AM62PX_IOPAD(0x0130, PIN_INPUT, 0) /* (B17) RGMII1_TXC */ 226 AM62PX_IOPAD(0x012c, PIN_INPUT, 0) /* (B18) RGMII1_TX_CTL */ 227 >; 228 bootph-all; 229 }; 230 231 pinctrl_spi0: main-spi0-default-pins { 232 pinctrl-single,pins = < 233 AM62PX_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (B21) SPI0_CLK */ 234 AM62PX_IOPAD(0x01b4, PIN_OUTPUT, 0) /* (D20) SPI0_CS0 */ 235 AM62PX_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (B20) SPI0_D0 */ 236 AM62PX_IOPAD(0x01c4, PIN_INPUT, 0) /* (C21) SPI0_D1 */ 237 >; 238 }; 239 240 pinctrl_uart5: main-uart5-default-pins { 241 pinctrl-single,pins = < 242 AM62PX_IOPAD(0x00ec, PIN_INPUT, 4) /* (AC21) VOUT0_DATA13.UART5_CTSn */ 243 AM62PX_IOPAD(0x00e8, PIN_OUTPUT, 4) /* (AD21) VOUT0_DATA12.UART5_RTSn */ 244 AM62PX_IOPAD(0x00d0, PIN_INPUT, 4) /* (AC23) VOUT0_DATA6.UART5_RXD */ 245 AM62PX_IOPAD(0x00d4, PIN_OUTPUT, 4) /* (AE23) VOUT0_DATA7.UART5_TXD */ 246 >; 247 }; 248 249 pinctrl_bt: main-btgrp-pins { 250 pinctrl-single,pins = < 251 AM62PX_IOPAD(0x00f4, PIN_OUTPUT, 7) /* (Y20) VOUT0_DATA15.GPIO0_60 (BT_EN) */ 252 >; 253 }; 254 255 pinctrl_restouch: main-restouch-pins { 256 pinctrl-single,pins = < 257 AM62PX_IOPAD(0x00c4, PIN_INPUT_PULLUP, 7) /* (Y23) VOUT0_DATA3.GPIO0_48 */ 258 >; 259 }; 260 261 pinctrl_wifi: main-wifi-default-pins { 262 pinctrl-single,pins = < 263 AM62PX_IOPAD(0x00dc, PIN_OUTPUT, 7) /* (AC22) VOUT0_DATA9.GPIO0_54 - WIFI_PWR_EN - */ 264 AM62PX_IOPAD(0x00f0, PIN_OUTPUT, 7) /* (AA20) VOUT0_DATA14.GPIO0_59 - WIFI_EN - */ 265 >; 266 }; 267}; 268 269&mcu_pmx0 { 270 pinctrl_wkup_clkout0: wkup-clkout0-default-pins { 271 pinctrl-single,pins = < 272 AM62PX_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (F13) WKUP_CLKOUT0 */ 273 >; 274 }; 275}; 276 277&main_spi0 { 278 pinctrl-names = "default"; 279 pinctrl-0 = <&pinctrl_spi0>; 280 ti,pindir-d0-out-d1-in; 281 status = "okay"; 282}; 283 284&main_uart5 { 285 pinctrl-names = "default"; 286 pinctrl-0 = <&pinctrl_uart5>, <&pinctrl_bt>; 287 uart-has-rtscts; 288 status = "okay"; 289 290 bluetooth { 291 compatible = "nxp,88w8987-bt"; 292 }; 293}; 294 295&sdhci0 { 296 /* On-module eMMC */ 297 ti,driver-strength-ohm = <50>; 298 mmc-pwrseq = <&mmc_pwrseq>; 299 bootph-all; 300 status = "okay"; 301}; 302 303&sdhci2 { 304 /* On-module WiFi */ 305 pinctrl-names = "default"; 306 pinctrl-0 = <&pinctrl_mmc2>, <&pinctrl_wifi>; 307 bus-width = <4>; 308 non-removable; 309 keep-power-in-suspend; 310 mmc-pwrseq = <&wifi_pwrseq>; 311 ti,fails-without-test-cd; 312 status = "okay"; 313}; 314 315&usbss0 { 316 ti,vbus-divider; 317}; 318 319&usbss1 { 320 ti,vbus-divider; 321}; 322 323&mailbox0_cluster0 { 324 status = "okay"; 325 326 mbox_r5_0: mbox-r5-0 { 327 ti,mbox-rx = <0 0 0>; 328 ti,mbox-tx = <1 0 0>; 329 }; 330}; 331 332&mailbox0_cluster1 { 333 status = "okay"; 334 335 mbox_mcu_r5_0: mbox-mcu-r5-0 { 336 ti,mbox-rx = <0 0 0>; 337 ti,mbox-tx = <1 0 0>; 338 }; 339}; 340 341&mcu_r5fss0 { 342 status = "okay"; 343}; 344 345&mcu_r5fss0_core0 { 346 mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; 347 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 348 <&mcu_r5fss0_core0_memory_region>; 349}; 350 351&wkup_r5fss0 { 352 status = "okay"; 353}; 354 355&wkup_r5fss0_core0 { 356 mboxes = <&mailbox0_cluster0 &mbox_r5_0>; 357 memory-region = <&wkup_r5fss0_core0_dma_memory_region>, 358 <&wkup_r5fss0_core0_memory_region>; 359}; 360 361/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */ 362&mcu_gpio0 { 363 status = "reserved"; 364}; 365 366&mcu_gpio_intr { 367 status = "reserved"; 368}; 369 370&wkup_rtc0 { 371 status = "disabled"; 372}; 373 374&wkup_rti0 { 375 /* WKUP RTI0 is used by DM firmware */ 376 status = "reserved"; 377}; 378 379&wkup_uart0 { 380 /* WKUP UART0 is used by DM firmware */ 381 status = "reserved"; 382}; 383 384&main_uart1 { 385 /* Main UART1 is used by TIFS firmware */ 386 status = "reserved"; 387}; 388