1*6bd0449bSBeleswar Padhi// SPDX-License-Identifier: GPL-2.0-only OR MIT 2*6bd0449bSBeleswar Padhi/** 3*6bd0449bSBeleswar Padhi * Device Tree Source for enabling IPC using TI SDK firmware on AM62P SoCs 4*6bd0449bSBeleswar Padhi * 5*6bd0449bSBeleswar Padhi * Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti.com/ 6*6bd0449bSBeleswar Padhi */ 7*6bd0449bSBeleswar Padhi 8*6bd0449bSBeleswar Padhi&reserved_memory { 9*6bd0449bSBeleswar Padhi mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { 10*6bd0449bSBeleswar Padhi compatible = "shared-dma-pool"; 11*6bd0449bSBeleswar Padhi reg = <0x00 0x9b800000 0x00 0x100000>; 12*6bd0449bSBeleswar Padhi no-map; 13*6bd0449bSBeleswar Padhi }; 14*6bd0449bSBeleswar Padhi 15*6bd0449bSBeleswar Padhi mcu_r5fss0_core0_memory_region: memory@9b900000 { 16*6bd0449bSBeleswar Padhi compatible = "shared-dma-pool"; 17*6bd0449bSBeleswar Padhi reg = <0x00 0x9b900000 0x00 0xf00000>; 18*6bd0449bSBeleswar Padhi no-map; 19*6bd0449bSBeleswar Padhi }; 20*6bd0449bSBeleswar Padhi}; 21*6bd0449bSBeleswar Padhi 22*6bd0449bSBeleswar Padhi&mailbox0_cluster0 { 23*6bd0449bSBeleswar Padhi status = "okay"; 24*6bd0449bSBeleswar Padhi 25*6bd0449bSBeleswar Padhi mbox_r5_0: mbox-r5-0 { 26*6bd0449bSBeleswar Padhi ti,mbox-rx = <0 0 0>; 27*6bd0449bSBeleswar Padhi ti,mbox-tx = <1 0 0>; 28*6bd0449bSBeleswar Padhi }; 29*6bd0449bSBeleswar Padhi}; 30*6bd0449bSBeleswar Padhi 31*6bd0449bSBeleswar Padhi&mailbox0_cluster1 { 32*6bd0449bSBeleswar Padhi status = "okay"; 33*6bd0449bSBeleswar Padhi 34*6bd0449bSBeleswar Padhi mbox_mcu_r5_0: mbox-mcu-r5-0 { 35*6bd0449bSBeleswar Padhi ti,mbox-rx = <0 0 0>; 36*6bd0449bSBeleswar Padhi ti,mbox-tx = <1 0 0>; 37*6bd0449bSBeleswar Padhi }; 38*6bd0449bSBeleswar Padhi}; 39*6bd0449bSBeleswar Padhi 40*6bd0449bSBeleswar Padhi&wkup_r5fss0 { 41*6bd0449bSBeleswar Padhi status = "okay"; 42*6bd0449bSBeleswar Padhi}; 43*6bd0449bSBeleswar Padhi 44*6bd0449bSBeleswar Padhi&wkup_r5fss0_core0 { 45*6bd0449bSBeleswar Padhi mboxes = <&mailbox0_cluster0 &mbox_r5_0>; 46*6bd0449bSBeleswar Padhi memory-region = <&wkup_r5fss0_core0_dma_memory_region>, 47*6bd0449bSBeleswar Padhi <&wkup_r5fss0_core0_memory_region>; 48*6bd0449bSBeleswar Padhi status = "okay"; 49*6bd0449bSBeleswar Padhi}; 50*6bd0449bSBeleswar Padhi 51*6bd0449bSBeleswar Padhi&mcu_r5fss0 { 52*6bd0449bSBeleswar Padhi status = "okay"; 53*6bd0449bSBeleswar Padhi}; 54*6bd0449bSBeleswar Padhi 55*6bd0449bSBeleswar Padhi&mcu_r5fss0_core0 { 56*6bd0449bSBeleswar Padhi mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; 57*6bd0449bSBeleswar Padhi memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 58*6bd0449bSBeleswar Padhi <&mcu_r5fss0_core0_memory_region>; 59*6bd0449bSBeleswar Padhi status = "okay"; 60*6bd0449bSBeleswar Padhi}; 61