1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/** 3 * Device Tree Source for enabling IPC using TI SDK firmware on AM62P SoCs 4 * 5 * Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&reserved_memory { 9 mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { 10 compatible = "shared-dma-pool"; 11 reg = <0x00 0x9b800000 0x00 0x100000>; 12 no-map; 13 }; 14 15 mcu_r5fss0_core0_memory_region: memory@9b900000 { 16 compatible = "shared-dma-pool"; 17 reg = <0x00 0x9b900000 0x00 0xf00000>; 18 no-map; 19 }; 20}; 21 22&mailbox0_cluster0 { 23 status = "okay"; 24 25 mbox_r5_0: mbox-r5-0 { 26 ti,mbox-rx = <0 0 0>; 27 ti,mbox-tx = <1 0 0>; 28 }; 29}; 30 31&mailbox0_cluster1 { 32 status = "okay"; 33 34 mbox_mcu_r5_0: mbox-mcu-r5-0 { 35 ti,mbox-rx = <0 0 0>; 36 ti,mbox-tx = <1 0 0>; 37 }; 38}; 39 40&wkup_r5fss0 { 41 status = "okay"; 42}; 43 44&wkup_r5fss0_core0 { 45 mboxes = <&mailbox0_cluster0 &mbox_r5_0>; 46 memory-region = <&wkup_r5fss0_core0_dma_memory_region>, 47 <&wkup_r5fss0_core0_memory_region>; 48 status = "okay"; 49}; 50 51&mcu_r5fss0 { 52 status = "okay"; 53}; 54 55&mcu_r5fss0_core0 { 56 mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; 57 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 58 <&mcu_r5fss0_core0_memory_region>; 59 status = "okay"; 60}; 61