1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Common dtsi for Variscite VAR-SOM-AM62 4 * 5 * Link: https://variscite.com/system-on-module-som/ti-sitara-am62x/var-som-am62/ 6 * 7 * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ 8 * Copyright (C) 2026 Stefano Radaelli <stefano.r@variscite.com> 9 * 10 */ 11 12/dts-v1/; 13 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/input/input.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/leds/common.h> 18#include <dt-bindings/pwm/pwm.h> 19#include "k3-am625.dtsi" 20 21/ { 22 compatible = "variscite,var-som-am62", "ti,am625"; 23 24 memory@80000000 { 25 /* 2G RAM */ 26 reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 27 device_type = "memory"; 28 bootph-pre-ram; 29 }; 30 31 mmc_pwrseq: mmc-pwrseq { 32 compatible = "mmc-pwrseq-emmc"; 33 pinctrl-names = "default"; 34 pinctrl-0 = <&pinctrl_mmc_pwrseq>; 35 reset-gpios = <&main_gpio0 49 GPIO_ACTIVE_LOW>; 36 }; 37 38 opp-table { 39 /* Add 1.4GHz OPP. Requires VDD_CORE to be at 0.85V */ 40 opp-1400000000 { 41 opp-hz = /bits/ 64 <1400000000>; 42 opp-supported-hw = <0x01 0x0004>; 43 clock-latency-ns = <6000000>; 44 }; 45 }; 46 47 reserved_memory: reserved-memory { 48 #address-cells = <2>; 49 #size-cells = <2>; 50 ranges; 51 52 ramoops@9ca00000 { 53 compatible = "ramoops"; 54 reg = <0x00 0x9ca00000 0x00 0x00100000>; 55 record-size = <0x8000>; 56 console-size = <0x8000>; 57 ftrace-size = <0x00>; 58 pmsg-size = <0x8000>; 59 }; 60 61 /* global cma region */ 62 linux,cma { 63 compatible = "shared-dma-pool"; 64 reusable; 65 size = <0x00 0x8000000>; 66 linux,cma-default; 67 }; 68 69 rtos_ipc_memory_region: rtos-ipc-memory@9b500000 { 70 compatible = "shared-dma-pool"; 71 reg = <0x00 0x9b500000 0x00 0x00300000>; 72 no-map; 73 }; 74 75 wkup_r5fss0_core0_dma_memory_region: memory@9da00000 { 76 compatible = "shared-dma-pool"; 77 reg = <0x00 0x9da00000 0x00 0x100000>; 78 no-map; 79 }; 80 81 wkup_r5fss0_core0_memory_region: memory@9db00000 { 82 compatible = "shared-dma-pool"; 83 reg = <0x00 0x9db00000 0x00 0xc00000>; 84 no-map; 85 }; 86 87 secure_tfa_ddr: tfa@9e780000 { 88 reg = <0x00 0x9e780000 0x00 0x80000>; 89 alignment = <0x1000>; 90 no-map; 91 }; 92 93 secure_ddr: optee@9e800000 { 94 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 95 alignment = <0x1000>; 96 no-map; 97 }; 98 }; 99 100 reg_1v8: regulator-1v8 { 101 compatible = "regulator-fixed"; 102 regulator-name = "On-module +V1.8"; 103 regulator-min-microvolt = <1800000>; 104 regulator-max-microvolt = <1800000>; 105 vin-supply = <®_3v3>; 106 regulator-always-on; 107 regulator-boot-on; 108 }; 109 110 reg_3v3: regulator-3v3 { 111 compatible = "regulator-fixed"; 112 regulator-name = "On-module +V3.3"; 113 regulator-min-microvolt = <3300000>; 114 regulator-max-microvolt = <3300000>; 115 regulator-always-on; 116 regulator-boot-on; 117 }; 118 119 reg_3v3_phy: regulator-3v3-phy { 120 compatible = "regulator-fixed"; 121 regulator-name = "On-module +V3.3_PHY"; 122 pinctrl-names = "default"; 123 pinctrl-0 = <&pinctrl_eth_phy>; 124 gpios = <&main_gpio0 45 GPIO_ACTIVE_HIGH>; 125 enable-active-high; 126 regulator-always-on; 127 }; 128 129 sound { 130 compatible = "simple-audio-card"; 131 simple-audio-card,bitclock-master = <&codec_dai>; 132 simple-audio-card,format = "dsp_b"; 133 simple-audio-card,frame-master = <&codec_dai>; 134 simple-audio-card,name = "wm8904-audio"; 135 simple-audio-card,mclk-fs = <256>; 136 simple-audio-card,routing = 137 "Headphone Jack", "HPOUTL", 138 "Headphone Jack", "HPOUTR", 139 "IN2L", "Line In Jack", 140 "IN2R", "Line In Jack", 141 "IN1L", "Microphone Jack", 142 "IN1R", "Microphone Jack"; 143 simple-audio-card,widgets = 144 "Microphone", "Microphone Jack", 145 "Headphone", "Headphone Jack", 146 "Line", "Line In Jack"; 147 148 codec_dai: simple-audio-card,codec { 149 sound-dai = <&wm8904>; 150 }; 151 152 simple-audio-card,cpu { 153 sound-dai = <&mcasp1>; 154 }; 155 }; 156}; 157 158&audio_refclk1 { 159 assigned-clock-rates = <12000000>; 160}; 161 162&cpsw3g { 163 pinctrl-names = "default"; 164 pinctrl-0 = <&pinctrl_rgmii1>; 165 status = "okay"; 166}; 167 168&cpsw3g_mdio { 169 pinctrl-names = "default"; 170 pinctrl-0 = <&pinctrl_mdio1>; 171 status = "okay"; 172 173 cpsw3g_phy0: ethernet-phy@4 { 174 compatible = "ethernet-phy-id0283.bc30"; 175 reg = <4>; 176 bootph-all; 177 reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>; 178 reset-assert-us = <10000>; 179 reset-deassert-us = <20000>; 180 }; 181}; 182 183&cpsw_port1 { 184 /* 185 * The required RGMII TX and RX 2ns delays are implemented directly 186 * in hardware via passive delay elements on the SOM PCB. 187 * No delay configuration is needed in software via PHY driver. 188 */ 189 phy-mode = "rgmii"; 190 phy-handle = <&cpsw3g_phy0>; 191 status = "okay"; 192}; 193 194&main_i2c2 { 195 pinctrl-names = "default"; 196 pinctrl-0 = <&pinctrl_i2c2>; 197 clock-frequency = <400000>; 198 status = "okay"; 199 200 wm8904: audio-codec@1a { 201 compatible = "wlf,wm8904"; 202 reg = <0x1a>; 203 #sound-dai-cells = <0>; 204 clocks = <&audio_refclk1>; 205 clock-names = "mclk"; 206 AVDD-supply = <®_1v8>; 207 CPVDD-supply = <®_1v8>; 208 DBVDD-supply = <®_3v3>; 209 DCVDD-supply = <®_1v8>; 210 MICVDD-supply = <®_1v8>; 211 wlf,drc-cfg-names = "default", "peaklimiter", "tradition", 212 "soft", "music"; 213 /* 214 * Config registers per name, respectively: 215 * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 216 * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 217 * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 218 * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 219 * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 220 */ 221 wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, 222 /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, 223 /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, 224 /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, 225 /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; 226 /* GPIO1 = DMIC_CLK, don't touch others */ 227 wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; 228 }; 229}; 230 231&main_i2c3 { 232 pinctrl-names = "default"; 233 pinctrl-0 = <&pinctrl_i2c3>; 234 clock-frequency = <400000>; 235 status = "okay"; 236}; 237 238&main_pmx0 { 239 pinctrl_i2c2: main-i2c2-default-pins { 240 pinctrl-single,pins = < 241 AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ 242 AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ 243 >; 244 }; 245 246 pinctrl_i2c3: main-i2c3-default-pins { 247 pinctrl-single,pins = < 248 AM62X_IOPAD(0x01d0, PIN_INPUT, 2) /* (A15) UART0_CTSn.I2C3_SCL */ 249 AM62X_IOPAD(0x01d4, PIN_INPUT, 2) /* (B15) UART0_RTSn.I2C3_SDA */ 250 >; 251 }; 252 253 pinctrl_mcasp1: main-mcasp1-default-pins { 254 pinctrl-single,pins = < 255 AM62X_IOPAD(0x0090, PIN_INPUT, 2) /* (M24) GPMC0_BE0N_CLE.MCASP1_ACLKX */ 256 AM62X_IOPAD(0x0098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */ 257 AM62X_IOPAD(0x008c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEN.MCASP1_AXR0 */ 258 AM62X_IOPAD(0x0084, PIN_INPUT, 2) /* (L23) GPMC0_ADVN_ALE.MCASP1_AXR2 */ 259 AM62X_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (K25) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ 260 >; 261 }; 262 263 pinctrl_mdio1: main-mdio1-default-pins { 264 pinctrl-single,pins = < 265 AM62X_IOPAD(0x160, PIN_INPUT, 0) /* (AD24) MDIO0_MDC */ 266 AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ 267 >; 268 }; 269 270 pinctrl_mmc_pwrseq: pinmux-mmc-pwrseq-pins { 271 pinctrl-single,pins = < 272 AM62X_IOPAD(0x00c8, PIN_OUTPUT, 7) /* (Y25) VOUT0_DATA4.GPIO0_49 */ 273 >; 274 }; 275 276 pinctrl_mmc0: main-mmc0-default-pins { 277 bootph-all; 278 pinctrl-single,pins = < 279 AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ 280 AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ 281 AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ 282 AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */ 283 AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */ 284 AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */ 285 AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */ 286 AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */ 287 AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */ 288 AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ 289 >; 290 }; 291 292 pinctrl_mmc2: main-mmc2-default-pins { 293 pinctrl-single,pins = < 294 AM62X_IOPAD(0x120, PIN_INPUT_PULLUP, 0) /* (C24) MMC2_CMD */ 295 AM62X_IOPAD(0x118, PIN_INPUT_PULLDOWN, 0) /* (D25) MMC2_CLK */ 296 AM62X_IOPAD(0x114, PIN_INPUT_PULLUP, 0) /* (B24) MMC2_DAT0 */ 297 AM62X_IOPAD(0x110, PIN_INPUT_PULLUP, 0) /* (C25) MMC2_DAT1 */ 298 AM62X_IOPAD(0x10c, PIN_INPUT_PULLUP, 0) /* (E23) MMC2_DAT2 */ 299 AM62X_IOPAD(0x108, PIN_INPUT_PULLUP, 0) /* (D24) MMC2_DAT3 */ 300 AM62X_IOPAD(0x11c, PIN_INPUT_PULLUP, 0) /* (#N/A) MMC2_CLKB */ 301 >; 302 }; 303 304 pinctrl_restouch: main-restouch-pins { 305 pinctrl-single,pins = < 306 AM62X_IOPAD(0x00c4, PIN_INPUT_PULLUP, 7) /* (W24) VOUT0_DATA3.GPIO0_48 */ 307 >; 308 }; 309 310 pinctrl_rgmii1: main-rgmii1-default-pins { 311 bootph-all; 312 pinctrl-single,pins = < 313 AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ 314 AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ 315 AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ 316 AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ 317 AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ 318 AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ 319 AM62X_IOPAD(0x134, PIN_INPUT, 0) /* (AE20) RGMII1_TD0 */ 320 AM62X_IOPAD(0x138, PIN_INPUT, 0) /* (AD20) RGMII1_TD1 */ 321 AM62X_IOPAD(0x13c, PIN_INPUT, 0) /* (AE18) RGMII1_TD2 */ 322 AM62X_IOPAD(0x140, PIN_INPUT, 0) /* (AD18) RGMII1_TD3 */ 323 AM62X_IOPAD(0x130, PIN_INPUT, 0) /* (AE19) RGMII1_TXC */ 324 AM62X_IOPAD(0x12c, PIN_INPUT, 0) /* (AD19) RGMII1_TX_CTL */ 325 AM62X_IOPAD(0x00bc, PIN_INPUT, 7) /* (V24) VOUT0_DATA1.GPIO0_46 */ 326 >; 327 }; 328 329 pinctrl_eth_phy: main-eth-phy-default-pins { 330 pinctrl-single,pins = < 331 AM62X_IOPAD(0x00b8, PIN_INPUT, 7) /* (U22) VOUT0_DATA0.GPIO0_45 */ 332 >; 333 }; 334 335 pinctrl_spi0: main-spi0-default-pins { 336 pinctrl-single,pins = < 337 AM62X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (A14) SPI0_CLK */ 338 AM62X_IOPAD(0x01b4, PIN_OUTPUT, 0) /* (A13) SPI0_CS0 */ 339 AM62X_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (B13) SPI0_D0 */ 340 AM62X_IOPAD(0x01c4, PIN_INPUT, 0) /* (B14) SPI0_D1 */ 341 >; 342 }; 343 344 pinctrl_uart5: main-uart5-default-pins { 345 pinctrl-single,pins = < 346 AM62X_IOPAD(0x00ec, PIN_INPUT, 4) /* (AA24) VOUT0_DATA13.UART5_CTSn */ 347 AM62X_IOPAD(0x00e8, PIN_OUTPUT, 4) /* (AB25) VOUT0_DATA12.UART5_RTSn */ 348 AM62X_IOPAD(0x00d0, PIN_INPUT, 4) /* (Y23) VOUT0_DATA6.UART5_RXD */ 349 AM62X_IOPAD(0x00d4, PIN_OUTPUT, 4) /* (AA25) VOUT0_DATA7.UART5_TXD */ 350 >; 351 }; 352}; 353 354&mcu_pmx0 { 355 pinctrl_wkup_clkout0: wkup-clkout0-default-pins { 356 pinctrl-single,pins = < 357 AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (F13) WKUP_CLKOUT0 */ 358 >; 359 }; 360}; 361 362&main_spi0 { 363 pinctrl-names = "default"; 364 pinctrl-0 = <&pinctrl_spi0>; 365 ti,pindir-d0-out-d1-in; 366 status = "okay"; 367 368 /* Resistive touch controller */ 369 ads7846: touchscreen@0 { 370 compatible = "ti,ads7846"; 371 reg = <0>; 372 pinctrl-names = "default"; 373 pinctrl-0 = <&pinctrl_restouch>; 374 interrupt-parent = <&main_gpio0>; 375 interrupts = <48 IRQ_TYPE_EDGE_FALLING>; 376 spi-max-frequency = <1500000>; 377 pendown-gpio = <&main_gpio0 48 GPIO_ACTIVE_LOW>; 378 ti,x-min = /bits/ 16 <125>; 379 ti,x-max = /bits/ 16 <4008>; 380 ti,y-min = /bits/ 16 <282>; 381 ti,y-max = /bits/ 16 <3864>; 382 ti,x-plate-ohms = /bits/ 16 <180>; 383 ti,pressure-max = /bits/ 16 <255>; 384 ti,debounce-max = /bits/ 16 <10>; 385 ti,debounce-tol = /bits/ 16 <3>; 386 ti,debounce-rep = /bits/ 16 <1>; 387 ti,settle-delay-usec = /bits/ 16 <150>; 388 ti,keep-vref-on; 389 wakeup-source; 390 }; 391}; 392 393/* On-module Bluetooth */ 394&main_uart5 { 395 pinctrl-names = "default"; 396 pinctrl-0 = <&pinctrl_uart5>; 397 uart-has-rtscts; 398 status = "okay"; 399}; 400 401&mcasp1 { 402 pinctrl-names = "default"; 403 pinctrl-0 = <&pinctrl_mcasp1>; 404 op-mode = <0>; /* MCASP_IIS_MODE */ 405 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 406 1 0 2 0 407 0 0 0 0 408 0 0 0 0 409 0 0 0 0 410 >; 411 tdm-slots = <2>; 412 #sound-dai-cells = <0>; 413 status = "okay"; 414}; 415 416/* On-module eMMC */ 417&sdhci0 { 418 pinctrl-names = "default"; 419 pinctrl-0 = <&pinctrl_mmc0>; 420 bootph-all; 421 disable-wp; 422 mmc-pwrseq = <&mmc_pwrseq>; 423 non-removable; 424 status="okay"; 425}; 426 427/* On-module Wi-Fi */ 428&sdhci2 { 429 pinctrl-names = "default"; 430 pinctrl-0 = <&pinctrl_mmc2>, <&pinctrl_wkup_clkout0>; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 assigned-clocks = <&k3_clks 157 158>; /* wkup_clkout_sel_out0 */ 434 assigned-clock-parents = <&k3_clks 157 164>; /* clk_32k_rc_sel_out0 */ 435 bus-width = <4>; 436 disable-wp; 437 non-removable; 438 cap-power-off-card; 439 status = "okay"; 440 441 brcmf: wifi@1 { 442 compatible = "brcm,bcm4329-fmac"; 443 reg = <1>; 444 }; 445}; 446 447&usbss0 { 448 ti,vbus-divider; 449}; 450 451&usbss1 { 452 ti,vbus-divider; 453}; 454 455/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */ 456&mcu_gpio0 { 457 status = "reserved"; 458}; 459 460&mcu_gpio_intr { 461 status = "reserved"; 462}; 463 464&wkup_rtc0 { 465 status = "disabled"; 466}; 467 468&wkup_rti0 { 469 /* WKUP RTI0 is used by DM firmware */ 470 status = "reserved"; 471}; 472 473&wkup_uart0 { 474 /* WKUP UART0 is used by DM firmware */ 475 status = "reserved"; 476}; 477 478&main_uart1 { 479 /* Main UART1 is used by TIFS firmware */ 480 status = "reserved"; 481}; 482 483#include "k3-am62-ti-ipc-firmware.dtsi" 484