1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2025 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7 8/ { 9 #address-cells = <2>; 10 #size-cells = <2>; 11 12 cpus { 13 #address-cells = <1>; 14 #size-cells = <0>; 15 16 cpu0: cpu@0 { 17 compatible = "arm,cortex-a35"; 18 reg = <0>; 19 device_type = "cpu"; 20 enable-method = "psci"; 21 }; 22 }; 23 24 arm-pmu { 25 compatible = "arm,cortex-a35-pmu"; 26 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 27 interrupt-affinity = <&cpu0>; 28 interrupt-parent = <&intc>; 29 }; 30 31 arm_wdt: watchdog { 32 compatible = "arm,smc-wdt"; 33 arm,smc-id = <0xbc000000>; 34 status = "disabled"; 35 }; 36 37 ck_flexgen_08: clock-64000000 { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <64000000>; 41 }; 42 43 ck_flexgen_51: clock-200000000 { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <200000000>; 47 }; 48 49 firmware { 50 optee { 51 compatible = "linaro,optee-tz"; 52 method = "smc"; 53 }; 54 55 scmi: scmi { 56 compatible = "linaro,scmi-optee"; 57 #address-cells = <1>; 58 #size-cells = <0>; 59 linaro,optee-channel-id = <0>; 60 61 scmi_clk: protocol@14 { 62 reg = <0x14>; 63 #clock-cells = <1>; 64 }; 65 66 scmi_reset: protocol@16 { 67 reg = <0x16>; 68 #reset-cells = <1>; 69 }; 70 }; 71 }; 72 73 psci { 74 compatible = "arm,psci-1.0"; 75 method = "smc"; 76 }; 77 78 timer { 79 compatible = "arm,armv8-timer"; 80 interrupt-parent = <&intc>; 81 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 82 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 83 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 84 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 85 arm,no-tick-in-suspend; 86 }; 87 88 soc@0 { 89 compatible = "simple-bus"; 90 ranges = <0x0 0x0 0x0 0x0 0x80000000>; 91 dma-ranges = <0x0 0x0 0x80000000 0x1 0x0>; 92 interrupt-parent = <&intc>; 93 #address-cells = <1>; 94 #size-cells = <2>; 95 96 rifsc: bus@42080000 { 97 compatible = "simple-bus"; 98 reg = <0x42080000 0x0 0x1000>; 99 ranges; 100 dma-ranges; 101 #address-cells = <1>; 102 #size-cells = <2>; 103 104 usart2: serial@400e0000 { 105 compatible = "st,stm32h7-uart"; 106 reg = <0x400e0000 0x0 0x400>; 107 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 108 clocks = <&ck_flexgen_08>; 109 status = "disabled"; 110 }; 111 }; 112 113 syscfg: syscon@44230000 { 114 compatible = "st,stm32mp21-syscfg", "syscon"; 115 reg = <0x44230000 0x0 0x10000>; 116 }; 117 118 intc: interrupt-controller@4ac10000 { 119 compatible = "arm,gic-400"; 120 reg = <0x4ac10000 0x0 0x1000>, 121 <0x4ac20000 0x0 0x20000>, 122 <0x4ac40000 0x0 0x20000>, 123 <0x4ac60000 0x0 0x20000>; 124 #interrupt-cells = <3>; 125 interrupt-controller; 126 }; 127 }; 128}; 129