1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Spreadtrum SC9860 SoC 4 * 5 * Copyright (C) 2016, Spreadtrum Communications Inc. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/gpio/gpio.h> 11#include "whale2.dtsi" 12 13/ { 14 cpus { 15 #address-cells = <2>; 16 #size-cells = <0>; 17 18 cpu-map { 19 cluster0 { 20 core0 { 21 cpu = <&CPU0>; 22 }; 23 core1 { 24 cpu = <&CPU1>; 25 }; 26 core2 { 27 cpu = <&CPU2>; 28 }; 29 core3 { 30 cpu = <&CPU3>; 31 }; 32 }; 33 34 cluster1 { 35 core0 { 36 cpu = <&CPU4>; 37 }; 38 core1 { 39 cpu = <&CPU5>; 40 }; 41 core2 { 42 cpu = <&CPU6>; 43 }; 44 core3 { 45 cpu = <&CPU7>; 46 }; 47 }; 48 }; 49 50 CPU0: cpu@530000 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0 0x530000>; 54 enable-method = "psci"; 55 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 56 }; 57 58 CPU1: cpu@530001 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a53"; 61 reg = <0x0 0x530001>; 62 enable-method = "psci"; 63 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 64 }; 65 66 CPU2: cpu@530002 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a53"; 69 reg = <0x0 0x530002>; 70 enable-method = "psci"; 71 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 72 }; 73 74 CPU3: cpu@530003 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53"; 77 reg = <0x0 0x530003>; 78 enable-method = "psci"; 79 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 80 }; 81 82 CPU4: cpu@530100 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a53"; 85 reg = <0x0 0x530100>; 86 enable-method = "psci"; 87 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 88 }; 89 90 CPU5: cpu@530101 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a53"; 93 reg = <0x0 0x530101>; 94 enable-method = "psci"; 95 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 96 }; 97 98 CPU6: cpu@530102 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a53"; 101 reg = <0x0 0x530102>; 102 enable-method = "psci"; 103 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 104 }; 105 106 CPU7: cpu@530103 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53"; 109 reg = <0x0 0x530103>; 110 enable-method = "psci"; 111 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 112 }; 113 }; 114 115 idle-states { 116 entry-method = "psci"; 117 118 CORE_PD: cpu-pd { 119 compatible = "arm,idle-state"; 120 entry-latency-us = <1000>; 121 exit-latency-us = <700>; 122 min-residency-us = <2500>; 123 local-timer-stop; 124 arm,psci-suspend-param = <0x00010002>; 125 }; 126 127 CLUSTER_PD: cluster-pd { 128 compatible = "arm,idle-state"; 129 entry-latency-us = <1000>; 130 exit-latency-us = <1000>; 131 min-residency-us = <3000>; 132 local-timer-stop; 133 arm,psci-suspend-param = <0x01010003>; 134 }; 135 }; 136 137 psci { 138 compatible = "arm,psci-0.2"; 139 method = "smc"; 140 }; 141 142 timer { 143 compatible = "arm,armv8-timer"; 144 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) 145 | IRQ_TYPE_LEVEL_LOW)>, 146 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) 147 | IRQ_TYPE_LEVEL_LOW)>, 148 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) 149 | IRQ_TYPE_LEVEL_LOW)>, 150 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) 151 | IRQ_TYPE_LEVEL_LOW)>; 152 }; 153 154 pmu { 155 compatible = "arm,cortex-a53-pmu"; 156 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 164 interrupt-affinity = <&CPU0>, 165 <&CPU1>, 166 <&CPU2>, 167 <&CPU3>, 168 <&CPU4>, 169 <&CPU5>, 170 <&CPU6>, 171 <&CPU7>; 172 }; 173 174 soc { 175 gic: interrupt-controller@12001000 { 176 compatible = "arm,gic-400"; 177 reg = <0 0x12001000 0 0x1000>, 178 <0 0x12002000 0 0x2000>, 179 <0 0x12004000 0 0x2000>, 180 <0 0x12006000 0 0x2000>; 181 #interrupt-cells = <3>; 182 interrupt-controller; 183 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) 184 | IRQ_TYPE_LEVEL_HIGH)>; 185 }; 186 187 ap_clk: clock-controller@20000000 { 188 compatible = "sprd,sc9860-ap-clk"; 189 reg = <0 0x20000000 0 0x400>; 190 clocks = <&ext_26m>, <&pll 0>, 191 <&pmu_gate 0>; 192 #clock-cells = <1>; 193 }; 194 195 aon_prediv: aon-prediv@402d0000 { 196 compatible = "sprd,sc9860-aon-prediv"; 197 reg = <0 0x402d0000 0 0x400>; 198 clocks = <&ext_26m>, <&pll 0>, 199 <&pmu_gate 0>; 200 #clock-cells = <1>; 201 }; 202 203 204 aonsecure_clk: clock-controller@40880000 { 205 compatible = "sprd,sc9860-aonsecure-clk"; 206 reg = <0 0x40880000 0 0x400>; 207 clocks = <&ext_26m>, <&pll 0>; 208 #clock-cells = <1>; 209 }; 210 211 gpu_clk: clock-controller@60200000 { 212 compatible = "sprd,sc9860-gpu-clk"; 213 reg = <0 0x60200000 0 0x400>; 214 clocks = <&pll 0>; 215 #clock-cells = <1>; 216 }; 217 218 vsp_clk: clock-controller@61000000 { 219 compatible = "sprd,sc9860-vsp-clk"; 220 reg = <0 0x61000000 0 0x400>; 221 clocks = <&ext_26m>, <&pll 0>; 222 #clock-cells = <1>; 223 }; 224 225 cam_clk: clock-controller@62000000 { 226 compatible = "sprd,sc9860-cam-clk"; 227 reg = <0 0x62000000 0 0x4000>; 228 clocks = <&ext_26m>, <&pll 0>; 229 #clock-cells = <1>; 230 }; 231 232 disp_clk: clock-controller@63000000 { 233 compatible = "sprd,sc9860-disp-clk"; 234 reg = <0 0x63000000 0 0x400>; 235 clocks = <&ext_26m>, <&pll 0>; 236 #clock-cells = <1>; 237 }; 238 239 funnel@10001000 { /* SoC Funnel */ 240 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 241 reg = <0 0x10001000 0 0x1000>; 242 clocks = <&ext_26m>; 243 clock-names = "apb_pclk"; 244 out-ports { 245 port { 246 soc_funnel_out_port: endpoint { 247 remote-endpoint = <&etb_in>; 248 }; 249 }; 250 }; 251 252 in-ports { 253 #address-cells = <1>; 254 #size-cells = <0>; 255 256 port@0 { 257 reg = <0>; 258 soc_funnel_in_port0: endpoint { 259 remote-endpoint = 260 <&main_funnel_out_port>; 261 }; 262 }; 263 264 port@4 { 265 reg = <4>; 266 soc_funnel_in_port1: endpoint { 267 remote-endpoint = 268 <&stm_out_port>; 269 }; 270 }; 271 }; 272 }; 273 274 etb@10003000 { 275 compatible = "arm,coresight-tmc", "arm,primecell"; 276 reg = <0 0x10003000 0 0x1000>; 277 clocks = <&ext_26m>; 278 clock-names = "apb_pclk"; 279 280 in-ports { 281 port { 282 etb_in: endpoint { 283 remote-endpoint = 284 <&soc_funnel_out_port>; 285 }; 286 }; 287 }; 288 }; 289 290 stm@10006000 { 291 compatible = "arm,coresight-stm", "arm,primecell"; 292 reg = <0 0x10006000 0 0x1000>, 293 <0 0x01000000 0 0x180000>; 294 reg-names = "stm-base", "stm-stimulus-base"; 295 clocks = <&ext_26m>; 296 clock-names = "apb_pclk"; 297 out-ports { 298 port { 299 stm_out_port: endpoint { 300 remote-endpoint = 301 <&soc_funnel_in_port1>; 302 }; 303 }; 304 }; 305 }; 306 307 funnel@11001000 { /* Cluster0 Funnel */ 308 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 309 reg = <0 0x11001000 0 0x1000>; 310 clocks = <&ext_26m>; 311 clock-names = "apb_pclk"; 312 out-ports { 313 port { 314 cluster0_funnel_out_port: endpoint { 315 remote-endpoint = 316 <&cluster0_etf_in>; 317 }; 318 }; 319 }; 320 321 in-ports { 322 #address-cells = <1>; 323 #size-cells = <0>; 324 325 port@0 { 326 reg = <0>; 327 cluster0_funnel_in_port0: endpoint { 328 remote-endpoint = <&etm0_out>; 329 }; 330 }; 331 332 port@1 { 333 reg = <1>; 334 cluster0_funnel_in_port1: endpoint { 335 remote-endpoint = <&etm1_out>; 336 }; 337 }; 338 339 port@2 { 340 reg = <2>; 341 cluster0_funnel_in_port2: endpoint { 342 remote-endpoint = <&etm2_out>; 343 }; 344 }; 345 346 port@4 { 347 reg = <4>; 348 cluster0_funnel_in_port3: endpoint { 349 remote-endpoint = <&etm3_out>; 350 }; 351 }; 352 }; 353 }; 354 355 funnel@11002000 { /* Cluster1 Funnel */ 356 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 357 reg = <0 0x11002000 0 0x1000>; 358 clocks = <&ext_26m>; 359 clock-names = "apb_pclk"; 360 out-ports { 361 port { 362 cluster1_funnel_out_port: endpoint { 363 remote-endpoint = 364 <&cluster1_etf_in>; 365 }; 366 }; 367 }; 368 369 in-ports { 370 #address-cells = <1>; 371 #size-cells = <0>; 372 373 port@0 { 374 reg = <0>; 375 cluster1_funnel_in_port0: endpoint { 376 remote-endpoint = <&etm4_out>; 377 }; 378 }; 379 380 port@1 { 381 reg = <1>; 382 cluster1_funnel_in_port1: endpoint { 383 remote-endpoint = <&etm5_out>; 384 }; 385 }; 386 387 port@2 { 388 reg = <2>; 389 cluster1_funnel_in_port2: endpoint { 390 remote-endpoint = <&etm6_out>; 391 }; 392 }; 393 394 port@3 { 395 reg = <3>; 396 cluster1_funnel_in_port3: endpoint { 397 remote-endpoint = <&etm7_out>; 398 }; 399 }; 400 }; 401 }; 402 403 etf@11003000 { /* ETF on Cluster0 */ 404 compatible = "arm,coresight-tmc", "arm,primecell"; 405 reg = <0 0x11003000 0 0x1000>; 406 clocks = <&ext_26m>; 407 clock-names = "apb_pclk"; 408 409 out-ports { 410 port { 411 cluster0_etf_out: endpoint { 412 remote-endpoint = 413 <&main_funnel_in_port0>; 414 }; 415 }; 416 }; 417 418 in-ports { 419 port { 420 cluster0_etf_in: endpoint { 421 remote-endpoint = 422 <&cluster0_funnel_out_port>; 423 }; 424 }; 425 }; 426 }; 427 428 etf@11004000 { /* ETF on Cluster1 */ 429 compatible = "arm,coresight-tmc", "arm,primecell"; 430 reg = <0 0x11004000 0 0x1000>; 431 clocks = <&ext_26m>; 432 clock-names = "apb_pclk"; 433 434 out-ports { 435 port { 436 cluster1_etf_out: endpoint { 437 remote-endpoint = 438 <&main_funnel_in_port1>; 439 }; 440 }; 441 }; 442 443 in-ports { 444 port { 445 cluster1_etf_in: endpoint { 446 remote-endpoint = 447 <&cluster1_funnel_out_port>; 448 }; 449 }; 450 }; 451 }; 452 453 funnel@11005000 { /* Main Funnel */ 454 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 455 reg = <0 0x11005000 0 0x1000>; 456 clocks = <&ext_26m>; 457 clock-names = "apb_pclk"; 458 459 out-ports { 460 port { 461 main_funnel_out_port: endpoint { 462 remote-endpoint = 463 <&soc_funnel_in_port0>; 464 }; 465 }; 466 }; 467 468 in-ports { 469 #address-cells = <1>; 470 #size-cells = <0>; 471 472 port@0 { 473 reg = <0>; 474 main_funnel_in_port0: endpoint { 475 remote-endpoint = 476 <&cluster0_etf_out>; 477 }; 478 }; 479 480 port@1 { 481 reg = <1>; 482 main_funnel_in_port1: endpoint { 483 remote-endpoint = 484 <&cluster1_etf_out>; 485 }; 486 }; 487 }; 488 }; 489 490 etm@11440000 { 491 compatible = "arm,coresight-etm4x", "arm,primecell"; 492 reg = <0 0x11440000 0 0x1000>; 493 cpu = <&CPU0>; 494 clocks = <&ext_26m>; 495 clock-names = "apb_pclk"; 496 497 out-ports { 498 port { 499 etm0_out: endpoint { 500 remote-endpoint = 501 <&cluster0_funnel_in_port0>; 502 }; 503 }; 504 }; 505 }; 506 507 etm@11540000 { 508 compatible = "arm,coresight-etm4x", "arm,primecell"; 509 reg = <0 0x11540000 0 0x1000>; 510 cpu = <&CPU1>; 511 clocks = <&ext_26m>; 512 clock-names = "apb_pclk"; 513 514 out-ports { 515 port { 516 etm1_out: endpoint { 517 remote-endpoint = 518 <&cluster0_funnel_in_port1>; 519 }; 520 }; 521 }; 522 }; 523 524 etm@11640000 { 525 compatible = "arm,coresight-etm4x", "arm,primecell"; 526 reg = <0 0x11640000 0 0x1000>; 527 cpu = <&CPU2>; 528 clocks = <&ext_26m>; 529 clock-names = "apb_pclk"; 530 531 out-ports { 532 port { 533 etm2_out: endpoint { 534 remote-endpoint = 535 <&cluster0_funnel_in_port2>; 536 }; 537 }; 538 }; 539 }; 540 541 etm@11740000 { 542 compatible = "arm,coresight-etm4x", "arm,primecell"; 543 reg = <0 0x11740000 0 0x1000>; 544 cpu = <&CPU3>; 545 clocks = <&ext_26m>; 546 clock-names = "apb_pclk"; 547 548 out-ports { 549 port { 550 etm3_out: endpoint { 551 remote-endpoint = 552 <&cluster0_funnel_in_port3>; 553 }; 554 }; 555 }; 556 }; 557 558 etm@11840000 { 559 compatible = "arm,coresight-etm4x", "arm,primecell"; 560 reg = <0 0x11840000 0 0x1000>; 561 cpu = <&CPU4>; 562 clocks = <&ext_26m>; 563 clock-names = "apb_pclk"; 564 565 out-ports { 566 port { 567 etm4_out: endpoint { 568 remote-endpoint = 569 <&cluster1_funnel_in_port0>; 570 }; 571 }; 572 }; 573 }; 574 575 etm@11940000 { 576 compatible = "arm,coresight-etm4x", "arm,primecell"; 577 reg = <0 0x11940000 0 0x1000>; 578 cpu = <&CPU5>; 579 clocks = <&ext_26m>; 580 clock-names = "apb_pclk"; 581 582 out-ports { 583 port { 584 etm5_out: endpoint { 585 remote-endpoint = 586 <&cluster1_funnel_in_port1>; 587 }; 588 }; 589 }; 590 }; 591 592 etm@11a40000 { 593 compatible = "arm,coresight-etm4x", "arm,primecell"; 594 reg = <0 0x11a40000 0 0x1000>; 595 cpu = <&CPU6>; 596 clocks = <&ext_26m>; 597 clock-names = "apb_pclk"; 598 599 out-ports { 600 port { 601 etm6_out: endpoint { 602 remote-endpoint = 603 <&cluster1_funnel_in_port2>; 604 }; 605 }; 606 }; 607 }; 608 609 etm@11b40000 { 610 compatible = "arm,coresight-etm4x", "arm,primecell"; 611 reg = <0 0x11b40000 0 0x1000>; 612 cpu = <&CPU7>; 613 clocks = <&ext_26m>; 614 clock-names = "apb_pclk"; 615 616 out-ports { 617 port { 618 etm7_out: endpoint { 619 remote-endpoint = 620 <&cluster1_funnel_in_port3>; 621 }; 622 }; 623 }; 624 }; 625 }; 626}; 627