1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Spreadtrum SC9860 SoC 4 * 5 * Copyright (C) 2016, Spreadtrum Communications Inc. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/gpio/gpio.h> 11#include "whale2.dtsi" 12 13/ { 14 cpus { 15 #address-cells = <2>; 16 #size-cells = <0>; 17 18 cpu-map { 19 cluster0 { 20 core0 { 21 cpu = <&CPU0>; 22 }; 23 core1 { 24 cpu = <&CPU1>; 25 }; 26 core2 { 27 cpu = <&CPU2>; 28 }; 29 core3 { 30 cpu = <&CPU3>; 31 }; 32 }; 33 34 cluster1 { 35 core0 { 36 cpu = <&CPU4>; 37 }; 38 core1 { 39 cpu = <&CPU5>; 40 }; 41 core2 { 42 cpu = <&CPU6>; 43 }; 44 core3 { 45 cpu = <&CPU7>; 46 }; 47 }; 48 }; 49 50 CPU0: cpu@530000 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0 0x530000>; 54 enable-method = "psci"; 55 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 56 }; 57 58 CPU1: cpu@530001 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a53"; 61 reg = <0x0 0x530001>; 62 enable-method = "psci"; 63 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 64 }; 65 66 CPU2: cpu@530002 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a53"; 69 reg = <0x0 0x530002>; 70 enable-method = "psci"; 71 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 72 }; 73 74 CPU3: cpu@530003 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53"; 77 reg = <0x0 0x530003>; 78 enable-method = "psci"; 79 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 80 }; 81 82 CPU4: cpu@530100 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a53"; 85 reg = <0x0 0x530100>; 86 enable-method = "psci"; 87 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 88 }; 89 90 CPU5: cpu@530101 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a53"; 93 reg = <0x0 0x530101>; 94 enable-method = "psci"; 95 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 96 }; 97 98 CPU6: cpu@530102 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a53"; 101 reg = <0x0 0x530102>; 102 enable-method = "psci"; 103 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 104 }; 105 106 CPU7: cpu@530103 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53"; 109 reg = <0x0 0x530103>; 110 enable-method = "psci"; 111 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 112 }; 113 }; 114 115 idle-states { 116 entry-method = "psci"; 117 118 CORE_PD: core_pd { 119 compatible = "arm,idle-state"; 120 entry-latency-us = <1000>; 121 exit-latency-us = <700>; 122 min-residency-us = <2500>; 123 local-timer-stop; 124 arm,psci-suspend-param = <0x00010002>; 125 }; 126 127 CLUSTER_PD: cluster_pd { 128 compatible = "arm,idle-state"; 129 entry-latency-us = <1000>; 130 exit-latency-us = <1000>; 131 min-residency-us = <3000>; 132 local-timer-stop; 133 arm,psci-suspend-param = <0x01010003>; 134 }; 135 }; 136 137 psci { 138 compatible = "arm,psci-0.2"; 139 method = "smc"; 140 }; 141 142 timer { 143 compatible = "arm,armv8-timer"; 144 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) 145 | IRQ_TYPE_LEVEL_LOW)>, 146 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) 147 | IRQ_TYPE_LEVEL_LOW)>, 148 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) 149 | IRQ_TYPE_LEVEL_LOW)>, 150 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) 151 | IRQ_TYPE_LEVEL_LOW)>; 152 }; 153 154 pmu { 155 compatible = "arm,cortex-a53-pmu"; 156 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 164 interrupt-affinity = <&CPU0>, 165 <&CPU1>, 166 <&CPU2>, 167 <&CPU3>, 168 <&CPU4>, 169 <&CPU5>, 170 <&CPU6>, 171 <&CPU7>; 172 }; 173 174 soc { 175 gic: interrupt-controller@12001000 { 176 compatible = "arm,gic-400"; 177 reg = <0 0x12001000 0 0x1000>, 178 <0 0x12002000 0 0x2000>, 179 <0 0x12004000 0 0x2000>, 180 <0 0x12006000 0 0x2000>; 181 #interrupt-cells = <3>; 182 interrupt-controller; 183 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) 184 | IRQ_TYPE_LEVEL_HIGH)>; 185 }; 186 187 pmu_gate: pmu-gate { 188 compatible = "sprd,sc9860-pmu-gate"; 189 sprd,syscon = <&pmu_regs>; /* 0x402b0000 */ 190 clocks = <&ext_26m>; 191 #clock-cells = <1>; 192 }; 193 194 pll: pll { 195 compatible = "sprd,sc9860-pll"; 196 sprd,syscon = <&ana_regs>; /* 0x40400000 */ 197 clocks = <&pmu_gate 0>; 198 #clock-cells = <1>; 199 }; 200 201 ap_clk: clock-controller@20000000 { 202 compatible = "sprd,sc9860-ap-clk"; 203 reg = <0 0x20000000 0 0x400>; 204 clocks = <&ext_26m>, <&pll 0>, 205 <&pmu_gate 0>; 206 #clock-cells = <1>; 207 }; 208 209 aon_prediv: aon-prediv@402d0000 { 210 compatible = "sprd,sc9860-aon-prediv"; 211 reg = <0 0x402d0000 0 0x400>; 212 clocks = <&ext_26m>, <&pll 0>, 213 <&pmu_gate 0>; 214 #clock-cells = <1>; 215 }; 216 217 apahb_gate: apahb-gate { 218 compatible = "sprd,sc9860-apahb-gate"; 219 sprd,syscon = <&ap_ahb_regs>; /* 0x20210000 */ 220 clocks = <&aon_prediv 0>; 221 #clock-cells = <1>; 222 }; 223 224 aon_gate: aon-gate { 225 compatible = "sprd,sc9860-aon-gate"; 226 sprd,syscon = <&aon_regs>; /* 0x402e0000 */ 227 clocks = <&aon_prediv 0>; 228 #clock-cells = <1>; 229 }; 230 231 aonsecure_clk: clock-controller@40880000 { 232 compatible = "sprd,sc9860-aonsecure-clk"; 233 reg = <0 0x40880000 0 0x400>; 234 clocks = <&ext_26m>, <&pll 0>; 235 #clock-cells = <1>; 236 }; 237 238 agcp_gate: agcp-gate { 239 compatible = "sprd,sc9860-agcp-gate"; 240 sprd,syscon = <&agcp_regs>; /* 0x415e0000 */ 241 clocks = <&aon_prediv 0>; 242 #clock-cells = <1>; 243 }; 244 245 gpu_clk: clock-controller@60200000 { 246 compatible = "sprd,sc9860-gpu-clk"; 247 reg = <0 0x60200000 0 0x400>; 248 clocks = <&pll 0>; 249 #clock-cells = <1>; 250 }; 251 252 vsp_clk: clock-controller@61000000 { 253 compatible = "sprd,sc9860-vsp-clk"; 254 reg = <0 0x61000000 0 0x400>; 255 clocks = <&ext_26m>, <&pll 0>; 256 #clock-cells = <1>; 257 }; 258 259 vsp_gate: vsp-gate { 260 compatible = "sprd,sc9860-vsp-gate"; 261 sprd,syscon = <&vsp_regs>; /* 0x61100000 */ 262 clocks = <&vsp_clk 0>; 263 #clock-cells = <1>; 264 }; 265 266 cam_clk: clock-controller@62000000 { 267 compatible = "sprd,sc9860-cam-clk"; 268 reg = <0 0x62000000 0 0x4000>; 269 clocks = <&ext_26m>, <&pll 0>; 270 #clock-cells = <1>; 271 }; 272 273 cam_gate: cam-gate { 274 compatible = "sprd,sc9860-cam-gate"; 275 sprd,syscon = <&cam_regs>; /* 0x62100000 */ 276 clocks = <&cam_clk 0>; 277 #clock-cells = <1>; 278 }; 279 280 disp_clk: clock-controller@63000000 { 281 compatible = "sprd,sc9860-disp-clk"; 282 reg = <0 0x63000000 0 0x400>; 283 clocks = <&ext_26m>, <&pll 0>; 284 #clock-cells = <1>; 285 }; 286 287 disp_gate: disp-gate { 288 compatible = "sprd,sc9860-disp-gate"; 289 sprd,syscon = <&disp_regs>; /* 0x63100000 */ 290 clocks = <&disp_clk 0>; 291 #clock-cells = <1>; 292 }; 293 294 apapb_gate: apapb-gate { 295 compatible = "sprd,sc9860-apapb-gate"; 296 sprd,syscon = <&ap_apb_regs>; /* 0x70b00000 */ 297 clocks = <&ap_clk 0>; 298 #clock-cells = <1>; 299 }; 300 301 funnel@10001000 { /* SoC Funnel */ 302 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 303 reg = <0 0x10001000 0 0x1000>; 304 clocks = <&ext_26m>; 305 clock-names = "apb_pclk"; 306 out-ports { 307 port { 308 soc_funnel_out_port: endpoint { 309 remote-endpoint = <&etb_in>; 310 }; 311 }; 312 }; 313 314 in-ports { 315 #address-cells = <1>; 316 #size-cells = <0>; 317 318 port@0 { 319 reg = <0>; 320 soc_funnel_in_port0: endpoint { 321 remote-endpoint = 322 <&main_funnel_out_port>; 323 }; 324 }; 325 326 port@4 { 327 reg = <4>; 328 soc_funnel_in_port1: endpoint { 329 remote-endpoint = 330 <&stm_out_port>; 331 }; 332 }; 333 }; 334 }; 335 336 etb@10003000 { 337 compatible = "arm,coresight-tmc", "arm,primecell"; 338 reg = <0 0x10003000 0 0x1000>; 339 clocks = <&ext_26m>; 340 clock-names = "apb_pclk"; 341 out-ports { 342 port { 343 etb_in: endpoint { 344 remote-endpoint = 345 <&soc_funnel_out_port>; 346 }; 347 }; 348 }; 349 }; 350 351 stm@10006000 { 352 compatible = "arm,coresight-stm", "arm,primecell"; 353 reg = <0 0x10006000 0 0x1000>, 354 <0 0x01000000 0 0x180000>; 355 reg-names = "stm-base", "stm-stimulus-base"; 356 clocks = <&ext_26m>; 357 clock-names = "apb_pclk"; 358 out-ports { 359 port { 360 stm_out_port: endpoint { 361 remote-endpoint = 362 <&soc_funnel_in_port1>; 363 }; 364 }; 365 }; 366 }; 367 368 funnel@11001000 { /* Cluster0 Funnel */ 369 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 370 reg = <0 0x11001000 0 0x1000>; 371 clocks = <&ext_26m>; 372 clock-names = "apb_pclk"; 373 out-ports { 374 port { 375 cluster0_funnel_out_port: endpoint { 376 remote-endpoint = 377 <&cluster0_etf_in>; 378 }; 379 }; 380 }; 381 382 in-ports { 383 #address-cells = <1>; 384 #size-cells = <0>; 385 386 port@0 { 387 reg = <0>; 388 cluster0_funnel_in_port0: endpoint { 389 remote-endpoint = <&etm0_out>; 390 }; 391 }; 392 393 port@1 { 394 reg = <1>; 395 cluster0_funnel_in_port1: endpoint { 396 remote-endpoint = <&etm1_out>; 397 }; 398 }; 399 400 port@2 { 401 reg = <2>; 402 cluster0_funnel_in_port2: endpoint { 403 remote-endpoint = <&etm2_out>; 404 }; 405 }; 406 407 port@4 { 408 reg = <4>; 409 cluster0_funnel_in_port3: endpoint { 410 remote-endpoint = <&etm3_out>; 411 }; 412 }; 413 }; 414 }; 415 416 funnel@11002000 { /* Cluster1 Funnel */ 417 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 418 reg = <0 0x11002000 0 0x1000>; 419 clocks = <&ext_26m>; 420 clock-names = "apb_pclk"; 421 out-ports { 422 port { 423 cluster1_funnel_out_port: endpoint { 424 remote-endpoint = 425 <&cluster1_etf_in>; 426 }; 427 }; 428 }; 429 430 in-ports { 431 #address-cells = <1>; 432 #size-cells = <0>; 433 434 port@0 { 435 reg = <0>; 436 cluster1_funnel_in_port0: endpoint { 437 remote-endpoint = <&etm4_out>; 438 }; 439 }; 440 441 port@1 { 442 reg = <1>; 443 cluster1_funnel_in_port1: endpoint { 444 remote-endpoint = <&etm5_out>; 445 }; 446 }; 447 448 port@2 { 449 reg = <2>; 450 cluster1_funnel_in_port2: endpoint { 451 remote-endpoint = <&etm6_out>; 452 }; 453 }; 454 455 port@3 { 456 reg = <3>; 457 cluster1_funnel_in_port3: endpoint { 458 remote-endpoint = <&etm7_out>; 459 }; 460 }; 461 }; 462 }; 463 464 etf@11003000 { /* ETF on Cluster0 */ 465 compatible = "arm,coresight-tmc", "arm,primecell"; 466 reg = <0 0x11003000 0 0x1000>; 467 clocks = <&ext_26m>; 468 clock-names = "apb_pclk"; 469 470 out-ports { 471 port { 472 cluster0_etf_out: endpoint { 473 remote-endpoint = 474 <&main_funnel_in_port0>; 475 }; 476 }; 477 }; 478 479 in-ports { 480 port { 481 cluster0_etf_in: endpoint { 482 remote-endpoint = 483 <&cluster0_funnel_out_port>; 484 }; 485 }; 486 }; 487 }; 488 489 etf@11004000 { /* ETF on Cluster1 */ 490 compatible = "arm,coresight-tmc", "arm,primecell"; 491 reg = <0 0x11004000 0 0x1000>; 492 clocks = <&ext_26m>; 493 clock-names = "apb_pclk"; 494 495 out-ports { 496 port { 497 cluster1_etf_out: endpoint { 498 remote-endpoint = 499 <&main_funnel_in_port1>; 500 }; 501 }; 502 }; 503 504 in-ports { 505 port { 506 cluster1_etf_in: endpoint { 507 remote-endpoint = 508 <&cluster1_funnel_out_port>; 509 }; 510 }; 511 }; 512 }; 513 514 funnel@11005000 { /* Main Funnel */ 515 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 516 reg = <0 0x11005000 0 0x1000>; 517 clocks = <&ext_26m>; 518 clock-names = "apb_pclk"; 519 520 out-ports { 521 port { 522 main_funnel_out_port: endpoint { 523 remote-endpoint = 524 <&soc_funnel_in_port0>; 525 }; 526 }; 527 }; 528 529 in-ports { 530 #address-cells = <1>; 531 #size-cells = <0>; 532 533 port@0 { 534 reg = <0>; 535 main_funnel_in_port0: endpoint { 536 remote-endpoint = 537 <&cluster0_etf_out>; 538 }; 539 }; 540 541 port@1 { 542 reg = <1>; 543 main_funnel_in_port1: endpoint { 544 remote-endpoint = 545 <&cluster1_etf_out>; 546 }; 547 }; 548 }; 549 }; 550 551 etm@11440000 { 552 compatible = "arm,coresight-etm4x", "arm,primecell"; 553 reg = <0 0x11440000 0 0x1000>; 554 cpu = <&CPU0>; 555 clocks = <&ext_26m>; 556 clock-names = "apb_pclk"; 557 558 out-ports { 559 port { 560 etm0_out: endpoint { 561 remote-endpoint = 562 <&cluster0_funnel_in_port0>; 563 }; 564 }; 565 }; 566 }; 567 568 etm@11540000 { 569 compatible = "arm,coresight-etm4x", "arm,primecell"; 570 reg = <0 0x11540000 0 0x1000>; 571 cpu = <&CPU1>; 572 clocks = <&ext_26m>; 573 clock-names = "apb_pclk"; 574 575 out-ports { 576 port { 577 etm1_out: endpoint { 578 remote-endpoint = 579 <&cluster0_funnel_in_port1>; 580 }; 581 }; 582 }; 583 }; 584 585 etm@11640000 { 586 compatible = "arm,coresight-etm4x", "arm,primecell"; 587 reg = <0 0x11640000 0 0x1000>; 588 cpu = <&CPU2>; 589 clocks = <&ext_26m>; 590 clock-names = "apb_pclk"; 591 592 out-ports { 593 port { 594 etm2_out: endpoint { 595 remote-endpoint = 596 <&cluster0_funnel_in_port2>; 597 }; 598 }; 599 }; 600 }; 601 602 etm@11740000 { 603 compatible = "arm,coresight-etm4x", "arm,primecell"; 604 reg = <0 0x11740000 0 0x1000>; 605 cpu = <&CPU3>; 606 clocks = <&ext_26m>; 607 clock-names = "apb_pclk"; 608 609 out-ports { 610 port { 611 etm3_out: endpoint { 612 remote-endpoint = 613 <&cluster0_funnel_in_port3>; 614 }; 615 }; 616 }; 617 }; 618 619 etm@11840000 { 620 compatible = "arm,coresight-etm4x", "arm,primecell"; 621 reg = <0 0x11840000 0 0x1000>; 622 cpu = <&CPU4>; 623 clocks = <&ext_26m>; 624 clock-names = "apb_pclk"; 625 626 out-ports { 627 port { 628 etm4_out: endpoint { 629 remote-endpoint = 630 <&cluster1_funnel_in_port0>; 631 }; 632 }; 633 }; 634 }; 635 636 etm@11940000 { 637 compatible = "arm,coresight-etm4x", "arm,primecell"; 638 reg = <0 0x11940000 0 0x1000>; 639 cpu = <&CPU5>; 640 clocks = <&ext_26m>; 641 clock-names = "apb_pclk"; 642 643 out-ports { 644 port { 645 etm5_out: endpoint { 646 remote-endpoint = 647 <&cluster1_funnel_in_port1>; 648 }; 649 }; 650 }; 651 }; 652 653 etm@11a40000 { 654 compatible = "arm,coresight-etm4x", "arm,primecell"; 655 reg = <0 0x11a40000 0 0x1000>; 656 cpu = <&CPU6>; 657 clocks = <&ext_26m>; 658 clock-names = "apb_pclk"; 659 660 out-ports { 661 port { 662 etm6_out: endpoint { 663 remote-endpoint = 664 <&cluster1_funnel_in_port2>; 665 }; 666 }; 667 }; 668 }; 669 670 etm@11b40000 { 671 compatible = "arm,coresight-etm4x", "arm,primecell"; 672 reg = <0 0x11b40000 0 0x1000>; 673 cpu = <&CPU7>; 674 clocks = <&ext_26m>; 675 clock-names = "apb_pclk"; 676 677 out-ports { 678 port { 679 etm7_out: endpoint { 680 remote-endpoint = 681 <&cluster1_funnel_in_port3>; 682 }; 683 }; 684 }; 685 }; 686 }; 687}; 688