1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2025 Joseph Kogut <joseph.kogut@gmail.com> 4 */ 5 6/* 7 * CM5 data sheet 8 * https://dl.radxa.com/cm5/v2210/radxa_cm5_v2210_schematic.pdf 9 */ 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/leds/common.h> 13#include <dt-bindings/soc/rockchip,vop2.h> 14#include <dt-bindings/usb/pd.h> 15 16/ { 17 compatible = "radxa,cm5", "rockchip,rk3588s"; 18 19 aliases { 20 mmc0 = &sdhci; 21 }; 22 23 leds { 24 compatible = "gpio-leds"; 25 26 led_sys: led-0 { 27 color = <LED_COLOR_ID_BLUE>; 28 default-state = "on"; 29 function = LED_FUNCTION_HEARTBEAT; 30 gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; 31 linux,default-trigger = "heartbeat"; 32 }; 33 }; 34}; 35 36&cpu_b0 { 37 cpu-supply = <&vdd_cpu_big0_s0>; 38}; 39 40&cpu_b1 { 41 cpu-supply = <&vdd_cpu_big0_s0>; 42}; 43 44&cpu_b2 { 45 cpu-supply = <&vdd_cpu_big1_s0>; 46}; 47 48&cpu_b3 { 49 cpu-supply = <&vdd_cpu_big1_s0>; 50}; 51 52&cpu_l0 { 53 cpu-supply = <&vdd_cpu_lit_s0>; 54}; 55 56&cpu_l1 { 57 cpu-supply = <&vdd_cpu_lit_s0>; 58}; 59 60&cpu_l2 { 61 cpu-supply = <&vdd_cpu_lit_s0>; 62}; 63 64&cpu_l3 { 65 cpu-supply = <&vdd_cpu_lit_s0>; 66}; 67 68&gmac1 { 69 clock_in_out = "output"; 70 phy-handle = <&rgmii_phy1>; 71 phy-mode = "rgmii-id"; 72 phy-supply = <&vcc_3v3_s0>; 73 pinctrl-names = "default"; 74 pinctrl-0 = <&gmac1_miim 75 &gmac1_tx_bus2 76 &gmac1_rx_bus2 77 &gmac1_rgmii_clk 78 &gmac1_rgmii_bus 79 &gmac1_clkinout>; 80}; 81 82&gpu { 83 mali-supply = <&vdd_gpu_s0>; 84 status = "okay"; 85}; 86 87&i2c0 { 88 pinctrl-names = "default"; 89 pinctrl-0 = <&i2c0m2_xfer>; 90 status = "okay"; 91 92 vdd_cpu_big0_s0: regulator@42 { 93 compatible = "rockchip,rk8602"; 94 reg = <0x42>; 95 fcs,suspend-voltage-selector = <1>; 96 regulator-name = "vdd_cpu_big0_s0"; 97 regulator-always-on; 98 regulator-boot-on; 99 regulator-min-microvolt = <550000>; 100 regulator-max-microvolt = <1050000>; 101 regulator-ramp-delay = <2300>; 102 vin-supply = <&vcc5v0_sys>; 103 104 regulator-state-mem { 105 regulator-off-in-suspend; 106 }; 107 }; 108 109 vdd_cpu_big1_s0: regulator@43 { 110 compatible = "rockchip,rk8602"; 111 reg = <0x43>; 112 fcs,suspend-voltage-selector = <1>; 113 regulator-name = "vdd_cpu_big1_s0"; 114 regulator-always-on; 115 regulator-boot-on; 116 regulator-min-microvolt = <550000>; 117 regulator-max-microvolt = <1050000>; 118 regulator-ramp-delay = <2300>; 119 vin-supply = <&vcc5v0_sys>; 120 121 regulator-state-mem { 122 regulator-off-in-suspend; 123 }; 124 }; 125}; 126 127&mdio1 { 128 rgmii_phy1: phy@1 { 129 compatible = "ethernet-phy-ieee802.3-c22"; 130 reg = <0x1>; 131 }; 132}; 133 134&pd_gpu { 135 domain-supply = <&vdd_gpu_s0>; 136}; 137 138&sdhci { 139 bus-width = <8>; 140 no-sdio; 141 no-sd; 142 non-removable; 143 max-frequency = <200000000>; 144 mmc-hs400-1_8v; 145 mmc-hs400-enhanced-strobe; 146 mmc-hs200-1_8v; 147 status = "okay"; 148}; 149 150&spi2 { 151 assigned-clocks = <&cru CLK_SPI2>; 152 assigned-clock-rates = <200000000>; 153 num-cs = <1>; 154 pinctrl-names = "default"; 155 pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; 156 status = "okay"; 157 158 pmic@0 { 159 compatible = "rockchip,rk806"; 160 reg = <0x0>; 161 interrupt-parent = <&gpio0>; 162 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 163 pinctrl-names = "default"; 164 pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, 165 <&rk806_dvs2_null>, <&rk806_dvs3_null>; 166 spi-max-frequency = <1000000>; 167 system-power-controller; 168 169 vcc1-supply = <&vcc5v0_sys>; 170 vcc2-supply = <&vcc5v0_sys>; 171 vcc3-supply = <&vcc5v0_sys>; 172 vcc4-supply = <&vcc5v0_sys>; 173 vcc5-supply = <&vcc5v0_sys>; 174 vcc6-supply = <&vcc5v0_sys>; 175 vcc7-supply = <&vcc5v0_sys>; 176 vcc8-supply = <&vcc5v0_sys>; 177 vcc9-supply = <&vcc5v0_sys>; 178 vcc10-supply = <&vcc5v0_sys>; 179 vcc11-supply = <&vcc_2v0_pldo_s3>; 180 vcc12-supply = <&vcc5v0_sys>; 181 vcc13-supply = <&vdd2_ddr_s3>; 182 vcc14-supply = <&vdd2_ddr_s3>; 183 vcca-supply = <&vcc5v0_sys>; 184 185 gpio-controller; 186 #gpio-cells = <2>; 187 188 rk806_dvs1_null: dvs1-null-pins { 189 pins = "gpio_pwrctrl1"; 190 function = "pin_fun0"; 191 }; 192 193 rk806_dvs2_null: dvs2-null-pins { 194 pins = "gpio_pwrctrl2"; 195 function = "pin_fun0"; 196 }; 197 198 rk806_dvs3_null: dvs3-null-pins { 199 pins = "gpio_pwrctrl3"; 200 function = "pin_fun0"; 201 }; 202 203 regulators { 204 vdd_gpu_s0: dcdc-reg1 { 205 regulator-name = "vdd_gpu_s0"; 206 regulator-boot-on; 207 regulator-enable-ramp-delay = <400>; 208 regulator-min-microvolt = <550000>; 209 regulator-max-microvolt = <950000>; 210 regulator-ramp-delay = <12500>; 211 212 regulator-state-mem { 213 regulator-off-in-suspend; 214 }; 215 }; 216 217 vdd_cpu_lit_s0: dcdc-reg2 { 218 regulator-name = "vdd_cpu_lit_s0"; 219 regulator-always-on; 220 regulator-boot-on; 221 regulator-min-microvolt = <550000>; 222 regulator-max-microvolt = <950000>; 223 regulator-ramp-delay = <12500>; 224 225 regulator-state-mem { 226 regulator-off-in-suspend; 227 }; 228 }; 229 230 vccio_sd_s0: pldo-reg5 { 231 regulator-always-on; 232 regulator-boot-on; 233 regulator-min-microvolt = <1800000>; 234 regulator-max-microvolt = <3300000>; 235 regulator-name = "vccio_sd_s0"; 236 237 regulator-state-mem { 238 regulator-off-in-suspend; 239 }; 240 }; 241 242 vdd2_ddr_s3: dcdc-reg6 { 243 regulator-name = "vdd2_ddr_s3"; 244 regulator-always-on; 245 regulator-boot-on; 246 247 regulator-state-mem { 248 regulator-on-in-suspend; 249 }; 250 }; 251 252 vcc_2v0_pldo_s3: dcdc-reg7 { 253 regulator-name = "vdd_2v0_pldo_s3"; 254 regulator-always-on; 255 regulator-boot-on; 256 regulator-min-microvolt = <2000000>; 257 regulator-max-microvolt = <2000000>; 258 regulator-ramp-delay = <12500>; 259 260 regulator-state-mem { 261 regulator-on-in-suspend; 262 regulator-suspend-microvolt = <2000000>; 263 }; 264 }; 265 266 vcc_3v3_s3: dcdc-reg8 { 267 regulator-name = "vcc_3v3_s3"; 268 regulator-always-on; 269 regulator-boot-on; 270 regulator-min-microvolt = <3300000>; 271 regulator-max-microvolt = <3300000>; 272 273 regulator-state-mem { 274 regulator-on-in-suspend; 275 regulator-suspend-microvolt = <3300000>; 276 }; 277 }; 278 }; 279 }; 280}; 281