1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 3/dts-v1/; 4 5#include <dt-bindings/clock/rockchip,rk3588-cru.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7 8#include "rk3588s.dtsi" 9#include "rk8xx.h" 10 11/ { 12 aliases { 13 mmc0 = &sdhci; 14 }; 15 16 /* Can't be verified due to missing schematics for the CM5. */ 17 vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { 18 compatible = "regulator-fixed"; 19 regulator-name = "vcc_1v1_nldo_s3"; 20 regulator-always-on; 21 regulator-boot-on; 22 regulator-min-microvolt = <1100000>; 23 regulator-max-microvolt = <1100000>; 24 vin-supply = <&vcc5v0_sys>; 25 }; 26}; 27 28&cpu_b0 { 29 cpu-supply = <&vdd_cpu_big0_s0>; 30}; 31 32&cpu_b1 { 33 cpu-supply = <&vdd_cpu_big0_s0>; 34}; 35 36&cpu_b2 { 37 cpu-supply = <&vdd_cpu_big1_s0>; 38}; 39 40&cpu_b3 { 41 cpu-supply = <&vdd_cpu_big1_s0>; 42}; 43 44&cpu_l0 { 45 cpu-supply = <&vdd_cpu_lit_s0>; 46}; 47 48&cpu_l1 { 49 cpu-supply = <&vdd_cpu_lit_s0>; 50}; 51 52&cpu_l2 { 53 cpu-supply = <&vdd_cpu_lit_s0>; 54}; 55 56&cpu_l3 { 57 cpu-supply = <&vdd_cpu_lit_s0>; 58}; 59 60&gpu { 61 mali-supply = <&vdd_gpu_s0>; 62 status = "okay"; 63}; 64 65&i2c0 { 66 pinctrl-0 = <&i2c0m2_xfer>; 67 status = "okay"; 68 69 vdd_cpu_big0_s0: regulator@42 { 70 compatible = "rockchip,rk8602"; 71 reg = <0x42>; 72 fcs,suspend-voltage-selector = <1>; 73 regulator-name = "vdd_cpu_big0_s0"; 74 regulator-always-on; 75 regulator-boot-on; 76 regulator-min-microvolt = <550000>; 77 regulator-max-microvolt = <1050000>; 78 regulator-ramp-delay = <2300>; 79 vin-supply = <&vcc5v0_sys>; 80 81 regulator-state-mem { 82 regulator-off-in-suspend; 83 }; 84 }; 85 86 vdd_cpu_big1_s0: regulator@43 { 87 compatible = "rockchip,rk8603", "rockchip,rk8602"; 88 reg = <0x43>; 89 fcs,suspend-voltage-selector = <1>; 90 regulator-name = "vdd_cpu_big1_s0"; 91 regulator-always-on; 92 regulator-boot-on; 93 regulator-min-microvolt = <550000>; 94 regulator-max-microvolt = <1050000>; 95 regulator-ramp-delay = <2300>; 96 vin-supply = <&vcc5v0_sys>; 97 98 regulator-state-mem { 99 regulator-off-in-suspend; 100 }; 101 }; 102}; 103 104&i2c2 { 105 status = "okay"; 106 107 vdd_npu_s0: regulator@42 { 108 compatible = "rockchip,rk8602"; 109 reg = <0x42>; 110 fcs,suspend-voltage-selector = <1>; 111 regulator-name = "vdd_npu_s0"; 112 regulator-always-on; 113 regulator-boot-on; 114 regulator-min-microvolt = <550000>; 115 regulator-max-microvolt = <950000>; 116 regulator-ramp-delay = <2300>; 117 vin-supply = <&vcc5v0_sys>; 118 119 regulator-state-mem { 120 regulator-off-in-suspend; 121 }; 122 }; 123}; 124 125&pd_gpu { 126 domain-supply = <&vdd_gpu_s0>; 127}; 128 129&sdhci { 130 bus-width = <8>; 131 no-sdio; 132 no-sd; 133 non-removable; 134 max-frequency = <200000000>; 135 mmc-hs400-1_8v; 136 mmc-hs400-enhanced-strobe; 137 status = "okay"; 138}; 139 140&spi2 { 141 assigned-clocks = <&cru CLK_SPI2>; 142 assigned-clock-rates = <200000000>; 143 num-cs = <1>; 144 pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; 145 status = "okay"; 146 147 pmic@0 { 148 compatible = "rockchip,rk806"; 149 reg = <0x0>; 150 interrupt-parent = <&gpio0>; 151 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 152 gpio-controller; 153 #gpio-cells = <2>; 154 pinctrl-names = "default"; 155 pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, 156 <&rk806_dvs2_null>, <&rk806_dvs3_null>; 157 spi-max-frequency = <1000000>; 158 system-power-controller; 159 rockchip,reset-mode = <RK806_RESET>; 160 161 vcc1-supply = <&vcc5v0_sys>; 162 vcc2-supply = <&vcc5v0_sys>; 163 vcc3-supply = <&vcc5v0_sys>; 164 vcc4-supply = <&vcc5v0_sys>; 165 vcc5-supply = <&vcc5v0_sys>; 166 vcc6-supply = <&vcc5v0_sys>; 167 vcc7-supply = <&vcc5v0_sys>; 168 vcc8-supply = <&vcc5v0_sys>; 169 vcc9-supply = <&vcc5v0_sys>; 170 vcc10-supply = <&vcc5v0_sys>; 171 vcc11-supply = <&vcc_2v0_pldo_s3>; 172 vcc12-supply = <&vcc5v0_sys>; 173 vcc13-supply = <&vcc_1v1_nldo_s3>; 174 vcc14-supply = <&vcc_1v1_nldo_s3>; 175 vcca-supply = <&vcc5v0_sys>; 176 177 rk806_dvs1_null: dvs1-null-pins { 178 pins = "gpio_pwrctrl1"; 179 function = "pin_fun0"; 180 }; 181 182 rk806_dvs2_null: dvs2-null-pins { 183 pins = "gpio_pwrctrl2"; 184 function = "pin_fun0"; 185 }; 186 187 rk806_dvs3_null: dvs3-null-pins { 188 pins = "gpio_pwrctrl3"; 189 function = "pin_fun0"; 190 }; 191 192 regulators { 193 vdd_gpu_s0: dcdc-reg1 { 194 regulator-name = "vdd_gpu_s0"; 195 regulator-boot-on; 196 regulator-min-microvolt = <550000>; 197 regulator-max-microvolt = <950000>; 198 regulator-ramp-delay = <12500>; 199 regulator-enable-ramp-delay = <400>; 200 201 regulator-state-mem { 202 regulator-off-in-suspend; 203 }; 204 }; 205 206 vdd_cpu_lit_s0: dcdc-reg2 { 207 regulator-name = "vdd_cpu_lit_s0"; 208 regulator-always-on; 209 regulator-boot-on; 210 regulator-min-microvolt = <550000>; 211 regulator-max-microvolt = <950000>; 212 regulator-ramp-delay = <12500>; 213 214 regulator-state-mem { 215 regulator-off-in-suspend; 216 }; 217 }; 218 219 vdd_log_s0: dcdc-reg3 { 220 regulator-name = "vdd_log_s0"; 221 regulator-always-on; 222 regulator-boot-on; 223 regulator-min-microvolt = <675000>; 224 regulator-max-microvolt = <750000>; 225 regulator-ramp-delay = <12500>; 226 227 regulator-state-mem { 228 regulator-off-in-suspend; 229 regulator-suspend-microvolt = <750000>; 230 }; 231 }; 232 233 vdd_vdenc_s0: dcdc-reg4 { 234 regulator-name = "vdd_vdenc_s0"; 235 regulator-always-on; 236 regulator-boot-on; 237 regulator-min-microvolt = <550000>; 238 regulator-max-microvolt = <950000>; 239 regulator-ramp-delay = <12500>; 240 241 regulator-state-mem { 242 regulator-off-in-suspend; 243 }; 244 }; 245 246 vdd_ddr_s0: dcdc-reg5 { 247 regulator-name = "vdd_ddr_s0"; 248 regulator-always-on; 249 regulator-boot-on; 250 regulator-min-microvolt = <675000>; 251 regulator-max-microvolt = <900000>; 252 regulator-ramp-delay = <12500>; 253 254 regulator-state-mem { 255 regulator-off-in-suspend; 256 regulator-suspend-microvolt = <850000>; 257 }; 258 }; 259 260 vdd2_ddr_s3: dcdc-reg6 { 261 regulator-name = "vdd2_ddr_s3"; 262 regulator-always-on; 263 regulator-boot-on; 264 regulator-max-microvolt = <1100000>; 265 regulator-min-microvolt = <1100000>; 266 267 regulator-state-mem { 268 regulator-on-in-suspend; 269 }; 270 }; 271 272 vcc_2v0_pldo_s3: dcdc-reg7 { 273 regulator-name = "vdd_2v0_pldo_s3"; 274 regulator-always-on; 275 regulator-boot-on; 276 regulator-min-microvolt = <2000000>; 277 regulator-max-microvolt = <2000000>; 278 279 regulator-state-mem { 280 regulator-on-in-suspend; 281 regulator-suspend-microvolt = <2000000>; 282 }; 283 }; 284 285 vcc_3v3_s3: dcdc-reg8 { 286 regulator-name = "vcc_3v3_s3"; 287 regulator-always-on; 288 regulator-boot-on; 289 regulator-min-microvolt = <3300000>; 290 regulator-max-microvolt = <3300000>; 291 292 regulator-state-mem { 293 regulator-on-in-suspend; 294 regulator-suspend-microvolt = <3300000>; 295 }; 296 }; 297 298 vddq_ddr_s0: dcdc-reg9 { 299 regulator-name = "vddq_ddr_s0"; 300 regulator-always-on; 301 regulator-boot-on; 302 303 regulator-state-mem { 304 regulator-off-in-suspend; 305 }; 306 }; 307 308 vcc_1v8_s3: dcdc-reg10 { 309 regulator-name = "vcc_1v8_s3"; 310 regulator-always-on; 311 regulator-boot-on; 312 regulator-min-microvolt = <1800000>; 313 regulator-max-microvolt = <1800000>; 314 315 regulator-state-mem { 316 regulator-on-in-suspend; 317 regulator-suspend-microvolt = <1800000>; 318 }; 319 }; 320 321 avcc_1v8_s0: pldo-reg1 { 322 regulator-name = "avcc_1v8_s0"; 323 regulator-always-on; 324 regulator-boot-on; 325 regulator-min-microvolt = <1800000>; 326 regulator-max-microvolt = <1800000>; 327 328 regulator-state-mem { 329 regulator-off-in-suspend; 330 }; 331 }; 332 333 vcc_1v8_s0: pldo-reg2 { 334 regulator-name = "vcc_1v8_s0"; 335 regulator-always-on; 336 regulator-boot-on; 337 regulator-min-microvolt = <1800000>; 338 regulator-max-microvolt = <1800000>; 339 340 regulator-state-mem { 341 regulator-off-in-suspend; 342 regulator-suspend-microvolt = <1800000>; 343 }; 344 }; 345 346 avdd_1v2_s0: pldo-reg3 { 347 regulator-name = "avdd_1v2_s0"; 348 regulator-always-on; 349 regulator-boot-on; 350 regulator-min-microvolt = <1200000>; 351 regulator-max-microvolt = <1200000>; 352 353 regulator-state-mem { 354 regulator-off-in-suspend; 355 }; 356 }; 357 358 vcc_3v3_s0: pldo-reg4 { 359 regulator-name = "vcc_3v3_s0"; 360 regulator-always-on; 361 regulator-boot-on; 362 regulator-min-microvolt = <3300000>; 363 regulator-max-microvolt = <3300000>; 364 365 regulator-state-mem { 366 regulator-off-in-suspend; 367 }; 368 }; 369 370 vccio_sd_s0: pldo-reg5 { 371 regulator-name = "vccio_sd_s0"; 372 regulator-always-on; 373 regulator-boot-on; 374 regulator-min-microvolt = <1800000>; 375 regulator-max-microvolt = <3300000>; 376 377 regulator-state-mem { 378 regulator-off-in-suspend; 379 }; 380 }; 381 382 pldo6_s3: pldo-reg6 { 383 regulator-name = "pldo6_s3"; 384 regulator-always-on; 385 regulator-boot-on; 386 regulator-min-microvolt = <1800000>; 387 regulator-max-microvolt = <1800000>; 388 389 regulator-state-mem { 390 regulator-on-in-suspend; 391 regulator-suspend-microvolt = <1800000>; 392 }; 393 }; 394 395 vdd_0v75_s3: nldo-reg1 { 396 regulator-name = "vdd_0v75_s3"; 397 regulator-always-on; 398 regulator-boot-on; 399 regulator-min-microvolt = <750000>; 400 regulator-max-microvolt = <750000>; 401 402 regulator-state-mem { 403 regulator-on-in-suspend; 404 regulator-suspend-microvolt = <750000>; 405 }; 406 }; 407 408 vdd_ddr_pll_s0: nldo-reg2 { 409 regulator-name = "vdd_ddr_pll_s0"; 410 regulator-always-on; 411 regulator-boot-on; 412 regulator-min-microvolt = <850000>; 413 regulator-max-microvolt = <850000>; 414 415 regulator-state-mem { 416 regulator-off-in-suspend; 417 regulator-suspend-microvolt = <850000>; 418 }; 419 }; 420 421 avdd_0v75_s0: nldo-reg3 { 422 regulator-name = "avdd_0v75_s0"; 423 regulator-always-on; 424 regulator-boot-on; 425 regulator-min-microvolt = <750000>; 426 regulator-max-microvolt = <750000>; 427 428 regulator-state-mem { 429 regulator-off-in-suspend; 430 }; 431 }; 432 433 vdd_0v85_s0: nldo-reg4 { 434 regulator-name = "vdd_0v85_s0"; 435 regulator-always-on; 436 regulator-boot-on; 437 regulator-min-microvolt = <850000>; 438 regulator-max-microvolt = <850000>; 439 440 regulator-state-mem { 441 regulator-off-in-suspend; 442 }; 443 }; 444 445 vdd_0v75_s0: nldo-reg5 { 446 regulator-name = "vdd_0v75_s0"; 447 regulator-always-on; 448 regulator-boot-on; 449 regulator-min-microvolt = <750000>; 450 regulator-max-microvolt = <750000>; 451 452 regulator-state-mem { 453 regulator-off-in-suspend; 454 }; 455 }; 456 }; 457 }; 458}; 459 460&tsadc { 461 /* 462 * The TSADC_SHUT pin is exposed to carrier boards as a signal named 463 * PMIC_RESET_L, meant to be driven externally. Reference carrier 464 * boards connect it to a reset button that pulls the signal to GND 465 * through a 100Ω resistor. This is too weak to overcome even the 466 * minimum drive strength of the TSADC_SHUT pin when driven in 467 * push-pull mode. Configure it as a GPIO, reset will be generated 468 * through the CRU. 469 */ 470 pinctrl-0 = <&tsadc_gpio_func>; 471 status = "okay"; 472}; 473