1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 * Copyright (c) 2024 Heiko Stuebner <heiko@sntech.de> 5 */ 6 7/dts-v1/; 8 9#include "rk3566.dtsi" 10#include "rk3568-qnap-tsx33.dtsi" 11 12/ { 13 model = "Qnap TS-133-2G NAS System 1-Bay"; 14 compatible = "qnap,ts133", "rockchip,rk3566"; 15 16 aliases { 17 ethernet0 = &gmac1; 18 }; 19}; 20 21&gmac1 { 22 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; 23 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; 24 assigned-clock-rates = <0>, <125000000>; 25 clock_in_out = "output"; 26 phy-handle = <&rgmii_phy0>; 27 phy-mode = "rgmii-id"; 28 pinctrl-names = "default"; 29 pinctrl-0 = <&gmac1m1_miim 30 &gmac1m1_tx_bus2 31 &gmac1m1_rx_bus2 32 &gmac1m1_rgmii_clk 33 &gmac1m1_rgmii_bus>; 34 status = "okay"; 35}; 36 37&mcu { 38 compatible = "qnap,ts133-mcu"; 39}; 40 41&mdio1 { 42 rgmii_phy0: ethernet-phy@3 { 43 /* Motorcomm YT8521 phy */ 44 compatible = "ethernet-phy-ieee802.3-c22"; 45 reg = <0x3>; 46 pinctrl-0 = <ð_phy0_reset_pin>; 47 pinctrl-names = "default"; 48 reset-assert-us = <10000>; 49 reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; 50 }; 51}; 52 53&pinctrl { 54 gmac1 { 55 eth_phy0_reset_pin: eth-phy0-reset-pin { 56 rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; 57 }; 58 }; 59}; 60 61/* connected to usb_host1_xhci */ 62&usb2phy0_host { 63 phy-supply = <&vcc5v0_otg>; 64 status = "okay"; 65}; 66 67/* USB3 port on backside */ 68&usb_host1_xhci { 69 dr_mode = "host"; 70 status = "okay"; 71}; 72