xref: /linux/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts (revision 115e74a29b530d121891238e9551c4bcdf7b04b5) 
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/V2N EVK board
4 *
5 * Copyright (C) 2025 Renesas Electronics Corp.
6 */
7
8/dts-v1/;
9
10#include <dt-bindings/gpio/gpio.h>
11#include "r9a09g056.dtsi"
12
13/ {
14	model = "Renesas RZ/V2N EVK Board based on r9a09g056n48";
15	compatible = "renesas,rzv2n-evk", "renesas,r9a09g056n48", "renesas,r9a09g056";
16
17	aliases {
18		ethernet0 = &eth0;
19		ethernet1 = &eth1;
20		i2c0 = &i2c0;
21		i2c1 = &i2c1;
22		i2c2 = &i2c2;
23		i2c3 = &i2c3;
24		i2c6 = &i2c6;
25		i2c7 = &i2c7;
26		i2c8 = &i2c8;
27		mmc1 = &sdhi1;
28		serial0 = &scif;
29	};
30
31	chosen {
32		bootargs = "ignore_loglevel";
33		stdout-path = "serial0:115200n8";
34	};
35
36	memory@48000000 {
37		device_type = "memory";
38		/* first 128MB is reserved for secure area. */
39		reg = <0x0 0x48000000 0x1 0xf8000000>;
40	};
41
42	reg_0p8v: regulator-0p8v {
43		compatible = "regulator-fixed";
44		regulator-name = "fixed-0.8V";
45		regulator-min-microvolt = <800000>;
46		regulator-max-microvolt = <800000>;
47		regulator-boot-on;
48		regulator-always-on;
49	};
50
51	reg_1p8v: regulator-1p8v {
52		compatible = "regulator-fixed";
53		regulator-name = "fixed-1.8V";
54		regulator-min-microvolt = <1800000>;
55		regulator-max-microvolt = <1800000>;
56		regulator-boot-on;
57		regulator-always-on;
58	};
59
60	reg_3p3v: regulator-3p3v {
61		compatible = "regulator-fixed";
62		regulator-name = "fixed-3.3V";
63		regulator-min-microvolt = <3300000>;
64		regulator-max-microvolt = <3300000>;
65		regulator-boot-on;
66		regulator-always-on;
67	};
68
69	vqmmc_sdhi1: regulator-vqmmc-sdhi1 {
70		compatible = "regulator-gpio";
71		regulator-name = "SDHI1 VqmmC";
72		gpios = <&pinctrl RZV2N_GPIO(A, 2) GPIO_ACTIVE_HIGH>;
73		regulator-min-microvolt = <1800000>;
74		regulator-max-microvolt = <3300000>;
75		gpios-states = <0>;
76		states = <3300000 0>, <1800000 1>;
77	};
78
79	/* 32.768kHz crystal */
80	x6: x6-clock {
81		compatible = "fixed-clock";
82		#clock-cells = <0>;
83		clock-frequency = <32768>;
84	};
85};
86
87&audio_extal_clk {
88	clock-frequency = <22579200>;
89};
90
91&ehci0 {
92	dr_mode = "otg";
93	status = "okay";
94};
95
96&eth0 {
97	pinctrl-0 = <&eth0_pins>;
98	pinctrl-names = "default";
99	phy-handle = <&phy0>;
100	phy-mode = "rgmii-id";
101	status = "okay";
102};
103
104&eth1 {
105	pinctrl-0 = <&eth1_pins>;
106	pinctrl-names = "default";
107	phy-handle = <&phy1>;
108	phy-mode = "rgmii-id";
109	status = "okay";
110};
111
112&gpu {
113	status = "okay";
114	mali-supply = <&reg_0p8v>;
115};
116
117&hsusb {
118	dr_mode = "otg";
119	status = "okay";
120};
121
122&i2c0 {
123	pinctrl-0 = <&i2c0_pins>;
124	pinctrl-names = "default";
125	clock-frequency = <400000>;
126	status = "okay";
127};
128
129&i2c1 {
130	pinctrl-0 = <&i2c1_pins>;
131	pinctrl-names = "default";
132	clock-frequency = <400000>;
133	status = "okay";
134};
135
136&i2c2 {
137	pinctrl-0 = <&i2c2_pins>;
138	pinctrl-names = "default";
139	clock-frequency = <400000>;
140	status = "okay";
141};
142
143&i2c3 {
144	pinctrl-0 = <&i2c3_pins>;
145	pinctrl-names = "default";
146	clock-frequency = <400000>;
147	status = "okay";
148};
149
150&i2c6 {
151	pinctrl-0 = <&i2c6_pins>;
152	pinctrl-names = "default";
153	clock-frequency = <400000>;
154	status = "okay";
155};
156
157&i2c7 {
158	pinctrl-0 = <&i2c7_pins>;
159	pinctrl-names = "default";
160	clock-frequency = <400000>;
161	status = "okay";
162};
163
164&i2c8 {
165	pinctrl-0 = <&i2c8_pins>;
166	pinctrl-names = "default";
167	clock-frequency = <400000>;
168	status = "okay";
169
170	raa215300: pmic@12 {
171		compatible = "renesas,raa215300";
172		reg = <0x12>, <0x6f>;
173		reg-names = "main", "rtc";
174		clocks = <&x6>;
175		clock-names = "xin";
176	};
177};
178
179&mdio0 {
180	phy0: ethernet-phy@0 {
181		compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22";
182		reg = <0>;
183		rxc-skew-psec = <0>;
184		txc-skew-psec = <0>;
185		rxdv-skew-psec = <0>;
186		txdv-skew-psec = <0>;
187		rxd0-skew-psec = <0>;
188		rxd1-skew-psec = <0>;
189		rxd2-skew-psec = <0>;
190		rxd3-skew-psec = <0>;
191		txd0-skew-psec = <0>;
192		txd1-skew-psec = <0>;
193		txd2-skew-psec = <0>;
194		txd3-skew-psec = <0>;
195	};
196};
197
198&mdio1 {
199	phy1: ethernet-phy@1 {
200		compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22";
201		reg = <0>;
202		rxc-skew-psec = <0>;
203		txc-skew-psec = <0>;
204		rxdv-skew-psec = <0>;
205		txdv-skew-psec = <0>;
206		rxd0-skew-psec = <0>;
207		rxd1-skew-psec = <0>;
208		rxd2-skew-psec = <0>;
209		rxd3-skew-psec = <0>;
210		txd0-skew-psec = <0>;
211		txd1-skew-psec = <0>;
212		txd2-skew-psec = <0>;
213		txd3-skew-psec = <0>;
214	};
215};
216
217&ohci0 {
218	dr_mode = "otg";
219	status = "okay";
220};
221
222&ostm0 {
223	status = "okay";
224};
225
226&ostm1 {
227	status = "okay";
228};
229
230&ostm2 {
231	status = "okay";
232};
233
234&ostm3 {
235	status = "okay";
236};
237
238&ostm4 {
239	status = "okay";
240};
241
242&ostm5 {
243	status = "okay";
244};
245
246&ostm6 {
247	status = "okay";
248};
249
250&ostm7 {
251	status = "okay";
252};
253
254&pinctrl {
255	eth0_pins: eth0 {
256		pins = "ET0_TXC_TXCLK";
257		output-enable;
258	};
259
260	eth1_pins: eth1 {
261		pins = "ET1_TXC_TXCLK";
262		output-enable;
263	};
264
265	i2c0_pins: i2c0 {
266		pinmux = <RZV2N_PORT_PINMUX(3, 0, 1)>, /* I2C0_SDA */
267			 <RZV2N_PORT_PINMUX(3, 1, 1)>; /* I2C0_SCL */
268	};
269
270	i2c1_pins: i2c1 {
271		pinmux = <RZV2N_PORT_PINMUX(3, 2, 1)>, /* I2C1_SDA */
272			 <RZV2N_PORT_PINMUX(3, 3, 1)>; /* I2C1_SCL */
273	};
274
275	i2c2_pins: i2c2 {
276		pinmux = <RZV2N_PORT_PINMUX(2, 0, 4)>, /* I2C2_SDA */
277			 <RZV2N_PORT_PINMUX(2, 1, 4)>; /* I2C2_SCL */
278	};
279
280	i2c3_pins: i2c3 {
281		pinmux = <RZV2N_PORT_PINMUX(3, 6, 1)>, /* I2C3_SDA */
282			 <RZV2N_PORT_PINMUX(3, 7, 1)>; /* I2C3_SCL */
283	};
284
285	i2c6_pins: i2c6 {
286		pinmux = <RZV2N_PORT_PINMUX(4, 4, 1)>, /* I2C6_SDA */
287			 <RZV2N_PORT_PINMUX(4, 5, 1)>; /* I2C6_SCL */
288		/* There are no pull-up resistors on the EVK, so enable the internal pull-up */
289		bias-pull-up;
290	};
291
292	i2c7_pins: i2c7 {
293		pinmux = <RZV2N_PORT_PINMUX(4, 6, 1)>, /* I2C7_SDA */
294			 <RZV2N_PORT_PINMUX(4, 7, 1)>; /* I2C7_SCL */
295		/* There are no pull-up resistors on the EVK, so enable the internal pull-up */
296		bias-pull-up;
297	};
298
299	i2c8_pins: i2c8 {
300		pinmux = <RZV2N_PORT_PINMUX(0, 6, 1)>, /* I2C8_SDA */
301			 <RZV2N_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */
302	};
303
304	scif_pins: scif {
305		pins = "SCIF_TXD", "SCIF_RXD";
306		renesas,output-impedance = <1>;
307	};
308
309	sd1-pwr-en-hog {
310		gpio-hog;
311		gpios = <RZV2N_GPIO(A, 3) GPIO_ACTIVE_HIGH>;
312		output-high;
313		line-name = "sd1_pwr_en";
314	};
315
316	sdhi1_pins: sd1 {
317		sd1-cd {
318			pinmux = <RZV2N_PORT_PINMUX(9, 4, 14)>; /* SD1_CD */
319		};
320
321		sd1-clk {
322			pins = "SD1CLK";
323			renesas,output-impedance = <3>;
324			slew-rate = <0>;
325		};
326
327		sd1-dat-cmd {
328			pins = "SD1DAT0", "SD1DAT1", "SD1DAT2", "SD1DAT3", "SD1CMD";
329			input-enable;
330			renesas,output-impedance = <3>;
331			slew-rate = <0>;
332		};
333	};
334
335	usb20_pins: usb20 {
336		ovc {
337			pinmux =  <RZV2N_PORT_PINMUX(9, 6, 14)>; /* OVC */
338		};
339
340		vbus {
341			pinmux = <RZV2N_PORT_PINMUX(9, 5, 14)>; /* VBUS */
342		};
343	};
344
345	xspi_pins: xspi0 {
346		ctrl {
347			pins = "XSPI0_RESET0N", "XSPI0_CS0N", "XSPI0_CKP";
348			output-enable;
349		};
350
351		io {
352			pins = "XSPI0_IO0", "XSPI0_IO1", "XSPI0_IO2", "XSPI0_IO3";
353			renesas,output-impedance = <3>;
354		};
355	};
356};
357
358&qextal_clk {
359	clock-frequency = <24000000>;
360};
361
362&rtxin_clk {
363	clock-frequency = <32768>;
364};
365
366&scif {
367	pinctrl-0 = <&scif_pins>;
368	pinctrl-names = "default";
369	status = "okay";
370};
371
372&sdhi1 {
373	pinctrl-0 = <&sdhi1_pins>;
374	pinctrl-1 = <&sdhi1_pins>;
375	pinctrl-names = "default", "state_uhs";
376	vmmc-supply = <&reg_3p3v>;
377	vqmmc-supply = <&vqmmc_sdhi1>;
378	bus-width = <4>;
379	sd-uhs-sdr50;
380	sd-uhs-sdr104;
381	status = "okay";
382};
383
384&usb20phyrst {
385	status = "okay";
386};
387
388&usb2_phy0 {
389	pinctrl-0 = <&usb20_pins>;
390	pinctrl-names = "default";
391
392	status = "okay";
393};
394
395&wdt1 {
396	status = "okay";
397};
398
399&xspi {
400	pinctrl-0 = <&xspi_pins>;
401	pinctrl-names = "default";
402	/*
403	 * MT25QU512ABB8E12 flash chip is capable of running at 166MHz
404	 * clock frequency. Set the clock frequency to the maximum 133MHz
405	 * supported by the RZ/V2N SoC.
406	 */
407	assigned-clocks = <&cpg CPG_CORE R9A09G056_SPI_CLK_SPI>;
408	assigned-clock-rates = <133333334>;
409	status = "okay";
410
411	flash@0 {
412		compatible = "jedec,spi-nor";
413		reg = <0>;
414		vcc-supply = <&reg_1p8v>;
415		m25p,fast-read;
416		spi-tx-bus-width = <4>;
417		spi-rx-bus-width = <4>;
418
419		partitions {
420			compatible = "fixed-partitions";
421			#address-cells = <1>;
422			#size-cells = <1>;
423
424			partition@0 {
425				label = "bl2";
426				reg = <0x00000000 0x00060000>;
427			};
428
429			partition@60000 {
430				label = "fip";
431				reg = <0x00060000 0x1fa0000>;
432			};
433
434			partition@2000000 {
435				label = "user";
436				reg = <0x2000000 0x2000000>;
437			};
438		};
439	};
440};
441