1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/V2N SoC 4 * 5 * Copyright (C) 2025 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g056-cpg.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 11 12/* RZV2N_Px = Offset address of PFC_P_mn - 0x20 */ 13#define RZV2N_P0 0 14#define RZV2N_P1 1 15#define RZV2N_P2 2 16#define RZV2N_P3 3 17#define RZV2N_P4 4 18#define RZV2N_P5 5 19#define RZV2N_P6 6 20#define RZV2N_P7 7 21#define RZV2N_P8 8 22#define RZV2N_P9 9 23#define RZV2N_PA 10 24#define RZV2N_PB 11 25 26#define RZV2N_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZV2N_P##b, p, f) 27#define RZV2N_GPIO(port, pin) RZG2L_GPIO(RZV2N_P##port, pin) 28 29/ { 30 compatible = "renesas,r9a09g056"; 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 audio_extal_clk: audio-clk { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 /* This value must be overridden by the board */ 38 clock-frequency = <0>; 39 }; 40 41 /* 42 * The default cluster table is based on the assumption that the PLLCA55 clock 43 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to 44 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be 45 * clocked to 1.8GHz as well). The table below should be overridden in the board 46 * DTS based on the PLLCA55 clock frequency. 47 */ 48 cluster0_opp: opp-table-0 { 49 compatible = "operating-points-v2"; 50 51 opp-1700000000 { 52 opp-hz = /bits/ 64 <1700000000>; 53 opp-microvolt = <900000>; 54 clock-latency-ns = <300000>; 55 }; 56 opp-850000000 { 57 opp-hz = /bits/ 64 <850000000>; 58 opp-microvolt = <800000>; 59 clock-latency-ns = <300000>; 60 }; 61 opp-425000000 { 62 opp-hz = /bits/ 64 <425000000>; 63 opp-microvolt = <800000>; 64 clock-latency-ns = <300000>; 65 }; 66 opp-212500000 { 67 opp-hz = /bits/ 64 <212500000>; 68 opp-microvolt = <800000>; 69 clock-latency-ns = <300000>; 70 opp-suspend; 71 }; 72 }; 73 74 cpus { 75 #address-cells = <1>; 76 #size-cells = <0>; 77 78 cpu0: cpu@0 { 79 compatible = "arm,cortex-a55"; 80 reg = <0>; 81 device_type = "cpu"; 82 next-level-cache = <&L3_CA55>; 83 enable-method = "psci"; 84 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK0>; 85 operating-points-v2 = <&cluster0_opp>; 86 }; 87 88 cpu1: cpu@100 { 89 compatible = "arm,cortex-a55"; 90 reg = <0x100>; 91 device_type = "cpu"; 92 next-level-cache = <&L3_CA55>; 93 enable-method = "psci"; 94 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK1>; 95 operating-points-v2 = <&cluster0_opp>; 96 }; 97 98 cpu2: cpu@200 { 99 compatible = "arm,cortex-a55"; 100 reg = <0x200>; 101 device_type = "cpu"; 102 next-level-cache = <&L3_CA55>; 103 enable-method = "psci"; 104 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK2>; 105 operating-points-v2 = <&cluster0_opp>; 106 }; 107 108 cpu3: cpu@300 { 109 compatible = "arm,cortex-a55"; 110 reg = <0x300>; 111 device_type = "cpu"; 112 next-level-cache = <&L3_CA55>; 113 enable-method = "psci"; 114 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK3>; 115 operating-points-v2 = <&cluster0_opp>; 116 }; 117 118 L3_CA55: cache-controller-0 { 119 compatible = "cache"; 120 cache-unified; 121 cache-size = <0x100000>; 122 cache-level = <3>; 123 }; 124 }; 125 126 gpu_opp_table: opp-table-1 { 127 compatible = "operating-points-v2"; 128 129 opp-630000000 { 130 opp-hz = /bits/ 64 <630000000>; 131 opp-microvolt = <800000>; 132 }; 133 134 opp-315000000 { 135 opp-hz = /bits/ 64 <315000000>; 136 opp-microvolt = <800000>; 137 }; 138 139 opp-157500000 { 140 opp-hz = /bits/ 64 <157500000>; 141 opp-microvolt = <800000>; 142 }; 143 144 opp-78750000 { 145 opp-hz = /bits/ 64 <78750000>; 146 opp-microvolt = <800000>; 147 }; 148 149 opp-19687500 { 150 opp-hz = /bits/ 64 <19687500>; 151 opp-microvolt = <800000>; 152 }; 153 }; 154 155 psci { 156 compatible = "arm,psci-1.0", "arm,psci-0.2"; 157 method = "smc"; 158 }; 159 160 qextal_clk: qextal-clk { 161 compatible = "fixed-clock"; 162 #clock-cells = <0>; 163 /* This value must be overridden by the board */ 164 clock-frequency = <0>; 165 }; 166 167 rtxin_clk: rtxin-clk { 168 compatible = "fixed-clock"; 169 #clock-cells = <0>; 170 /* This value must be overridden by the board */ 171 clock-frequency = <0>; 172 }; 173 174 soc: soc { 175 compatible = "simple-bus"; 176 interrupt-parent = <&gic>; 177 #address-cells = <2>; 178 #size-cells = <2>; 179 ranges; 180 181 pinctrl: pinctrl@10410000 { 182 compatible = "renesas,r9a09g056-pinctrl"; 183 reg = <0 0x10410000 0 0x10000>; 184 clocks = <&cpg CPG_CORE R9A09G056_IOTOP_0_SHCLK>; 185 gpio-controller; 186 #gpio-cells = <2>; 187 gpio-ranges = <&pinctrl 0 0 96>; 188 power-domains = <&cpg>; 189 resets = <&cpg 0xa5>, <&cpg 0xa6>; 190 }; 191 192 cpg: clock-controller@10420000 { 193 compatible = "renesas,r9a09g056-cpg"; 194 reg = <0 0x10420000 0 0x10000>; 195 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; 196 clock-names = "audio_extal", "rtxin", "qextal"; 197 #clock-cells = <2>; 198 #reset-cells = <1>; 199 #power-domain-cells = <0>; 200 }; 201 202 sys: system-controller@10430000 { 203 compatible = "renesas,r9a09g056-sys"; 204 reg = <0 0x10430000 0 0x10000>; 205 clocks = <&cpg CPG_CORE R9A09G056_SYS_0_PCLK>; 206 resets = <&cpg 0x30>; 207 }; 208 209 xspi: spi@11030000 { 210 compatible = "renesas,r9a09g056-xspi", "renesas,r9a09g047-xspi"; 211 reg = <0 0x11030000 0 0x10000>, 212 <0 0x20000000 0 0x10000000>; 213 reg-names = "regs", "dirmap"; 214 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, 215 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>; 216 interrupt-names = "pulse", "err_pulse"; 217 clocks = <&cpg CPG_MOD 0x9f>, 218 <&cpg CPG_MOD 0xa0>, 219 <&cpg CPG_CORE R9A09G056_SPI_CLK_SPI>, 220 <&cpg CPG_MOD 0xa1>; 221 clock-names = "ahb", "axi", "spi", "spix2"; 222 resets = <&cpg 0xa3>, <&cpg 0xa4>; 223 reset-names = "hresetn", "aresetn"; 224 power-domains = <&cpg>; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 status = "disabled"; 228 }; 229 230 ostm0: timer@11800000 { 231 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 232 reg = <0x0 0x11800000 0x0 0x1000>; 233 interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>; 234 clocks = <&cpg CPG_MOD 0x43>; 235 resets = <&cpg 0x6d>; 236 power-domains = <&cpg>; 237 status = "disabled"; 238 }; 239 240 ostm1: timer@11801000 { 241 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 242 reg = <0x0 0x11801000 0x0 0x1000>; 243 interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>; 244 clocks = <&cpg CPG_MOD 0x44>; 245 resets = <&cpg 0x6e>; 246 power-domains = <&cpg>; 247 status = "disabled"; 248 }; 249 250 ostm2: timer@14000000 { 251 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 252 reg = <0x0 0x14000000 0x0 0x1000>; 253 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>; 254 clocks = <&cpg CPG_MOD 0x45>; 255 resets = <&cpg 0x6f>; 256 power-domains = <&cpg>; 257 status = "disabled"; 258 }; 259 260 ostm3: timer@14001000 { 261 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 262 reg = <0x0 0x14001000 0x0 0x1000>; 263 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>; 264 clocks = <&cpg CPG_MOD 0x46>; 265 resets = <&cpg 0x70>; 266 power-domains = <&cpg>; 267 status = "disabled"; 268 }; 269 270 ostm4: timer@12c00000 { 271 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 272 reg = <0x0 0x12c00000 0x0 0x1000>; 273 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 274 clocks = <&cpg CPG_MOD 0x47>; 275 resets = <&cpg 0x71>; 276 power-domains = <&cpg>; 277 status = "disabled"; 278 }; 279 280 ostm5: timer@12c01000 { 281 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 282 reg = <0x0 0x12c01000 0x0 0x1000>; 283 interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 284 clocks = <&cpg CPG_MOD 0x48>; 285 resets = <&cpg 0x72>; 286 power-domains = <&cpg>; 287 status = "disabled"; 288 }; 289 290 ostm6: timer@12c02000 { 291 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 292 reg = <0x0 0x12c02000 0x0 0x1000>; 293 interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; 294 clocks = <&cpg CPG_MOD 0x49>; 295 resets = <&cpg 0x73>; 296 power-domains = <&cpg>; 297 status = "disabled"; 298 }; 299 300 ostm7: timer@12c03000 { 301 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 302 reg = <0x0 0x12c03000 0x0 0x1000>; 303 interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>; 304 clocks = <&cpg CPG_MOD 0x4a>; 305 resets = <&cpg 0x74>; 306 power-domains = <&cpg>; 307 status = "disabled"; 308 }; 309 310 wdt0: watchdog@11c00400 { 311 compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt"; 312 reg = <0 0x11c00400 0 0x400>; 313 clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>; 314 clock-names = "pclk", "oscclk"; 315 resets = <&cpg 0x75>; 316 power-domains = <&cpg>; 317 status = "disabled"; 318 }; 319 320 wdt1: watchdog@14400000 { 321 compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt"; 322 reg = <0 0x14400000 0 0x400>; 323 clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; 324 clock-names = "pclk", "oscclk"; 325 resets = <&cpg 0x76>; 326 power-domains = <&cpg>; 327 status = "disabled"; 328 }; 329 330 wdt2: watchdog@13000000 { 331 compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt"; 332 reg = <0 0x13000000 0 0x400>; 333 clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>; 334 clock-names = "pclk", "oscclk"; 335 resets = <&cpg 0x77>; 336 power-domains = <&cpg>; 337 status = "disabled"; 338 }; 339 340 wdt3: watchdog@13000400 { 341 compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt"; 342 reg = <0 0x13000400 0 0x400>; 343 clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>; 344 clock-names = "pclk", "oscclk"; 345 resets = <&cpg 0x78>; 346 power-domains = <&cpg>; 347 status = "disabled"; 348 }; 349 350 scif: serial@11c01400 { 351 compatible = "renesas,scif-r9a09g056", 352 "renesas,scif-r9a09g057"; 353 reg = <0 0x11c01400 0 0x400>; 354 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, 362 <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; 363 interrupt-names = "eri", "rxi", "txi", "bri", "dri", 364 "tei", "tei-dri", "rxi-edge", "txi-edge"; 365 clocks = <&cpg CPG_MOD 0x8f>; 366 clock-names = "fck"; 367 power-domains = <&cpg>; 368 resets = <&cpg 0x95>; 369 status = "disabled"; 370 }; 371 372 i3c: i3c@12400000 { 373 compatible = "renesas,r9a09g056-i3c", "renesas,r9a09g047-i3c"; 374 reg = <0 0x12400000 0 0x10000>; 375 clocks = <&cpg CPG_MOD 0x91>, <&cpg CPG_MOD 0x92>, <&cpg CPG_MOD 0x90>; 376 clock-names = "pclk", "tclk", "pclkrw"; 377 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 677 IRQ_TYPE_EDGE_RISING>, 381 <GIC_SPI 678 IRQ_TYPE_EDGE_RISING>, 382 <GIC_SPI 679 IRQ_TYPE_EDGE_RISING>, 383 <GIC_SPI 680 IRQ_TYPE_EDGE_RISING>, 384 <GIC_SPI 681 IRQ_TYPE_EDGE_RISING>, 385 <GIC_SPI 682 IRQ_TYPE_EDGE_RISING>, 386 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 393 interrupt-names = "ierr", "terr", "abort", "resp", 394 "cmd", "ibi", "rx", "tx", "rcv", 395 "st", "sp", "tend", "nack", 396 "al", "tmo", "wu"; 397 resets = <&cpg 0x96>, <&cpg 0x97>; 398 reset-names = "presetn", "tresetn"; 399 power-domains = <&cpg>; 400 #address-cells = <3>; 401 #size-cells = <0>; 402 status = "disabled"; 403 }; 404 405 i2c0: i2c@14400400 { 406 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 407 reg = <0 0x14400400 0 0x400>; 408 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, 410 <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>, 411 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 416 interrupt-names = "tei", "ri", "ti", "spi", "sti", 417 "naki", "ali", "tmoi"; 418 clocks = <&cpg CPG_MOD 0x94>; 419 resets = <&cpg 0x98>; 420 power-domains = <&cpg>; 421 #address-cells = <1>; 422 #size-cells = <0>; 423 status = "disabled"; 424 }; 425 426 i2c1: i2c@14400800 { 427 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 428 reg = <0 0x14400800 0 0x400>; 429 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>, 431 <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, 432 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 437 interrupt-names = "tei", "ri", "ti", "spi", "sti", 438 "naki", "ali", "tmoi"; 439 clocks = <&cpg CPG_MOD 0x95>; 440 resets = <&cpg 0x99>; 441 power-domains = <&cpg>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 status = "disabled"; 445 }; 446 447 i2c2: i2c@14400c00 { 448 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 449 reg = <0 0x14400c00 0 0x400>; 450 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>, 452 <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>, 453 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 458 interrupt-names = "tei", "ri", "ti", "spi", "sti", 459 "naki", "ali", "tmoi"; 460 clocks = <&cpg CPG_MOD 0x96>; 461 resets = <&cpg 0x9a>; 462 power-domains = <&cpg>; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 status = "disabled"; 466 }; 467 468 i2c3: i2c@14401000 { 469 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 470 reg = <0 0x14401000 0 0x400>; 471 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>, 473 <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>, 474 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 479 interrupt-names = "tei", "ri", "ti", "spi", "sti", 480 "naki", "ali", "tmoi"; 481 clocks = <&cpg CPG_MOD 0x97>; 482 resets = <&cpg 0x9b>; 483 power-domains = <&cpg>; 484 #address-cells = <1>; 485 #size-cells = <0>; 486 status = "disabled"; 487 }; 488 489 i2c4: i2c@14401400 { 490 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 491 reg = <0 0x14401400 0 0x400>; 492 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>, 494 <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>, 495 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 500 interrupt-names = "tei", "ri", "ti", "spi", "sti", 501 "naki", "ali", "tmoi"; 502 clocks = <&cpg CPG_MOD 0x98>; 503 resets = <&cpg 0x9c>; 504 power-domains = <&cpg>; 505 #address-cells = <1>; 506 #size-cells = <0>; 507 status = "disabled"; 508 }; 509 510 i2c5: i2c@14401800 { 511 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 512 reg = <0 0x14401800 0 0x400>; 513 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>, 515 <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>, 516 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 521 interrupt-names = "tei", "ri", "ti", "spi", "sti", 522 "naki", "ali", "tmoi"; 523 clocks = <&cpg CPG_MOD 0x99>; 524 resets = <&cpg 0x9d>; 525 power-domains = <&cpg>; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 status = "disabled"; 529 }; 530 531 i2c6: i2c@14401c00 { 532 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 533 reg = <0 0x14401c00 0 0x400>; 534 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>, 536 <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, 537 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 542 interrupt-names = "tei", "ri", "ti", "spi", "sti", 543 "naki", "ali", "tmoi"; 544 clocks = <&cpg CPG_MOD 0x9a>; 545 resets = <&cpg 0x9e>; 546 power-domains = <&cpg>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 status = "disabled"; 550 }; 551 552 i2c7: i2c@14402000 { 553 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 554 reg = <0 0x14402000 0 0x400>; 555 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>, 557 <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>, 558 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 563 interrupt-names = "tei", "ri", "ti", "spi", "sti", 564 "naki", "ali", "tmoi"; 565 clocks = <&cpg CPG_MOD 0x9b>; 566 resets = <&cpg 0x9f>; 567 power-domains = <&cpg>; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 status = "disabled"; 571 }; 572 573 i2c8: i2c@11c01000 { 574 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 575 reg = <0 0x11c01000 0 0x400>; 576 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>, 578 <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>, 579 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 584 interrupt-names = "tei", "ri", "ti", "spi", "sti", 585 "naki", "ali", "tmoi"; 586 clocks = <&cpg CPG_MOD 0x93>; 587 resets = <&cpg 0xa0>; 588 power-domains = <&cpg>; 589 #address-cells = <1>; 590 #size-cells = <0>; 591 status = "disabled"; 592 }; 593 594 gpu: gpu@14850000 { 595 compatible = "renesas,r9a09g056-mali", 596 "arm,mali-bifrost"; 597 reg = <0x0 0x14850000 0x0 0x10000>; 598 interrupts = <GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>; 602 interrupt-names = "job", "mmu", "gpu", "event"; 603 clocks = <&cpg CPG_MOD 0xf0>, 604 <&cpg CPG_MOD 0xf1>, 605 <&cpg CPG_MOD 0xf2>; 606 clock-names = "gpu", "bus", "bus_ace"; 607 resets = <&cpg 0xdd>, 608 <&cpg 0xde>, 609 <&cpg 0xdf>; 610 reset-names = "rst", "axi_rst", "ace_rst"; 611 power-domains = <&cpg>; 612 operating-points-v2 = <&gpu_opp_table>; 613 status = "disabled"; 614 }; 615 616 gic: interrupt-controller@14900000 { 617 compatible = "arm,gic-v3"; 618 reg = <0x0 0x14900000 0 0x20000>, 619 <0x0 0x14940000 0 0x80000>; 620 #interrupt-cells = <3>; 621 #address-cells = <0>; 622 interrupt-controller; 623 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 624 }; 625 626 ohci0: usb@15800000 { 627 compatible = "generic-ohci"; 628 reg = <0 0x15800000 0 0x100>; 629 interrupts = <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>; 631 resets = <&usb20phyrst>, <&cpg 0xac>; 632 phys = <&usb2_phy0 1>; 633 phy-names = "usb"; 634 power-domains = <&cpg>; 635 status = "disabled"; 636 }; 637 638 ehci0: usb@15800100 { 639 compatible = "generic-ehci"; 640 reg = <0 0x15800100 0 0x100>; 641 interrupts = <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>; 643 resets = <&usb20phyrst>, <&cpg 0xac>; 644 phys = <&usb2_phy0 2>; 645 phy-names = "usb"; 646 companion = <&ohci0>; 647 power-domains = <&cpg>; 648 status = "disabled"; 649 }; 650 651 usb2_phy0: usb-phy@15800200 { 652 compatible = "renesas,usb2-phy-r9a09g056", "renesas,usb2-phy-r9a09g057"; 653 reg = <0 0x15800200 0 0x700>; 654 interrupts = <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>; 655 clocks = <&cpg CPG_MOD 0xb3>, 656 <&cpg CPG_CORE R9A09G056_USB2_0_CLK_CORE0>; 657 clock-names = "fck", "usb_x1"; 658 resets = <&usb20phyrst>; 659 #phy-cells = <1>; 660 power-domains = <&cpg>; 661 status = "disabled"; 662 }; 663 664 hsusb: usb@15820000 { 665 compatible = "renesas,usbhs-r9a09g056", 666 "renesas,rzg2l-usbhs"; 667 reg = <0 0x15820000 0 0x10000>; 668 interrupts = <GIC_SPI 751 IRQ_TYPE_EDGE_RISING>, 669 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb5>; 673 resets = <&usb20phyrst>, 674 <&cpg 0xae>; 675 phys = <&usb2_phy0 3>; 676 phy-names = "usb"; 677 power-domains = <&cpg>; 678 status = "disabled"; 679 }; 680 681 usb20phyrst: usb20phy-reset@15830000 { 682 compatible = "renesas,r9a09g056-usb2phy-reset", 683 "renesas,r9a09g057-usb2phy-reset"; 684 reg = <0 0x15830000 0 0x10000>; 685 clocks = <&cpg CPG_MOD 0xb6>; 686 resets = <&cpg 0xaf>; 687 power-domains = <&cpg>; 688 #reset-cells = <0>; 689 status = "disabled"; 690 }; 691 692 sdhi0: mmc@15c00000 { 693 compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057"; 694 reg = <0x0 0x15c00000 0 0x10000>; 695 interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, 698 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; 699 clock-names = "core", "clkh", "cd", "aclk"; 700 resets = <&cpg 0xa7>; 701 power-domains = <&cpg>; 702 status = "disabled"; 703 704 sdhi0_vqmmc: vqmmc-regulator { 705 regulator-name = "SDHI0-VQMMC"; 706 regulator-min-microvolt = <1800000>; 707 regulator-max-microvolt = <3300000>; 708 status = "disabled"; 709 }; 710 }; 711 712 sdhi1: mmc@15c10000 { 713 compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057"; 714 reg = <0x0 0x15c10000 0 0x10000>; 715 interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, 718 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; 719 clock-names = "core", "clkh", "cd", "aclk"; 720 resets = <&cpg 0xa8>; 721 power-domains = <&cpg>; 722 status = "disabled"; 723 724 sdhi1_vqmmc: vqmmc-regulator { 725 regulator-name = "SDHI1-VQMMC"; 726 regulator-min-microvolt = <1800000>; 727 regulator-max-microvolt = <3300000>; 728 status = "disabled"; 729 }; 730 }; 731 732 sdhi2: mmc@15c20000 { 733 compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057"; 734 reg = <0x0 0x15c20000 0 0x10000>; 735 interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, 738 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; 739 clock-names = "core", "clkh", "cd", "aclk"; 740 resets = <&cpg 0xa9>; 741 power-domains = <&cpg>; 742 status = "disabled"; 743 744 sdhi2_vqmmc: vqmmc-regulator { 745 regulator-name = "SDHI2-VQMMC"; 746 regulator-min-microvolt = <1800000>; 747 regulator-max-microvolt = <3300000>; 748 status = "disabled"; 749 }; 750 }; 751 752 eth0: ethernet@15c30000 { 753 compatible = "renesas,r9a09g056-gbeth", "renesas,rzv2h-gbeth", 754 "snps,dwmac-5.20"; 755 reg = <0 0x15c30000 0 0x10000>; 756 interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>; 767 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 768 "rx-queue-0", "rx-queue-1", "rx-queue-2", 769 "rx-queue-3", "tx-queue-0", "tx-queue-1", 770 "tx-queue-2", "tx-queue-3"; 771 clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, 772 <&cpg CPG_CORE R9A09G056_GBETH_0_CLK_PTP_REF_I>, 773 <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, 774 <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; 775 clock-names = "stmmaceth", "pclk", "ptp_ref", 776 "tx", "rx", "tx-180", "rx-180"; 777 resets = <&cpg 0xb0>; 778 power-domains = <&cpg>; 779 snps,multicast-filter-bins = <256>; 780 snps,perfect-filter-entries = <128>; 781 rx-fifo-depth = <8192>; 782 tx-fifo-depth = <8192>; 783 snps,fixed-burst; 784 snps,no-pbl-x8; 785 snps,force_thresh_dma_mode; 786 snps,axi-config = <&stmmac_axi_setup>; 787 snps,mtl-rx-config = <&mtl_rx_setup0>; 788 snps,mtl-tx-config = <&mtl_tx_setup0>; 789 snps,txpbl = <32>; 790 snps,rxpbl = <32>; 791 status = "disabled"; 792 793 mdio0: mdio { 794 compatible = "snps,dwmac-mdio"; 795 #address-cells = <1>; 796 #size-cells = <0>; 797 }; 798 799 mtl_rx_setup0: rx-queues-config { 800 snps,rx-queues-to-use = <4>; 801 snps,rx-sched-sp; 802 803 queue0 { 804 snps,dcb-algorithm; 805 snps,priority = <0x1>; 806 snps,map-to-dma-channel = <0>; 807 }; 808 809 queue1 { 810 snps,dcb-algorithm; 811 snps,priority = <0x2>; 812 snps,map-to-dma-channel = <1>; 813 }; 814 815 queue2 { 816 snps,dcb-algorithm; 817 snps,priority = <0x4>; 818 snps,map-to-dma-channel = <2>; 819 }; 820 821 queue3 { 822 snps,dcb-algorithm; 823 snps,priority = <0x8>; 824 snps,map-to-dma-channel = <3>; 825 }; 826 }; 827 828 mtl_tx_setup0: tx-queues-config { 829 snps,tx-queues-to-use = <4>; 830 831 queue0 { 832 snps,dcb-algorithm; 833 snps,priority = <0x1>; 834 }; 835 836 queue1 { 837 snps,dcb-algorithm; 838 snps,priority = <0x2>; 839 }; 840 841 queue2 { 842 snps,dcb-algorithm; 843 snps,priority = <0x4>; 844 }; 845 846 queue3 { 847 snps,dcb-algorithm; 848 snps,priority = <0x8>; 849 }; 850 }; 851 }; 852 853 eth1: ethernet@15c40000 { 854 compatible = "renesas,r9a09g056-gbeth", "renesas,rzv2h-gbeth", 855 "snps,dwmac-5.20"; 856 reg = <0 0x15c40000 0 0x10000>; 857 interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>; 868 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 869 "rx-queue-0", "rx-queue-1", "rx-queue-2", 870 "rx-queue-3", "tx-queue-0", "tx-queue-1", 871 "tx-queue-2", "tx-queue-3"; 872 clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, 873 <&cpg CPG_CORE R9A09G056_GBETH_1_CLK_PTP_REF_I>, 874 <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, 875 <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; 876 clock-names = "stmmaceth", "pclk", "ptp_ref", 877 "tx", "rx", "tx-180", "rx-180"; 878 resets = <&cpg 0xb1>; 879 power-domains = <&cpg>; 880 snps,multicast-filter-bins = <256>; 881 snps,perfect-filter-entries = <128>; 882 rx-fifo-depth = <8192>; 883 tx-fifo-depth = <8192>; 884 snps,fixed-burst; 885 snps,no-pbl-x8; 886 snps,force_thresh_dma_mode; 887 snps,axi-config = <&stmmac_axi_setup>; 888 snps,mtl-rx-config = <&mtl_rx_setup1>; 889 snps,mtl-tx-config = <&mtl_tx_setup1>; 890 snps,txpbl = <32>; 891 snps,rxpbl = <32>; 892 status = "disabled"; 893 894 mdio1: mdio { 895 compatible = "snps,dwmac-mdio"; 896 #address-cells = <1>; 897 #size-cells = <0>; 898 }; 899 900 mtl_rx_setup1: rx-queues-config { 901 snps,rx-queues-to-use = <4>; 902 snps,rx-sched-sp; 903 904 queue0 { 905 snps,dcb-algorithm; 906 snps,priority = <0x1>; 907 snps,map-to-dma-channel = <0>; 908 }; 909 910 queue1 { 911 snps,dcb-algorithm; 912 snps,priority = <0x2>; 913 snps,map-to-dma-channel = <1>; 914 }; 915 916 queue2 { 917 snps,dcb-algorithm; 918 snps,priority = <0x4>; 919 snps,map-to-dma-channel = <2>; 920 }; 921 922 queue3 { 923 snps,dcb-algorithm; 924 snps,priority = <0x8>; 925 snps,map-to-dma-channel = <3>; 926 }; 927 }; 928 929 mtl_tx_setup1: tx-queues-config { 930 snps,tx-queues-to-use = <4>; 931 932 queue0 { 933 snps,dcb-algorithm; 934 snps,priority = <0x1>; 935 }; 936 937 queue1 { 938 snps,dcb-algorithm; 939 snps,priority = <0x2>; 940 }; 941 942 queue2 { 943 snps,dcb-algorithm; 944 snps,priority = <0x4>; 945 }; 946 947 queue3 { 948 snps,dcb-algorithm; 949 snps,priority = <0x8>; 950 }; 951 }; 952 }; 953 }; 954 955 stmmac_axi_setup: stmmac-axi-config { 956 snps,lpi_en; 957 snps,wr_osr_lmt = <0xf>; 958 snps,rd_osr_lmt = <0xf>; 959 snps,blen = <16 8 4 0 0 0 0>; 960 }; 961 962 timer { 963 compatible = "arm,armv8-timer"; 964 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 965 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 966 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 967 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 968 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 969 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 970 }; 971}; 972