1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G3E SMARC EVK board 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8/dts-v1/; 9 10/* Switch selection settings */ 11#define SW_LCD_EN 0 12#define SW_GPIO8_CAN0_STB 0 13#define SW_GPIO9_CAN1_STB 0 14#define SW_LCD_EN 0 15#define SW_PDM_EN 0 16#define SW_SD0_DEV_SEL 0 17#define SW_SDIO_M2E 0 18 19#define PMOD_GPIO4 0 20#define PMOD_GPIO6 0 21#define PMOD_GPIO7 0 22 23#define KEY_1_GPIO RZG3E_GPIO(3, 1) 24#define KEY_2_GPIO RZG3E_GPIO(8, 4) 25#define KEY_3_GPIO RZG3E_GPIO(8, 5) 26 27#include <dt-bindings/gpio/gpio.h> 28#include <dt-bindings/input/input.h> 29#include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h> 30#include "r9a09g047e57.dtsi" 31#include "rzg3e-smarc-som.dtsi" 32#include "renesas-smarc2.dtsi" 33 34/ { 35 model = "Renesas SMARC EVK version 2 based on r9a09g047e57"; 36 compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm", 37 "renesas,r9a09g047e57", "renesas,r9a09g047"; 38 39 vqmmc_sd1_pvdd: regulator-vqmmc-sd1-pvdd { 40 compatible = "regulator-gpio"; 41 regulator-name = "SD1_PVDD"; 42 regulator-min-microvolt = <1800000>; 43 regulator-max-microvolt = <3300000>; 44 gpios = <&pinctrl RZG3E_GPIO(1, 5) GPIO_ACTIVE_HIGH>; 45 gpios-states = <0>; 46 states = <3300000 0>, <1800000 1>; 47 }; 48}; 49 50&canfd { 51 pinctrl-0 = <&canfd_pins>; 52 pinctrl-names = "default"; 53 54#if (!SW_PDM_EN) 55 channel1 { 56 status = "okay"; 57#if (!SW_LCD_EN) && (SW_GPIO9_CAN1_STB) 58 phys = <&can_transceiver1>; 59#endif 60 }; 61#endif 62 63#if (!SW_LCD_EN) 64 channel4 { 65 status = "okay"; 66#if (SW_GPIO8_CAN0_STB) 67 phys = <&can_transceiver0>; 68#endif 69 }; 70#endif 71}; 72 73#if (!SW_LCD_EN) && (SW_GPIO8_CAN0_STB) 74&can_transceiver0 { 75 standby-gpios = <&pinctrl RZG3E_GPIO(5, 4) GPIO_ACTIVE_HIGH>; 76 status = "okay"; 77}; 78#endif 79 80#if (!SW_LCD_EN) && (SW_GPIO9_CAN1_STB) 81&can_transceiver1 { 82 standby-gpios = <&pinctrl RZG3E_GPIO(5, 5) GPIO_ACTIVE_HIGH>; 83 status = "okay"; 84}; 85#endif 86 87&i2c0 { 88 pinctrl-0 = <&i2c0_pins>; 89 pinctrl-names = "default"; 90}; 91 92&keys { 93 key-sleep { 94 pinctrl-0 = <&nmi_pins>; 95 pinctrl-names = "default"; 96 97 interrupts-extended = <&icu 0 IRQ_TYPE_EDGE_FALLING>; 98 linux,code = <KEY_SLEEP>; 99 label = "SLEEP"; 100 debounce-interval = <20>; 101 }; 102#if PMOD_GPIO4 103 /delete-node/ key-1; 104#endif 105 106#if SW_LCD_EN || PMOD_GPIO6 107 /delete-node/ key-2; 108#endif 109 110#if SW_LCD_EN || PMOD_GPIO7 111 /delete-node/ key-3; 112#endif 113}; 114 115&pinctrl { 116 canfd_pins: canfd { 117 can1_pins: can1 { 118 pinmux = <RZG3E_PORT_PINMUX(L, 2, 3)>, /* RX */ 119 <RZG3E_PORT_PINMUX(L, 3, 3)>; /* TX */ 120 }; 121 122 can4_pins: can4 { 123 pinmux = <RZG3E_PORT_PINMUX(5, 2, 3)>, /* RX */ 124 <RZG3E_PORT_PINMUX(5, 3, 3)>; /* TX */ 125 }; 126 }; 127 128 i2c0_pins: i2c0 { 129 pinmux = <RZG3E_PORT_PINMUX(D, 4, 4)>, /* SCL0 */ 130 <RZG3E_PORT_PINMUX(D, 5, 4)>; /* SDA0 */ 131 }; 132 133 nmi_pins: nmi { 134 pinmux = <RZG3E_PORT_PINMUX(S, 0, 0)>; /* NMI */ 135 }; 136 137 scif_pins: scif { 138 pins = "SCIF_TXD", "SCIF_RXD"; 139 renesas,output-impedance = <1>; 140 }; 141 142 sd1-pwr-en-hog { 143 gpio-hog; 144 gpios = <RZG3E_GPIO(1, 6) GPIO_ACTIVE_HIGH>; 145 output-high; 146 line-name = "sd1_pwr_en"; 147 }; 148 149 sdhi1_pins: sd1 { 150 sd1-cd { 151 pinmux = <RZG3E_PORT_PINMUX(1, 4, 8)>; /* SD1CD */ 152 }; 153 154 sd1-ctrl { 155 pinmux = <RZG3E_PORT_PINMUX(G, 0, 1)>, /* SD1CLK */ 156 <RZG3E_PORT_PINMUX(G, 1, 1)>; /* SD1CMD */ 157 }; 158 159 sd1-data { 160 pinmux = <RZG3E_PORT_PINMUX(G, 2, 1)>, /* SD1DAT0 */ 161 <RZG3E_PORT_PINMUX(G, 3, 1)>, /* SD1DAT1 */ 162 <RZG3E_PORT_PINMUX(G, 4, 1)>, /* SD1DAT2 */ 163 <RZG3E_PORT_PINMUX(G, 5, 1)>; /* SD1DAT3 */ 164 }; 165 }; 166}; 167 168&scif0 { 169 pinctrl-0 = <&scif_pins>; 170 pinctrl-names = "default"; 171}; 172 173&sdhi1 { 174 pinctrl-0 = <&sdhi1_pins>; 175 pinctrl-1 = <&sdhi1_pins>; 176 pinctrl-names = "default", "state_uhs"; 177 178 vmmc-supply = <®_3p3v>; 179 vqmmc-supply = <&vqmmc_sd1_pvdd>; 180}; 181