xref: /linux/arch/arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts (revision 2f24482304ebd32c5aa374f31465b9941a860b92)
1*e58ada28SJulien Massot// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*e58ada28SJulien Massot/*
3*e58ada28SJulien Massot * Device Tree Source for the MYIR Remi Pi
4*e58ada28SJulien Massot *
5*e58ada28SJulien Massot * Copyright (C) 2022 MYIR Electronics Corp.
6*e58ada28SJulien Massot * Copyright (C) 2025 Collabora Ltd.
7*e58ada28SJulien Massot */
8*e58ada28SJulien Massot
9*e58ada28SJulien Massot/dts-v1/;
10*e58ada28SJulien Massot
11*e58ada28SJulien Massot#include <dt-bindings/gpio/gpio.h>
12*e58ada28SJulien Massot#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
13*e58ada28SJulien Massot
14*e58ada28SJulien Massot#include "r9a07g044l2.dtsi"
15*e58ada28SJulien Massot
16*e58ada28SJulien Massot/ {
17*e58ada28SJulien Massot	model = "MYIR Tech Limited Remi Pi MYB-YG2LX-REMI";
18*e58ada28SJulien Massot	compatible = "myir,remi-pi", "renesas,r9a07g044l2", "renesas,r9a07g044";
19*e58ada28SJulien Massot
20*e58ada28SJulien Massot	aliases {
21*e58ada28SJulien Massot		ethernet0 = &eth0;
22*e58ada28SJulien Massot		ethernet1 = &eth1;
23*e58ada28SJulien Massot
24*e58ada28SJulien Massot		i2c0 = &i2c0;
25*e58ada28SJulien Massot		i2c1 = &i2c1;
26*e58ada28SJulien Massot		i2c2 = &i2c2;
27*e58ada28SJulien Massot		i2c3 = &i2c3;
28*e58ada28SJulien Massot
29*e58ada28SJulien Massot		mmc0 = &sdhi0;
30*e58ada28SJulien Massot
31*e58ada28SJulien Massot		serial0 = &scif0;
32*e58ada28SJulien Massot		serial4 = &scif4;
33*e58ada28SJulien Massot	};
34*e58ada28SJulien Massot
35*e58ada28SJulien Massot	chosen {
36*e58ada28SJulien Massot		stdout-path = "serial0:115200n8";
37*e58ada28SJulien Massot	};
38*e58ada28SJulien Massot
39*e58ada28SJulien Massot	hdmi-out {
40*e58ada28SJulien Massot		compatible = "hdmi-connector";
41*e58ada28SJulien Massot		type = "a";
42*e58ada28SJulien Massot		ddc-i2c-bus = <&i2c1>;
43*e58ada28SJulien Massot
44*e58ada28SJulien Massot		port {
45*e58ada28SJulien Massot			hdmi_con: endpoint {
46*e58ada28SJulien Massot				remote-endpoint = <&lt8912_out>;
47*e58ada28SJulien Massot			};
48*e58ada28SJulien Massot		};
49*e58ada28SJulien Massot	};
50*e58ada28SJulien Massot
51*e58ada28SJulien Massot	memory@48000000 {
52*e58ada28SJulien Massot		device_type = "memory";
53*e58ada28SJulien Massot		/* first 128MB is reserved for secure area. */
54*e58ada28SJulien Massot		reg = <0x0 0x48000000 0x0 0x38000000>;
55*e58ada28SJulien Massot	};
56*e58ada28SJulien Massot
57*e58ada28SJulien Massot	reg_1p8v: regulator-1p8v {
58*e58ada28SJulien Massot		compatible = "regulator-fixed";
59*e58ada28SJulien Massot		regulator-name = "fixed-1.8V";
60*e58ada28SJulien Massot		vin-supply = <&reg_5p0v>;
61*e58ada28SJulien Massot		regulator-min-microvolt = <1800000>;
62*e58ada28SJulien Massot		regulator-max-microvolt = <1800000>;
63*e58ada28SJulien Massot		regulator-always-on;
64*e58ada28SJulien Massot	};
65*e58ada28SJulien Massot
66*e58ada28SJulien Massot	reg_3p3v: regulator-3p3v {
67*e58ada28SJulien Massot		compatible = "regulator-fixed";
68*e58ada28SJulien Massot		regulator-name = "fixed-3.3V";
69*e58ada28SJulien Massot		vin-supply = <&reg_5p0v>;
70*e58ada28SJulien Massot		regulator-min-microvolt = <3300000>;
71*e58ada28SJulien Massot		regulator-max-microvolt = <3300000>;
72*e58ada28SJulien Massot		regulator-always-on;
73*e58ada28SJulien Massot	};
74*e58ada28SJulien Massot
75*e58ada28SJulien Massot	reg_5p0v: regulator-5p0v {
76*e58ada28SJulien Massot		compatible = "regulator-fixed";
77*e58ada28SJulien Massot		regulator-name = "fixed-5.0V";
78*e58ada28SJulien Massot		regulator-min-microvolt = <5000000>;
79*e58ada28SJulien Massot		regulator-max-microvolt = <5000000>;
80*e58ada28SJulien Massot	};
81*e58ada28SJulien Massot
82*e58ada28SJulien Massot	reg_1p1v: regulator-vdd-core {
83*e58ada28SJulien Massot		compatible = "regulator-fixed";
84*e58ada28SJulien Massot		regulator-name = "fixed-1.1V";
85*e58ada28SJulien Massot		regulator-min-microvolt = <1100000>;
86*e58ada28SJulien Massot		regulator-max-microvolt = <1100000>;
87*e58ada28SJulien Massot		regulator-always-on;
88*e58ada28SJulien Massot	};
89*e58ada28SJulien Massot};
90*e58ada28SJulien Massot
91*e58ada28SJulien Massot&dsi {
92*e58ada28SJulien Massot	status = "okay";
93*e58ada28SJulien Massot
94*e58ada28SJulien Massot	ports {
95*e58ada28SJulien Massot		port@1 {
96*e58ada28SJulien Massot			dsi_out: endpoint {
97*e58ada28SJulien Massot				remote-endpoint = <&lt8912_in>;
98*e58ada28SJulien Massot				data-lanes = <1 2 3 4>;
99*e58ada28SJulien Massot			};
100*e58ada28SJulien Massot		};
101*e58ada28SJulien Massot	};
102*e58ada28SJulien Massot};
103*e58ada28SJulien Massot
104*e58ada28SJulien Massot&du {
105*e58ada28SJulien Massot	status = "okay";
106*e58ada28SJulien Massot};
107*e58ada28SJulien Massot
108*e58ada28SJulien Massot&ehci1 {
109*e58ada28SJulien Massot	status = "okay";
110*e58ada28SJulien Massot};
111*e58ada28SJulien Massot
112*e58ada28SJulien Massot&eth0 {
113*e58ada28SJulien Massot	pinctrl-0 = <&eth0_pins>;
114*e58ada28SJulien Massot	pinctrl-names = "default";
115*e58ada28SJulien Massot	phy-handle = <&phy0>;
116*e58ada28SJulien Massot	phy-mode = "rgmii-id";
117*e58ada28SJulien Massot	status = "okay";
118*e58ada28SJulien Massot
119*e58ada28SJulien Massot	phy0: ethernet-phy@4 {
120*e58ada28SJulien Massot		compatible = "ethernet-phy-ieee802.3-c22";
121*e58ada28SJulien Massot		reg = <4>;
122*e58ada28SJulien Massot		interrupts-extended = <&pinctrl RZG2L_GPIO(44, 2) IRQ_TYPE_LEVEL_LOW>;
123*e58ada28SJulien Massot		reset-gpios = <&pinctrl RZG2L_GPIO(44, 3) GPIO_ACTIVE_LOW>;
124*e58ada28SJulien Massot	};
125*e58ada28SJulien Massot};
126*e58ada28SJulien Massot
127*e58ada28SJulien Massot&eth1 {
128*e58ada28SJulien Massot	pinctrl-0 = <&eth1_pins>;
129*e58ada28SJulien Massot	pinctrl-names = "default";
130*e58ada28SJulien Massot	phy-handle = <&phy1>;
131*e58ada28SJulien Massot	phy-mode = "rgmii-id";
132*e58ada28SJulien Massot	status = "okay";
133*e58ada28SJulien Massot
134*e58ada28SJulien Massot	phy1: ethernet-phy@6 {
135*e58ada28SJulien Massot		compatible = "ethernet-phy-ieee802.3-c22";
136*e58ada28SJulien Massot		reg = <6>;
137*e58ada28SJulien Massot		interrupts-extended = <&pinctrl RZG2L_GPIO(43, 2) IRQ_TYPE_LEVEL_LOW>;
138*e58ada28SJulien Massot		reset-gpios = <&pinctrl RZG2L_GPIO(43, 3) GPIO_ACTIVE_LOW>;
139*e58ada28SJulien Massot	};
140*e58ada28SJulien Massot};
141*e58ada28SJulien Massot
142*e58ada28SJulien Massot&extal_clk {
143*e58ada28SJulien Massot	clock-frequency = <24000000>;
144*e58ada28SJulien Massot};
145*e58ada28SJulien Massot
146*e58ada28SJulien Massot&gpu {
147*e58ada28SJulien Massot	mali-supply = <&reg_1p1v>;
148*e58ada28SJulien Massot};
149*e58ada28SJulien Massot
150*e58ada28SJulien Massot&i2c0 {
151*e58ada28SJulien Massot	pinctrl-0 = <&i2c0_pins>;
152*e58ada28SJulien Massot	pinctrl-names = "default";
153*e58ada28SJulien Massot
154*e58ada28SJulien Massot	clock-frequency = <400000>;
155*e58ada28SJulien Massot	status = "okay";
156*e58ada28SJulien Massot
157*e58ada28SJulien Massot	hdmi-bridge@48 {
158*e58ada28SJulien Massot		compatible = "lontium,lt8912b";
159*e58ada28SJulien Massot		reg = <0x48> ;
160*e58ada28SJulien Massot		reset-gpios = <&pinctrl RZG2L_GPIO(42, 2) GPIO_ACTIVE_LOW>;
161*e58ada28SJulien Massot
162*e58ada28SJulien Massot		ports {
163*e58ada28SJulien Massot			#address-cells = <1>;
164*e58ada28SJulien Massot			#size-cells = <0>;
165*e58ada28SJulien Massot
166*e58ada28SJulien Massot			port@0 {
167*e58ada28SJulien Massot				reg = <0>;
168*e58ada28SJulien Massot
169*e58ada28SJulien Massot				lt8912_in: endpoint {
170*e58ada28SJulien Massot					data-lanes = <1 2 3 4>;
171*e58ada28SJulien Massot					remote-endpoint = <&dsi_out>;
172*e58ada28SJulien Massot				};
173*e58ada28SJulien Massot			};
174*e58ada28SJulien Massot
175*e58ada28SJulien Massot			port@1 {
176*e58ada28SJulien Massot				reg = <1>;
177*e58ada28SJulien Massot
178*e58ada28SJulien Massot				lt8912_out: endpoint {
179*e58ada28SJulien Massot					remote-endpoint = <&hdmi_con>;
180*e58ada28SJulien Massot				};
181*e58ada28SJulien Massot			};
182*e58ada28SJulien Massot		};
183*e58ada28SJulien Massot	};
184*e58ada28SJulien Massot};
185*e58ada28SJulien Massot
186*e58ada28SJulien Massot&i2c1 {
187*e58ada28SJulien Massot	pinctrl-0 = <&i2c1_pins>;
188*e58ada28SJulien Massot	pinctrl-names = "default";
189*e58ada28SJulien Massot	clock-frequency = <100000>;
190*e58ada28SJulien Massot	status = "okay";
191*e58ada28SJulien Massot};
192*e58ada28SJulien Massot
193*e58ada28SJulien Massot&i2c2 {
194*e58ada28SJulien Massot	pinctrl-0 = <&i2c2_pins>;
195*e58ada28SJulien Massot	pinctrl-names = "default";
196*e58ada28SJulien Massot	clock-frequency = <100000>;
197*e58ada28SJulien Massot	status = "okay";
198*e58ada28SJulien Massot};
199*e58ada28SJulien Massot
200*e58ada28SJulien Massot&i2c3 {
201*e58ada28SJulien Massot	pinctrl-0 = <&i2c3_pins>;
202*e58ada28SJulien Massot	pinctrl-names = "default";
203*e58ada28SJulien Massot	clock-frequency = <100000>;
204*e58ada28SJulien Massot	status = "okay";
205*e58ada28SJulien Massot};
206*e58ada28SJulien Massot
207*e58ada28SJulien Massot&mtu3 {
208*e58ada28SJulien Massot	status = "okay";
209*e58ada28SJulien Massot};
210*e58ada28SJulien Massot
211*e58ada28SJulien Massot&ohci1 {
212*e58ada28SJulien Massot	status = "okay";
213*e58ada28SJulien Massot};
214*e58ada28SJulien Massot
215*e58ada28SJulien Massot&ostm1 {
216*e58ada28SJulien Massot	status = "okay";
217*e58ada28SJulien Massot};
218*e58ada28SJulien Massot
219*e58ada28SJulien Massot&ostm2 {
220*e58ada28SJulien Massot	status = "okay";
221*e58ada28SJulien Massot};
222*e58ada28SJulien Massot
223*e58ada28SJulien Massot&phyrst {
224*e58ada28SJulien Massot	status = "okay";
225*e58ada28SJulien Massot};
226*e58ada28SJulien Massot
227*e58ada28SJulien Massot&pinctrl {
228*e58ada28SJulien Massot	eth0_pins: eth0 {
229*e58ada28SJulien Massot		pinmux = <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
230*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
231*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
232*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
233*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
234*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
235*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
236*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
237*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
238*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
239*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
240*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
241*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
242*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
243*e58ada28SJulien Massot	};
244*e58ada28SJulien Massot
245*e58ada28SJulien Massot	eth1_pins: eth1 {
246*e58ada28SJulien Massot		pinmux = <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
247*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
248*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
249*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
250*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
251*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
252*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
253*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
254*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
255*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
256*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
257*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
258*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
259*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
260*e58ada28SJulien Massot	};
261*e58ada28SJulien Massot
262*e58ada28SJulien Massot	i2c0_pins: i2c0 {
263*e58ada28SJulien Massot		pins = "RIIC0_SDA", "RIIC0_SCL";
264*e58ada28SJulien Massot		input-enable;
265*e58ada28SJulien Massot	};
266*e58ada28SJulien Massot
267*e58ada28SJulien Massot	i2c1_pins: i2c1 {
268*e58ada28SJulien Massot		pins = "RIIC1_SDA", "RIIC1_SCL";
269*e58ada28SJulien Massot		input-enable;
270*e58ada28SJulien Massot	};
271*e58ada28SJulien Massot
272*e58ada28SJulien Massot	i2c2_pins: i2c2 {
273*e58ada28SJulien Massot		pinmux = <RZG2L_PORT_PINMUX(3, 0, 2)>, /* SDA */
274*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(3, 1, 2)>; /* SCL */
275*e58ada28SJulien Massot	};
276*e58ada28SJulien Massot
277*e58ada28SJulien Massot	i2c3_pins: i2c3 {
278*e58ada28SJulien Massot		pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */
279*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
280*e58ada28SJulien Massot	};
281*e58ada28SJulien Massot
282*e58ada28SJulien Massot	scif0_pins: scif0 {
283*e58ada28SJulien Massot		pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
284*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
285*e58ada28SJulien Massot	};
286*e58ada28SJulien Massot
287*e58ada28SJulien Massot	scif4_pins: scif4 {
288*e58ada28SJulien Massot		pinmux = <RZG2L_PORT_PINMUX(2, 0, 5)>, /* TxD */
289*e58ada28SJulien Massot			 <RZG2L_PORT_PINMUX(2, 1, 5)>; /* RxD */
290*e58ada28SJulien Massot	};
291*e58ada28SJulien Massot
292*e58ada28SJulien Massot	sdhi0_pins: sd0 {
293*e58ada28SJulien Massot		sd0-ctrl {
294*e58ada28SJulien Massot			pins = "SD0_CLK", "SD0_CMD";
295*e58ada28SJulien Massot			power-source = <1800>;
296*e58ada28SJulien Massot		};
297*e58ada28SJulien Massot
298*e58ada28SJulien Massot		sd0-data {
299*e58ada28SJulien Massot			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
300*e58ada28SJulien Massot			       "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
301*e58ada28SJulien Massot			power-source = <1800>;
302*e58ada28SJulien Massot		};
303*e58ada28SJulien Massot
304*e58ada28SJulien Massot		sd0-rst {
305*e58ada28SJulien Massot			pins = "SD0_RST#";
306*e58ada28SJulien Massot			power-source = <1800>;
307*e58ada28SJulien Massot		};
308*e58ada28SJulien Massot	};
309*e58ada28SJulien Massot};
310*e58ada28SJulien Massot
311*e58ada28SJulien Massot&scif0 {
312*e58ada28SJulien Massot	pinctrl-0 = <&scif0_pins>;
313*e58ada28SJulien Massot	pinctrl-names = "default";
314*e58ada28SJulien Massot	status = "okay";
315*e58ada28SJulien Massot};
316*e58ada28SJulien Massot
317*e58ada28SJulien Massot&scif4 {
318*e58ada28SJulien Massot	pinctrl-0 = <&scif4_pins>;
319*e58ada28SJulien Massot	pinctrl-names = "default";
320*e58ada28SJulien Massot	status = "okay";
321*e58ada28SJulien Massot};
322*e58ada28SJulien Massot
323*e58ada28SJulien Massot&sdhi0 {
324*e58ada28SJulien Massot	pinctrl-0 = <&sdhi0_pins>;
325*e58ada28SJulien Massot	pinctrl-1 = <&sdhi0_pins>;
326*e58ada28SJulien Massot	pinctrl-names = "default", "state_uhs";
327*e58ada28SJulien Massot
328*e58ada28SJulien Massot	vmmc-supply = <&reg_3p3v>;
329*e58ada28SJulien Massot	vqmmc-supply = <&reg_1p8v>;
330*e58ada28SJulien Massot	bus-width = <8>;
331*e58ada28SJulien Massot	mmc-hs200-1_8v;
332*e58ada28SJulien Massot	non-removable;
333*e58ada28SJulien Massot	fixed-emmc-driver-type = <1>;
334*e58ada28SJulien Massot	status = "okay";
335*e58ada28SJulien Massot};
336*e58ada28SJulien Massot
337*e58ada28SJulien Massot&usb2_phy1 {
338*e58ada28SJulien Massot	status = "okay";
339*e58ada28SJulien Massot};
340