xref: /linux/arch/arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts (revision 2f24482304ebd32c5aa374f31465b9941a860b92) 
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the MYIR Remi Pi
4 *
5 * Copyright (C) 2022 MYIR Electronics Corp.
6 * Copyright (C) 2025 Collabora Ltd.
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
13
14#include "r9a07g044l2.dtsi"
15
16/ {
17	model = "MYIR Tech Limited Remi Pi MYB-YG2LX-REMI";
18	compatible = "myir,remi-pi", "renesas,r9a07g044l2", "renesas,r9a07g044";
19
20	aliases {
21		ethernet0 = &eth0;
22		ethernet1 = &eth1;
23
24		i2c0 = &i2c0;
25		i2c1 = &i2c1;
26		i2c2 = &i2c2;
27		i2c3 = &i2c3;
28
29		mmc0 = &sdhi0;
30
31		serial0 = &scif0;
32		serial4 = &scif4;
33	};
34
35	chosen {
36		stdout-path = "serial0:115200n8";
37	};
38
39	hdmi-out {
40		compatible = "hdmi-connector";
41		type = "a";
42		ddc-i2c-bus = <&i2c1>;
43
44		port {
45			hdmi_con: endpoint {
46				remote-endpoint = <&lt8912_out>;
47			};
48		};
49	};
50
51	memory@48000000 {
52		device_type = "memory";
53		/* first 128MB is reserved for secure area. */
54		reg = <0x0 0x48000000 0x0 0x38000000>;
55	};
56
57	reg_1p8v: regulator-1p8v {
58		compatible = "regulator-fixed";
59		regulator-name = "fixed-1.8V";
60		vin-supply = <&reg_5p0v>;
61		regulator-min-microvolt = <1800000>;
62		regulator-max-microvolt = <1800000>;
63		regulator-always-on;
64	};
65
66	reg_3p3v: regulator-3p3v {
67		compatible = "regulator-fixed";
68		regulator-name = "fixed-3.3V";
69		vin-supply = <&reg_5p0v>;
70		regulator-min-microvolt = <3300000>;
71		regulator-max-microvolt = <3300000>;
72		regulator-always-on;
73	};
74
75	reg_5p0v: regulator-5p0v {
76		compatible = "regulator-fixed";
77		regulator-name = "fixed-5.0V";
78		regulator-min-microvolt = <5000000>;
79		regulator-max-microvolt = <5000000>;
80	};
81
82	reg_1p1v: regulator-vdd-core {
83		compatible = "regulator-fixed";
84		regulator-name = "fixed-1.1V";
85		regulator-min-microvolt = <1100000>;
86		regulator-max-microvolt = <1100000>;
87		regulator-always-on;
88	};
89};
90
91&dsi {
92	status = "okay";
93
94	ports {
95		port@1 {
96			dsi_out: endpoint {
97				remote-endpoint = <&lt8912_in>;
98				data-lanes = <1 2 3 4>;
99			};
100		};
101	};
102};
103
104&du {
105	status = "okay";
106};
107
108&ehci1 {
109	status = "okay";
110};
111
112&eth0 {
113	pinctrl-0 = <&eth0_pins>;
114	pinctrl-names = "default";
115	phy-handle = <&phy0>;
116	phy-mode = "rgmii-id";
117	status = "okay";
118
119	phy0: ethernet-phy@4 {
120		compatible = "ethernet-phy-ieee802.3-c22";
121		reg = <4>;
122		interrupts-extended = <&pinctrl RZG2L_GPIO(44, 2) IRQ_TYPE_LEVEL_LOW>;
123		reset-gpios = <&pinctrl RZG2L_GPIO(44, 3) GPIO_ACTIVE_LOW>;
124	};
125};
126
127&eth1 {
128	pinctrl-0 = <&eth1_pins>;
129	pinctrl-names = "default";
130	phy-handle = <&phy1>;
131	phy-mode = "rgmii-id";
132	status = "okay";
133
134	phy1: ethernet-phy@6 {
135		compatible = "ethernet-phy-ieee802.3-c22";
136		reg = <6>;
137		interrupts-extended = <&pinctrl RZG2L_GPIO(43, 2) IRQ_TYPE_LEVEL_LOW>;
138		reset-gpios = <&pinctrl RZG2L_GPIO(43, 3) GPIO_ACTIVE_LOW>;
139	};
140};
141
142&extal_clk {
143	clock-frequency = <24000000>;
144};
145
146&gpu {
147	mali-supply = <&reg_1p1v>;
148};
149
150&i2c0 {
151	pinctrl-0 = <&i2c0_pins>;
152	pinctrl-names = "default";
153
154	clock-frequency = <400000>;
155	status = "okay";
156
157	hdmi-bridge@48 {
158		compatible = "lontium,lt8912b";
159		reg = <0x48> ;
160		reset-gpios = <&pinctrl RZG2L_GPIO(42, 2) GPIO_ACTIVE_LOW>;
161
162		ports {
163			#address-cells = <1>;
164			#size-cells = <0>;
165
166			port@0 {
167				reg = <0>;
168
169				lt8912_in: endpoint {
170					data-lanes = <1 2 3 4>;
171					remote-endpoint = <&dsi_out>;
172				};
173			};
174
175			port@1 {
176				reg = <1>;
177
178				lt8912_out: endpoint {
179					remote-endpoint = <&hdmi_con>;
180				};
181			};
182		};
183	};
184};
185
186&i2c1 {
187	pinctrl-0 = <&i2c1_pins>;
188	pinctrl-names = "default";
189	clock-frequency = <100000>;
190	status = "okay";
191};
192
193&i2c2 {
194	pinctrl-0 = <&i2c2_pins>;
195	pinctrl-names = "default";
196	clock-frequency = <100000>;
197	status = "okay";
198};
199
200&i2c3 {
201	pinctrl-0 = <&i2c3_pins>;
202	pinctrl-names = "default";
203	clock-frequency = <100000>;
204	status = "okay";
205};
206
207&mtu3 {
208	status = "okay";
209};
210
211&ohci1 {
212	status = "okay";
213};
214
215&ostm1 {
216	status = "okay";
217};
218
219&ostm2 {
220	status = "okay";
221};
222
223&phyrst {
224	status = "okay";
225};
226
227&pinctrl {
228	eth0_pins: eth0 {
229		pinmux = <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
230			 <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
231			 <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
232			 <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
233			 <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
234			 <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
235			 <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
236			 <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
237			 <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
238			 <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
239			 <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
240			 <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
241			 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
242			 <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
243	};
244
245	eth1_pins: eth1 {
246		pinmux = <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
247			 <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
248			 <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
249			 <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
250			 <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
251			 <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
252			 <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
253			 <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
254			 <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
255			 <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
256			 <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
257			 <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
258			 <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
259			 <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
260	};
261
262	i2c0_pins: i2c0 {
263		pins = "RIIC0_SDA", "RIIC0_SCL";
264		input-enable;
265	};
266
267	i2c1_pins: i2c1 {
268		pins = "RIIC1_SDA", "RIIC1_SCL";
269		input-enable;
270	};
271
272	i2c2_pins: i2c2 {
273		pinmux = <RZG2L_PORT_PINMUX(3, 0, 2)>, /* SDA */
274			 <RZG2L_PORT_PINMUX(3, 1, 2)>; /* SCL */
275	};
276
277	i2c3_pins: i2c3 {
278		pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */
279			 <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
280	};
281
282	scif0_pins: scif0 {
283		pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
284			 <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
285	};
286
287	scif4_pins: scif4 {
288		pinmux = <RZG2L_PORT_PINMUX(2, 0, 5)>, /* TxD */
289			 <RZG2L_PORT_PINMUX(2, 1, 5)>; /* RxD */
290	};
291
292	sdhi0_pins: sd0 {
293		sd0-ctrl {
294			pins = "SD0_CLK", "SD0_CMD";
295			power-source = <1800>;
296		};
297
298		sd0-data {
299			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
300			       "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
301			power-source = <1800>;
302		};
303
304		sd0-rst {
305			pins = "SD0_RST#";
306			power-source = <1800>;
307		};
308	};
309};
310
311&scif0 {
312	pinctrl-0 = <&scif0_pins>;
313	pinctrl-names = "default";
314	status = "okay";
315};
316
317&scif4 {
318	pinctrl-0 = <&scif4_pins>;
319	pinctrl-names = "default";
320	status = "okay";
321};
322
323&sdhi0 {
324	pinctrl-0 = <&sdhi0_pins>;
325	pinctrl-1 = <&sdhi0_pins>;
326	pinctrl-names = "default", "state_uhs";
327
328	vmmc-supply = <&reg_3p3v>;
329	vqmmc-supply = <&reg_1p8v>;
330	bus-width = <8>;
331	mmc-hs200-1_8v;
332	non-removable;
333	fixed-emmc-driver-type = <1>;
334	status = "okay";
335};
336
337&usb2_phy1 {
338	status = "okay";
339};
340