1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G2UL SoC 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr 11 12#include "r9a07g043.dtsi" 13 14/ { 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a55"; 21 reg = <0>; 22 device_type = "cpu"; 23 #cooling-cells = <2>; 24 next-level-cache = <&L3_CA55>; 25 enable-method = "psci"; 26 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; 27 operating-points-v2 = <&cluster0_opp>; 28 }; 29 30 L3_CA55: cache-controller-0 { 31 compatible = "cache"; 32 cache-unified; 33 cache-size = <0x40000>; 34 cache-level = <3>; 35 }; 36 }; 37 38 psci { 39 compatible = "arm,psci-1.0", "arm,psci-0.2"; 40 method = "smc"; 41 }; 42 43 timer { 44 compatible = "arm,armv8-timer"; 45 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 46 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 47 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 48 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 49 }; 50}; 51 52&soc { 53 interrupt-parent = <&gic>; 54 55 irqc: interrupt-controller@110a0000 { 56 compatible = "renesas,r9a07g043u-irqc", 57 "renesas,rzg2l-irqc"; 58 reg = <0 0x110a0000 0 0x10000>; 59 #interrupt-cells = <2>; 60 #address-cells = <0>; 61 interrupt-controller; 62 interrupts = <SOC_PERIPHERAL_IRQ(0) IRQ_TYPE_LEVEL_HIGH>, 63 <SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>, 64 <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>, 65 <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>, 66 <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>, 67 <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>, 68 <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>, 69 <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>, 70 <SOC_PERIPHERAL_IRQ(8) IRQ_TYPE_LEVEL_HIGH>, 71 <SOC_PERIPHERAL_IRQ(444) IRQ_TYPE_LEVEL_HIGH>, 72 <SOC_PERIPHERAL_IRQ(445) IRQ_TYPE_LEVEL_HIGH>, 73 <SOC_PERIPHERAL_IRQ(446) IRQ_TYPE_LEVEL_HIGH>, 74 <SOC_PERIPHERAL_IRQ(447) IRQ_TYPE_LEVEL_HIGH>, 75 <SOC_PERIPHERAL_IRQ(448) IRQ_TYPE_LEVEL_HIGH>, 76 <SOC_PERIPHERAL_IRQ(449) IRQ_TYPE_LEVEL_HIGH>, 77 <SOC_PERIPHERAL_IRQ(450) IRQ_TYPE_LEVEL_HIGH>, 78 <SOC_PERIPHERAL_IRQ(451) IRQ_TYPE_LEVEL_HIGH>, 79 <SOC_PERIPHERAL_IRQ(452) IRQ_TYPE_LEVEL_HIGH>, 80 <SOC_PERIPHERAL_IRQ(453) IRQ_TYPE_LEVEL_HIGH>, 81 <SOC_PERIPHERAL_IRQ(454) IRQ_TYPE_LEVEL_HIGH>, 82 <SOC_PERIPHERAL_IRQ(455) IRQ_TYPE_LEVEL_HIGH>, 83 <SOC_PERIPHERAL_IRQ(456) IRQ_TYPE_LEVEL_HIGH>, 84 <SOC_PERIPHERAL_IRQ(457) IRQ_TYPE_LEVEL_HIGH>, 85 <SOC_PERIPHERAL_IRQ(458) IRQ_TYPE_LEVEL_HIGH>, 86 <SOC_PERIPHERAL_IRQ(459) IRQ_TYPE_LEVEL_HIGH>, 87 <SOC_PERIPHERAL_IRQ(460) IRQ_TYPE_LEVEL_HIGH>, 88 <SOC_PERIPHERAL_IRQ(461) IRQ_TYPE_LEVEL_HIGH>, 89 <SOC_PERIPHERAL_IRQ(462) IRQ_TYPE_LEVEL_HIGH>, 90 <SOC_PERIPHERAL_IRQ(463) IRQ_TYPE_LEVEL_HIGH>, 91 <SOC_PERIPHERAL_IRQ(464) IRQ_TYPE_LEVEL_HIGH>, 92 <SOC_PERIPHERAL_IRQ(465) IRQ_TYPE_LEVEL_HIGH>, 93 <SOC_PERIPHERAL_IRQ(466) IRQ_TYPE_LEVEL_HIGH>, 94 <SOC_PERIPHERAL_IRQ(467) IRQ_TYPE_LEVEL_HIGH>, 95 <SOC_PERIPHERAL_IRQ(468) IRQ_TYPE_LEVEL_HIGH>, 96 <SOC_PERIPHERAL_IRQ(469) IRQ_TYPE_LEVEL_HIGH>, 97 <SOC_PERIPHERAL_IRQ(470) IRQ_TYPE_LEVEL_HIGH>, 98 <SOC_PERIPHERAL_IRQ(471) IRQ_TYPE_LEVEL_HIGH>, 99 <SOC_PERIPHERAL_IRQ(472) IRQ_TYPE_LEVEL_HIGH>, 100 <SOC_PERIPHERAL_IRQ(473) IRQ_TYPE_LEVEL_HIGH>, 101 <SOC_PERIPHERAL_IRQ(474) IRQ_TYPE_LEVEL_HIGH>, 102 <SOC_PERIPHERAL_IRQ(475) IRQ_TYPE_LEVEL_HIGH>, 103 <SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>; 104 interrupt-names = "nmi", 105 "irq0", "irq1", "irq2", "irq3", 106 "irq4", "irq5", "irq6", "irq7", 107 "tint0", "tint1", "tint2", "tint3", 108 "tint4", "tint5", "tint6", "tint7", 109 "tint8", "tint9", "tint10", "tint11", 110 "tint12", "tint13", "tint14", "tint15", 111 "tint16", "tint17", "tint18", "tint19", 112 "tint20", "tint21", "tint22", "tint23", 113 "tint24", "tint25", "tint26", "tint27", 114 "tint28", "tint29", "tint30", "tint31", 115 "bus-err"; 116 clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>, 117 <&cpg CPG_MOD R9A07G043_IA55_PCLK>; 118 clock-names = "clk", "pclk"; 119 power-domains = <&cpg>; 120 resets = <&cpg R9A07G043_IA55_RESETN>; 121 }; 122 123 gic: interrupt-controller@11900000 { 124 compatible = "arm,gic-v3"; 125 #interrupt-cells = <3>; 126 #address-cells = <0>; 127 interrupt-controller; 128 reg = <0x0 0x11900000 0 0x40000>, 129 <0x0 0x11940000 0 0x60000>; 130 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 131 }; 132}; 133 134&sysc { 135 interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>, 136 <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>, 137 <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>, 138 <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>; 139 interrupt-names = "lpm_int", "ca55stbydone_int", 140 "cm33stbyr_int", "ca55_deny"; 141}; 142