1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6/* X1P42100 is heavily based on X1E80100, with some meaningful differences */ 7#include "x1e80100.dtsi" 8 9/delete-node/ &bwmon_cluster0; 10/delete-node/ &cluster_pd2; 11/delete-node/ &cpu_map_cluster2; 12/delete-node/ &cpu8; 13/delete-node/ &cpu9; 14/delete-node/ &cpu10; 15/delete-node/ &cpu11; 16/delete-node/ &cpu_pd8; 17/delete-node/ &cpu_pd9; 18/delete-node/ &cpu_pd10; 19/delete-node/ &cpu_pd11; 20/delete-node/ &pcie3_phy; 21 22&gcc { 23 compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc"; 24}; 25 26/* The GPU is physically different and will be brought up later */ 27&gpu { 28 /delete-property/ compatible; 29}; 30 31&gpucc { 32 compatible = "qcom,x1p42100-gpucc"; 33}; 34 35/* PCIe3 has half the lanes compared to X1E80100 */ 36&pcie3 { 37 num-lanes = <4>; 38}; 39 40&pcie6a_phy { 41 compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy"; 42}; 43 44&soc { 45 /* The PCIe3 PHY on X1P42100 uses a different IP block */ 46 pcie3_phy: phy@1bd4000 { 47 compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy"; 48 reg = <0x0 0x01bd4000 0x0 0x2000>, 49 <0x0 0x01bd6000 0x0 0x2000>; 50 51 clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>, 52 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 53 <&tcsr TCSR_PCIE_8L_CLKREF_EN>, 54 <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>, 55 <&gcc GCC_PCIE_3_PIPE_CLK>, 56 <&gcc GCC_PCIE_3_PIPEDIV2_CLK>; 57 clock-names = "aux", 58 "cfg_ahb", 59 "ref", 60 "rchng", 61 "pipe", 62 "pipediv2"; 63 64 resets = <&gcc GCC_PCIE_3_PHY_BCR>, 65 <&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>; 66 reset-names = "phy", 67 "phy_nocsr"; 68 69 assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>; 70 assigned-clock-rates = <100000000>; 71 72 power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>; 73 74 #clock-cells = <0>; 75 clock-output-names = "pcie3_pipe_clk"; 76 77 #phy-cells = <0>; 78 79 status = "disabled"; 80 }; 81}; 82