1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6#include <dt-bindings/clock/qcom,dispcc-qcm2290.h> 7#include <dt-bindings/clock/qcom,qcm2290-gpucc.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/clock/qcom,shikra-gcc.h> 10#include <dt-bindings/interconnect/qcom,icc.h> 11#include <dt-bindings/interconnect/qcom,osm-l3.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/interconnect/qcom,rpm-icc.h> 14#include <dt-bindings/interconnect/qcom,shikra.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/thermal/thermal.h> 18 19/ { 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 clocks { 26 xo_board: xo-board { 27 compatible = "fixed-clock"; 28 clock-frequency = <38400000>; 29 #clock-cells = <0>; 30 }; 31 32 sleep_clk: sleep-clk { 33 compatible = "fixed-clock"; 34 clock-frequency = <32764>; 35 #clock-cells = <0>; 36 }; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 cpu0: cpu@0 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a55"; 46 reg = <0x0 0x0>; 47 enable-method = "psci"; 48 next-level-cache = <&l3>; 49 capacity-dmips-mhz = <1024>; 50 dynamic-power-coefficient = <100>; 51 clocks = <&cpufreq_hw 0>; 52 qcom,freq-domain = <&cpufreq_hw 0>; 53 #cooling-cells = <2>; 54 operating-points-v2 = <&cpu0_opp_table>; 55 interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG 56 &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, 57 <&epss_l3 MASTER_EPSS_L3_APPS 58 &epss_l3 SLAVE_EPSS_L3_SHARED>; 59 }; 60 61 cpu1: cpu@100 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a55"; 64 reg = <0x0 0x100>; 65 enable-method = "psci"; 66 next-level-cache = <&l3>; 67 capacity-dmips-mhz = <1024>; 68 dynamic-power-coefficient = <100>; 69 clocks = <&cpufreq_hw 0>; 70 qcom,freq-domain = <&cpufreq_hw 0>; 71 #cooling-cells = <2>; 72 operating-points-v2 = <&cpu0_opp_table>; 73 interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG 74 &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, 75 <&epss_l3 MASTER_EPSS_L3_APPS 76 &epss_l3 SLAVE_EPSS_L3_SHARED>; 77 }; 78 79 cpu2: cpu@200 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a55"; 82 reg = <0x0 0x200>; 83 enable-method = "psci"; 84 next-level-cache = <&l3>; 85 capacity-dmips-mhz = <1024>; 86 dynamic-power-coefficient = <100>; 87 clocks = <&cpufreq_hw 0>; 88 qcom,freq-domain = <&cpufreq_hw 0>; 89 #cooling-cells = <2>; 90 operating-points-v2 = <&cpu0_opp_table>; 91 interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG 92 &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, 93 <&epss_l3 MASTER_EPSS_L3_APPS 94 &epss_l3 SLAVE_EPSS_L3_SHARED>; 95 }; 96 97 cpu3: cpu@300 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a78c"; 100 reg = <0x0 0x300>; 101 enable-method = "psci"; 102 next-level-cache = <&l2_3>; 103 capacity-dmips-mhz = <1946>; 104 dynamic-power-coefficient = <489>; 105 clocks = <&cpufreq_hw 1>; 106 qcom,freq-domain = <&cpufreq_hw 1>; 107 #cooling-cells = <2>; 108 operating-points-v2 = <&cpu3_opp_table>; 109 interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG 110 &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, 111 <&epss_l3 MASTER_EPSS_L3_APPS 112 &epss_l3 SLAVE_EPSS_L3_SHARED>; 113 114 l2_3: l2-cache { 115 compatible = "cache"; 116 cache-level = <2>; 117 cache-unified; 118 next-level-cache = <&l3>; 119 cache-size = <0x40000>; 120 }; 121 }; 122 123 cpu-map { 124 cluster0 { 125 core0 { 126 cpu = <&cpu0>; 127 }; 128 129 core1 { 130 cpu = <&cpu1>; 131 }; 132 133 core2 { 134 cpu = <&cpu2>; 135 }; 136 }; 137 138 cluster1 { 139 core0 { 140 cpu = <&cpu3>; 141 }; 142 }; 143 }; 144 145 l3: l3-cache { 146 compatible = "cache"; 147 cache-level = <3>; 148 cache-unified; 149 cache-size = <0x80000>; 150 }; 151 }; 152 153 firmware { 154 scm { 155 compatible = "qcom,scm-shikra", "qcom,scm"; 156 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 157 clock-names = "core"; 158 qcom,dload-mode = <&tcsr_regs 0x13000>; 159 #reset-cells = <1>; 160 interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG 161 &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 162 }; 163 }; 164 165 memory@80000000 { 166 device_type = "memory"; 167 /* We expect the bootloader to fill in the size */ 168 reg = <0x0 0x80000000 0x0 0x0>; 169 }; 170 171 cpu0_opp_table: opp-table-cpu0 { 172 compatible = "operating-points-v2"; 173 opp-shared; 174 175 opp-768000000 { 176 opp-hz = /bits/ 64 <768000000>; 177 opp-peak-kBps = <1200000 17817600>; 178 }; 179 180 opp-1017600000 { 181 opp-hz = /bits/ 64 <1017600000>; 182 opp-peak-kBps = <2188000 25804800>; 183 }; 184 185 opp-1094400000 { 186 opp-hz = /bits/ 64 <1094400000>; 187 opp-peak-kBps = <3072000 30105600>; 188 }; 189 190 opp-1497600000 { 191 opp-hz = /bits/ 64 <1497600000>; 192 opp-peak-kBps = <4068000 38707200>; 193 }; 194 195 opp-1612800000 { 196 opp-hz = /bits/ 64 <1612800000>; 197 opp-peak-kBps = <6220000 43008000>; 198 }; 199 200 opp-1804800000 { 201 opp-hz = /bits/ 64 <1804800000>; 202 opp-peak-kBps = <7216000 43622400>; 203 }; 204 205 opp-2208000000 { 206 opp-hz = /bits/ 64 <2208000000>; 207 opp-peak-kBps = <7216000 43622400>; 208 }; 209 }; 210 211 cpu3_opp_table: opp-table-cpu3 { 212 compatible = "operating-points-v2"; 213 opp-shared; 214 215 opp-768000000 { 216 opp-hz = /bits/ 64 <768000000>; 217 opp-peak-kBps = <1200000 17817600>; 218 }; 219 220 opp-1017600000 { 221 opp-hz = /bits/ 64 <1017600000>; 222 opp-peak-kBps = <2188000 25804800>; 223 }; 224 225 opp-1190400000 { 226 opp-hz = /bits/ 64 <1190400000>; 227 opp-peak-kBps = <3072000 30105600>; 228 }; 229 230 opp-1497600000 { 231 opp-hz = /bits/ 64 <1497600000>; 232 opp-peak-kBps = <4068000 38707200>; 233 }; 234 235 opp-1708800000 { 236 opp-hz = /bits/ 64 <1708800000>; 237 opp-peak-kBps = <6220000 43008000>; 238 }; 239 240 opp-1900800000 { 241 opp-hz = /bits/ 64 <1900800000>; 242 opp-peak-kBps = <7216000 43622400>; 243 }; 244 245 opp-2208000000 { 246 opp-hz = /bits/ 64 <2208000000>; 247 opp-peak-kBps = <7216000 43622400>; 248 }; 249 }; 250 251 pmu-a55 { 252 compatible = "arm,cortex-a55-pmu"; 253 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 254 }; 255 256 pmu-a78c { 257 compatible = "arm,cortex-a78-pmu"; 258 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 259 }; 260 261 psci { 262 compatible = "arm,psci-1.0"; 263 method = "smc"; 264 }; 265 266 rpm: remoteproc { 267 compatible = "qcom,shikra-rpm-proc", "qcom,rpm-proc"; 268 269 glink-edge { 270 compatible = "qcom,glink-rpm"; 271 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING 0>; 272 qcom,rpm-msg-ram = <&rpm_msg_ram>; 273 mboxes = <&apcs_glb 0>; 274 275 rpm_requests: rpm-requests { 276 compatible = "qcom,rpm-shikra", "qcom,glink-smd-rpm"; 277 qcom,glink-channels = "rpm_requests"; 278 279 rpmcc: clock-controller { 280 compatible = "qcom,rpmcc-shikra", "qcom,rpmcc-qcm2290", "qcom,rpmcc"; 281 clocks = <&xo_board>; 282 clock-names = "xo"; 283 #clock-cells = <1>; 284 }; 285 286 rpmpd: power-controller { 287 compatible = "qcom,shikra-rpmpd"; 288 #power-domain-cells = <1>; 289 operating-points-v2 = <&rpmpd_opp_table>; 290 291 rpmpd_opp_table: opp-table { 292 compatible = "operating-points-v2"; 293 294 rpmpd_opp_min_svs: opp1 { 295 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 296 }; 297 298 rpmpd_opp_low_svs: opp2 { 299 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 300 }; 301 302 rpmpd_opp_svs: opp3 { 303 opp-level = <RPM_SMD_LEVEL_SVS>; 304 }; 305 306 rpmpd_opp_svs_plus: opp4 { 307 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 308 }; 309 310 rpmpd_opp_nom: opp5 { 311 opp-level = <RPM_SMD_LEVEL_NOM>; 312 }; 313 314 rpmpd_opp_nom_plus: opp6 { 315 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 316 }; 317 318 rpmpd_opp_turbo: opp7 { 319 opp-level = <RPM_SMD_LEVEL_TURBO>; 320 }; 321 322 rpmpd_opp_turbo_plus: opp8 { 323 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 324 }; 325 }; 326 }; 327 }; 328 }; 329 330 mpm: interrupt-controller { 331 compatible = "qcom,mpm"; 332 qcom,rpm-msg-ram = <&apss_mpm>; 333 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING 0>; 334 mboxes = <&apcs_glb 1>; 335 interrupt-controller; 336 #interrupt-cells = <2>; 337 #power-domain-cells = <0>; 338 interrupt-parent = <&intc>; 339 qcom,mpm-pin-count = <96>; 340 qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */ 341 <12 422>, /* DWC3 ss_phy_irq */ 342 <58 272>, /* QUSB2_PHY dmse_hv_vddmx */ 343 <59 273>, /* QUSB2_PHY dpse_hv_vddmx */ 344 <86 183>, /* MPM wake, SPMI */ 345 <90 157>, /* QUSB2_PHY DM */ 346 <91 158>; /* QUSB2_PHY DP */ 347 }; 348 }; 349 350 reserved_memory: reserved-memory { 351 #address-cells = <2>; 352 #size-cells = <2>; 353 ranges; 354 355 hyp_mem: hyp@80000000 { 356 reg = <0x0 0x80000000 0x0 0x1600000>; 357 no-map; 358 }; 359 360 xblboot_mem: xblboot@85e00000 { 361 reg = <0x0 0x85e00000 0x0 0x100000>; 362 no-map; 363 }; 364 365 secdata_apss_mem: secdata-apss@85fff000 { 366 reg = <0x0 0x85fff000 0x0 0x1000>; 367 no-map; 368 }; 369 370 smem_mem: smem@86000000 { 371 compatible = "qcom,smem"; 372 reg = <0x0 0x86000000 0x0 0x200000>; 373 no-map; 374 375 hwlocks = <&tcsr_mutex 3>; 376 }; 377 378 audio_heap_mem: audio-heap@86200000 { 379 reg = <0x0 0x86200000 0x0 0x100000>; 380 no-map; 381 }; 382 383 tz_stat_mem: tz-stat@a0000000 { 384 reg = <0x0 0xa0000000 0x0 0x100000>; 385 no-map; 386 }; 387 388 qtee_mem: qtee@a1300000 { 389 reg = <0x0 0xa1300000 0x0 0x500000>; 390 no-map; 391 }; 392 393 tz_apps_mem: tz-apps@a1800000 { 394 reg = <0x0 0xa1800000 0x0 0x2100000>; 395 no-map; 396 }; 397 398 mpss_wlan_mem: mpss-wlan@ab000000 { 399 reg = <0x0 0xab000000 0x0 0x6e00000>; 400 no-map; 401 }; 402 403 wlan_mem: wlan@b2300000 { 404 reg = <0x0 0xb2300000 0x0 0x100000>; 405 no-map; 406 }; 407 408 cdsp_mem: cdsp@b2400000 { 409 reg = <0x0 0xb2400000 0x0 0x1900000>; 410 no-map; 411 }; 412 413 gpu_micro_code_mem: gpu-micro-code@b3d00000 { 414 reg = <0x0 0xb3d00000 0x0 0x2000>; 415 no-map; 416 }; 417 418 video_mem: video@b3d02000 { 419 reg = <0x0 0xb3d02000 0x0 0x700000>; 420 no-map; 421 }; 422 423 lmcu_mem: lmcu@b4402000 { 424 reg = <0x0 0xb4402000 0x0 0x300000>; 425 no-map; 426 }; 427 428 lmcu_dtb_mem: lmcu-dtb@b4702000 { 429 reg = <0x0 0xb4702000 0x0 0x40000>; 430 no-map; 431 }; 432 }; 433 434 smp2p-cdsp { 435 compatible = "qcom,smp2p"; 436 qcom,smem = <94>, <432>; 437 438 interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING 0>; 439 440 mboxes = <&apcs_glb 6>; 441 442 qcom,local-pid = <0>; 443 qcom,remote-pid = <5>; 444 445 cdsp_smp2p_out: master-kernel { 446 qcom,entry-name = "master-kernel"; 447 #qcom,smem-state-cells = <1>; 448 }; 449 450 cdsp_smp2p_in: slave-kernel { 451 qcom,entry-name = "slave-kernel"; 452 interrupt-controller; 453 #interrupt-cells = <2>; 454 }; 455 }; 456 457 smp2p-lmcu { 458 compatible = "qcom,smp2p"; 459 qcom,smem = <617>, <616>; 460 461 interrupts = <GIC_SPI 287 IRQ_TYPE_EDGE_RISING 0>; 462 463 mboxes = <&apcs_glb 10>; 464 465 qcom,local-pid = <0>; 466 qcom,remote-pid = <26>; 467 468 lmcu_smp2p_out: master-kernel { 469 qcom,entry-name = "master-kernel"; 470 #qcom,smem-state-cells = <1>; 471 }; 472 473 lmcu_smp2p_in: slave-kernel { 474 qcom,entry-name = "slave-kernel"; 475 interrupt-controller; 476 #interrupt-cells = <2>; 477 }; 478 }; 479 480 smp2p-mpss { 481 compatible = "qcom,smp2p"; 482 qcom,smem = <435>, <428>; 483 484 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING 0>; 485 486 mboxes = <&apcs_glb 14>; 487 488 qcom,local-pid = <0>; 489 qcom,remote-pid = <1>; 490 491 modem_smp2p_out: master-kernel { 492 qcom,entry-name = "master-kernel"; 493 #qcom,smem-state-cells = <1>; 494 }; 495 496 modem_smp2p_in: slave-kernel { 497 qcom,entry-name = "slave-kernel"; 498 interrupt-controller; 499 #interrupt-cells = <2>; 500 }; 501 }; 502 503 soc: soc@0 { 504 compatible = "simple-bus"; 505 506 #address-cells = <2>; 507 #size-cells = <2>; 508 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; 509 ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; 510 511 tcsr_mutex: syscon@340000 { 512 compatible = "qcom,tcsr-mutex"; 513 reg = <0x0 0x00340000 0x0 0x20000>; 514 #hwlock-cells = <1>; 515 }; 516 517 tcsr_regs: syscon@3c0000 { 518 compatible = "qcom,shikra-tcsr", "syscon"; 519 reg = <0x0 0x003c0000 0x0 0x40000>; 520 }; 521 522 tlmm: pinctrl@500000 { 523 compatible = "qcom,shikra-tlmm"; 524 reg = <0x0 0x00500000 0x0 0x700000>; 525 526 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>; 527 528 gpio-controller; 529 #gpio-cells = <2>; 530 531 interrupt-controller; 532 #interrupt-cells = <2>; 533 534 gpio-ranges = <&tlmm 0 0 165>; 535 wakeup-parent = <&mpm>; 536 537 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 538 /* SDA, SCL */ 539 pins = "gpio2", "gpio3"; 540 function = "qup0_se0"; 541 drive-strength = <2>; 542 bias-pull-up; 543 }; 544 545 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 546 /* SDA, SCL */ 547 pins = "gpio4", "gpio5"; 548 function = "qup0_se1_01"; 549 drive-strength = <2>; 550 bias-pull-up; 551 }; 552 553 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 554 /* SDA, SCL */ 555 pins = "gpio6", "gpio7"; 556 function = "qup0_se2"; 557 drive-strength = <2>; 558 bias-pull-up; 559 }; 560 561 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 562 /* SDA, SCL */ 563 pins = "gpio10", "gpio11"; 564 function = "qup0_se3_01"; 565 drive-strength = <2>; 566 bias-pull-up; 567 }; 568 569 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 570 /* SDA, SCL */ 571 pins = "gpio12", "gpio13"; 572 function = "qup0_se4_01"; 573 drive-strength = <2>; 574 bias-pull-up; 575 }; 576 577 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 578 /* SDA, SCL */ 579 pins = "gpio14", "gpio15"; 580 function = "qup0_se5"; 581 drive-strength = <2>; 582 bias-pull-up; 583 }; 584 585 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 586 /* SDA, SCL */ 587 pins = "gpio18", "gpio19"; 588 function = "qup0_se6"; 589 drive-strength = <2>; 590 bias-pull-up; 591 }; 592 593 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 594 /* SDA, SCL */ 595 pins = "gpio20", "gpio21"; 596 function = "qup0_se7_01"; 597 drive-strength = <2>; 598 bias-pull-up; 599 }; 600 601 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 602 /* SDA, SCL */ 603 pins = "gpio22", "gpio23"; 604 function = "qup0_se8"; 605 drive-strength = <2>; 606 bias-pull-up; 607 }; 608 609 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 610 /* SDA, SCL */ 611 pins = "gpio27", "gpio26"; 612 function = "qup0_se9_01"; 613 drive-strength = <2>; 614 bias-pull-up; 615 }; 616 617 qup_spi0_cs: qup-spi0-cs-state { 618 pins = "gpio1"; 619 function = "qup0_se0"; 620 drive-strength = <6>; 621 bias-disable; 622 }; 623 624 qup_spi0_data_clk: qup-spi0-data-clk-state { 625 /* MISO, MOSI, CLK */ 626 pins = "gpio2", "gpio3", "gpio0"; 627 function = "qup0_se0"; 628 drive-strength = <6>; 629 bias-disable; 630 }; 631 632 qup_spi2_cs: qup-spi2-cs-state { 633 pins = "gpio9"; 634 function = "qup0_se2"; 635 drive-strength = <6>; 636 bias-disable; 637 }; 638 639 qup_spi2_data_clk: qup-spi2-data-clk-state { 640 /* MISO, MOSI, CLK */ 641 pins = "gpio6", "gpio7", "gpio8"; 642 function = "qup0_se2"; 643 drive-strength = <6>; 644 bias-disable; 645 }; 646 647 qup_spi5_cs: qup-spi5-cs-state { 648 pins = "gpio17"; 649 function = "qup0_se5"; 650 drive-strength = <6>; 651 bias-disable; 652 }; 653 654 qup_spi5_data_clk: qup-spi5-data-clk-state { 655 /* MISO, MOSI, CLK */ 656 pins = "gpio14", "gpio15", "gpio16"; 657 function = "qup0_se5"; 658 drive-strength = <6>; 659 bias-disable; 660 }; 661 662 qup_spi6_cs: qup-spi6-cs-state { 663 pins = "gpio29"; 664 function = "qup0_se6"; 665 drive-strength = <6>; 666 bias-disable; 667 }; 668 669 qup_spi6_data_clk: qup-spi6-data-clk-state { 670 /* MISO, MOSI, CLK */ 671 pins = "gpio18", "gpio19", "gpio28"; 672 function = "qup0_se6"; 673 drive-strength = <6>; 674 bias-disable; 675 }; 676 677 qup_spi8_cs: qup-spi8-cs-state { 678 pins = "gpio25"; 679 function = "qup0_se8"; 680 drive-strength = <6>; 681 bias-disable; 682 }; 683 684 qup_spi8_data_clk: qup-spi8-data-clk-state { 685 /* MISO, MOSI, CLK */ 686 pins = "gpio22", "gpio23", "gpio24"; 687 function = "qup0_se8"; 688 drive-strength = <6>; 689 bias-disable; 690 }; 691 692 qup_uart0_default: qup-uart0-default-state { 693 pins = "gpio0", "gpio1"; 694 function = "qup0_se0"; 695 drive-strength = <2>; 696 bias-disable; 697 }; 698 699 qup_uart1_default: qup-uart1-default-state { 700 pins = "gpio4", "gpio5"; 701 function = "qup0_se1_23"; 702 drive-strength = <2>; 703 bias-disable; 704 }; 705 706 qup_uart2_default: qup-uart2-default-state { 707 /* TX, RX */ 708 pins = "gpio8", "gpio9"; 709 function = "qup0_se2"; 710 drive-strength = <2>; 711 bias-pull-up; 712 }; 713 714 qup_uart2_cts_rts: qup-uart2-cts-rts-state { 715 /* CTS, RTS */ 716 pins = "gpio6", "gpio7"; 717 function = "qup0_se2"; 718 drive-strength = <2>; 719 bias-pull-down; 720 }; 721 722 qup_uart3_default: qup-uart3-default-state { 723 pins = "gpio10", "gpio11"; 724 function = "qup0_se3_23"; 725 drive-strength = <2>; 726 bias-disable; 727 }; 728 729 qup_uart4_default: qup-uart4-default-state { 730 pins = "gpio12", "gpio13"; 731 function = "qup0_se4_23"; 732 drive-strength = <2>; 733 bias-disable; 734 }; 735 736 qup_uart5_default: qup-uart5-default-state { 737 /* TX, RX */ 738 pins = "gpio16", "gpio17"; 739 function = "qup0_se5"; 740 drive-strength = <2>; 741 bias-pull-up; 742 }; 743 744 qup_uart5_cts_rts: qup-uart5-cts-rts-state { 745 /* CTS, RTS */ 746 pins = "gpio14", "gpio15"; 747 function = "qup0_se5"; 748 drive-strength = <2>; 749 bias-pull-down; 750 }; 751 752 qup_uart6_default: qup-uart6-default-state { 753 /* TX, RX */ 754 pins = "gpio28", "gpio29"; 755 function = "qup0_se6"; 756 drive-strength = <2>; 757 bias-pull-up; 758 }; 759 760 qup_uart6_cts_rts: qup-uart6-cts-rts-state { 761 /* CTS, RTS */ 762 pins = "gpio18", "gpio19"; 763 function = "qup0_se6"; 764 drive-strength = <2>; 765 bias-pull-down; 766 }; 767 768 qup_uart7_default: qup-uart7-default-state { 769 pins = "gpio20", "gpio21"; 770 function = "qup0_se7_23"; 771 drive-strength = <2>; 772 bias-disable; 773 }; 774 775 qup_uart8_default: qup-uart8-default-state { 776 /* TX, RX */ 777 pins = "gpio24", "gpio25"; 778 function = "qup0_se8"; 779 drive-strength = <2>; 780 bias-pull-up; 781 }; 782 783 qup_uart8_cts_rts: qup-uart8-cts-rts-state { 784 /* CTS, RTS */ 785 pins = "gpio22", "gpio23"; 786 function = "qup0_se8"; 787 drive-strength = <2>; 788 bias-pull-down; 789 }; 790 791 qup_uart9_default: qup-uart9-default-state { 792 pins = "gpio26", "gpio27"; 793 function = "qup0_se9_23"; 794 drive-strength = <2>; 795 bias-disable; 796 }; 797 798 sdc1_state_on: sdc1-on-state { 799 clk-pins { 800 pins = "sdc1_clk"; 801 drive-strength = <6>; 802 bias-disable; 803 }; 804 805 cmd-pins { 806 pins = "sdc1_cmd"; 807 drive-strength = <6>; 808 bias-pull-up; 809 }; 810 811 data-pins { 812 pins = "sdc1_data"; 813 drive-strength = <6>; 814 bias-pull-up; 815 }; 816 817 rclk-pins { 818 pins = "sdc1_rclk"; 819 bias-pull-down; 820 }; 821 }; 822 823 sdc1_state_off: sdc1-off-state { 824 clk-pins { 825 pins = "sdc1_clk"; 826 drive-strength = <2>; 827 bias-bus-hold; 828 }; 829 830 cmd-pins { 831 pins = "sdc1_cmd"; 832 drive-strength = <2>; 833 bias-bus-hold; 834 }; 835 836 data-pins { 837 pins = "sdc1_data"; 838 drive-strength = <2>; 839 bias-bus-hold; 840 }; 841 842 rclk-pins { 843 pins = "sdc1_rclk"; 844 bias-bus-hold; 845 }; 846 }; 847 }; 848 849 pmu@c91000 { 850 compatible = "qcom,shikra-cpu-bwmon", "qcom,sc7280-llcc-bwmon"; 851 reg = <0x0 0x00c91000 0x0 0x1000>; 852 853 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH 0>; 854 855 interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG 856 &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>; 857 858 operating-points-v2 = <&cpu_bwmon_opp_table>; 859 860 cpu_bwmon_opp_table: opp-table { 861 compatible = "operating-points-v2"; 862 863 opp-0 { 864 opp-peak-kBps = <1200000>; 865 }; 866 867 opp-1 { 868 opp-peak-kBps = <2188000>; 869 }; 870 871 opp-2 { 872 opp-peak-kBps = <3072000>; 873 }; 874 875 opp-3 { 876 opp-peak-kBps = <4068000>; 877 }; 878 879 opp-4 { 880 opp-peak-kBps = <6220000>; 881 }; 882 883 opp-5 { 884 opp-peak-kBps = <7216000>; 885 }; 886 }; 887 }; 888 889 mem_noc: interconnect@d00000 { 890 compatible = "qcom,shikra-mem-noc-core"; 891 reg = <0x0 0x00d00000 0x0 0x43080>; 892 clocks = <&gcc GCC_DDRSS_GPU_AXI_CLK>; 893 clock-names = "gpu_axi"; 894 #interconnect-cells = <2>; 895 }; 896 897 llcc: system-cache-controller@e00000 { 898 compatible = "qcom,shikra-llcc"; 899 reg = <0x0 0x00e00000 0x0 0x80000>, 900 <0x0 0x00f00000 0x0 0x80000>, 901 <0x0 0x01000000 0x0 0x80000>; 902 reg-names = "llcc0_base", 903 "llcc1_base", 904 "llcc_broadcast_base"; 905 interrupts = <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH 0>; 906 }; 907 908 gcc: clock-controller@1400000 { 909 compatible = "qcom,shikra-gcc"; 910 reg = <0x0 0x01400000 0x0 0x1f0000>; 911 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 912 <&sleep_clk>, 913 <0>, 914 <0>, 915 <0>, 916 <0>, 917 <0>, 918 <0>; 919 power-domains = <&rpmpd RPMPD_VDDCX>; 920 #clock-cells = <1>; 921 #reset-cells = <1>; 922 #power-domain-cells = <1>; 923 }; 924 925 system_noc: interconnect@1880000 { 926 compatible = "qcom,shikra-sys-noc"; 927 reg = <0x0 0x01880000 0x0 0x6a080>; 928 clocks = <&gcc GCC_EMAC0_AXI_SYS_NOC_CLK>, 929 <&gcc GCC_EMAC1_AXI_SYS_NOC_CLK>, 930 <&gcc GCC_SYS_NOC_USB2_PRIM_AXI_CLK>, 931 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>; 932 clock-names = "emac0_axi", 933 "emac1_axi", 934 "usb2_axi", 935 "usb3_axi"; 936 #interconnect-cells = <2>; 937 938 clk_virt: interconnect-clk { 939 compatible = "qcom,shikra-clk-virt"; 940 #interconnect-cells = <2>; 941 }; 942 943 mc_virt: interconnect-mc { 944 compatible = "qcom,shikra-mc-virt"; 945 #interconnect-cells = <2>; 946 }; 947 948 mmrt_virt: interconnect-mmrt { 949 compatible = "qcom,shikra-mmrt-virt"; 950 #interconnect-cells = <2>; 951 }; 952 953 mmnrt_virt: interconnect-mmnrt { 954 compatible = "qcom,shikra-mmnrt-virt"; 955 #interconnect-cells = <2>; 956 }; 957 }; 958 959 config_noc: interconnect@1900000 { 960 compatible = "qcom,shikra-config-noc"; 961 reg = <0x0 0x01900000 0x0 0x8080>; 962 #interconnect-cells = <2>; 963 }; 964 965 qfprom: efuse@1b44000 { 966 compatible = "qcom,shikra-qfprom", "qcom,qfprom"; 967 reg = <0x0 0x01b44000 0x0 0x3000>; 968 #address-cells = <1>; 969 #size-cells = <1>; 970 971 qusb2_hstx_trim_1: hstx-trim@25b { 972 reg = <0x25b 0x1>; 973 bits = <1 4>; 974 }; 975 976 gpu_speed_bin: gpu-speed-bin@2006 { 977 reg = <0x2006 0x2>; 978 bits = <5 8>; 979 }; 980 }; 981 982 spmi_bus: spmi@1c40000 { 983 compatible = "qcom,spmi-pmic-arb"; 984 reg = <0x0 0x01c40000 0x0 0x1100>, 985 <0x0 0x01e00000 0x0 0x2000000>, 986 <0x0 0x03e00000 0x0 0x100000>, 987 <0x0 0x03f00000 0x0 0xa0000>, 988 <0x0 0x01c0a000 0x0 0x26000>; 989 reg-names = "core", 990 "chnls", 991 "obsrvr", 992 "intr", 993 "cnfg"; 994 interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>; 995 interrupt-names = "periph_irq"; 996 interrupt-controller; 997 #interrupt-cells = <4>; 998 #address-cells = <2>; 999 #size-cells = <0>; 1000 qcom,channel = <0>; 1001 qcom,ee = <0>; 1002 }; 1003 1004 tsens0: thermal-sensor@4411000 { 1005 compatible = "qcom,shikra-tsens", "qcom,tsens-v2"; 1006 reg = <0x0 0x04411000 0x0 0x1000>, 1007 <0x0 0x04410000 0x0 0x1000>; 1008 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>, 1009 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>; 1010 interrupt-names = "uplow", 1011 "critical"; 1012 #qcom,sensors = <14>; 1013 #thermal-sensor-cells = <1>; 1014 }; 1015 1016 rpm_msg_ram: sram@45f0000 { 1017 compatible = "qcom,rpm-msg-ram", "mmio-sram"; 1018 reg = <0x0 0x045f0000 0x0 0x7000>; 1019 1020 #address-cells = <1>; 1021 #size-cells = <1>; 1022 ranges = <0x0 0x0 0x045f0000 0x7000>; 1023 1024 apss_mpm: sram@1b8 { 1025 reg = <0x1b8 0x48>; 1026 }; 1027 }; 1028 1029 sram@4690000 { 1030 compatible = "qcom,rpm-stats"; 1031 reg = <0x0 0x04690000 0x0 0x14000>; 1032 }; 1033 1034 sdhc_1: mmc@4744000 { 1035 compatible = "qcom,shikra-sdhci", "qcom,sdhci-msm-v5"; 1036 1037 reg = <0x0 0x04744000 0x0 0x1000>, 1038 <0x0 0x04745000 0x0 0x1000>; 1039 reg-names = "hc", 1040 "cqhci"; 1041 1042 iommus = <&apps_smmu 0xc0 0x0>; 1043 1044 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>, 1045 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH 0>; 1046 interrupt-names = "hc_irq", 1047 "pwr_irq"; 1048 1049 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1050 <&gcc GCC_SDCC1_APPS_CLK>, 1051 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1052 clock-names = "iface", 1053 "core", 1054 "xo"; 1055 1056 interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG 1057 &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, 1058 <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG 1059 &config_noc SLAVE_SDCC_1 RPM_ACTIVE_TAG>; 1060 interconnect-names = "sdhc-ddr", 1061 "cpu-sdhc"; 1062 1063 power-domains = <&rpmpd RPMPD_VDDCX>; 1064 operating-points-v2 = <&sdhc1_opp_table>; 1065 1066 qcom,dll-config = <0x000f642c>; 1067 qcom,ddr-config = <0x80040868>; 1068 1069 bus-width = <8>; 1070 1071 mmc-ddr-1_8v; 1072 mmc-hs200-1_8v; 1073 mmc-hs400-1_8v; 1074 mmc-hs400-enhanced-strobe; 1075 1076 resets = <&gcc GCC_SDCC1_BCR>; 1077 1078 status = "disabled"; 1079 1080 sdhc1_opp_table: opp-table { 1081 compatible = "operating-points-v2"; 1082 1083 opp-100000000 { 1084 opp-hz = /bits/ 64 <100000000>; 1085 required-opps = <&rpmpd_opp_low_svs>; 1086 opp-peak-kBps = <250000 133320>; 1087 opp-avg-kBps = <104000 0>; 1088 }; 1089 1090 opp-384000000 { 1091 opp-hz = /bits/ 64 <384000000>; 1092 required-opps = <&rpmpd_opp_nom>; 1093 opp-peak-kBps = <800000 300000>; 1094 opp-avg-kBps = <400000 0>; 1095 }; 1096 }; 1097 }; 1098 1099 gpi_dma0: dma-controller@4a00000 { 1100 compatible = "qcom,shikra-gpi-dma", "qcom,sm6350-gpi-dma"; 1101 reg = <0x0 0x04a00000 0x0 0x60000>; 1102 1103 interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH 0>, 1104 <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH 0>, 1105 <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>, 1106 <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH 0>, 1107 <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH 0>, 1108 <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH 0>, 1109 <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>, 1110 <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH 0>, 1111 <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH 0>, 1112 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH 0>, 1113 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH 0>, 1114 <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH 0>, 1115 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH 0>, 1116 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH 0>, 1117 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH 0>, 1118 <GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH 0>; 1119 1120 dma-channels = <16>; 1121 dma-channel-mask = <0xff>; 1122 #dma-cells = <3>; 1123 1124 iommus = <&apps_smmu 0xf6 0x0>; 1125 }; 1126 1127 qupv3_0: geniqup@4ac0000 { 1128 compatible = "qcom,geni-se-qup"; 1129 reg = <0x0 0x04ac0000 0x0 0x2000>; 1130 1131 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1132 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1133 clock-names = "m-ahb", 1134 "s-ahb"; 1135 1136 iommus = <&apps_smmu 0xe3 0x0>; 1137 1138 #address-cells = <2>; 1139 #size-cells = <2>; 1140 ranges; 1141 1142 status = "disabled"; 1143 1144 i2c0: i2c@4a80000 { 1145 compatible = "qcom,geni-i2c"; 1146 reg = <0x0 0x4a80000 0x0 0x4000>; 1147 1148 interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH 0>; 1149 1150 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1151 clock-names = "se"; 1152 1153 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1154 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1155 <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1156 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1157 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1158 &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1159 interconnect-names = "qup-core", 1160 "qup-config", 1161 "qup-memory"; 1162 1163 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1164 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1165 dma-names = "tx", "rx"; 1166 1167 pinctrl-0 = <&qup_i2c0_data_clk>; 1168 pinctrl-names = "default"; 1169 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 1173 status = "disabled"; 1174 }; 1175 1176 spi0: spi@4a80000 { 1177 compatible = "qcom,geni-spi"; 1178 reg = <0x0 0x4a80000 0x0 0x4000>; 1179 1180 interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH 0>; 1181 1182 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1183 clock-names = "se"; 1184 1185 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1186 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1187 <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1188 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1189 interconnect-names = "qup-core", 1190 "qup-config"; 1191 1192 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1193 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1194 dma-names = "tx", "rx"; 1195 1196 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1197 pinctrl-names = "default"; 1198 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 1202 status = "disabled"; 1203 }; 1204 1205 uart0: serial@4a80000 { 1206 compatible = "qcom,geni-debug-uart"; 1207 reg = <0x0 0x04a80000 0x0 0x4000>; 1208 1209 interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH 0>; 1210 1211 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1212 clock-names = "se"; 1213 1214 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1215 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1216 <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1217 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1218 interconnect-names = "qup-core", 1219 "qup-config"; 1220 1221 pinctrl-0 = <&qup_uart0_default>; 1222 pinctrl-names = "default"; 1223 1224 status = "disabled"; 1225 }; 1226 1227 i2c1: i2c@4a84000 { 1228 compatible = "qcom,geni-i2c"; 1229 reg = <0x0 0x4a84000 0x0 0x4000>; 1230 1231 interrupts = <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH 0>; 1232 1233 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1234 clock-names = "se"; 1235 1236 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1237 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1238 <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1239 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1240 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1241 &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1242 interconnect-names = "qup-core", 1243 "qup-config", 1244 "qup-memory"; 1245 1246 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1247 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1248 dma-names = "tx", "rx"; 1249 1250 pinctrl-0 = <&qup_i2c1_data_clk>; 1251 pinctrl-names = "default"; 1252 1253 #address-cells = <1>; 1254 #size-cells = <0>; 1255 1256 status = "disabled"; 1257 }; 1258 1259 uart1: serial@4a84000 { 1260 compatible = "qcom,geni-uart"; 1261 reg = <0x0 0x04a84000 0x0 0x4000>; 1262 1263 interrupts = <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH 0>; 1264 1265 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1266 clock-names = "se"; 1267 1268 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1269 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1270 <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1271 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1272 interconnect-names = "qup-core", 1273 "qup-config"; 1274 1275 pinctrl-0 = <&qup_uart1_default>; 1276 pinctrl-names = "default"; 1277 1278 status = "disabled"; 1279 }; 1280 1281 i2c2: i2c@4a88000 { 1282 compatible = "qcom,geni-i2c"; 1283 reg = <0x0 0x4a88000 0x0 0x4000>; 1284 1285 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH 0>; 1286 1287 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1288 clock-names = "se"; 1289 1290 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1291 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1292 <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1293 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1294 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1295 &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1296 interconnect-names = "qup-core", 1297 "qup-config", 1298 "qup-memory"; 1299 1300 pinctrl-0 = <&qup_i2c2_data_clk>; 1301 pinctrl-names = "default"; 1302 1303 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1304 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1305 dma-names = "tx", "rx"; 1306 1307 #address-cells = <1>; 1308 #size-cells = <0>; 1309 1310 status = "disabled"; 1311 }; 1312 1313 spi2: spi@4a88000 { 1314 compatible = "qcom,geni-spi"; 1315 reg = <0x0 0x4a88000 0x0 0x4000>; 1316 1317 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH 0>; 1318 1319 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1320 clock-names = "se"; 1321 1322 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1323 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1324 <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1325 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1326 interconnect-names = "qup-core", 1327 "qup-config"; 1328 1329 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1330 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1331 dma-names = "tx", "rx"; 1332 1333 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1334 pinctrl-names = "default"; 1335 1336 #address-cells = <1>; 1337 #size-cells = <0>; 1338 1339 status = "disabled"; 1340 }; 1341 1342 uart2: serial@4a88000 { 1343 compatible = "qcom,geni-uart"; 1344 reg = <0x0 0x04a88000 0x0 0x4000>; 1345 1346 interrupts-extended = <&intc GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH 0>, 1347 <&tlmm 9 IRQ_TYPE_LEVEL_HIGH>; 1348 1349 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1350 clock-names = "se"; 1351 1352 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1353 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1354 <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1355 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1356 interconnect-names = "qup-core", 1357 "qup-config"; 1358 1359 pinctrl-0 = <&qup_uart2_default>, <&qup_uart2_cts_rts>; 1360 pinctrl-names = "default"; 1361 1362 status = "disabled"; 1363 }; 1364 1365 i2c3: i2c@4a8c000 { 1366 compatible = "qcom,geni-i2c"; 1367 reg = <0x0 0x4a8c000 0x0 0x4000>; 1368 1369 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; 1370 1371 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1372 clock-names = "se"; 1373 1374 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1375 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1376 <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1377 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1378 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1379 &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1380 interconnect-names = "qup-core", 1381 "qup-config", 1382 "qup-memory"; 1383 1384 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1385 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1386 dma-names = "tx", "rx"; 1387 1388 pinctrl-0 = <&qup_i2c3_data_clk>; 1389 pinctrl-names = "default"; 1390 1391 #address-cells = <1>; 1392 #size-cells = <0>; 1393 1394 status = "disabled"; 1395 }; 1396 1397 uart3: serial@4a8c000 { 1398 compatible = "qcom,geni-uart"; 1399 reg = <0x0 0x04a8c000 0x0 0x4000>; 1400 1401 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; 1402 1403 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1404 clock-names = "se"; 1405 1406 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1407 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1408 <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1409 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1410 interconnect-names = "qup-core", 1411 "qup-config"; 1412 1413 pinctrl-0 = <&qup_uart3_default>; 1414 pinctrl-names = "default"; 1415 1416 status = "disabled"; 1417 }; 1418 1419 i2c4: i2c@4a90000 { 1420 compatible = "qcom,geni-i2c"; 1421 reg = <0x0 0x4a90000 0x0 0x4000>; 1422 1423 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH 0>; 1424 1425 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1426 clock-names = "se"; 1427 1428 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1429 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1430 <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1431 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1432 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1433 &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1434 interconnect-names = "qup-core", 1435 "qup-config", 1436 "qup-memory"; 1437 1438 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1439 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1440 dma-names = "tx", "rx"; 1441 1442 pinctrl-0 = <&qup_i2c4_data_clk>; 1443 pinctrl-names = "default"; 1444 1445 #address-cells = <1>; 1446 #size-cells = <0>; 1447 1448 status = "disabled"; 1449 }; 1450 1451 uart4: serial@4a90000 { 1452 compatible = "qcom,geni-uart"; 1453 reg = <0x0 0x04a90000 0x0 0x4000>; 1454 1455 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH 0>; 1456 1457 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1458 clock-names = "se"; 1459 1460 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1461 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1462 <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1463 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1464 interconnect-names = "qup-core", 1465 "qup-config"; 1466 1467 pinctrl-0 = <&qup_uart4_default>; 1468 pinctrl-names = "default"; 1469 1470 status = "disabled"; 1471 }; 1472 1473 i2c5: i2c@4a94000 { 1474 compatible = "qcom,geni-i2c"; 1475 reg = <0x0 0x4a94000 0x0 0x4000>; 1476 1477 interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>; 1478 1479 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1480 clock-names = "se"; 1481 1482 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1483 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1484 <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1485 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1486 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1487 &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1488 interconnect-names = "qup-core", 1489 "qup-config", 1490 "qup-memory"; 1491 1492 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1493 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1494 dma-names = "tx", "rx"; 1495 1496 pinctrl-0 = <&qup_i2c5_data_clk>; 1497 pinctrl-names = "default"; 1498 1499 #address-cells = <1>; 1500 #size-cells = <0>; 1501 1502 status = "disabled"; 1503 }; 1504 1505 spi5: spi@4a94000 { 1506 compatible = "qcom,geni-spi"; 1507 reg = <0x0 0x4a94000 0x0 0x4000>; 1508 1509 interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>; 1510 1511 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1512 clock-names = "se"; 1513 1514 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1515 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1516 <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1517 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1518 interconnect-names = "qup-core", 1519 "qup-config"; 1520 1521 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1522 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1523 dma-names = "tx", "rx"; 1524 1525 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1526 pinctrl-names = "default"; 1527 1528 #address-cells = <1>; 1529 #size-cells = <0>; 1530 1531 status = "disabled"; 1532 }; 1533 1534 uart5: serial@4a94000 { 1535 compatible = "qcom,geni-uart"; 1536 reg = <0x0 0x04a94000 0x0 0x4000>; 1537 1538 interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>; 1539 1540 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1541 clock-names = "se"; 1542 1543 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1544 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1545 <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1546 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1547 interconnect-names = "qup-core", 1548 "qup-config"; 1549 1550 pinctrl-0 = <&qup_uart5_default>, <&qup_uart5_cts_rts>; 1551 pinctrl-names = "default"; 1552 1553 status = "disabled"; 1554 }; 1555 1556 i2c6: i2c@4a98000 { 1557 compatible = "qcom,geni-i2c"; 1558 reg = <0x0 0x4a98000 0x0 0x4000>; 1559 1560 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1561 1562 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1563 clock-names = "se"; 1564 1565 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1566 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1567 <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1568 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1569 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1570 &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1571 interconnect-names = "qup-core", 1572 "qup-config", 1573 "qup-memory"; 1574 1575 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1576 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1577 dma-names = "tx", "rx"; 1578 1579 pinctrl-0 = <&qup_i2c6_data_clk>; 1580 pinctrl-names = "default"; 1581 1582 #address-cells = <1>; 1583 #size-cells = <0>; 1584 1585 status = "disabled"; 1586 }; 1587 1588 spi6: spi@4a98000 { 1589 compatible = "qcom,geni-spi"; 1590 reg = <0x0 0x4a98000 0x0 0x4000>; 1591 1592 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1593 1594 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1595 clock-names = "se"; 1596 1597 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1598 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1599 <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1600 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1601 interconnect-names = "qup-core", 1602 "qup-config"; 1603 1604 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1605 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1606 dma-names = "tx", "rx"; 1607 1608 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1609 pinctrl-names = "default"; 1610 1611 #address-cells = <1>; 1612 #size-cells = <0>; 1613 1614 status = "disabled"; 1615 }; 1616 1617 uart6: serial@4a98000 { 1618 compatible = "qcom,geni-uart"; 1619 reg = <0x0 0x04a98000 0x0 0x4000>; 1620 1621 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1622 1623 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1624 clock-names = "se"; 1625 1626 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1627 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1628 <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1629 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1630 interconnect-names = "qup-core", 1631 "qup-config"; 1632 1633 pinctrl-0 = <&qup_uart6_default>, <&qup_uart6_cts_rts>; 1634 pinctrl-names = "default"; 1635 1636 status = "disabled"; 1637 }; 1638 1639 i2c7: i2c@4a9c000 { 1640 compatible = "qcom,geni-i2c"; 1641 reg = <0x0 0x4a9c000 0x0 0x4000>; 1642 1643 interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH 0>; 1644 1645 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1646 clock-names = "se"; 1647 1648 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1649 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1650 <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1651 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1652 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1653 &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1654 interconnect-names = "qup-core", 1655 "qup-config", 1656 "qup-memory"; 1657 1658 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1659 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1660 dma-names = "tx", "rx"; 1661 1662 pinctrl-0 = <&qup_i2c7_data_clk>; 1663 pinctrl-names = "default"; 1664 1665 #address-cells = <1>; 1666 #size-cells = <0>; 1667 1668 status = "disabled"; 1669 }; 1670 1671 uart7: serial@4a9c000 { 1672 compatible = "qcom,geni-uart"; 1673 reg = <0x0 0x04a9c000 0x0 0x4000>; 1674 1675 interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH 0>; 1676 1677 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1678 clock-names = "se"; 1679 1680 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1681 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1682 <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1683 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1684 interconnect-names = "qup-core", 1685 "qup-config"; 1686 1687 pinctrl-0 = <&qup_uart7_default>; 1688 pinctrl-names = "default"; 1689 1690 status = "disabled"; 1691 }; 1692 1693 i2c8: i2c@4aa0000 { 1694 compatible = "qcom,geni-i2c"; 1695 reg = <0x0 0x4aa0000 0x0 0x4000>; 1696 1697 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>; 1698 1699 clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>; 1700 clock-names = "se"; 1701 1702 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1703 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1704 <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1705 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1706 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1707 &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1708 interconnect-names = "qup-core", 1709 "qup-config", 1710 "qup-memory"; 1711 1712 dmas = <&gpi_dma0 0 8 QCOM_GPI_I2C>, 1713 <&gpi_dma0 1 8 QCOM_GPI_I2C>; 1714 dma-names = "tx", "rx"; 1715 1716 pinctrl-0 = <&qup_i2c8_data_clk>; 1717 pinctrl-names = "default"; 1718 1719 #address-cells = <1>; 1720 #size-cells = <0>; 1721 1722 status = "disabled"; 1723 }; 1724 1725 spi8: spi@4aa0000 { 1726 compatible = "qcom,geni-spi"; 1727 reg = <0x0 0x4aa0000 0x0 0x4000>; 1728 1729 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>; 1730 1731 clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>; 1732 clock-names = "se"; 1733 1734 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1735 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1736 <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1737 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1738 interconnect-names = "qup-core", 1739 "qup-config"; 1740 1741 dmas = <&gpi_dma0 0 8 QCOM_GPI_SPI>, 1742 <&gpi_dma0 1 8 QCOM_GPI_SPI>; 1743 dma-names = "tx", "rx"; 1744 1745 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1746 pinctrl-names = "default"; 1747 1748 #address-cells = <1>; 1749 #size-cells = <0>; 1750 1751 status = "disabled"; 1752 }; 1753 1754 uart8: serial@4aa0000 { 1755 compatible = "qcom,geni-uart"; 1756 reg = <0x0 0x04aa0000 0x0 0x4000>; 1757 1758 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>; 1759 1760 clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>; 1761 clock-names = "se"; 1762 1763 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1764 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1765 <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1766 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1767 interconnect-names = "qup-core", 1768 "qup-config"; 1769 1770 pinctrl-0 = <&qup_uart8_default>, <&qup_uart8_cts_rts>; 1771 pinctrl-names = "default"; 1772 1773 status = "disabled"; 1774 }; 1775 1776 i2c9: i2c@4aa4000 { 1777 compatible = "qcom,geni-i2c"; 1778 reg = <0x0 0x4aa4000 0x0 0x4000>; 1779 1780 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1781 1782 clocks = <&gcc GCC_QUPV3_WRAP0_S9_CLK>; 1783 clock-names = "se"; 1784 1785 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1786 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1787 <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1788 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1789 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1790 &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1791 interconnect-names = "qup-core", 1792 "qup-config", 1793 "qup-memory"; 1794 1795 dmas = <&gpi_dma0 0 9 QCOM_GPI_I2C>, 1796 <&gpi_dma0 1 9 QCOM_GPI_I2C>; 1797 dma-names = "tx", "rx"; 1798 1799 pinctrl-0 = <&qup_i2c9_data_clk>; 1800 pinctrl-names = "default"; 1801 1802 #address-cells = <1>; 1803 #size-cells = <0>; 1804 1805 status = "disabled"; 1806 }; 1807 1808 uart9: serial@4aa4000 { 1809 compatible = "qcom,geni-uart"; 1810 reg = <0x0 0x04aa4000 0x0 0x4000>; 1811 1812 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1813 1814 clocks = <&gcc GCC_QUPV3_WRAP0_S9_CLK>; 1815 clock-names = "se"; 1816 1817 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1818 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1819 <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1820 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1821 interconnect-names = "qup-core", 1822 "qup-config"; 1823 1824 pinctrl-0 = <&qup_uart9_default>; 1825 pinctrl-names = "default"; 1826 1827 status = "disabled"; 1828 }; 1829 }; 1830 1831 remoteproc_mpss: remoteproc@6080000 { 1832 compatible = "qcom,shikra-mpss-pas"; 1833 reg = <0x0 0x06080000 0x0 0x100>; 1834 1835 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING 0>, 1836 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1837 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1838 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1839 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1840 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1841 interrupt-names = "wdog", 1842 "fatal", 1843 "ready", 1844 "handover", 1845 "stop-ack", 1846 "shutdown-ack"; 1847 1848 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1849 clock-names = "xo"; 1850 1851 interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1852 &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1853 1854 power-domains = <&rpmpd RPMHPD_CX>; 1855 1856 memory-region = <&mpss_wlan_mem>; 1857 1858 qcom,smem-states = <&modem_smp2p_out 0>; 1859 qcom,smem-state-names = "stop"; 1860 1861 status = "disabled"; 1862 1863 glink-edge { 1864 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING 0>; 1865 mboxes = <&apcs_glb 12>; 1866 qcom,remote-pid = <1>; 1867 label = "mpss"; 1868 }; 1869 }; 1870 1871 remoteproc_cdsp: remoteproc@b300000 { 1872 compatible = "qcom,shikra-cdsp-pas"; 1873 reg = <0x0 0x0b300000 0x0 0x100000>; 1874 1875 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING 0>, 1876 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1877 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1878 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1879 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1880 <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1881 interrupt-names = "wdog", 1882 "fatal", 1883 "ready", 1884 "handover", 1885 "stop-ack", 1886 "shutdown-ack"; 1887 1888 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1889 clock-names = "xo"; 1890 1891 interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1892 &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1893 1894 power-domains = <&rpmpd RPMHPD_CX>; 1895 1896 memory-region = <&cdsp_mem>; 1897 1898 qcom,smem-states = <&cdsp_smp2p_out 0>; 1899 qcom,smem-state-names = "stop"; 1900 1901 status = "disabled"; 1902 1903 glink-edge { 1904 interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING 0>; 1905 mboxes = <&apcs_glb 4>; 1906 qcom,remote-pid = <5>; 1907 label = "cdsp"; 1908 1909 fastrpc { 1910 compatible = "qcom,fastrpc"; 1911 #address-cells = <1>; 1912 #size-cells = <0>; 1913 label = "cdsp"; 1914 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1915 1916 compute-cb@1 { 1917 compatible = "qcom,fastrpc-compute-cb"; 1918 reg = <1>; 1919 iommus = <&apps_smmu 0x0201 0x0000>; 1920 }; 1921 1922 compute-cb@2 { 1923 compatible = "qcom,fastrpc-compute-cb"; 1924 reg = <2>; 1925 iommus = <&apps_smmu 0x0202 0x0000>; 1926 }; 1927 1928 compute-cb@3 { 1929 compatible = "qcom,fastrpc-compute-cb"; 1930 reg = <3>; 1931 iommus = <&apps_smmu 0x0203 0x0000>; 1932 }; 1933 1934 compute-cb@4 { 1935 compatible = "qcom,fastrpc-compute-cb"; 1936 reg = <4>; 1937 iommus = <&apps_smmu 0x0204 0x0000>; 1938 }; 1939 1940 compute-cb@5 { 1941 compatible = "qcom,fastrpc-compute-cb"; 1942 reg = <5>; 1943 iommus = <&apps_smmu 0x0205 0x0000>; 1944 }; 1945 1946 compute-cb@6 { 1947 compatible = "qcom,fastrpc-compute-cb"; 1948 reg = <6>; 1949 iommus = <&apps_smmu 0x0206 0x0000>; 1950 }; 1951 1952 compute-cb@9 { 1953 compatible = "qcom,fastrpc-compute-cb"; 1954 reg = <9>; 1955 iommus = <&apps_smmu 0x0209 0x0000>; 1956 }; 1957 }; 1958 }; 1959 }; 1960 1961 remoteproc_lpaicp: remoteproc@b800000 { 1962 compatible = "qcom,shikra-lpaicp-pas"; 1963 reg = <0x0 0x0b800000 0x0 0x200000>; 1964 1965 interrupts-extended = <&intc GIC_SPI 257 IRQ_TYPE_EDGE_RISING 0>, 1966 <&lmcu_smp2p_in 0 IRQ_TYPE_NONE>, 1967 <&lmcu_smp2p_in 1 IRQ_TYPE_NONE>, 1968 <&lmcu_smp2p_in 2 IRQ_TYPE_NONE>, 1969 <&lmcu_smp2p_in 3 IRQ_TYPE_NONE>; 1970 1971 interrupt-names = "wdog", 1972 "fatal", 1973 "ready", 1974 "handover", 1975 "stop-ack"; 1976 1977 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1978 clock-names = "xo"; 1979 1980 memory-region = <&lmcu_mem &lmcu_dtb_mem>; 1981 1982 qcom,smem-states = <&lmcu_smp2p_out 0>; 1983 qcom,smem-state-names = "stop"; 1984 1985 status = "disabled"; 1986 1987 glink-edge { 1988 interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING 0>; 1989 mboxes = <&apcs_glb 9>; 1990 qcom,remote-pid = <26>; 1991 label = "lpaicp"; 1992 }; 1993 }; 1994 1995 gpucc: clock-controller@5990000 { 1996 compatible = "qcom,shikra-gpucc"; 1997 reg = <0x0 0x05990000 0x0 0x9000>; 1998 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1999 <&rpmcc RPM_SMD_XO_CLK_SRC>, 2000 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2001 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2002 power-domains = <&rpmpd RPMPD_VDDCX>; 2003 #clock-cells = <1>; 2004 #reset-cells = <1>; 2005 #power-domain-cells = <1>; 2006 }; 2007 2008 dispcc: clock-controller@5f00000 { 2009 compatible = "qcom,shikra-dispcc", "qcom,qcm2290-dispcc"; 2010 reg = <0x0 0x05f00000 0x0 0x20000>; 2011 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 2012 <&rpmcc RPM_SMD_XO_A_CLK_SRC>, 2013 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2014 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 2015 <0>, 2016 <0>; 2017 clock-names = "bi_tcxo", 2018 "bi_tcxo_ao", 2019 "gcc_disp_gpll0_clk_src", 2020 "gcc_disp_gpll0_div_clk_src", 2021 "dsi0_phy_pll_out_byteclk", 2022 "dsi0_phy_pll_out_dsiclk"; 2023 power-domains = <&rpmpd RPMPD_VDDCX>; 2024 #clock-cells = <1>; 2025 #reset-cells = <1>; 2026 #power-domain-cells = <1>; 2027 }; 2028 2029 sram@c11e000 { 2030 compatible = "qcom,shikra-imem", "mmio-sram"; 2031 reg = <0x0 0x0c11e000 0x0 0x1000>; 2032 ranges = <0x0 0x0 0x0c11e000 0x1000>; 2033 2034 no-memory-wc; 2035 2036 #address-cells = <1>; 2037 #size-cells = <1>; 2038 2039 pil-sram@94c { 2040 compatible = "qcom,pil-reloc-info"; 2041 reg = <0x94c 0xc8>; 2042 }; 2043 }; 2044 2045 apps_smmu: iommu@c600000 { 2046 compatible = "qcom,shikra-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2047 reg = <0x0 0x0c600000 0x0 0x80000>; 2048 #iommu-cells = <2>; 2049 #global-interrupts = <1>; 2050 2051 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>, 2052 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>, 2053 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>, 2054 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>, 2055 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>, 2056 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>, 2057 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>, 2058 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>, 2059 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>, 2060 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>, 2061 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>, 2062 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>, 2063 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>, 2064 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>, 2065 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>, 2066 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, 2067 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>, 2068 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 2069 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 2070 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>, 2071 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>, 2072 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>, 2073 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 2074 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 2075 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>, 2076 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>, 2077 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>, 2078 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>, 2079 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 2080 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>, 2081 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>, 2082 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>, 2083 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>, 2084 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>, 2085 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>, 2086 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>, 2087 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>, 2088 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>, 2089 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>, 2090 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>, 2091 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>, 2092 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>, 2093 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>, 2094 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>, 2095 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, 2096 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, 2097 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>, 2098 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>, 2099 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH 0>, 2100 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>, 2101 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>, 2102 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH 0>, 2103 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>, 2104 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>, 2105 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH 0>, 2106 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>, 2107 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>, 2108 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>, 2109 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>, 2110 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>, 2111 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>, 2112 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>, 2113 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>, 2114 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>, 2115 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 2116 }; 2117 2118 wifi: wifi@c800000 { 2119 compatible = "qcom,wcn3990-wifi"; 2120 reg = <0x0 0x0c800000 0x0 0x800000>; 2121 reg-names = "membase"; 2122 memory-region = <&wlan_mem>; 2123 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>, 2124 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 0>, 2125 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>, 2126 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>, 2127 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>, 2128 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>, 2129 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0>, 2130 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 0>, 2131 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 0>, 2132 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>, 2133 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH 0>, 2134 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>; 2135 iommus = <&apps_smmu 0x1a0 0x1>; 2136 qcom,msa-fixed-perm; 2137 2138 status = "disabled"; 2139 }; 2140 2141 intc: interrupt-controller@f200000 { 2142 compatible = "arm,gic-v3"; 2143 reg = <0x0 0xf200000 0x0 0x10000>, 2144 <0x0 0xf240000 0x0 0x80000>; 2145 2146 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 2147 2148 #interrupt-cells = <4>; 2149 interrupt-controller; 2150 2151 #redistributor-regions = <1>; 2152 redistributor-stride = <0x0 0x20000>; 2153 2154 #address-cells = <2>; 2155 #size-cells = <2>; 2156 ranges; 2157 2158 ppi-partitions { 2159 ppi_cluster0: interrupt-partition-0 { 2160 affinity = <&cpu0 &cpu1 &cpu2>; 2161 }; 2162 2163 ppi_cluster1: interrupt-partition-1 { 2164 affinity = <&cpu3>; 2165 }; 2166 }; 2167 }; 2168 2169 apcs_glb: mailbox@f400000 { 2170 compatible = "qcom,shikra-apss-shared", "qcom,sdm845-apss-shared"; 2171 reg = <0x0 0x0f400000 0x0 0x1000>; 2172 #mbox-cells = <1>; 2173 }; 2174 2175 watchdog@f410000 { 2176 compatible = "qcom,apss-wdt-shikra", "qcom,kpss-wdt"; 2177 reg = <0x0 0x0f410000 0x0 0x1000>; 2178 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>, 2179 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>; 2180 clocks = <&sleep_clk>; 2181 }; 2182 2183 timer@f420000 { 2184 compatible = "arm,armv7-timer-mem"; 2185 reg = <0x0 0x0f420000 0x0 0x1000>; 2186 2187 #address-cells = <1>; 2188 #size-cells = <1>; 2189 ranges = <0x0 0x0 0x0 0x10000000>; 2190 2191 frame@f421000 { 2192 reg = <0x0f421000 0x1000>, 2193 <0x0f422000 0x1000>; 2194 frame-number = <0>; 2195 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>, 2196 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 2197 }; 2198 2199 frame@f423000 { 2200 reg = <0x0f423000 0x1000>; 2201 frame-number = <1>; 2202 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 2203 status = "disabled"; 2204 }; 2205 2206 frame@f425000 { 2207 reg = <0x0f425000 0x1000>; 2208 frame-number = <2>; 2209 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 2210 status = "disabled"; 2211 }; 2212 2213 frame@f427000 { 2214 reg = <0x0f427000 0x1000>; 2215 frame-number = <3>; 2216 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 2217 status = "disabled"; 2218 }; 2219 2220 frame@f429000 { 2221 reg = <0x0f429000 0x1000>; 2222 frame-number = <4>; 2223 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 2224 status = "disabled"; 2225 }; 2226 2227 frame@f42b000 { 2228 reg = <0x0f42b000 0x1000>; 2229 frame-number = <5>; 2230 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>; 2231 status = "disabled"; 2232 }; 2233 2234 frame@f42d000 { 2235 reg = <0x0f42d000 0x1000>; 2236 frame-number = <6>; 2237 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 2238 status = "disabled"; 2239 }; 2240 }; 2241 2242 epss_l3: interconnect@fd90000 { 2243 compatible = "qcom,shikra-epss-l3"; 2244 reg = <0x0 0x0fd90000 0x0 0x1000>; 2245 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 2246 clock-names = "xo", "alternate"; 2247 #interconnect-cells = <1>; 2248 }; 2249 2250 cpufreq_hw: cpufreq@fd91000 { 2251 compatible = "qcom,shikra-epss"; 2252 reg = <0x0 0x0fd91000 0x0 0x1000>, 2253 <0x0 0x0fd92000 0x0 0x1000>; 2254 reg-names = "freq-domain0", 2255 "freq-domain1"; 2256 2257 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 2258 clock-names = "xo", "alternate"; 2259 2260 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>, 2261 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 2262 interrupt-names = "dcvsh-irq-0", 2263 "dcvsh-irq-1"; 2264 2265 #freq-domain-cells = <1>; 2266 #clock-cells = <1>; 2267 }; 2268 }; 2269 2270 thermal_zones: thermal-zones { 2271 aoss0-thermal { 2272 thermal-sensors = <&tsens0 0>; 2273 2274 trips { 2275 trip-point0 { 2276 temperature = <110000>; 2277 hysteresis = <5000>; 2278 type = "hot"; 2279 }; 2280 2281 aoss0-critical { 2282 temperature = <115000>; 2283 hysteresis = <0>; 2284 type = "critical"; 2285 }; 2286 }; 2287 }; 2288 2289 cpu-0-0-thermal { 2290 thermal-sensors = <&tsens0 1>; 2291 2292 trips { 2293 trip-point0 { 2294 temperature = <110000>; 2295 hysteresis = <5000>; 2296 type = "hot"; 2297 }; 2298 2299 cpu00-critical { 2300 temperature = <115000>; 2301 hysteresis = <0>; 2302 type = "critical"; 2303 }; 2304 }; 2305 }; 2306 2307 cpu-0-1-thermal { 2308 thermal-sensors = <&tsens0 2>; 2309 2310 trips { 2311 trip-point0 { 2312 temperature = <110000>; 2313 hysteresis = <5000>; 2314 type = "hot"; 2315 }; 2316 2317 cpu01-critical { 2318 temperature = <115000>; 2319 hysteresis = <0>; 2320 type = "critical"; 2321 }; 2322 }; 2323 }; 2324 2325 cpu-1-0-thermal { 2326 thermal-sensors = <&tsens0 3>; 2327 2328 trips { 2329 trip-point0 { 2330 temperature = <110000>; 2331 hysteresis = <5000>; 2332 type = "hot"; 2333 }; 2334 2335 cpu10-critical { 2336 temperature = <115000>; 2337 hysteresis = <0>; 2338 type = "critical"; 2339 }; 2340 }; 2341 }; 2342 2343 cpu-1-1-thermal { 2344 thermal-sensors = <&tsens0 4>; 2345 2346 trips { 2347 trip-point0 { 2348 temperature = <110000>; 2349 hysteresis = <5000>; 2350 type = "hot"; 2351 }; 2352 2353 cpu11-critical { 2354 temperature = <115000>; 2355 hysteresis = <0>; 2356 type = "critical"; 2357 }; 2358 }; 2359 }; 2360 2361 cpuss0-thermal { 2362 thermal-sensors = <&tsens0 5>; 2363 2364 trips { 2365 trip-point0 { 2366 temperature = <110000>; 2367 hysteresis = <5000>; 2368 type = "hot"; 2369 }; 2370 2371 cpuss0-critical { 2372 temperature = <115000>; 2373 hysteresis = <0>; 2374 type = "critical"; 2375 }; 2376 }; 2377 }; 2378 2379 gpuss-thermal { 2380 thermal-sensors = <&tsens0 6>; 2381 2382 trips { 2383 trip-point0 { 2384 temperature = <110000>; 2385 hysteresis = <5000>; 2386 type = "hot"; 2387 }; 2388 2389 gpuss-critical { 2390 temperature = <115000>; 2391 hysteresis = <0>; 2392 type = "critical"; 2393 }; 2394 }; 2395 }; 2396 2397 nsp-thermal { 2398 thermal-sensors = <&tsens0 7>; 2399 2400 trips { 2401 trip-point0 { 2402 temperature = <110000>; 2403 hysteresis = <5000>; 2404 type = "hot"; 2405 }; 2406 2407 nsp-critical { 2408 temperature = <115000>; 2409 hysteresis = <0>; 2410 type = "critical"; 2411 }; 2412 }; 2413 }; 2414 2415 mdmss0-thermal { 2416 thermal-sensors = <&tsens0 8>; 2417 2418 trips { 2419 trip-point0 { 2420 temperature = <110000>; 2421 hysteresis = <5000>; 2422 type = "hot"; 2423 }; 2424 2425 mdmss0-critical { 2426 temperature = <115000>; 2427 hysteresis = <0>; 2428 type = "critical"; 2429 }; 2430 }; 2431 }; 2432 2433 mdmss1-thermal { 2434 thermal-sensors = <&tsens0 9>; 2435 2436 trips { 2437 trip-point0 { 2438 temperature = <110000>; 2439 hysteresis = <5000>; 2440 type = "hot"; 2441 }; 2442 2443 mdmss1-critical { 2444 temperature = <115000>; 2445 hysteresis = <0>; 2446 type = "critical"; 2447 }; 2448 }; 2449 }; 2450 2451 camera-thermal { 2452 thermal-sensors = <&tsens0 10>; 2453 2454 trips { 2455 trip-point0 { 2456 temperature = <110000>; 2457 hysteresis = <5000>; 2458 type = "hot"; 2459 }; 2460 2461 camera-critical { 2462 temperature = <115000>; 2463 hysteresis = <0>; 2464 type = "critical"; 2465 }; 2466 }; 2467 }; 2468 2469 video-thermal { 2470 thermal-sensors = <&tsens0 11>; 2471 2472 trips { 2473 trip-point0 { 2474 temperature = <110000>; 2475 hysteresis = <5000>; 2476 type = "hot"; 2477 }; 2478 2479 video-critical { 2480 temperature = <115000>; 2481 hysteresis = <0>; 2482 type = "critical"; 2483 }; 2484 }; 2485 }; 2486 2487 cpu-0-2-thermal { 2488 thermal-sensors = <&tsens0 12>; 2489 2490 trips { 2491 trip-point0 { 2492 temperature = <110000>; 2493 hysteresis = <5000>; 2494 type = "hot"; 2495 }; 2496 2497 cpu02-critical { 2498 temperature = <115000>; 2499 hysteresis = <0>; 2500 type = "critical"; 2501 }; 2502 }; 2503 }; 2504 2505 cpuss1-thermal { 2506 thermal-sensors = <&tsens0 13>; 2507 2508 trips { 2509 trip-point0 { 2510 temperature = <110000>; 2511 hysteresis = <5000>; 2512 type = "hot"; 2513 }; 2514 2515 cpuss1-critical { 2516 temperature = <115000>; 2517 hysteresis = <0>; 2518 type = "critical"; 2519 }; 2520 }; 2521 }; 2522 }; 2523 2524 timer { 2525 compatible = "arm,armv8-timer"; 2526 2527 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW 0>, 2528 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW 0>, 2529 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW 0>, 2530 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW 0>; 2531 }; 2532}; 2533