1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,camcc-sdm845.h> 9#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 10#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 11#include <dt-bindings/clock/qcom,gcc-sdm845.h> 12#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 13#include <dt-bindings/clock/qcom,lpass-sdm845.h> 14#include <dt-bindings/clock/qcom,rpmh.h> 15#include <dt-bindings/clock/qcom,videocc-sdm845.h> 16#include <dt-bindings/dma/qcom-gpi.h> 17#include <dt-bindings/firmware/qcom,scm.h> 18#include <dt-bindings/gpio/gpio.h> 19#include <dt-bindings/interconnect/qcom,icc.h> 20#include <dt-bindings/interconnect/qcom,osm-l3.h> 21#include <dt-bindings/interconnect/qcom,sdm845.h> 22#include <dt-bindings/interrupt-controller/arm-gic.h> 23#include <dt-bindings/phy/phy-qcom-qmp.h> 24#include <dt-bindings/phy/phy-qcom-qusb2.h> 25#include <dt-bindings/power/qcom-rpmpd.h> 26#include <dt-bindings/reset/qcom,sdm845-aoss.h> 27#include <dt-bindings/reset/qcom,sdm845-pdc.h> 28#include <dt-bindings/soc/qcom,apr.h> 29#include <dt-bindings/soc/qcom,rpmh-rsc.h> 30#include <dt-bindings/clock/qcom,gcc-sdm845.h> 31#include <dt-bindings/thermal/thermal.h> 32 33/ { 34 interrupt-parent = <&intc>; 35 36 #address-cells = <2>; 37 #size-cells = <2>; 38 39 aliases { 40 i2c0 = &i2c0; 41 i2c1 = &i2c1; 42 i2c2 = &i2c2; 43 i2c3 = &i2c3; 44 i2c4 = &i2c4; 45 i2c5 = &i2c5; 46 i2c6 = &i2c6; 47 i2c7 = &i2c7; 48 i2c8 = &i2c8; 49 i2c9 = &i2c9; 50 i2c10 = &i2c10; 51 i2c11 = &i2c11; 52 i2c12 = &i2c12; 53 i2c13 = &i2c13; 54 i2c14 = &i2c14; 55 i2c15 = &i2c15; 56 spi0 = &spi0; 57 spi1 = &spi1; 58 spi2 = &spi2; 59 spi3 = &spi3; 60 spi4 = &spi4; 61 spi5 = &spi5; 62 spi6 = &spi6; 63 spi7 = &spi7; 64 spi8 = &spi8; 65 spi9 = &spi9; 66 spi10 = &spi10; 67 spi11 = &spi11; 68 spi12 = &spi12; 69 spi13 = &spi13; 70 spi14 = &spi14; 71 spi15 = &spi15; 72 }; 73 74 chosen { }; 75 76 clocks { 77 xo_board: xo-board { 78 compatible = "fixed-clock"; 79 #clock-cells = <0>; 80 clock-frequency = <38400000>; 81 clock-output-names = "xo_board"; 82 }; 83 84 sleep_clk: sleep-clk { 85 compatible = "fixed-clock"; 86 #clock-cells = <0>; 87 clock-frequency = <32764>; 88 }; 89 }; 90 91 cpus: cpus { 92 #address-cells = <2>; 93 #size-cells = <0>; 94 95 cpu0: cpu@0 { 96 device_type = "cpu"; 97 compatible = "qcom,kryo385"; 98 reg = <0x0 0x0>; 99 clocks = <&cpufreq_hw 0>; 100 enable-method = "psci"; 101 capacity-dmips-mhz = <611>; 102 dynamic-power-coefficient = <154>; 103 qcom,freq-domain = <&cpufreq_hw 0>; 104 operating-points-v2 = <&cpu0_opp_table>; 105 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 106 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 107 power-domains = <&cpu_pd0>; 108 power-domain-names = "psci"; 109 #cooling-cells = <2>; 110 next-level-cache = <&l2_0>; 111 l2_0: l2-cache { 112 compatible = "cache"; 113 cache-level = <2>; 114 cache-unified; 115 next-level-cache = <&l3_0>; 116 l3_0: l3-cache { 117 compatible = "cache"; 118 cache-level = <3>; 119 cache-unified; 120 }; 121 }; 122 }; 123 124 cpu1: cpu@100 { 125 device_type = "cpu"; 126 compatible = "qcom,kryo385"; 127 reg = <0x0 0x100>; 128 clocks = <&cpufreq_hw 0>; 129 enable-method = "psci"; 130 capacity-dmips-mhz = <611>; 131 dynamic-power-coefficient = <154>; 132 qcom,freq-domain = <&cpufreq_hw 0>; 133 operating-points-v2 = <&cpu0_opp_table>; 134 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 135 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 136 power-domains = <&cpu_pd1>; 137 power-domain-names = "psci"; 138 #cooling-cells = <2>; 139 next-level-cache = <&l2_100>; 140 l2_100: l2-cache { 141 compatible = "cache"; 142 cache-level = <2>; 143 cache-unified; 144 next-level-cache = <&l3_0>; 145 }; 146 }; 147 148 cpu2: cpu@200 { 149 device_type = "cpu"; 150 compatible = "qcom,kryo385"; 151 reg = <0x0 0x200>; 152 clocks = <&cpufreq_hw 0>; 153 enable-method = "psci"; 154 capacity-dmips-mhz = <611>; 155 dynamic-power-coefficient = <154>; 156 qcom,freq-domain = <&cpufreq_hw 0>; 157 operating-points-v2 = <&cpu0_opp_table>; 158 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 159 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 160 power-domains = <&cpu_pd2>; 161 power-domain-names = "psci"; 162 #cooling-cells = <2>; 163 next-level-cache = <&l2_200>; 164 l2_200: l2-cache { 165 compatible = "cache"; 166 cache-level = <2>; 167 cache-unified; 168 next-level-cache = <&l3_0>; 169 }; 170 }; 171 172 cpu3: cpu@300 { 173 device_type = "cpu"; 174 compatible = "qcom,kryo385"; 175 reg = <0x0 0x300>; 176 clocks = <&cpufreq_hw 0>; 177 enable-method = "psci"; 178 capacity-dmips-mhz = <611>; 179 dynamic-power-coefficient = <154>; 180 qcom,freq-domain = <&cpufreq_hw 0>; 181 operating-points-v2 = <&cpu0_opp_table>; 182 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 183 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 184 #cooling-cells = <2>; 185 power-domains = <&cpu_pd3>; 186 power-domain-names = "psci"; 187 next-level-cache = <&l2_300>; 188 l2_300: l2-cache { 189 compatible = "cache"; 190 cache-level = <2>; 191 cache-unified; 192 next-level-cache = <&l3_0>; 193 }; 194 }; 195 196 cpu4: cpu@400 { 197 device_type = "cpu"; 198 compatible = "qcom,kryo385"; 199 reg = <0x0 0x400>; 200 clocks = <&cpufreq_hw 1>; 201 enable-method = "psci"; 202 capacity-dmips-mhz = <1024>; 203 dynamic-power-coefficient = <442>; 204 qcom,freq-domain = <&cpufreq_hw 1>; 205 operating-points-v2 = <&cpu4_opp_table>; 206 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 207 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 208 power-domains = <&cpu_pd4>; 209 power-domain-names = "psci"; 210 #cooling-cells = <2>; 211 next-level-cache = <&l2_400>; 212 l2_400: l2-cache { 213 compatible = "cache"; 214 cache-level = <2>; 215 cache-unified; 216 next-level-cache = <&l3_0>; 217 }; 218 }; 219 220 cpu5: cpu@500 { 221 device_type = "cpu"; 222 compatible = "qcom,kryo385"; 223 reg = <0x0 0x500>; 224 clocks = <&cpufreq_hw 1>; 225 enable-method = "psci"; 226 capacity-dmips-mhz = <1024>; 227 dynamic-power-coefficient = <442>; 228 qcom,freq-domain = <&cpufreq_hw 1>; 229 operating-points-v2 = <&cpu4_opp_table>; 230 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 231 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 232 power-domains = <&cpu_pd5>; 233 power-domain-names = "psci"; 234 #cooling-cells = <2>; 235 next-level-cache = <&l2_500>; 236 l2_500: l2-cache { 237 compatible = "cache"; 238 cache-level = <2>; 239 cache-unified; 240 next-level-cache = <&l3_0>; 241 }; 242 }; 243 244 cpu6: cpu@600 { 245 device_type = "cpu"; 246 compatible = "qcom,kryo385"; 247 reg = <0x0 0x600>; 248 clocks = <&cpufreq_hw 1>; 249 enable-method = "psci"; 250 capacity-dmips-mhz = <1024>; 251 dynamic-power-coefficient = <442>; 252 qcom,freq-domain = <&cpufreq_hw 1>; 253 operating-points-v2 = <&cpu4_opp_table>; 254 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 255 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 256 power-domains = <&cpu_pd6>; 257 power-domain-names = "psci"; 258 #cooling-cells = <2>; 259 next-level-cache = <&l2_600>; 260 l2_600: l2-cache { 261 compatible = "cache"; 262 cache-level = <2>; 263 cache-unified; 264 next-level-cache = <&l3_0>; 265 }; 266 }; 267 268 cpu7: cpu@700 { 269 device_type = "cpu"; 270 compatible = "qcom,kryo385"; 271 reg = <0x0 0x700>; 272 clocks = <&cpufreq_hw 1>; 273 enable-method = "psci"; 274 capacity-dmips-mhz = <1024>; 275 dynamic-power-coefficient = <442>; 276 qcom,freq-domain = <&cpufreq_hw 1>; 277 operating-points-v2 = <&cpu4_opp_table>; 278 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 279 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 280 power-domains = <&cpu_pd7>; 281 power-domain-names = "psci"; 282 #cooling-cells = <2>; 283 next-level-cache = <&l2_700>; 284 l2_700: l2-cache { 285 compatible = "cache"; 286 cache-level = <2>; 287 cache-unified; 288 next-level-cache = <&l3_0>; 289 }; 290 }; 291 292 cpu-map { 293 cluster0 { 294 core0 { 295 cpu = <&cpu0>; 296 }; 297 298 core1 { 299 cpu = <&cpu1>; 300 }; 301 302 core2 { 303 cpu = <&cpu2>; 304 }; 305 306 core3 { 307 cpu = <&cpu3>; 308 }; 309 310 core4 { 311 cpu = <&cpu4>; 312 }; 313 314 core5 { 315 cpu = <&cpu5>; 316 }; 317 318 core6 { 319 cpu = <&cpu6>; 320 }; 321 322 core7 { 323 cpu = <&cpu7>; 324 }; 325 }; 326 }; 327 328 cpu_idle_states: idle-states { 329 entry-method = "psci"; 330 331 little_cpu_sleep_0: cpu-sleep-0-0 { 332 compatible = "arm,idle-state"; 333 idle-state-name = "little-rail-power-collapse"; 334 arm,psci-suspend-param = <0x40000004>; 335 entry-latency-us = <350>; 336 exit-latency-us = <461>; 337 min-residency-us = <1890>; 338 local-timer-stop; 339 }; 340 341 big_cpu_sleep_0: cpu-sleep-1-0 { 342 compatible = "arm,idle-state"; 343 idle-state-name = "big-rail-power-collapse"; 344 arm,psci-suspend-param = <0x40000004>; 345 entry-latency-us = <264>; 346 exit-latency-us = <621>; 347 min-residency-us = <952>; 348 local-timer-stop; 349 }; 350 }; 351 352 domain-idle-states { 353 cluster_sleep_0: cluster-sleep-0 { 354 compatible = "domain-idle-state"; 355 arm,psci-suspend-param = <0x4100c244>; 356 entry-latency-us = <3263>; 357 exit-latency-us = <6562>; 358 min-residency-us = <9987>; 359 }; 360 }; 361 }; 362 363 firmware { 364 scm { 365 compatible = "qcom,scm-sdm845", "qcom,scm"; 366 }; 367 }; 368 369 memory@80000000 { 370 device_type = "memory"; 371 /* We expect the bootloader to fill in the size */ 372 reg = <0 0x80000000 0 0>; 373 }; 374 375 cpu0_opp_table: opp-table-cpu0 { 376 compatible = "operating-points-v2"; 377 opp-shared; 378 379 cpu0_opp1: opp-300000000 { 380 opp-hz = /bits/ 64 <300000000>; 381 opp-peak-kBps = <800000 4800000>; 382 }; 383 384 cpu0_opp2: opp-403200000 { 385 opp-hz = /bits/ 64 <403200000>; 386 opp-peak-kBps = <800000 4800000>; 387 }; 388 389 cpu0_opp3: opp-480000000 { 390 opp-hz = /bits/ 64 <480000000>; 391 opp-peak-kBps = <800000 6451200>; 392 }; 393 394 cpu0_opp4: opp-576000000 { 395 opp-hz = /bits/ 64 <576000000>; 396 opp-peak-kBps = <800000 6451200>; 397 }; 398 399 cpu0_opp5: opp-652800000 { 400 opp-hz = /bits/ 64 <652800000>; 401 opp-peak-kBps = <800000 7680000>; 402 }; 403 404 cpu0_opp6: opp-748800000 { 405 opp-hz = /bits/ 64 <748800000>; 406 opp-peak-kBps = <1804000 9216000>; 407 }; 408 409 cpu0_opp7: opp-825600000 { 410 opp-hz = /bits/ 64 <825600000>; 411 opp-peak-kBps = <1804000 9216000>; 412 }; 413 414 cpu0_opp8: opp-902400000 { 415 opp-hz = /bits/ 64 <902400000>; 416 opp-peak-kBps = <1804000 10444800>; 417 }; 418 419 cpu0_opp9: opp-979200000 { 420 opp-hz = /bits/ 64 <979200000>; 421 opp-peak-kBps = <1804000 11980800>; 422 }; 423 424 cpu0_opp10: opp-1056000000 { 425 opp-hz = /bits/ 64 <1056000000>; 426 opp-peak-kBps = <1804000 11980800>; 427 }; 428 429 cpu0_opp11: opp-1132800000 { 430 opp-hz = /bits/ 64 <1132800000>; 431 opp-peak-kBps = <2188000 13516800>; 432 }; 433 434 cpu0_opp12: opp-1228800000 { 435 opp-hz = /bits/ 64 <1228800000>; 436 opp-peak-kBps = <2188000 15052800>; 437 }; 438 439 cpu0_opp13: opp-1324800000 { 440 opp-hz = /bits/ 64 <1324800000>; 441 opp-peak-kBps = <2188000 16588800>; 442 }; 443 444 cpu0_opp14: opp-1420800000 { 445 opp-hz = /bits/ 64 <1420800000>; 446 opp-peak-kBps = <3072000 18124800>; 447 }; 448 449 cpu0_opp15: opp-1516800000 { 450 opp-hz = /bits/ 64 <1516800000>; 451 opp-peak-kBps = <3072000 19353600>; 452 }; 453 454 cpu0_opp16: opp-1612800000 { 455 opp-hz = /bits/ 64 <1612800000>; 456 opp-peak-kBps = <4068000 19353600>; 457 }; 458 459 cpu0_opp17: opp-1689600000 { 460 opp-hz = /bits/ 64 <1689600000>; 461 opp-peak-kBps = <4068000 20889600>; 462 }; 463 464 cpu0_opp18: opp-1766400000 { 465 opp-hz = /bits/ 64 <1766400000>; 466 opp-peak-kBps = <4068000 22425600>; 467 }; 468 }; 469 470 cpu4_opp_table: opp-table-cpu4 { 471 compatible = "operating-points-v2"; 472 opp-shared; 473 474 cpu4_opp1: opp-300000000 { 475 opp-hz = /bits/ 64 <300000000>; 476 opp-peak-kBps = <800000 4800000>; 477 }; 478 479 cpu4_opp2: opp-403200000 { 480 opp-hz = /bits/ 64 <403200000>; 481 opp-peak-kBps = <800000 4800000>; 482 }; 483 484 cpu4_opp3: opp-480000000 { 485 opp-hz = /bits/ 64 <480000000>; 486 opp-peak-kBps = <1804000 4800000>; 487 }; 488 489 cpu4_opp4: opp-576000000 { 490 opp-hz = /bits/ 64 <576000000>; 491 opp-peak-kBps = <1804000 4800000>; 492 }; 493 494 cpu4_opp5: opp-652800000 { 495 opp-hz = /bits/ 64 <652800000>; 496 opp-peak-kBps = <1804000 4800000>; 497 }; 498 499 cpu4_opp6: opp-748800000 { 500 opp-hz = /bits/ 64 <748800000>; 501 opp-peak-kBps = <1804000 4800000>; 502 }; 503 504 cpu4_opp7: opp-825600000 { 505 opp-hz = /bits/ 64 <825600000>; 506 opp-peak-kBps = <2188000 9216000>; 507 }; 508 509 cpu4_opp8: opp-902400000 { 510 opp-hz = /bits/ 64 <902400000>; 511 opp-peak-kBps = <2188000 9216000>; 512 }; 513 514 cpu4_opp9: opp-979200000 { 515 opp-hz = /bits/ 64 <979200000>; 516 opp-peak-kBps = <2188000 9216000>; 517 }; 518 519 cpu4_opp10: opp-1056000000 { 520 opp-hz = /bits/ 64 <1056000000>; 521 opp-peak-kBps = <3072000 9216000>; 522 }; 523 524 cpu4_opp11: opp-1132800000 { 525 opp-hz = /bits/ 64 <1132800000>; 526 opp-peak-kBps = <3072000 11980800>; 527 }; 528 529 cpu4_opp12: opp-1209600000 { 530 opp-hz = /bits/ 64 <1209600000>; 531 opp-peak-kBps = <4068000 11980800>; 532 }; 533 534 cpu4_opp13: opp-1286400000 { 535 opp-hz = /bits/ 64 <1286400000>; 536 opp-peak-kBps = <4068000 11980800>; 537 }; 538 539 cpu4_opp14: opp-1363200000 { 540 opp-hz = /bits/ 64 <1363200000>; 541 opp-peak-kBps = <4068000 15052800>; 542 }; 543 544 cpu4_opp15: opp-1459200000 { 545 opp-hz = /bits/ 64 <1459200000>; 546 opp-peak-kBps = <4068000 15052800>; 547 }; 548 549 cpu4_opp16: opp-1536000000 { 550 opp-hz = /bits/ 64 <1536000000>; 551 opp-peak-kBps = <5412000 15052800>; 552 }; 553 554 cpu4_opp17: opp-1612800000 { 555 opp-hz = /bits/ 64 <1612800000>; 556 opp-peak-kBps = <5412000 15052800>; 557 }; 558 559 cpu4_opp18: opp-1689600000 { 560 opp-hz = /bits/ 64 <1689600000>; 561 opp-peak-kBps = <5412000 19353600>; 562 }; 563 564 cpu4_opp19: opp-1766400000 { 565 opp-hz = /bits/ 64 <1766400000>; 566 opp-peak-kBps = <6220000 19353600>; 567 }; 568 569 cpu4_opp20: opp-1843200000 { 570 opp-hz = /bits/ 64 <1843200000>; 571 opp-peak-kBps = <6220000 19353600>; 572 }; 573 574 cpu4_opp21: opp-1920000000 { 575 opp-hz = /bits/ 64 <1920000000>; 576 opp-peak-kBps = <7216000 19353600>; 577 }; 578 579 cpu4_opp22: opp-1996800000 { 580 opp-hz = /bits/ 64 <1996800000>; 581 opp-peak-kBps = <7216000 20889600>; 582 }; 583 584 cpu4_opp23: opp-2092800000 { 585 opp-hz = /bits/ 64 <2092800000>; 586 opp-peak-kBps = <7216000 20889600>; 587 }; 588 589 cpu4_opp24: opp-2169600000 { 590 opp-hz = /bits/ 64 <2169600000>; 591 opp-peak-kBps = <7216000 20889600>; 592 }; 593 594 cpu4_opp25: opp-2246400000 { 595 opp-hz = /bits/ 64 <2246400000>; 596 opp-peak-kBps = <7216000 20889600>; 597 }; 598 599 cpu4_opp26: opp-2323200000 { 600 opp-hz = /bits/ 64 <2323200000>; 601 opp-peak-kBps = <7216000 20889600>; 602 }; 603 604 cpu4_opp27: opp-2400000000 { 605 opp-hz = /bits/ 64 <2400000000>; 606 opp-peak-kBps = <7216000 22425600>; 607 }; 608 609 cpu4_opp28: opp-2476800000 { 610 opp-hz = /bits/ 64 <2476800000>; 611 opp-peak-kBps = <7216000 22425600>; 612 }; 613 614 cpu4_opp29: opp-2553600000 { 615 opp-hz = /bits/ 64 <2553600000>; 616 opp-peak-kBps = <7216000 22425600>; 617 }; 618 619 cpu4_opp30: opp-2649600000 { 620 opp-hz = /bits/ 64 <2649600000>; 621 opp-peak-kBps = <7216000 22425600>; 622 }; 623 624 cpu4_opp31: opp-2745600000 { 625 opp-hz = /bits/ 64 <2745600000>; 626 opp-peak-kBps = <7216000 25497600>; 627 }; 628 629 cpu4_opp32: opp-2803200000 { 630 opp-hz = /bits/ 64 <2803200000>; 631 opp-peak-kBps = <7216000 25497600>; 632 }; 633 }; 634 635 dsi_opp_table: opp-table-dsi { 636 compatible = "operating-points-v2"; 637 638 opp-19200000 { 639 opp-hz = /bits/ 64 <19200000>; 640 required-opps = <&rpmhpd_opp_min_svs>; 641 }; 642 643 opp-180000000 { 644 opp-hz = /bits/ 64 <180000000>; 645 required-opps = <&rpmhpd_opp_low_svs>; 646 }; 647 648 opp-275000000 { 649 opp-hz = /bits/ 64 <275000000>; 650 required-opps = <&rpmhpd_opp_svs>; 651 }; 652 653 opp-328580000 { 654 opp-hz = /bits/ 64 <328580000>; 655 required-opps = <&rpmhpd_opp_svs_l1>; 656 }; 657 658 opp-358000000 { 659 opp-hz = /bits/ 64 <358000000>; 660 required-opps = <&rpmhpd_opp_nom>; 661 }; 662 }; 663 664 qspi_opp_table: opp-table-qspi { 665 compatible = "operating-points-v2"; 666 667 opp-19200000 { 668 opp-hz = /bits/ 64 <19200000>; 669 required-opps = <&rpmhpd_opp_min_svs>; 670 }; 671 672 opp-100000000 { 673 opp-hz = /bits/ 64 <100000000>; 674 required-opps = <&rpmhpd_opp_low_svs>; 675 }; 676 677 opp-150000000 { 678 opp-hz = /bits/ 64 <150000000>; 679 required-opps = <&rpmhpd_opp_svs>; 680 }; 681 682 opp-300000000 { 683 opp-hz = /bits/ 64 <300000000>; 684 required-opps = <&rpmhpd_opp_nom>; 685 }; 686 }; 687 688 qup_opp_table: opp-table-qup { 689 compatible = "operating-points-v2"; 690 691 opp-50000000 { 692 opp-hz = /bits/ 64 <50000000>; 693 required-opps = <&rpmhpd_opp_min_svs>; 694 }; 695 696 opp-75000000 { 697 opp-hz = /bits/ 64 <75000000>; 698 required-opps = <&rpmhpd_opp_low_svs>; 699 }; 700 701 opp-100000000 { 702 opp-hz = /bits/ 64 <100000000>; 703 required-opps = <&rpmhpd_opp_svs>; 704 }; 705 706 opp-128000000 { 707 opp-hz = /bits/ 64 <128000000>; 708 required-opps = <&rpmhpd_opp_nom>; 709 }; 710 }; 711 712 pmu { 713 compatible = "arm,armv8-pmuv3"; 714 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 715 }; 716 717 psci: psci { 718 compatible = "arm,psci-1.0"; 719 method = "smc"; 720 721 cpu_pd0: power-domain-cpu0 { 722 #power-domain-cells = <0>; 723 power-domains = <&cluster_pd>; 724 domain-idle-states = <&little_cpu_sleep_0>; 725 }; 726 727 cpu_pd1: power-domain-cpu1 { 728 #power-domain-cells = <0>; 729 power-domains = <&cluster_pd>; 730 domain-idle-states = <&little_cpu_sleep_0>; 731 }; 732 733 cpu_pd2: power-domain-cpu2 { 734 #power-domain-cells = <0>; 735 power-domains = <&cluster_pd>; 736 domain-idle-states = <&little_cpu_sleep_0>; 737 }; 738 739 cpu_pd3: power-domain-cpu3 { 740 #power-domain-cells = <0>; 741 power-domains = <&cluster_pd>; 742 domain-idle-states = <&little_cpu_sleep_0>; 743 }; 744 745 cpu_pd4: power-domain-cpu4 { 746 #power-domain-cells = <0>; 747 power-domains = <&cluster_pd>; 748 domain-idle-states = <&big_cpu_sleep_0>; 749 }; 750 751 cpu_pd5: power-domain-cpu5 { 752 #power-domain-cells = <0>; 753 power-domains = <&cluster_pd>; 754 domain-idle-states = <&big_cpu_sleep_0>; 755 }; 756 757 cpu_pd6: power-domain-cpu6 { 758 #power-domain-cells = <0>; 759 power-domains = <&cluster_pd>; 760 domain-idle-states = <&big_cpu_sleep_0>; 761 }; 762 763 cpu_pd7: power-domain-cpu7 { 764 #power-domain-cells = <0>; 765 power-domains = <&cluster_pd>; 766 domain-idle-states = <&big_cpu_sleep_0>; 767 }; 768 769 cluster_pd: power-domain-cluster { 770 #power-domain-cells = <0>; 771 domain-idle-states = <&cluster_sleep_0>; 772 }; 773 }; 774 775 reserved-memory { 776 #address-cells = <2>; 777 #size-cells = <2>; 778 ranges; 779 780 hyp_mem: hyp-mem@85700000 { 781 reg = <0 0x85700000 0 0x600000>; 782 no-map; 783 }; 784 785 xbl_mem: xbl-mem@85e00000 { 786 reg = <0 0x85e00000 0 0x100000>; 787 no-map; 788 }; 789 790 aop_mem: aop-mem@85fc0000 { 791 reg = <0 0x85fc0000 0 0x20000>; 792 no-map; 793 }; 794 795 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { 796 compatible = "qcom,cmd-db"; 797 reg = <0x0 0x85fe0000 0 0x20000>; 798 no-map; 799 }; 800 801 smem@86000000 { 802 compatible = "qcom,smem"; 803 reg = <0x0 0x86000000 0 0x200000>; 804 no-map; 805 hwlocks = <&tcsr_mutex 3>; 806 }; 807 808 tz_mem: tz@86200000 { 809 reg = <0 0x86200000 0 0x2d00000>; 810 no-map; 811 }; 812 813 rmtfs_mem: rmtfs@88f00000 { 814 compatible = "qcom,rmtfs-mem"; 815 reg = <0 0x88f00000 0 0x200000>; 816 no-map; 817 818 qcom,client-id = <1>; 819 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 820 }; 821 822 qseecom_mem: qseecom@8ab00000 { 823 reg = <0 0x8ab00000 0 0x1400000>; 824 no-map; 825 }; 826 827 camera_mem: camera-mem@8bf00000 { 828 reg = <0 0x8bf00000 0 0x500000>; 829 no-map; 830 }; 831 832 ipa_fw_mem: ipa-fw@8c400000 { 833 reg = <0 0x8c400000 0 0x10000>; 834 no-map; 835 }; 836 837 ipa_gsi_mem: ipa-gsi@8c410000 { 838 reg = <0 0x8c410000 0 0x5000>; 839 no-map; 840 }; 841 842 gpu_mem: gpu@8c415000 { 843 reg = <0 0x8c415000 0 0x2000>; 844 no-map; 845 }; 846 847 adsp_mem: adsp@8c500000 { 848 reg = <0 0x8c500000 0 0x1a00000>; 849 no-map; 850 }; 851 852 wlan_msa_mem: wlan-msa@8df00000 { 853 reg = <0 0x8df00000 0 0x100000>; 854 no-map; 855 }; 856 857 mpss_region: mpss@8e000000 { 858 reg = <0 0x8e000000 0 0x7800000>; 859 no-map; 860 }; 861 862 venus_mem: venus@95800000 { 863 reg = <0 0x95800000 0 0x500000>; 864 no-map; 865 }; 866 867 cdsp_mem: cdsp@95d00000 { 868 reg = <0 0x95d00000 0 0x800000>; 869 no-map; 870 }; 871 872 mba_region: mba@96500000 { 873 reg = <0 0x96500000 0 0x200000>; 874 no-map; 875 }; 876 877 slpi_mem: slpi@96700000 { 878 reg = <0 0x96700000 0 0x1400000>; 879 no-map; 880 }; 881 882 spss_mem: spss@97b00000 { 883 reg = <0 0x97b00000 0 0x100000>; 884 no-map; 885 }; 886 887 mdata_mem: mpss-metadata { 888 alloc-ranges = <0 0xa0000000 0 0x20000000>; 889 size = <0 0x4000>; 890 no-map; 891 }; 892 893 fastrpc_mem: fastrpc { 894 compatible = "shared-dma-pool"; 895 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; 896 alignment = <0x0 0x400000>; 897 size = <0x0 0x1000000>; 898 reusable; 899 }; 900 }; 901 902 adsp_pas: remoteproc-adsp { 903 compatible = "qcom,sdm845-adsp-pas"; 904 905 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 906 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 907 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 908 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 909 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 910 interrupt-names = "wdog", "fatal", "ready", 911 "handover", "stop-ack"; 912 913 clocks = <&rpmhcc RPMH_CXO_CLK>; 914 clock-names = "xo"; 915 916 memory-region = <&adsp_mem>; 917 918 qcom,qmp = <&aoss_qmp>; 919 920 qcom,smem-states = <&adsp_smp2p_out 0>; 921 qcom,smem-state-names = "stop"; 922 923 status = "disabled"; 924 925 glink-edge { 926 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 927 label = "lpass"; 928 qcom,remote-pid = <2>; 929 mboxes = <&apss_shared 8>; 930 931 apr { 932 compatible = "qcom,apr-v2"; 933 qcom,glink-channels = "apr_audio_svc"; 934 qcom,domain = <APR_DOMAIN_ADSP>; 935 #address-cells = <1>; 936 #size-cells = <0>; 937 qcom,intents = <512 20>; 938 939 service@3 { 940 reg = <APR_SVC_ADSP_CORE>; 941 compatible = "qcom,q6core"; 942 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 943 }; 944 945 q6afe: service@4 { 946 compatible = "qcom,q6afe"; 947 reg = <APR_SVC_AFE>; 948 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 949 q6afedai: dais { 950 compatible = "qcom,q6afe-dais"; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 #sound-dai-cells = <1>; 954 }; 955 }; 956 957 q6asm: service@7 { 958 compatible = "qcom,q6asm"; 959 reg = <APR_SVC_ASM>; 960 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 961 q6asmdai: dais { 962 compatible = "qcom,q6asm-dais"; 963 #address-cells = <1>; 964 #size-cells = <0>; 965 #sound-dai-cells = <1>; 966 iommus = <&apps_smmu 0x1821 0x0>; 967 }; 968 }; 969 970 q6adm: service@8 { 971 compatible = "qcom,q6adm"; 972 reg = <APR_SVC_ADM>; 973 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 974 q6routing: routing { 975 compatible = "qcom,q6adm-routing"; 976 #sound-dai-cells = <0>; 977 }; 978 }; 979 }; 980 981 fastrpc { 982 compatible = "qcom,fastrpc"; 983 qcom,glink-channels = "fastrpcglink-apps-dsp"; 984 label = "adsp"; 985 qcom,non-secure-domain; 986 #address-cells = <1>; 987 #size-cells = <0>; 988 989 compute-cb@3 { 990 compatible = "qcom,fastrpc-compute-cb"; 991 reg = <3>; 992 iommus = <&apps_smmu 0x1823 0x0>; 993 }; 994 995 compute-cb@4 { 996 compatible = "qcom,fastrpc-compute-cb"; 997 reg = <4>; 998 iommus = <&apps_smmu 0x1824 0x0>; 999 }; 1000 }; 1001 }; 1002 }; 1003 1004 cdsp_pas: remoteproc-cdsp { 1005 compatible = "qcom,sdm845-cdsp-pas"; 1006 1007 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 1008 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1009 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1010 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1011 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1012 interrupt-names = "wdog", "fatal", "ready", 1013 "handover", "stop-ack"; 1014 1015 clocks = <&rpmhcc RPMH_CXO_CLK>; 1016 clock-names = "xo"; 1017 1018 memory-region = <&cdsp_mem>; 1019 1020 qcom,qmp = <&aoss_qmp>; 1021 1022 qcom,smem-states = <&cdsp_smp2p_out 0>; 1023 qcom,smem-state-names = "stop"; 1024 1025 status = "disabled"; 1026 1027 glink-edge { 1028 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 1029 label = "turing"; 1030 qcom,remote-pid = <5>; 1031 mboxes = <&apss_shared 4>; 1032 fastrpc { 1033 compatible = "qcom,fastrpc"; 1034 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1035 label = "cdsp"; 1036 qcom,non-secure-domain; 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 1040 compute-cb@1 { 1041 compatible = "qcom,fastrpc-compute-cb"; 1042 reg = <1>; 1043 iommus = <&apps_smmu 0x1401 0x30>; 1044 }; 1045 1046 compute-cb@2 { 1047 compatible = "qcom,fastrpc-compute-cb"; 1048 reg = <2>; 1049 iommus = <&apps_smmu 0x1402 0x30>; 1050 }; 1051 1052 compute-cb@3 { 1053 compatible = "qcom,fastrpc-compute-cb"; 1054 reg = <3>; 1055 iommus = <&apps_smmu 0x1403 0x30>; 1056 }; 1057 1058 compute-cb@4 { 1059 compatible = "qcom,fastrpc-compute-cb"; 1060 reg = <4>; 1061 iommus = <&apps_smmu 0x1404 0x30>; 1062 }; 1063 1064 compute-cb@5 { 1065 compatible = "qcom,fastrpc-compute-cb"; 1066 reg = <5>; 1067 iommus = <&apps_smmu 0x1405 0x30>; 1068 }; 1069 1070 compute-cb@6 { 1071 compatible = "qcom,fastrpc-compute-cb"; 1072 reg = <6>; 1073 iommus = <&apps_smmu 0x1406 0x30>; 1074 }; 1075 1076 compute-cb@7 { 1077 compatible = "qcom,fastrpc-compute-cb"; 1078 reg = <7>; 1079 iommus = <&apps_smmu 0x1407 0x30>; 1080 }; 1081 1082 compute-cb@8 { 1083 compatible = "qcom,fastrpc-compute-cb"; 1084 reg = <8>; 1085 iommus = <&apps_smmu 0x1408 0x30>; 1086 }; 1087 }; 1088 }; 1089 }; 1090 1091 smp2p-cdsp { 1092 compatible = "qcom,smp2p"; 1093 qcom,smem = <94>, <432>; 1094 1095 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 1096 1097 mboxes = <&apss_shared 6>; 1098 1099 qcom,local-pid = <0>; 1100 qcom,remote-pid = <5>; 1101 1102 cdsp_smp2p_out: master-kernel { 1103 qcom,entry-name = "master-kernel"; 1104 #qcom,smem-state-cells = <1>; 1105 }; 1106 1107 cdsp_smp2p_in: slave-kernel { 1108 qcom,entry-name = "slave-kernel"; 1109 1110 interrupt-controller; 1111 #interrupt-cells = <2>; 1112 }; 1113 }; 1114 1115 smp2p-lpass { 1116 compatible = "qcom,smp2p"; 1117 qcom,smem = <443>, <429>; 1118 1119 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 1120 1121 mboxes = <&apss_shared 10>; 1122 1123 qcom,local-pid = <0>; 1124 qcom,remote-pid = <2>; 1125 1126 adsp_smp2p_out: master-kernel { 1127 qcom,entry-name = "master-kernel"; 1128 #qcom,smem-state-cells = <1>; 1129 }; 1130 1131 adsp_smp2p_in: slave-kernel { 1132 qcom,entry-name = "slave-kernel"; 1133 1134 interrupt-controller; 1135 #interrupt-cells = <2>; 1136 }; 1137 }; 1138 1139 smp2p-mpss { 1140 compatible = "qcom,smp2p"; 1141 qcom,smem = <435>, <428>; 1142 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 1143 mboxes = <&apss_shared 14>; 1144 qcom,local-pid = <0>; 1145 qcom,remote-pid = <1>; 1146 1147 modem_smp2p_out: master-kernel { 1148 qcom,entry-name = "master-kernel"; 1149 #qcom,smem-state-cells = <1>; 1150 }; 1151 1152 modem_smp2p_in: slave-kernel { 1153 qcom,entry-name = "slave-kernel"; 1154 interrupt-controller; 1155 #interrupt-cells = <2>; 1156 }; 1157 1158 ipa_smp2p_out: ipa-ap-to-modem { 1159 qcom,entry-name = "ipa"; 1160 #qcom,smem-state-cells = <1>; 1161 }; 1162 1163 ipa_smp2p_in: ipa-modem-to-ap { 1164 qcom,entry-name = "ipa"; 1165 interrupt-controller; 1166 #interrupt-cells = <2>; 1167 }; 1168 }; 1169 1170 smp2p-slpi { 1171 compatible = "qcom,smp2p"; 1172 qcom,smem = <481>, <430>; 1173 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 1174 mboxes = <&apss_shared 26>; 1175 qcom,local-pid = <0>; 1176 qcom,remote-pid = <3>; 1177 1178 slpi_smp2p_out: master-kernel { 1179 qcom,entry-name = "master-kernel"; 1180 #qcom,smem-state-cells = <1>; 1181 }; 1182 1183 slpi_smp2p_in: slave-kernel { 1184 qcom,entry-name = "slave-kernel"; 1185 interrupt-controller; 1186 #interrupt-cells = <2>; 1187 }; 1188 }; 1189 1190 soc: soc@0 { 1191 #address-cells = <2>; 1192 #size-cells = <2>; 1193 ranges = <0 0 0 0 0x10 0>; 1194 dma-ranges = <0 0 0 0 0x10 0>; 1195 compatible = "simple-bus"; 1196 1197 gcc: clock-controller@100000 { 1198 compatible = "qcom,gcc-sdm845"; 1199 reg = <0 0x00100000 0 0x1f0000>; 1200 clocks = <&rpmhcc RPMH_CXO_CLK>, 1201 <&rpmhcc RPMH_CXO_CLK_A>, 1202 <&sleep_clk>, 1203 <&pcie0_phy>, 1204 <&pcie1_phy>; 1205 clock-names = "bi_tcxo", 1206 "bi_tcxo_ao", 1207 "sleep_clk", 1208 "pcie_0_pipe_clk", 1209 "pcie_1_pipe_clk"; 1210 #clock-cells = <1>; 1211 #reset-cells = <1>; 1212 #power-domain-cells = <1>; 1213 power-domains = <&rpmhpd SDM845_CX>; 1214 }; 1215 1216 qfprom@784000 { 1217 compatible = "qcom,sdm845-qfprom", "qcom,qfprom"; 1218 reg = <0 0x00784000 0 0x8ff>; 1219 #address-cells = <1>; 1220 #size-cells = <1>; 1221 1222 qusb2p_hstx_trim: hstx-trim-primary@1eb { 1223 reg = <0x1eb 0x1>; 1224 bits = <1 4>; 1225 }; 1226 1227 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 1228 reg = <0x1eb 0x2>; 1229 bits = <6 4>; 1230 }; 1231 }; 1232 1233 rng: rng@793000 { 1234 compatible = "qcom,prng-ee"; 1235 reg = <0 0x00793000 0 0x1000>; 1236 clocks = <&gcc GCC_PRNG_AHB_CLK>; 1237 clock-names = "core"; 1238 }; 1239 1240 gpi_dma0: dma-controller@800000 { 1241 #dma-cells = <3>; 1242 compatible = "qcom,sdm845-gpi-dma"; 1243 reg = <0 0x00800000 0 0x60000>; 1244 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1257 dma-channels = <13>; 1258 dma-channel-mask = <0xfa>; 1259 iommus = <&apps_smmu 0x0016 0x0>; 1260 status = "disabled"; 1261 }; 1262 1263 qupv3_id_0: geniqup@8c0000 { 1264 compatible = "qcom,geni-se-qup"; 1265 reg = <0 0x008c0000 0 0x6000>; 1266 clock-names = "m-ahb", "s-ahb"; 1267 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1268 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1269 iommus = <&apps_smmu 0x3 0x0>; 1270 #address-cells = <2>; 1271 #size-cells = <2>; 1272 ranges; 1273 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>; 1274 interconnect-names = "qup-core"; 1275 status = "disabled"; 1276 1277 i2c0: i2c@880000 { 1278 compatible = "qcom,geni-i2c"; 1279 reg = <0 0x00880000 0 0x4000>; 1280 clock-names = "se"; 1281 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1282 pinctrl-names = "default"; 1283 pinctrl-0 = <&qup_i2c0_default>; 1284 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1285 #address-cells = <1>; 1286 #size-cells = <0>; 1287 power-domains = <&rpmhpd SDM845_CX>; 1288 operating-points-v2 = <&qup_opp_table>; 1289 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1290 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1291 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1292 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1293 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1294 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1295 dma-names = "tx", "rx"; 1296 status = "disabled"; 1297 }; 1298 1299 spi0: spi@880000 { 1300 compatible = "qcom,geni-spi"; 1301 reg = <0 0x00880000 0 0x4000>; 1302 clock-names = "se"; 1303 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1304 pinctrl-names = "default"; 1305 pinctrl-0 = <&qup_spi0_default>; 1306 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1307 #address-cells = <1>; 1308 #size-cells = <0>; 1309 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1310 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1311 interconnect-names = "qup-core", "qup-config"; 1312 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1313 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1314 dma-names = "tx", "rx"; 1315 status = "disabled"; 1316 }; 1317 1318 uart0: serial@880000 { 1319 compatible = "qcom,geni-uart"; 1320 reg = <0 0x00880000 0 0x4000>; 1321 clock-names = "se"; 1322 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1323 pinctrl-names = "default"; 1324 pinctrl-0 = <&qup_uart0_default>; 1325 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1326 power-domains = <&rpmhpd SDM845_CX>; 1327 operating-points-v2 = <&qup_opp_table>; 1328 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1329 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1330 interconnect-names = "qup-core", "qup-config"; 1331 status = "disabled"; 1332 }; 1333 1334 i2c1: i2c@884000 { 1335 compatible = "qcom,geni-i2c"; 1336 reg = <0 0x00884000 0 0x4000>; 1337 clock-names = "se"; 1338 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1339 pinctrl-names = "default"; 1340 pinctrl-0 = <&qup_i2c1_default>; 1341 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1342 #address-cells = <1>; 1343 #size-cells = <0>; 1344 power-domains = <&rpmhpd SDM845_CX>; 1345 operating-points-v2 = <&qup_opp_table>; 1346 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1347 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1348 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1349 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1350 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1351 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1352 dma-names = "tx", "rx"; 1353 status = "disabled"; 1354 }; 1355 1356 spi1: spi@884000 { 1357 compatible = "qcom,geni-spi"; 1358 reg = <0 0x00884000 0 0x4000>; 1359 clock-names = "se"; 1360 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1361 pinctrl-names = "default"; 1362 pinctrl-0 = <&qup_spi1_default>; 1363 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1364 #address-cells = <1>; 1365 #size-cells = <0>; 1366 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1367 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1368 interconnect-names = "qup-core", "qup-config"; 1369 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1370 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1371 dma-names = "tx", "rx"; 1372 status = "disabled"; 1373 }; 1374 1375 uart1: serial@884000 { 1376 compatible = "qcom,geni-uart"; 1377 reg = <0 0x00884000 0 0x4000>; 1378 clock-names = "se"; 1379 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1380 pinctrl-names = "default"; 1381 pinctrl-0 = <&qup_uart1_default>; 1382 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1383 power-domains = <&rpmhpd SDM845_CX>; 1384 operating-points-v2 = <&qup_opp_table>; 1385 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1386 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1387 interconnect-names = "qup-core", "qup-config"; 1388 status = "disabled"; 1389 }; 1390 1391 i2c2: i2c@888000 { 1392 compatible = "qcom,geni-i2c"; 1393 reg = <0 0x00888000 0 0x4000>; 1394 clock-names = "se"; 1395 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1396 pinctrl-names = "default"; 1397 pinctrl-0 = <&qup_i2c2_default>; 1398 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1399 #address-cells = <1>; 1400 #size-cells = <0>; 1401 power-domains = <&rpmhpd SDM845_CX>; 1402 operating-points-v2 = <&qup_opp_table>; 1403 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1404 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1405 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1406 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1407 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1408 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1409 dma-names = "tx", "rx"; 1410 status = "disabled"; 1411 }; 1412 1413 spi2: spi@888000 { 1414 compatible = "qcom,geni-spi"; 1415 reg = <0 0x00888000 0 0x4000>; 1416 clock-names = "se"; 1417 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1418 pinctrl-names = "default"; 1419 pinctrl-0 = <&qup_spi2_default>; 1420 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1421 #address-cells = <1>; 1422 #size-cells = <0>; 1423 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1424 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1425 interconnect-names = "qup-core", "qup-config"; 1426 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1427 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1428 dma-names = "tx", "rx"; 1429 status = "disabled"; 1430 }; 1431 1432 uart2: serial@888000 { 1433 compatible = "qcom,geni-uart"; 1434 reg = <0 0x00888000 0 0x4000>; 1435 clock-names = "se"; 1436 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1437 pinctrl-names = "default"; 1438 pinctrl-0 = <&qup_uart2_default>; 1439 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1440 power-domains = <&rpmhpd SDM845_CX>; 1441 operating-points-v2 = <&qup_opp_table>; 1442 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1443 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1444 interconnect-names = "qup-core", "qup-config"; 1445 status = "disabled"; 1446 }; 1447 1448 i2c3: i2c@88c000 { 1449 compatible = "qcom,geni-i2c"; 1450 reg = <0 0x0088c000 0 0x4000>; 1451 clock-names = "se"; 1452 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1453 pinctrl-names = "default"; 1454 pinctrl-0 = <&qup_i2c3_default>; 1455 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1456 #address-cells = <1>; 1457 #size-cells = <0>; 1458 power-domains = <&rpmhpd SDM845_CX>; 1459 operating-points-v2 = <&qup_opp_table>; 1460 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1461 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1462 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1463 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1464 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1465 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1466 dma-names = "tx", "rx"; 1467 status = "disabled"; 1468 }; 1469 1470 spi3: spi@88c000 { 1471 compatible = "qcom,geni-spi"; 1472 reg = <0 0x0088c000 0 0x4000>; 1473 clock-names = "se"; 1474 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1475 pinctrl-names = "default"; 1476 pinctrl-0 = <&qup_spi3_default>; 1477 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1478 #address-cells = <1>; 1479 #size-cells = <0>; 1480 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1481 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1482 interconnect-names = "qup-core", "qup-config"; 1483 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1484 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1485 dma-names = "tx", "rx"; 1486 status = "disabled"; 1487 }; 1488 1489 uart3: serial@88c000 { 1490 compatible = "qcom,geni-uart"; 1491 reg = <0 0x0088c000 0 0x4000>; 1492 clock-names = "se"; 1493 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1494 pinctrl-names = "default"; 1495 pinctrl-0 = <&qup_uart3_default>; 1496 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1497 power-domains = <&rpmhpd SDM845_CX>; 1498 operating-points-v2 = <&qup_opp_table>; 1499 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1500 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1501 interconnect-names = "qup-core", "qup-config"; 1502 status = "disabled"; 1503 }; 1504 1505 i2c4: i2c@890000 { 1506 compatible = "qcom,geni-i2c"; 1507 reg = <0 0x00890000 0 0x4000>; 1508 clock-names = "se"; 1509 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1510 pinctrl-names = "default"; 1511 pinctrl-0 = <&qup_i2c4_default>; 1512 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1513 #address-cells = <1>; 1514 #size-cells = <0>; 1515 power-domains = <&rpmhpd SDM845_CX>; 1516 operating-points-v2 = <&qup_opp_table>; 1517 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1518 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1519 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1520 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1521 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1522 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1523 dma-names = "tx", "rx"; 1524 status = "disabled"; 1525 }; 1526 1527 spi4: spi@890000 { 1528 compatible = "qcom,geni-spi"; 1529 reg = <0 0x00890000 0 0x4000>; 1530 clock-names = "se"; 1531 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1532 pinctrl-names = "default"; 1533 pinctrl-0 = <&qup_spi4_default>; 1534 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1535 #address-cells = <1>; 1536 #size-cells = <0>; 1537 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1538 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1539 interconnect-names = "qup-core", "qup-config"; 1540 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1541 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1542 dma-names = "tx", "rx"; 1543 status = "disabled"; 1544 }; 1545 1546 uart4: serial@890000 { 1547 compatible = "qcom,geni-uart"; 1548 reg = <0 0x00890000 0 0x4000>; 1549 clock-names = "se"; 1550 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1551 pinctrl-names = "default"; 1552 pinctrl-0 = <&qup_uart4_default>; 1553 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1554 power-domains = <&rpmhpd SDM845_CX>; 1555 operating-points-v2 = <&qup_opp_table>; 1556 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1557 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1558 interconnect-names = "qup-core", "qup-config"; 1559 status = "disabled"; 1560 }; 1561 1562 i2c5: i2c@894000 { 1563 compatible = "qcom,geni-i2c"; 1564 reg = <0 0x00894000 0 0x4000>; 1565 clock-names = "se"; 1566 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1567 pinctrl-names = "default"; 1568 pinctrl-0 = <&qup_i2c5_default>; 1569 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1570 #address-cells = <1>; 1571 #size-cells = <0>; 1572 power-domains = <&rpmhpd SDM845_CX>; 1573 operating-points-v2 = <&qup_opp_table>; 1574 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1575 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1576 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1577 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1578 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1579 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1580 dma-names = "tx", "rx"; 1581 status = "disabled"; 1582 }; 1583 1584 spi5: spi@894000 { 1585 compatible = "qcom,geni-spi"; 1586 reg = <0 0x00894000 0 0x4000>; 1587 clock-names = "se"; 1588 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1589 pinctrl-names = "default"; 1590 pinctrl-0 = <&qup_spi5_default>; 1591 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1592 #address-cells = <1>; 1593 #size-cells = <0>; 1594 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1595 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1596 interconnect-names = "qup-core", "qup-config"; 1597 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1598 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1599 dma-names = "tx", "rx"; 1600 status = "disabled"; 1601 }; 1602 1603 uart5: serial@894000 { 1604 compatible = "qcom,geni-uart"; 1605 reg = <0 0x00894000 0 0x4000>; 1606 clock-names = "se"; 1607 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1608 pinctrl-names = "default"; 1609 pinctrl-0 = <&qup_uart5_default>; 1610 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1611 power-domains = <&rpmhpd SDM845_CX>; 1612 operating-points-v2 = <&qup_opp_table>; 1613 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1614 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1615 interconnect-names = "qup-core", "qup-config"; 1616 status = "disabled"; 1617 }; 1618 1619 i2c6: i2c@898000 { 1620 compatible = "qcom,geni-i2c"; 1621 reg = <0 0x00898000 0 0x4000>; 1622 clock-names = "se"; 1623 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1624 pinctrl-names = "default"; 1625 pinctrl-0 = <&qup_i2c6_default>; 1626 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 power-domains = <&rpmhpd SDM845_CX>; 1630 operating-points-v2 = <&qup_opp_table>; 1631 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1632 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1633 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1634 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1635 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1636 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1637 dma-names = "tx", "rx"; 1638 status = "disabled"; 1639 }; 1640 1641 spi6: spi@898000 { 1642 compatible = "qcom,geni-spi"; 1643 reg = <0 0x00898000 0 0x4000>; 1644 clock-names = "se"; 1645 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1646 pinctrl-names = "default"; 1647 pinctrl-0 = <&qup_spi6_default>; 1648 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1649 #address-cells = <1>; 1650 #size-cells = <0>; 1651 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1652 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1653 interconnect-names = "qup-core", "qup-config"; 1654 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1655 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1656 dma-names = "tx", "rx"; 1657 status = "disabled"; 1658 }; 1659 1660 uart6: serial@898000 { 1661 compatible = "qcom,geni-uart"; 1662 reg = <0 0x00898000 0 0x4000>; 1663 clock-names = "se"; 1664 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1665 pinctrl-names = "default"; 1666 pinctrl-0 = <&qup_uart6_default>; 1667 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1668 power-domains = <&rpmhpd SDM845_CX>; 1669 operating-points-v2 = <&qup_opp_table>; 1670 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1671 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1672 interconnect-names = "qup-core", "qup-config"; 1673 status = "disabled"; 1674 }; 1675 1676 i2c7: i2c@89c000 { 1677 compatible = "qcom,geni-i2c"; 1678 reg = <0 0x0089c000 0 0x4000>; 1679 clock-names = "se"; 1680 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1681 pinctrl-names = "default"; 1682 pinctrl-0 = <&qup_i2c7_default>; 1683 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1684 #address-cells = <1>; 1685 #size-cells = <0>; 1686 power-domains = <&rpmhpd SDM845_CX>; 1687 operating-points-v2 = <&qup_opp_table>; 1688 status = "disabled"; 1689 }; 1690 1691 spi7: spi@89c000 { 1692 compatible = "qcom,geni-spi"; 1693 reg = <0 0x0089c000 0 0x4000>; 1694 clock-names = "se"; 1695 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1696 pinctrl-names = "default"; 1697 pinctrl-0 = <&qup_spi7_default>; 1698 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1699 #address-cells = <1>; 1700 #size-cells = <0>; 1701 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1702 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1703 interconnect-names = "qup-core", "qup-config"; 1704 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1705 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1706 dma-names = "tx", "rx"; 1707 status = "disabled"; 1708 }; 1709 1710 uart7: serial@89c000 { 1711 compatible = "qcom,geni-uart"; 1712 reg = <0 0x0089c000 0 0x4000>; 1713 clock-names = "se"; 1714 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1715 pinctrl-names = "default"; 1716 pinctrl-0 = <&qup_uart7_default>; 1717 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1718 power-domains = <&rpmhpd SDM845_CX>; 1719 operating-points-v2 = <&qup_opp_table>; 1720 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1721 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1722 interconnect-names = "qup-core", "qup-config"; 1723 status = "disabled"; 1724 }; 1725 }; 1726 1727 gpi_dma1: dma-controller@a00000 { 1728 #dma-cells = <3>; 1729 compatible = "qcom,sdm845-gpi-dma"; 1730 reg = <0 0x00a00000 0 0x60000>; 1731 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1743 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1744 dma-channels = <13>; 1745 dma-channel-mask = <0xfa>; 1746 iommus = <&apps_smmu 0x06d6 0x0>; 1747 status = "disabled"; 1748 }; 1749 1750 qupv3_id_1: geniqup@ac0000 { 1751 compatible = "qcom,geni-se-qup"; 1752 reg = <0 0x00ac0000 0 0x6000>; 1753 clock-names = "m-ahb", "s-ahb"; 1754 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1755 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1756 iommus = <&apps_smmu 0x6c3 0x0>; 1757 #address-cells = <2>; 1758 #size-cells = <2>; 1759 ranges; 1760 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>; 1761 interconnect-names = "qup-core"; 1762 status = "disabled"; 1763 1764 i2c8: i2c@a80000 { 1765 compatible = "qcom,geni-i2c"; 1766 reg = <0 0x00a80000 0 0x4000>; 1767 clock-names = "se"; 1768 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1769 pinctrl-names = "default"; 1770 pinctrl-0 = <&qup_i2c8_default>; 1771 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1772 #address-cells = <1>; 1773 #size-cells = <0>; 1774 power-domains = <&rpmhpd SDM845_CX>; 1775 operating-points-v2 = <&qup_opp_table>; 1776 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1777 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1778 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1779 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1780 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1781 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1782 dma-names = "tx", "rx"; 1783 status = "disabled"; 1784 }; 1785 1786 spi8: spi@a80000 { 1787 compatible = "qcom,geni-spi"; 1788 reg = <0 0x00a80000 0 0x4000>; 1789 clock-names = "se"; 1790 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1791 pinctrl-names = "default"; 1792 pinctrl-0 = <&qup_spi8_default>; 1793 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1794 #address-cells = <1>; 1795 #size-cells = <0>; 1796 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1797 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1798 interconnect-names = "qup-core", "qup-config"; 1799 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1800 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1801 dma-names = "tx", "rx"; 1802 status = "disabled"; 1803 }; 1804 1805 uart8: serial@a80000 { 1806 compatible = "qcom,geni-uart"; 1807 reg = <0 0x00a80000 0 0x4000>; 1808 clock-names = "se"; 1809 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1810 pinctrl-names = "default"; 1811 pinctrl-0 = <&qup_uart8_default>; 1812 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1813 power-domains = <&rpmhpd SDM845_CX>; 1814 operating-points-v2 = <&qup_opp_table>; 1815 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1816 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1817 interconnect-names = "qup-core", "qup-config"; 1818 status = "disabled"; 1819 }; 1820 1821 i2c9: i2c@a84000 { 1822 compatible = "qcom,geni-i2c"; 1823 reg = <0 0x00a84000 0 0x4000>; 1824 clock-names = "se"; 1825 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1826 pinctrl-names = "default"; 1827 pinctrl-0 = <&qup_i2c9_default>; 1828 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1829 #address-cells = <1>; 1830 #size-cells = <0>; 1831 power-domains = <&rpmhpd SDM845_CX>; 1832 operating-points-v2 = <&qup_opp_table>; 1833 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1834 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1835 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1836 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1837 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1838 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1839 dma-names = "tx", "rx"; 1840 status = "disabled"; 1841 }; 1842 1843 spi9: spi@a84000 { 1844 compatible = "qcom,geni-spi"; 1845 reg = <0 0x00a84000 0 0x4000>; 1846 clock-names = "se"; 1847 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1848 pinctrl-names = "default"; 1849 pinctrl-0 = <&qup_spi9_default>; 1850 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1851 #address-cells = <1>; 1852 #size-cells = <0>; 1853 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1854 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1855 interconnect-names = "qup-core", "qup-config"; 1856 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1857 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1858 dma-names = "tx", "rx"; 1859 status = "disabled"; 1860 }; 1861 1862 uart9: serial@a84000 { 1863 compatible = "qcom,geni-debug-uart"; 1864 reg = <0 0x00a84000 0 0x4000>; 1865 clock-names = "se"; 1866 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1867 pinctrl-names = "default"; 1868 pinctrl-0 = <&qup_uart9_default>; 1869 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1870 power-domains = <&rpmhpd SDM845_CX>; 1871 operating-points-v2 = <&qup_opp_table>; 1872 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1873 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1874 interconnect-names = "qup-core", "qup-config"; 1875 status = "disabled"; 1876 }; 1877 1878 i2c10: i2c@a88000 { 1879 compatible = "qcom,geni-i2c"; 1880 reg = <0 0x00a88000 0 0x4000>; 1881 clock-names = "se"; 1882 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1883 pinctrl-names = "default"; 1884 pinctrl-0 = <&qup_i2c10_default>; 1885 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1886 #address-cells = <1>; 1887 #size-cells = <0>; 1888 power-domains = <&rpmhpd SDM845_CX>; 1889 operating-points-v2 = <&qup_opp_table>; 1890 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1891 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1892 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1893 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1894 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1895 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1896 dma-names = "tx", "rx"; 1897 status = "disabled"; 1898 }; 1899 1900 spi10: spi@a88000 { 1901 compatible = "qcom,geni-spi"; 1902 reg = <0 0x00a88000 0 0x4000>; 1903 clock-names = "se"; 1904 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1905 pinctrl-names = "default"; 1906 pinctrl-0 = <&qup_spi10_default>; 1907 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1908 #address-cells = <1>; 1909 #size-cells = <0>; 1910 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1911 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1912 interconnect-names = "qup-core", "qup-config"; 1913 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1914 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1915 dma-names = "tx", "rx"; 1916 status = "disabled"; 1917 }; 1918 1919 uart10: serial@a88000 { 1920 compatible = "qcom,geni-uart"; 1921 reg = <0 0x00a88000 0 0x4000>; 1922 clock-names = "se"; 1923 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1924 pinctrl-names = "default"; 1925 pinctrl-0 = <&qup_uart10_default>; 1926 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1927 power-domains = <&rpmhpd SDM845_CX>; 1928 operating-points-v2 = <&qup_opp_table>; 1929 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1930 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1931 interconnect-names = "qup-core", "qup-config"; 1932 status = "disabled"; 1933 }; 1934 1935 i2c11: i2c@a8c000 { 1936 compatible = "qcom,geni-i2c"; 1937 reg = <0 0x00a8c000 0 0x4000>; 1938 clock-names = "se"; 1939 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1940 pinctrl-names = "default"; 1941 pinctrl-0 = <&qup_i2c11_default>; 1942 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1943 #address-cells = <1>; 1944 #size-cells = <0>; 1945 power-domains = <&rpmhpd SDM845_CX>; 1946 operating-points-v2 = <&qup_opp_table>; 1947 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1948 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1949 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1950 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1951 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1952 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1953 dma-names = "tx", "rx"; 1954 status = "disabled"; 1955 }; 1956 1957 spi11: spi@a8c000 { 1958 compatible = "qcom,geni-spi"; 1959 reg = <0 0x00a8c000 0 0x4000>; 1960 clock-names = "se"; 1961 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1962 pinctrl-names = "default"; 1963 pinctrl-0 = <&qup_spi11_default>; 1964 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1965 #address-cells = <1>; 1966 #size-cells = <0>; 1967 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1968 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1969 interconnect-names = "qup-core", "qup-config"; 1970 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1971 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1972 dma-names = "tx", "rx"; 1973 status = "disabled"; 1974 }; 1975 1976 uart11: serial@a8c000 { 1977 compatible = "qcom,geni-uart"; 1978 reg = <0 0x00a8c000 0 0x4000>; 1979 clock-names = "se"; 1980 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1981 pinctrl-names = "default"; 1982 pinctrl-0 = <&qup_uart11_default>; 1983 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1984 power-domains = <&rpmhpd SDM845_CX>; 1985 operating-points-v2 = <&qup_opp_table>; 1986 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1987 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1988 interconnect-names = "qup-core", "qup-config"; 1989 status = "disabled"; 1990 }; 1991 1992 i2c12: i2c@a90000 { 1993 compatible = "qcom,geni-i2c"; 1994 reg = <0 0x00a90000 0 0x4000>; 1995 clock-names = "se"; 1996 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1997 pinctrl-names = "default"; 1998 pinctrl-0 = <&qup_i2c12_default>; 1999 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2000 #address-cells = <1>; 2001 #size-cells = <0>; 2002 power-domains = <&rpmhpd SDM845_CX>; 2003 operating-points-v2 = <&qup_opp_table>; 2004 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2005 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2006 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2007 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2008 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 2009 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 2010 dma-names = "tx", "rx"; 2011 status = "disabled"; 2012 }; 2013 2014 spi12: spi@a90000 { 2015 compatible = "qcom,geni-spi"; 2016 reg = <0 0x00a90000 0 0x4000>; 2017 clock-names = "se"; 2018 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2019 pinctrl-names = "default"; 2020 pinctrl-0 = <&qup_spi12_default>; 2021 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2022 #address-cells = <1>; 2023 #size-cells = <0>; 2024 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2025 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2026 interconnect-names = "qup-core", "qup-config"; 2027 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 2028 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2029 dma-names = "tx", "rx"; 2030 status = "disabled"; 2031 }; 2032 2033 uart12: serial@a90000 { 2034 compatible = "qcom,geni-uart"; 2035 reg = <0 0x00a90000 0 0x4000>; 2036 clock-names = "se"; 2037 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2038 pinctrl-names = "default"; 2039 pinctrl-0 = <&qup_uart12_default>; 2040 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2041 power-domains = <&rpmhpd SDM845_CX>; 2042 operating-points-v2 = <&qup_opp_table>; 2043 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2044 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2045 interconnect-names = "qup-core", "qup-config"; 2046 status = "disabled"; 2047 }; 2048 2049 i2c13: i2c@a94000 { 2050 compatible = "qcom,geni-i2c"; 2051 reg = <0 0x00a94000 0 0x4000>; 2052 clock-names = "se"; 2053 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2054 pinctrl-names = "default"; 2055 pinctrl-0 = <&qup_i2c13_default>; 2056 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2057 #address-cells = <1>; 2058 #size-cells = <0>; 2059 power-domains = <&rpmhpd SDM845_CX>; 2060 operating-points-v2 = <&qup_opp_table>; 2061 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2062 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2063 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2064 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2065 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2066 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2067 dma-names = "tx", "rx"; 2068 status = "disabled"; 2069 }; 2070 2071 spi13: spi@a94000 { 2072 compatible = "qcom,geni-spi"; 2073 reg = <0 0x00a94000 0 0x4000>; 2074 clock-names = "se"; 2075 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2076 pinctrl-names = "default"; 2077 pinctrl-0 = <&qup_spi13_default>; 2078 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2079 #address-cells = <1>; 2080 #size-cells = <0>; 2081 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2082 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2083 interconnect-names = "qup-core", "qup-config"; 2084 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2085 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2086 dma-names = "tx", "rx"; 2087 status = "disabled"; 2088 }; 2089 2090 uart13: serial@a94000 { 2091 compatible = "qcom,geni-uart"; 2092 reg = <0 0x00a94000 0 0x4000>; 2093 clock-names = "se"; 2094 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2095 pinctrl-names = "default"; 2096 pinctrl-0 = <&qup_uart13_default>; 2097 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2098 power-domains = <&rpmhpd SDM845_CX>; 2099 operating-points-v2 = <&qup_opp_table>; 2100 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2101 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2102 interconnect-names = "qup-core", "qup-config"; 2103 status = "disabled"; 2104 }; 2105 2106 i2c14: i2c@a98000 { 2107 compatible = "qcom,geni-i2c"; 2108 reg = <0 0x00a98000 0 0x4000>; 2109 clock-names = "se"; 2110 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2111 pinctrl-names = "default"; 2112 pinctrl-0 = <&qup_i2c14_default>; 2113 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2114 #address-cells = <1>; 2115 #size-cells = <0>; 2116 power-domains = <&rpmhpd SDM845_CX>; 2117 operating-points-v2 = <&qup_opp_table>; 2118 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2119 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2120 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2121 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2122 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2123 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2124 dma-names = "tx", "rx"; 2125 status = "disabled"; 2126 }; 2127 2128 spi14: spi@a98000 { 2129 compatible = "qcom,geni-spi"; 2130 reg = <0 0x00a98000 0 0x4000>; 2131 clock-names = "se"; 2132 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2133 pinctrl-names = "default"; 2134 pinctrl-0 = <&qup_spi14_default>; 2135 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2136 #address-cells = <1>; 2137 #size-cells = <0>; 2138 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2139 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2140 interconnect-names = "qup-core", "qup-config"; 2141 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2142 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2143 dma-names = "tx", "rx"; 2144 status = "disabled"; 2145 }; 2146 2147 uart14: serial@a98000 { 2148 compatible = "qcom,geni-uart"; 2149 reg = <0 0x00a98000 0 0x4000>; 2150 clock-names = "se"; 2151 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2152 pinctrl-names = "default"; 2153 pinctrl-0 = <&qup_uart14_default>; 2154 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2155 power-domains = <&rpmhpd SDM845_CX>; 2156 operating-points-v2 = <&qup_opp_table>; 2157 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2158 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2159 interconnect-names = "qup-core", "qup-config"; 2160 status = "disabled"; 2161 }; 2162 2163 i2c15: i2c@a9c000 { 2164 compatible = "qcom,geni-i2c"; 2165 reg = <0 0x00a9c000 0 0x4000>; 2166 clock-names = "se"; 2167 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2168 pinctrl-names = "default"; 2169 pinctrl-0 = <&qup_i2c15_default>; 2170 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2171 #address-cells = <1>; 2172 #size-cells = <0>; 2173 power-domains = <&rpmhpd SDM845_CX>; 2174 operating-points-v2 = <&qup_opp_table>; 2175 status = "disabled"; 2176 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2177 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2178 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2179 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2180 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2181 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2182 dma-names = "tx", "rx"; 2183 }; 2184 2185 spi15: spi@a9c000 { 2186 compatible = "qcom,geni-spi"; 2187 reg = <0 0x00a9c000 0 0x4000>; 2188 clock-names = "se"; 2189 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2190 pinctrl-names = "default"; 2191 pinctrl-0 = <&qup_spi15_default>; 2192 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2193 #address-cells = <1>; 2194 #size-cells = <0>; 2195 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2196 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2197 interconnect-names = "qup-core", "qup-config"; 2198 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2199 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2200 dma-names = "tx", "rx"; 2201 status = "disabled"; 2202 }; 2203 2204 uart15: serial@a9c000 { 2205 compatible = "qcom,geni-uart"; 2206 reg = <0 0x00a9c000 0 0x4000>; 2207 clock-names = "se"; 2208 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2209 pinctrl-names = "default"; 2210 pinctrl-0 = <&qup_uart15_default>; 2211 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2212 power-domains = <&rpmhpd SDM845_CX>; 2213 operating-points-v2 = <&qup_opp_table>; 2214 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2215 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2216 interconnect-names = "qup-core", "qup-config"; 2217 status = "disabled"; 2218 }; 2219 }; 2220 2221 refgen: regulator@ff1000 { 2222 compatible = "qcom,sdm845-refgen-regulator"; 2223 reg = <0x0 0x00ff1000 0x0 0x60>; 2224 }; 2225 2226 llcc: system-cache-controller@1100000 { 2227 compatible = "qcom,sdm845-llcc"; 2228 reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>, 2229 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, 2230 <0 0x01300000 0 0x50000>; 2231 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2232 "llcc3_base", "llcc_broadcast_base"; 2233 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2234 }; 2235 2236 dma@10a2000 { 2237 compatible = "qcom,sdm845-dcc", "qcom,dcc"; 2238 reg = <0x0 0x010a2000 0x0 0x1000>, 2239 <0x0 0x010ae000 0x0 0x2000>; 2240 }; 2241 2242 pmu@114a000 { 2243 compatible = "qcom,sdm845-llcc-bwmon"; 2244 reg = <0 0x0114a000 0 0x1000>; 2245 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 2246 interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>; 2247 2248 operating-points-v2 = <&llcc_bwmon_opp_table>; 2249 2250 llcc_bwmon_opp_table: opp-table { 2251 compatible = "operating-points-v2"; 2252 2253 /* 2254 * The interconnect path bandwidth taken from 2255 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc 2256 * interconnect. This also matches the 2257 * bandwidth table of qcom,llccbw (qcom,bw-tbl, 2258 * bus width: 4 bytes) from msm-4.9 downstream 2259 * kernel. 2260 */ 2261 opp-0 { 2262 opp-peak-kBps = <800000>; 2263 }; 2264 opp-1 { 2265 opp-peak-kBps = <1804000>; 2266 }; 2267 opp-2 { 2268 opp-peak-kBps = <3072000>; 2269 }; 2270 opp-3 { 2271 opp-peak-kBps = <5412000>; 2272 }; 2273 opp-4 { 2274 opp-peak-kBps = <7216000>; 2275 }; 2276 }; 2277 }; 2278 2279 pmu@1436400 { 2280 compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon"; 2281 reg = <0 0x01436400 0 0x600>; 2282 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 2283 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>; 2284 2285 operating-points-v2 = <&cpu_bwmon_opp_table>; 2286 2287 cpu_bwmon_opp_table: opp-table { 2288 compatible = "operating-points-v2"; 2289 2290 /* 2291 * The interconnect path bandwidth taken from 2292 * cpu4_opp_table bandwidth for OSM L3 2293 * interconnect. This also matches the OSM L3 2294 * from bandwidth table of qcom,cpu4-l3lat-mon 2295 * (qcom,core-dev-table, bus width: 16 bytes) 2296 * from msm-4.9 downstream kernel. 2297 */ 2298 opp-0 { 2299 opp-peak-kBps = <4800000>; 2300 }; 2301 opp-1 { 2302 opp-peak-kBps = <9216000>; 2303 }; 2304 opp-2 { 2305 opp-peak-kBps = <15052800>; 2306 }; 2307 opp-3 { 2308 opp-peak-kBps = <20889600>; 2309 }; 2310 opp-4 { 2311 opp-peak-kBps = <25497600>; 2312 }; 2313 }; 2314 }; 2315 2316 pcie0: pcie@1c00000 { 2317 compatible = "qcom,pcie-sdm845"; 2318 reg = <0 0x01c00000 0 0x2000>, 2319 <0 0x60000000 0 0xf1d>, 2320 <0 0x60000f20 0 0xa8>, 2321 <0 0x60100000 0 0x100000>, 2322 <0 0x01c07000 0 0x1000>; 2323 reg-names = "parf", "dbi", "elbi", "config", "mhi"; 2324 device_type = "pci"; 2325 linux,pci-domain = <0>; 2326 bus-range = <0x00 0xff>; 2327 num-lanes = <1>; 2328 2329 #address-cells = <3>; 2330 #size-cells = <2>; 2331 2332 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 2333 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>; 2334 2335 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2336 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2337 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2338 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2339 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2340 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2341 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2342 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2343 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2344 interrupt-names = "msi0", 2345 "msi1", 2346 "msi2", 2347 "msi3", 2348 "msi4", 2349 "msi5", 2350 "msi6", 2351 "msi7", 2352 "global"; 2353 #interrupt-cells = <1>; 2354 interrupt-map-mask = <0 0 0 0x7>; 2355 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2356 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2357 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2358 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2359 2360 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2361 <&gcc GCC_PCIE_0_AUX_CLK>, 2362 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2363 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2364 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2365 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2366 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2367 clock-names = "pipe", 2368 "aux", 2369 "cfg", 2370 "bus_master", 2371 "bus_slave", 2372 "slave_q2a", 2373 "tbu"; 2374 2375 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, 2376 <0x100 &apps_smmu 0x1c11 0x1>, 2377 <0x200 &apps_smmu 0x1c12 0x1>, 2378 <0x300 &apps_smmu 0x1c13 0x1>, 2379 <0x400 &apps_smmu 0x1c14 0x1>, 2380 <0x500 &apps_smmu 0x1c15 0x1>, 2381 <0x600 &apps_smmu 0x1c16 0x1>, 2382 <0x700 &apps_smmu 0x1c17 0x1>, 2383 <0x800 &apps_smmu 0x1c18 0x1>, 2384 <0x900 &apps_smmu 0x1c19 0x1>, 2385 <0xa00 &apps_smmu 0x1c1a 0x1>, 2386 <0xb00 &apps_smmu 0x1c1b 0x1>, 2387 <0xc00 &apps_smmu 0x1c1c 0x1>, 2388 <0xd00 &apps_smmu 0x1c1d 0x1>, 2389 <0xe00 &apps_smmu 0x1c1e 0x1>, 2390 <0xf00 &apps_smmu 0x1c1f 0x1>; 2391 2392 resets = <&gcc GCC_PCIE_0_BCR>; 2393 reset-names = "pci"; 2394 2395 power-domains = <&gcc PCIE_0_GDSC>; 2396 2397 phys = <&pcie0_phy>; 2398 phy-names = "pciephy"; 2399 2400 status = "disabled"; 2401 2402 pcie@0 { 2403 device_type = "pci"; 2404 reg = <0x0 0x0 0x0 0x0 0x0>; 2405 bus-range = <0x01 0xff>; 2406 2407 #address-cells = <3>; 2408 #size-cells = <2>; 2409 ranges; 2410 }; 2411 }; 2412 2413 pcie0_phy: phy@1c06000 { 2414 compatible = "qcom,sdm845-qmp-pcie-phy"; 2415 reg = <0 0x01c06000 0 0x1000>; 2416 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2417 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2418 <&gcc GCC_PCIE_0_CLKREF_CLK>, 2419 <&gcc GCC_PCIE_PHY_REFGEN_CLK>, 2420 <&gcc GCC_PCIE_0_PIPE_CLK>; 2421 clock-names = "aux", 2422 "cfg_ahb", 2423 "ref", 2424 "refgen", 2425 "pipe"; 2426 2427 clock-output-names = "pcie_0_pipe_clk"; 2428 #clock-cells = <0>; 2429 2430 #phy-cells = <0>; 2431 2432 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2433 reset-names = "phy"; 2434 2435 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2436 assigned-clock-rates = <100000000>; 2437 2438 status = "disabled"; 2439 }; 2440 2441 pcie1: pcie@1c08000 { 2442 compatible = "qcom,pcie-sdm845"; 2443 reg = <0 0x01c08000 0 0x2000>, 2444 <0 0x40000000 0 0xf1d>, 2445 <0 0x40000f20 0 0xa8>, 2446 <0 0x40100000 0 0x100000>, 2447 <0 0x01c0c000 0 0x1000>; 2448 reg-names = "parf", "dbi", "elbi", "config", "mhi"; 2449 device_type = "pci"; 2450 linux,pci-domain = <1>; 2451 bus-range = <0x00 0xff>; 2452 num-lanes = <1>; 2453 2454 #address-cells = <3>; 2455 #size-cells = <2>; 2456 2457 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2458 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2459 2460 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2461 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2462 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2463 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2464 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2465 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2466 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2467 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2468 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 2469 interrupt-names = "msi0", 2470 "msi1", 2471 "msi2", 2472 "msi3", 2473 "msi4", 2474 "msi5", 2475 "msi6", 2476 "msi7", 2477 "global"; 2478 #interrupt-cells = <1>; 2479 interrupt-map-mask = <0 0 0 0x7>; 2480 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2481 <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2482 <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2483 <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2484 2485 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2486 <&gcc GCC_PCIE_1_AUX_CLK>, 2487 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2488 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2489 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2490 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2491 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2492 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2493 clock-names = "pipe", 2494 "aux", 2495 "cfg", 2496 "bus_master", 2497 "bus_slave", 2498 "slave_q2a", 2499 "ref", 2500 "tbu"; 2501 2502 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2503 assigned-clock-rates = <19200000>; 2504 2505 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2506 <0x100 &apps_smmu 0x1c01 0x1>, 2507 <0x200 &apps_smmu 0x1c02 0x1>, 2508 <0x300 &apps_smmu 0x1c03 0x1>, 2509 <0x400 &apps_smmu 0x1c04 0x1>, 2510 <0x500 &apps_smmu 0x1c05 0x1>, 2511 <0x600 &apps_smmu 0x1c06 0x1>, 2512 <0x700 &apps_smmu 0x1c07 0x1>, 2513 <0x800 &apps_smmu 0x1c08 0x1>, 2514 <0x900 &apps_smmu 0x1c09 0x1>, 2515 <0xa00 &apps_smmu 0x1c0a 0x1>, 2516 <0xb00 &apps_smmu 0x1c0b 0x1>, 2517 <0xc00 &apps_smmu 0x1c0c 0x1>, 2518 <0xd00 &apps_smmu 0x1c0d 0x1>, 2519 <0xe00 &apps_smmu 0x1c0e 0x1>, 2520 <0xf00 &apps_smmu 0x1c0f 0x1>; 2521 2522 resets = <&gcc GCC_PCIE_1_BCR>; 2523 reset-names = "pci"; 2524 2525 power-domains = <&gcc PCIE_1_GDSC>; 2526 2527 phys = <&pcie1_phy>; 2528 phy-names = "pciephy"; 2529 2530 status = "disabled"; 2531 2532 pcie@0 { 2533 device_type = "pci"; 2534 reg = <0x0 0x0 0x0 0x0 0x0>; 2535 bus-range = <0x01 0xff>; 2536 2537 #address-cells = <3>; 2538 #size-cells = <2>; 2539 ranges; 2540 }; 2541 }; 2542 2543 pcie1_phy: phy@1c0a000 { 2544 compatible = "qcom,sdm845-qhp-pcie-phy"; 2545 reg = <0 0x01c0a000 0 0x2000>; 2546 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2547 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2548 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2549 <&gcc GCC_PCIE_PHY_REFGEN_CLK>, 2550 <&gcc GCC_PCIE_1_PIPE_CLK>; 2551 clock-names = "aux", 2552 "cfg_ahb", 2553 "ref", 2554 "refgen", 2555 "pipe"; 2556 2557 clock-output-names = "pcie_1_pipe_clk"; 2558 #clock-cells = <0>; 2559 2560 #phy-cells = <0>; 2561 2562 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2563 reset-names = "phy"; 2564 2565 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2566 assigned-clock-rates = <100000000>; 2567 2568 status = "disabled"; 2569 }; 2570 2571 mem_noc: interconnect@1380000 { 2572 compatible = "qcom,sdm845-mem-noc"; 2573 reg = <0 0x01380000 0 0x27200>; 2574 #interconnect-cells = <2>; 2575 qcom,bcm-voters = <&apps_bcm_voter>; 2576 }; 2577 2578 dc_noc: interconnect@14e0000 { 2579 compatible = "qcom,sdm845-dc-noc"; 2580 reg = <0 0x014e0000 0 0x400>; 2581 #interconnect-cells = <2>; 2582 qcom,bcm-voters = <&apps_bcm_voter>; 2583 }; 2584 2585 config_noc: interconnect@1500000 { 2586 compatible = "qcom,sdm845-config-noc"; 2587 reg = <0 0x01500000 0 0x5080>; 2588 #interconnect-cells = <2>; 2589 qcom,bcm-voters = <&apps_bcm_voter>; 2590 }; 2591 2592 system_noc: interconnect@1620000 { 2593 compatible = "qcom,sdm845-system-noc"; 2594 reg = <0 0x01620000 0 0x18080>; 2595 #interconnect-cells = <2>; 2596 qcom,bcm-voters = <&apps_bcm_voter>; 2597 }; 2598 2599 aggre1_noc: interconnect@16e0000 { 2600 compatible = "qcom,sdm845-aggre1-noc"; 2601 reg = <0 0x016e0000 0 0x15080>; 2602 #interconnect-cells = <2>; 2603 qcom,bcm-voters = <&apps_bcm_voter>; 2604 }; 2605 2606 aggre2_noc: interconnect@1700000 { 2607 compatible = "qcom,sdm845-aggre2-noc"; 2608 reg = <0 0x01700000 0 0x1f300>; 2609 #interconnect-cells = <2>; 2610 qcom,bcm-voters = <&apps_bcm_voter>; 2611 }; 2612 2613 mmss_noc: interconnect@1740000 { 2614 compatible = "qcom,sdm845-mmss-noc"; 2615 reg = <0 0x01740000 0 0x1c100>; 2616 #interconnect-cells = <2>; 2617 qcom,bcm-voters = <&apps_bcm_voter>; 2618 }; 2619 2620 ufs_mem_hc: ufshc@1d84000 { 2621 compatible = "qcom,sdm845-ufshc", "qcom,ufshc", 2622 "jedec,ufs-2.0"; 2623 reg = <0 0x01d84000 0 0x2500>, 2624 <0 0x01d90000 0 0x8000>; 2625 reg-names = "std", "ice"; 2626 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2627 phys = <&ufs_mem_phy>; 2628 phy-names = "ufsphy"; 2629 lanes-per-direction = <2>; 2630 power-domains = <&gcc UFS_PHY_GDSC>; 2631 #reset-cells = <1>; 2632 resets = <&gcc GCC_UFS_PHY_BCR>; 2633 reset-names = "rst"; 2634 2635 iommus = <&apps_smmu 0x100 0xf>; 2636 2637 clock-names = 2638 "core_clk", 2639 "bus_aggr_clk", 2640 "iface_clk", 2641 "core_clk_unipro", 2642 "ref_clk", 2643 "tx_lane0_sync_clk", 2644 "rx_lane0_sync_clk", 2645 "rx_lane1_sync_clk", 2646 "ice_core_clk"; 2647 clocks = 2648 <&gcc GCC_UFS_PHY_AXI_CLK>, 2649 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2650 <&gcc GCC_UFS_PHY_AHB_CLK>, 2651 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2652 <&rpmhcc RPMH_CXO_CLK>, 2653 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2654 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2655 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2656 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2657 2658 operating-points-v2 = <&ufs_opp_table>; 2659 2660 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>, 2661 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 2662 interconnect-names = "ufs-ddr", "cpu-ufs"; 2663 2664 status = "disabled"; 2665 2666 ufs_opp_table: opp-table { 2667 compatible = "operating-points-v2"; 2668 2669 opp-50000000 { 2670 opp-hz = /bits/ 64 <50000000>, 2671 /bits/ 64 <0>, 2672 /bits/ 64 <0>, 2673 /bits/ 64 <37500000>, 2674 /bits/ 64 <0>, 2675 /bits/ 64 <0>, 2676 /bits/ 64 <0>, 2677 /bits/ 64 <0>, 2678 /bits/ 64 <75000000>; 2679 required-opps = <&rpmhpd_opp_low_svs>; 2680 }; 2681 2682 opp-200000000 { 2683 opp-hz = /bits/ 64 <200000000>, 2684 /bits/ 64 <0>, 2685 /bits/ 64 <0>, 2686 /bits/ 64 <150000000>, 2687 /bits/ 64 <0>, 2688 /bits/ 64 <0>, 2689 /bits/ 64 <0>, 2690 /bits/ 64 <0>, 2691 /bits/ 64 <300000000>; 2692 required-opps = <&rpmhpd_opp_nom>; 2693 }; 2694 }; 2695 }; 2696 2697 ufs_mem_phy: phy@1d87000 { 2698 compatible = "qcom,sdm845-qmp-ufs-phy"; 2699 reg = <0 0x01d87000 0 0x1000>; 2700 2701 clocks = <&rpmhcc RPMH_CXO_CLK>, 2702 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2703 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 2704 clock-names = "ref", 2705 "ref_aux", 2706 "qref"; 2707 2708 power-domains = <&gcc UFS_PHY_GDSC>; 2709 2710 resets = <&ufs_mem_hc 0>; 2711 reset-names = "ufsphy"; 2712 2713 #phy-cells = <0>; 2714 status = "disabled"; 2715 }; 2716 2717 cryptobam: dma-controller@1dc4000 { 2718 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2719 reg = <0 0x01dc4000 0 0x24000>; 2720 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2721 clocks = <&rpmhcc RPMH_CE_CLK>; 2722 clock-names = "bam_clk"; 2723 #dma-cells = <1>; 2724 qcom,ee = <0>; 2725 qcom,controlled-remotely; 2726 iommus = <&apps_smmu 0x704 0x1>, 2727 <&apps_smmu 0x706 0x1>, 2728 <&apps_smmu 0x714 0x1>, 2729 <&apps_smmu 0x716 0x1>; 2730 }; 2731 2732 crypto: crypto@1dfa000 { 2733 compatible = "qcom,crypto-v5.4"; 2734 reg = <0 0x01dfa000 0 0x6000>; 2735 clocks = <&gcc GCC_CE1_AHB_CLK>, 2736 <&gcc GCC_CE1_AXI_CLK>, 2737 <&rpmhcc RPMH_CE_CLK>; 2738 clock-names = "iface", "bus", "core"; 2739 dmas = <&cryptobam 6>, <&cryptobam 7>; 2740 dma-names = "rx", "tx"; 2741 iommus = <&apps_smmu 0x704 0x1>, 2742 <&apps_smmu 0x706 0x1>, 2743 <&apps_smmu 0x714 0x1>, 2744 <&apps_smmu 0x716 0x1>; 2745 }; 2746 2747 ipa: ipa@1e40000 { 2748 compatible = "qcom,sdm845-ipa"; 2749 2750 iommus = <&apps_smmu 0x720 0x0>, 2751 <&apps_smmu 0x722 0x0>; 2752 reg = <0 0x01e40000 0 0x7000>, 2753 <0 0x01e47000 0 0x2000>, 2754 <0 0x01e04000 0 0x2c000>; 2755 reg-names = "ipa-reg", 2756 "ipa-shared", 2757 "gsi"; 2758 2759 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 2760 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2761 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2762 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2763 interrupt-names = "ipa", 2764 "gsi", 2765 "ipa-clock-query", 2766 "ipa-setup-ready"; 2767 2768 clocks = <&rpmhcc RPMH_IPA_CLK>; 2769 clock-names = "core"; 2770 2771 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>, 2772 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 2773 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2774 interconnect-names = "memory", 2775 "imem", 2776 "config"; 2777 2778 qcom,smem-states = <&ipa_smp2p_out 0>, 2779 <&ipa_smp2p_out 1>; 2780 qcom,smem-state-names = "ipa-clock-enabled-valid", 2781 "ipa-clock-enabled"; 2782 2783 sram = <&ipa_modem_tables>; 2784 2785 status = "disabled"; 2786 }; 2787 2788 tcsr_mutex: hwlock@1f40000 { 2789 compatible = "qcom,tcsr-mutex"; 2790 reg = <0 0x01f40000 0 0x20000>; 2791 #hwlock-cells = <1>; 2792 }; 2793 2794 tcsr_regs_1: syscon@1f60000 { 2795 compatible = "qcom,sdm845-tcsr", "syscon"; 2796 reg = <0 0x01f60000 0 0x20000>; 2797 }; 2798 2799 tlmm: pinctrl@3400000 { 2800 compatible = "qcom,sdm845-pinctrl"; 2801 reg = <0 0x03400000 0 0xc00000>; 2802 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2803 gpio-controller; 2804 #gpio-cells = <2>; 2805 interrupt-controller; 2806 #interrupt-cells = <2>; 2807 gpio-ranges = <&tlmm 0 0 151>; 2808 wakeup-parent = <&pdc_intc>; 2809 2810 cam_mclk0_default: cam-mclk0-default-state { 2811 pins = "gpio13"; 2812 function = "cam_mclk"; 2813 drive-strength = <2>; 2814 bias-disable; 2815 }; 2816 2817 cam_mclk0_sleep: cam-mclk0-sleep-state { 2818 pins = "gpio13"; 2819 function = "cam_mclk"; 2820 drive-strength = <2>; 2821 bias-pull-down; 2822 }; 2823 2824 cam_mclk1_default: cam-mclk1-default-state { 2825 pins = "gpio14"; 2826 function = "cam_mclk"; 2827 drive-strength = <2>; 2828 bias-disable; 2829 }; 2830 2831 cam_mclk1_sleep: cam-mclk1-sleep-state { 2832 pins = "gpio14"; 2833 function = "cam_mclk"; 2834 drive-strength = <2>; 2835 bias-pull-down; 2836 }; 2837 2838 cam_mclk2_default: cam-mclk2-default-state { 2839 pins = "gpio15"; 2840 function = "cam_mclk"; 2841 drive-strength = <2>; 2842 bias-disable; 2843 }; 2844 2845 cam_mclk2_sleep: cam-mclk2-sleep-state { 2846 pins = "gpio15"; 2847 function = "cam_mclk"; 2848 drive-strength = <2>; 2849 bias-pull-down; 2850 }; 2851 2852 cam_mclk3_default: cam-mclk3-default-state { 2853 pins = "gpio16"; 2854 function = "cam_mclk"; 2855 drive-strength = <2>; 2856 bias-disable; 2857 }; 2858 2859 cam_mclk3_sleep: cam-mclk3-sleep-state { 2860 pins = "gpio16"; 2861 function = "cam_mclk"; 2862 drive-strength = <2>; 2863 bias-pull-down; 2864 }; 2865 2866 cci0_default: cci0-default-state { 2867 /* SDA, SCL */ 2868 pins = "gpio17", "gpio18"; 2869 function = "cci_i2c"; 2870 2871 bias-pull-up; 2872 drive-strength = <2>; /* 2 mA */ 2873 }; 2874 2875 cci0_sleep: cci0-sleep-state { 2876 /* SDA, SCL */ 2877 pins = "gpio17", "gpio18"; 2878 function = "cci_i2c"; 2879 2880 drive-strength = <2>; /* 2 mA */ 2881 bias-pull-down; 2882 }; 2883 2884 cci1_default: cci1-default-state { 2885 /* SDA, SCL */ 2886 pins = "gpio19", "gpio20"; 2887 function = "cci_i2c"; 2888 2889 bias-pull-up; 2890 drive-strength = <2>; /* 2 mA */ 2891 }; 2892 2893 cci1_sleep: cci1-sleep-state { 2894 /* SDA, SCL */ 2895 pins = "gpio19", "gpio20"; 2896 function = "cci_i2c"; 2897 2898 drive-strength = <2>; /* 2 mA */ 2899 bias-pull-down; 2900 }; 2901 2902 qspi_clk: qspi-clk-state { 2903 pins = "gpio95"; 2904 function = "qspi_clk"; 2905 }; 2906 2907 qspi_cs0: qspi-cs0-state { 2908 pins = "gpio90"; 2909 function = "qspi_cs"; 2910 }; 2911 2912 qspi_cs1: qspi-cs1-state { 2913 pins = "gpio89"; 2914 function = "qspi_cs"; 2915 }; 2916 2917 qspi_data0: qspi-data0-state { 2918 pins = "gpio91"; 2919 function = "qspi_data"; 2920 }; 2921 2922 qspi_data1: qspi-data1-state { 2923 pins = "gpio92"; 2924 function = "qspi_data"; 2925 }; 2926 2927 qspi_data23: qspi-data23-state { 2928 pins = "gpio93", "gpio94"; 2929 function = "qspi_data"; 2930 }; 2931 2932 qup_i2c0_default: qup-i2c0-default-state { 2933 pins = "gpio0", "gpio1"; 2934 function = "qup0"; 2935 }; 2936 2937 qup_i2c1_default: qup-i2c1-default-state { 2938 pins = "gpio17", "gpio18"; 2939 function = "qup1"; 2940 }; 2941 2942 qup_i2c2_default: qup-i2c2-default-state { 2943 pins = "gpio27", "gpio28"; 2944 function = "qup2"; 2945 }; 2946 2947 qup_i2c3_default: qup-i2c3-default-state { 2948 pins = "gpio41", "gpio42"; 2949 function = "qup3"; 2950 }; 2951 2952 qup_i2c4_default: qup-i2c4-default-state { 2953 pins = "gpio89", "gpio90"; 2954 function = "qup4"; 2955 }; 2956 2957 qup_i2c5_default: qup-i2c5-default-state { 2958 pins = "gpio85", "gpio86"; 2959 function = "qup5"; 2960 }; 2961 2962 qup_i2c6_default: qup-i2c6-default-state { 2963 pins = "gpio45", "gpio46"; 2964 function = "qup6"; 2965 }; 2966 2967 qup_i2c7_default: qup-i2c7-default-state { 2968 pins = "gpio93", "gpio94"; 2969 function = "qup7"; 2970 }; 2971 2972 qup_i2c8_default: qup-i2c8-default-state { 2973 pins = "gpio65", "gpio66"; 2974 function = "qup8"; 2975 }; 2976 2977 qup_i2c9_default: qup-i2c9-default-state { 2978 pins = "gpio6", "gpio7"; 2979 function = "qup9"; 2980 }; 2981 2982 qup_i2c10_default: qup-i2c10-default-state { 2983 pins = "gpio55", "gpio56"; 2984 function = "qup10"; 2985 }; 2986 2987 qup_i2c11_default: qup-i2c11-default-state { 2988 pins = "gpio31", "gpio32"; 2989 function = "qup11"; 2990 }; 2991 2992 qup_i2c12_default: qup-i2c12-default-state { 2993 pins = "gpio49", "gpio50"; 2994 function = "qup12"; 2995 }; 2996 2997 qup_i2c13_default: qup-i2c13-default-state { 2998 pins = "gpio105", "gpio106"; 2999 function = "qup13"; 3000 }; 3001 3002 qup_i2c14_default: qup-i2c14-default-state { 3003 pins = "gpio33", "gpio34"; 3004 function = "qup14"; 3005 }; 3006 3007 qup_i2c15_default: qup-i2c15-default-state { 3008 pins = "gpio81", "gpio82"; 3009 function = "qup15"; 3010 }; 3011 3012 qup_spi0_default: qup-spi0-default-state { 3013 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 3014 function = "qup0"; 3015 }; 3016 3017 qup_spi1_default: qup-spi1-default-state { 3018 pins = "gpio17", "gpio18", "gpio19", "gpio20"; 3019 function = "qup1"; 3020 }; 3021 3022 qup_spi2_default: qup-spi2-default-state { 3023 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 3024 function = "qup2"; 3025 }; 3026 3027 qup_spi3_default: qup-spi3-default-state { 3028 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 3029 function = "qup3"; 3030 }; 3031 3032 qup_spi4_default: qup-spi4-default-state { 3033 pins = "gpio89", "gpio90", "gpio91", "gpio92"; 3034 function = "qup4"; 3035 }; 3036 3037 qup_spi5_default: qup-spi5-default-state { 3038 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 3039 function = "qup5"; 3040 }; 3041 3042 qup_spi6_default: qup-spi6-default-state { 3043 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 3044 function = "qup6"; 3045 }; 3046 3047 qup_spi7_default: qup-spi7-default-state { 3048 pins = "gpio93", "gpio94", "gpio95", "gpio96"; 3049 function = "qup7"; 3050 }; 3051 3052 qup_spi8_default: qup-spi8-default-state { 3053 pins = "gpio65", "gpio66", "gpio67", "gpio68"; 3054 function = "qup8"; 3055 }; 3056 3057 qup_spi9_default: qup-spi9-default-state { 3058 pins = "gpio6", "gpio7", "gpio4", "gpio5"; 3059 function = "qup9"; 3060 }; 3061 3062 qup_spi10_default: qup-spi10-default-state { 3063 pins = "gpio55", "gpio56", "gpio53", "gpio54"; 3064 function = "qup10"; 3065 }; 3066 3067 qup_spi11_default: qup-spi11-default-state { 3068 pins = "gpio31", "gpio32", "gpio33", "gpio34"; 3069 function = "qup11"; 3070 }; 3071 3072 qup_spi12_default: qup-spi12-default-state { 3073 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 3074 function = "qup12"; 3075 }; 3076 3077 qup_spi13_default: qup-spi13-default-state { 3078 pins = "gpio105", "gpio106", "gpio107", "gpio108"; 3079 function = "qup13"; 3080 }; 3081 3082 qup_spi14_default: qup-spi14-default-state { 3083 pins = "gpio33", "gpio34", "gpio31", "gpio32"; 3084 function = "qup14"; 3085 }; 3086 3087 qup_spi15_default: qup-spi15-default-state { 3088 pins = "gpio81", "gpio82", "gpio83", "gpio84"; 3089 function = "qup15"; 3090 }; 3091 3092 qup_uart0_default: qup-uart0-default-state { 3093 qup_uart0_tx: tx-pins { 3094 pins = "gpio2"; 3095 function = "qup0"; 3096 }; 3097 3098 qup_uart0_rx: rx-pins { 3099 pins = "gpio3"; 3100 function = "qup0"; 3101 }; 3102 }; 3103 3104 qup_uart1_default: qup-uart1-default-state { 3105 qup_uart1_tx: tx-pins { 3106 pins = "gpio19"; 3107 function = "qup1"; 3108 }; 3109 3110 qup_uart1_rx: rx-pins { 3111 pins = "gpio20"; 3112 function = "qup1"; 3113 }; 3114 }; 3115 3116 qup_uart2_default: qup-uart2-default-state { 3117 qup_uart2_tx: tx-pins { 3118 pins = "gpio29"; 3119 function = "qup2"; 3120 }; 3121 3122 qup_uart2_rx: rx-pins { 3123 pins = "gpio30"; 3124 function = "qup2"; 3125 }; 3126 }; 3127 3128 qup_uart3_default: qup-uart3-default-state { 3129 qup_uart3_tx: tx-pins { 3130 pins = "gpio43"; 3131 function = "qup3"; 3132 }; 3133 3134 qup_uart3_rx: rx-pins { 3135 pins = "gpio44"; 3136 function = "qup3"; 3137 }; 3138 }; 3139 3140 qup_uart3_4pin: qup-uart3-4pin-state { 3141 qup_uart3_4pin_cts: cts-pins { 3142 pins = "gpio41"; 3143 function = "qup3"; 3144 }; 3145 3146 qup_uart3_4pin_rts_tx: rts-tx-pins { 3147 pins = "gpio42", "gpio43"; 3148 function = "qup3"; 3149 }; 3150 3151 qup_uart3_4pin_rx: rx-pins { 3152 pins = "gpio44"; 3153 function = "qup3"; 3154 }; 3155 }; 3156 3157 qup_uart4_default: qup-uart4-default-state { 3158 qup_uart4_tx: tx-pins { 3159 pins = "gpio91"; 3160 function = "qup4"; 3161 }; 3162 3163 qup_uart4_rx: rx-pins { 3164 pins = "gpio92"; 3165 function = "qup4"; 3166 }; 3167 }; 3168 3169 qup_uart5_default: qup-uart5-default-state { 3170 qup_uart5_tx: tx-pins { 3171 pins = "gpio87"; 3172 function = "qup5"; 3173 }; 3174 3175 qup_uart5_rx: rx-pins { 3176 pins = "gpio88"; 3177 function = "qup5"; 3178 }; 3179 }; 3180 3181 qup_uart6_default: qup-uart6-default-state { 3182 qup_uart6_tx: tx-pins { 3183 pins = "gpio47"; 3184 function = "qup6"; 3185 }; 3186 3187 qup_uart6_rx: rx-pins { 3188 pins = "gpio48"; 3189 function = "qup6"; 3190 }; 3191 }; 3192 3193 qup_uart6_4pin: qup-uart6-4pin-state { 3194 qup_uart6_4pin_cts: cts-pins { 3195 pins = "gpio45"; 3196 function = "qup6"; 3197 bias-pull-down; 3198 }; 3199 3200 qup_uart6_4pin_rts_tx: rts-tx-pins { 3201 pins = "gpio46", "gpio47"; 3202 function = "qup6"; 3203 drive-strength = <2>; 3204 bias-disable; 3205 }; 3206 3207 qup_uart6_4pin_rx: rx-pins { 3208 pins = "gpio48"; 3209 function = "qup6"; 3210 bias-pull-up; 3211 }; 3212 }; 3213 3214 qup_uart7_default: qup-uart7-default-state { 3215 qup_uart7_tx: tx-pins { 3216 pins = "gpio95"; 3217 function = "qup7"; 3218 }; 3219 3220 qup_uart7_rx: rx-pins { 3221 pins = "gpio96"; 3222 function = "qup7"; 3223 }; 3224 }; 3225 3226 qup_uart8_default: qup-uart8-default-state { 3227 qup_uart8_tx: tx-pins { 3228 pins = "gpio67"; 3229 function = "qup8"; 3230 }; 3231 3232 qup_uart8_rx: rx-pins { 3233 pins = "gpio68"; 3234 function = "qup8"; 3235 }; 3236 }; 3237 3238 qup_uart9_default: qup-uart9-default-state { 3239 qup_uart9_tx: tx-pins { 3240 pins = "gpio4"; 3241 function = "qup9"; 3242 }; 3243 3244 qup_uart9_rx: rx-pins { 3245 pins = "gpio5"; 3246 function = "qup9"; 3247 }; 3248 }; 3249 3250 qup_uart10_default: qup-uart10-default-state { 3251 qup_uart10_tx: tx-pins { 3252 pins = "gpio53"; 3253 function = "qup10"; 3254 }; 3255 3256 qup_uart10_rx: rx-pins { 3257 pins = "gpio54"; 3258 function = "qup10"; 3259 }; 3260 }; 3261 3262 qup_uart11_default: qup-uart11-default-state { 3263 qup_uart11_tx: tx-pins { 3264 pins = "gpio33"; 3265 function = "qup11"; 3266 }; 3267 3268 qup_uart11_rx: rx-pins { 3269 pins = "gpio34"; 3270 function = "qup11"; 3271 }; 3272 }; 3273 3274 qup_uart12_default: qup-uart12-default-state { 3275 qup_uart12_tx: tx-pins { 3276 pins = "gpio51"; 3277 function = "qup0"; 3278 }; 3279 3280 qup_uart12_rx: rx-pins { 3281 pins = "gpio52"; 3282 function = "qup0"; 3283 }; 3284 }; 3285 3286 qup_uart13_default: qup-uart13-default-state { 3287 qup_uart13_tx: tx-pins { 3288 pins = "gpio107"; 3289 function = "qup13"; 3290 }; 3291 3292 qup_uart13_rx: rx-pins { 3293 pins = "gpio108"; 3294 function = "qup13"; 3295 }; 3296 }; 3297 3298 qup_uart14_default: qup-uart14-default-state { 3299 qup_uart14_tx: tx-pins { 3300 pins = "gpio31"; 3301 function = "qup14"; 3302 }; 3303 3304 qup_uart14_rx: rx-pins { 3305 pins = "gpio32"; 3306 function = "qup14"; 3307 }; 3308 }; 3309 3310 qup_uart15_default: qup-uart15-default-state { 3311 qup_uart15_tx: tx-pins { 3312 pins = "gpio83"; 3313 function = "qup15"; 3314 }; 3315 3316 qup_uart15_rx: rx-pins { 3317 pins = "gpio84"; 3318 function = "qup15"; 3319 }; 3320 }; 3321 3322 quat_mi2s_sleep: quat-mi2s-sleep-state { 3323 pins = "gpio58", "gpio59"; 3324 function = "gpio"; 3325 drive-strength = <2>; 3326 bias-pull-down; 3327 }; 3328 3329 quat_mi2s_active: quat-mi2s-active-state { 3330 pins = "gpio58", "gpio59"; 3331 function = "qua_mi2s"; 3332 drive-strength = <8>; 3333 bias-disable; 3334 output-high; 3335 }; 3336 3337 quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state { 3338 pins = "gpio60"; 3339 function = "gpio"; 3340 drive-strength = <2>; 3341 bias-pull-down; 3342 }; 3343 3344 quat_mi2s_sd0_active: quat-mi2s-sd0-active-state { 3345 pins = "gpio60"; 3346 function = "qua_mi2s"; 3347 drive-strength = <8>; 3348 bias-disable; 3349 }; 3350 3351 quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state { 3352 pins = "gpio61"; 3353 function = "gpio"; 3354 drive-strength = <2>; 3355 bias-pull-down; 3356 }; 3357 3358 quat_mi2s_sd1_active: quat-mi2s-sd1-active-state { 3359 pins = "gpio61"; 3360 function = "qua_mi2s"; 3361 drive-strength = <8>; 3362 bias-disable; 3363 }; 3364 3365 quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state { 3366 pins = "gpio62"; 3367 function = "gpio"; 3368 drive-strength = <2>; 3369 bias-pull-down; 3370 }; 3371 3372 quat_mi2s_sd2_active: quat-mi2s-sd2-active-state { 3373 pins = "gpio62"; 3374 function = "qua_mi2s"; 3375 drive-strength = <8>; 3376 bias-disable; 3377 }; 3378 3379 quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state { 3380 pins = "gpio63"; 3381 function = "gpio"; 3382 drive-strength = <2>; 3383 bias-pull-down; 3384 }; 3385 3386 quat_mi2s_sd3_active: quat-mi2s-sd3-active-state { 3387 pins = "gpio63"; 3388 function = "qua_mi2s"; 3389 drive-strength = <8>; 3390 bias-disable; 3391 }; 3392 }; 3393 3394 mss_pil: remoteproc@4080000 { 3395 compatible = "qcom,sdm845-mss-pil"; 3396 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; 3397 reg-names = "qdsp6", "rmb"; 3398 3399 interrupts-extended = 3400 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 3401 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3402 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3403 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3404 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3405 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3406 interrupt-names = "wdog", "fatal", "ready", 3407 "handover", "stop-ack", 3408 "shutdown-ack"; 3409 3410 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 3411 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 3412 <&gcc GCC_BOOT_ROM_AHB_CLK>, 3413 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 3414 <&gcc GCC_MSS_SNOC_AXI_CLK>, 3415 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 3416 <&gcc GCC_PRNG_AHB_CLK>, 3417 <&rpmhcc RPMH_CXO_CLK>; 3418 clock-names = "iface", "bus", "mem", "gpll0_mss", 3419 "snoc_axi", "mnoc_axi", "prng", "xo"; 3420 3421 qcom,qmp = <&aoss_qmp>; 3422 3423 qcom,smem-states = <&modem_smp2p_out 0>; 3424 qcom,smem-state-names = "stop"; 3425 3426 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 3427 <&pdc_reset PDC_MODEM_SYNC_RESET>; 3428 reset-names = "mss_restart", "pdc_reset"; 3429 3430 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 3431 3432 power-domains = <&rpmhpd SDM845_CX>, 3433 <&rpmhpd SDM845_MX>, 3434 <&rpmhpd SDM845_MSS>; 3435 power-domain-names = "cx", "mx", "mss"; 3436 3437 status = "disabled"; 3438 3439 mba { 3440 memory-region = <&mba_region>; 3441 }; 3442 3443 mpss { 3444 memory-region = <&mpss_region>; 3445 }; 3446 3447 metadata { 3448 memory-region = <&mdata_mem>; 3449 }; 3450 3451 glink-edge { 3452 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 3453 label = "modem"; 3454 qcom,remote-pid = <1>; 3455 mboxes = <&apss_shared 12>; 3456 }; 3457 }; 3458 3459 gpucc: clock-controller@5090000 { 3460 compatible = "qcom,sdm845-gpucc"; 3461 reg = <0 0x05090000 0 0x9000>; 3462 #clock-cells = <1>; 3463 #reset-cells = <1>; 3464 #power-domain-cells = <1>; 3465 clocks = <&rpmhcc RPMH_CXO_CLK>, 3466 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3467 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3468 clock-names = "bi_tcxo", 3469 "gcc_gpu_gpll0_clk_src", 3470 "gcc_gpu_gpll0_div_clk_src"; 3471 }; 3472 3473 slpi_pas: remoteproc@5c00000 { 3474 compatible = "qcom,sdm845-slpi-pas"; 3475 reg = <0 0x5c00000 0 0x4000>; 3476 3477 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 3478 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3479 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3480 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3481 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3482 interrupt-names = "wdog", "fatal", "ready", 3483 "handover", "stop-ack"; 3484 3485 clocks = <&rpmhcc RPMH_CXO_CLK>; 3486 clock-names = "xo"; 3487 3488 qcom,qmp = <&aoss_qmp>; 3489 3490 power-domains = <&rpmhpd SDM845_LCX>, 3491 <&rpmhpd SDM845_LMX>; 3492 power-domain-names = "lcx", "lmx"; 3493 3494 memory-region = <&slpi_mem>; 3495 3496 qcom,smem-states = <&slpi_smp2p_out 0>; 3497 qcom,smem-state-names = "stop"; 3498 3499 status = "disabled"; 3500 3501 glink-edge { 3502 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 3503 label = "dsps"; 3504 qcom,remote-pid = <3>; 3505 mboxes = <&apss_shared 24>; 3506 3507 fastrpc { 3508 compatible = "qcom,fastrpc"; 3509 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3510 label = "sdsp"; 3511 qcom,non-secure-domain; 3512 qcom,vmids = <QCOM_SCM_VMID_HLOS QCOM_SCM_VMID_MSS_MSA 3513 QCOM_SCM_VMID_SSC_Q6 QCOM_SCM_VMID_ADSP_Q6>; 3514 memory-region = <&fastrpc_mem>; 3515 #address-cells = <1>; 3516 #size-cells = <0>; 3517 3518 compute-cb@0 { 3519 compatible = "qcom,fastrpc-compute-cb"; 3520 reg = <0>; 3521 }; 3522 }; 3523 }; 3524 }; 3525 3526 stm@6002000 { 3527 compatible = "arm,coresight-stm", "arm,primecell"; 3528 reg = <0 0x06002000 0 0x1000>, 3529 <0 0x16280000 0 0x180000>; 3530 reg-names = "stm-base", "stm-stimulus-base"; 3531 3532 clocks = <&aoss_qmp>; 3533 clock-names = "apb_pclk"; 3534 3535 out-ports { 3536 port { 3537 stm_out: endpoint { 3538 remote-endpoint = 3539 <&funnel0_in7>; 3540 }; 3541 }; 3542 }; 3543 }; 3544 3545 funnel@6041000 { 3546 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3547 reg = <0 0x06041000 0 0x1000>; 3548 3549 clocks = <&aoss_qmp>; 3550 clock-names = "apb_pclk"; 3551 3552 out-ports { 3553 port { 3554 funnel0_out: endpoint { 3555 remote-endpoint = 3556 <&merge_funnel_in0>; 3557 }; 3558 }; 3559 }; 3560 3561 in-ports { 3562 #address-cells = <1>; 3563 #size-cells = <0>; 3564 3565 port@7 { 3566 reg = <7>; 3567 funnel0_in7: endpoint { 3568 remote-endpoint = <&stm_out>; 3569 }; 3570 }; 3571 }; 3572 }; 3573 3574 funnel@6043000 { 3575 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3576 reg = <0 0x06043000 0 0x1000>; 3577 3578 clocks = <&aoss_qmp>; 3579 clock-names = "apb_pclk"; 3580 3581 out-ports { 3582 port { 3583 funnel2_out: endpoint { 3584 remote-endpoint = 3585 <&merge_funnel_in2>; 3586 }; 3587 }; 3588 }; 3589 3590 in-ports { 3591 #address-cells = <1>; 3592 #size-cells = <0>; 3593 3594 port@5 { 3595 reg = <5>; 3596 funnel2_in5: endpoint { 3597 remote-endpoint = 3598 <&apss_merge_funnel_out>; 3599 }; 3600 }; 3601 }; 3602 }; 3603 3604 funnel@6045000 { 3605 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3606 reg = <0 0x06045000 0 0x1000>; 3607 3608 clocks = <&aoss_qmp>; 3609 clock-names = "apb_pclk"; 3610 3611 out-ports { 3612 port { 3613 merge_funnel_out: endpoint { 3614 remote-endpoint = <&etf_in>; 3615 }; 3616 }; 3617 }; 3618 3619 in-ports { 3620 #address-cells = <1>; 3621 #size-cells = <0>; 3622 3623 port@0 { 3624 reg = <0>; 3625 merge_funnel_in0: endpoint { 3626 remote-endpoint = 3627 <&funnel0_out>; 3628 }; 3629 }; 3630 3631 port@2 { 3632 reg = <2>; 3633 merge_funnel_in2: endpoint { 3634 remote-endpoint = 3635 <&funnel2_out>; 3636 }; 3637 }; 3638 }; 3639 }; 3640 3641 replicator@6046000 { 3642 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3643 reg = <0 0x06046000 0 0x1000>; 3644 3645 clocks = <&aoss_qmp>; 3646 clock-names = "apb_pclk"; 3647 3648 out-ports { 3649 port { 3650 replicator_out: endpoint { 3651 remote-endpoint = <&etr_in>; 3652 }; 3653 }; 3654 }; 3655 3656 in-ports { 3657 port { 3658 replicator_in: endpoint { 3659 remote-endpoint = <&etf_out>; 3660 }; 3661 }; 3662 }; 3663 }; 3664 3665 etf@6047000 { 3666 compatible = "arm,coresight-tmc", "arm,primecell"; 3667 reg = <0 0x06047000 0 0x1000>; 3668 3669 clocks = <&aoss_qmp>; 3670 clock-names = "apb_pclk"; 3671 3672 out-ports { 3673 port { 3674 etf_out: endpoint { 3675 remote-endpoint = 3676 <&replicator_in>; 3677 }; 3678 }; 3679 }; 3680 3681 in-ports { 3682 3683 port { 3684 etf_in: endpoint { 3685 remote-endpoint = 3686 <&merge_funnel_out>; 3687 }; 3688 }; 3689 }; 3690 }; 3691 3692 etr@6048000 { 3693 compatible = "arm,coresight-tmc", "arm,primecell"; 3694 reg = <0 0x06048000 0 0x1000>; 3695 3696 clocks = <&aoss_qmp>; 3697 clock-names = "apb_pclk"; 3698 arm,scatter-gather; 3699 3700 in-ports { 3701 port { 3702 etr_in: endpoint { 3703 remote-endpoint = 3704 <&replicator_out>; 3705 }; 3706 }; 3707 }; 3708 }; 3709 3710 etm@7040000 { 3711 compatible = "arm,coresight-etm4x", "arm,primecell"; 3712 reg = <0 0x07040000 0 0x1000>; 3713 3714 cpu = <&cpu0>; 3715 3716 clocks = <&aoss_qmp>; 3717 clock-names = "apb_pclk"; 3718 arm,coresight-loses-context-with-cpu; 3719 3720 out-ports { 3721 port { 3722 etm0_out: endpoint { 3723 remote-endpoint = 3724 <&apss_funnel_in0>; 3725 }; 3726 }; 3727 }; 3728 }; 3729 3730 etm@7140000 { 3731 compatible = "arm,coresight-etm4x", "arm,primecell"; 3732 reg = <0 0x07140000 0 0x1000>; 3733 3734 cpu = <&cpu1>; 3735 3736 clocks = <&aoss_qmp>; 3737 clock-names = "apb_pclk"; 3738 arm,coresight-loses-context-with-cpu; 3739 3740 out-ports { 3741 port { 3742 etm1_out: endpoint { 3743 remote-endpoint = 3744 <&apss_funnel_in1>; 3745 }; 3746 }; 3747 }; 3748 }; 3749 3750 etm@7240000 { 3751 compatible = "arm,coresight-etm4x", "arm,primecell"; 3752 reg = <0 0x07240000 0 0x1000>; 3753 3754 cpu = <&cpu2>; 3755 3756 clocks = <&aoss_qmp>; 3757 clock-names = "apb_pclk"; 3758 arm,coresight-loses-context-with-cpu; 3759 3760 out-ports { 3761 port { 3762 etm2_out: endpoint { 3763 remote-endpoint = 3764 <&apss_funnel_in2>; 3765 }; 3766 }; 3767 }; 3768 }; 3769 3770 etm@7340000 { 3771 compatible = "arm,coresight-etm4x", "arm,primecell"; 3772 reg = <0 0x07340000 0 0x1000>; 3773 3774 cpu = <&cpu3>; 3775 3776 clocks = <&aoss_qmp>; 3777 clock-names = "apb_pclk"; 3778 arm,coresight-loses-context-with-cpu; 3779 3780 out-ports { 3781 port { 3782 etm3_out: endpoint { 3783 remote-endpoint = 3784 <&apss_funnel_in3>; 3785 }; 3786 }; 3787 }; 3788 }; 3789 3790 etm@7440000 { 3791 compatible = "arm,coresight-etm4x", "arm,primecell"; 3792 reg = <0 0x07440000 0 0x1000>; 3793 3794 cpu = <&cpu4>; 3795 3796 clocks = <&aoss_qmp>; 3797 clock-names = "apb_pclk"; 3798 arm,coresight-loses-context-with-cpu; 3799 3800 out-ports { 3801 port { 3802 etm4_out: endpoint { 3803 remote-endpoint = 3804 <&apss_funnel_in4>; 3805 }; 3806 }; 3807 }; 3808 }; 3809 3810 etm@7540000 { 3811 compatible = "arm,coresight-etm4x", "arm,primecell"; 3812 reg = <0 0x07540000 0 0x1000>; 3813 3814 cpu = <&cpu5>; 3815 3816 clocks = <&aoss_qmp>; 3817 clock-names = "apb_pclk"; 3818 arm,coresight-loses-context-with-cpu; 3819 3820 out-ports { 3821 port { 3822 etm5_out: endpoint { 3823 remote-endpoint = 3824 <&apss_funnel_in5>; 3825 }; 3826 }; 3827 }; 3828 }; 3829 3830 etm@7640000 { 3831 compatible = "arm,coresight-etm4x", "arm,primecell"; 3832 reg = <0 0x07640000 0 0x1000>; 3833 3834 cpu = <&cpu6>; 3835 3836 clocks = <&aoss_qmp>; 3837 clock-names = "apb_pclk"; 3838 arm,coresight-loses-context-with-cpu; 3839 3840 out-ports { 3841 port { 3842 etm6_out: endpoint { 3843 remote-endpoint = 3844 <&apss_funnel_in6>; 3845 }; 3846 }; 3847 }; 3848 }; 3849 3850 etm@7740000 { 3851 compatible = "arm,coresight-etm4x", "arm,primecell"; 3852 reg = <0 0x07740000 0 0x1000>; 3853 3854 cpu = <&cpu7>; 3855 3856 clocks = <&aoss_qmp>; 3857 clock-names = "apb_pclk"; 3858 arm,coresight-loses-context-with-cpu; 3859 3860 out-ports { 3861 port { 3862 etm7_out: endpoint { 3863 remote-endpoint = 3864 <&apss_funnel_in7>; 3865 }; 3866 }; 3867 }; 3868 }; 3869 3870 funnel@7800000 { /* APSS Funnel */ 3871 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3872 reg = <0 0x07800000 0 0x1000>; 3873 3874 clocks = <&aoss_qmp>; 3875 clock-names = "apb_pclk"; 3876 3877 out-ports { 3878 port { 3879 apss_funnel_out: endpoint { 3880 remote-endpoint = 3881 <&apss_merge_funnel_in>; 3882 }; 3883 }; 3884 }; 3885 3886 in-ports { 3887 #address-cells = <1>; 3888 #size-cells = <0>; 3889 3890 port@0 { 3891 reg = <0>; 3892 apss_funnel_in0: endpoint { 3893 remote-endpoint = 3894 <&etm0_out>; 3895 }; 3896 }; 3897 3898 port@1 { 3899 reg = <1>; 3900 apss_funnel_in1: endpoint { 3901 remote-endpoint = 3902 <&etm1_out>; 3903 }; 3904 }; 3905 3906 port@2 { 3907 reg = <2>; 3908 apss_funnel_in2: endpoint { 3909 remote-endpoint = 3910 <&etm2_out>; 3911 }; 3912 }; 3913 3914 port@3 { 3915 reg = <3>; 3916 apss_funnel_in3: endpoint { 3917 remote-endpoint = 3918 <&etm3_out>; 3919 }; 3920 }; 3921 3922 port@4 { 3923 reg = <4>; 3924 apss_funnel_in4: endpoint { 3925 remote-endpoint = 3926 <&etm4_out>; 3927 }; 3928 }; 3929 3930 port@5 { 3931 reg = <5>; 3932 apss_funnel_in5: endpoint { 3933 remote-endpoint = 3934 <&etm5_out>; 3935 }; 3936 }; 3937 3938 port@6 { 3939 reg = <6>; 3940 apss_funnel_in6: endpoint { 3941 remote-endpoint = 3942 <&etm6_out>; 3943 }; 3944 }; 3945 3946 port@7 { 3947 reg = <7>; 3948 apss_funnel_in7: endpoint { 3949 remote-endpoint = 3950 <&etm7_out>; 3951 }; 3952 }; 3953 }; 3954 }; 3955 3956 funnel@7810000 { 3957 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3958 reg = <0 0x07810000 0 0x1000>; 3959 3960 clocks = <&aoss_qmp>; 3961 clock-names = "apb_pclk"; 3962 3963 out-ports { 3964 port { 3965 apss_merge_funnel_out: endpoint { 3966 remote-endpoint = 3967 <&funnel2_in5>; 3968 }; 3969 }; 3970 }; 3971 3972 in-ports { 3973 port { 3974 apss_merge_funnel_in: endpoint { 3975 remote-endpoint = 3976 <&apss_funnel_out>; 3977 }; 3978 }; 3979 }; 3980 }; 3981 3982 sdhc_2: mmc@8804000 { 3983 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 3984 reg = <0 0x08804000 0 0x1000>; 3985 3986 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3987 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3988 interrupt-names = "hc_irq", "pwr_irq"; 3989 3990 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3991 <&gcc GCC_SDCC2_APPS_CLK>, 3992 <&rpmhcc RPMH_CXO_CLK>; 3993 clock-names = "iface", "core", "xo"; 3994 iommus = <&apps_smmu 0xa0 0xf>; 3995 power-domains = <&rpmhpd SDM845_CX>; 3996 operating-points-v2 = <&sdhc2_opp_table>; 3997 3998 status = "disabled"; 3999 4000 sdhc2_opp_table: opp-table { 4001 compatible = "operating-points-v2"; 4002 4003 opp-9600000 { 4004 opp-hz = /bits/ 64 <9600000>; 4005 required-opps = <&rpmhpd_opp_min_svs>; 4006 }; 4007 4008 opp-19200000 { 4009 opp-hz = /bits/ 64 <19200000>; 4010 required-opps = <&rpmhpd_opp_low_svs>; 4011 }; 4012 4013 opp-100000000 { 4014 opp-hz = /bits/ 64 <100000000>; 4015 required-opps = <&rpmhpd_opp_svs>; 4016 }; 4017 4018 opp-201500000 { 4019 opp-hz = /bits/ 64 <201500000>; 4020 required-opps = <&rpmhpd_opp_svs_l1>; 4021 }; 4022 }; 4023 }; 4024 4025 qspi: spi@88df000 { 4026 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 4027 reg = <0 0x088df000 0 0x600>; 4028 iommus = <&apps_smmu 0x160 0x0>; 4029 #address-cells = <1>; 4030 #size-cells = <0>; 4031 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 4032 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 4033 <&gcc GCC_QSPI_CORE_CLK>; 4034 clock-names = "iface", "core"; 4035 power-domains = <&rpmhpd SDM845_CX>; 4036 operating-points-v2 = <&qspi_opp_table>; 4037 status = "disabled"; 4038 }; 4039 4040 slim: slim-ngd@171c0000 { 4041 compatible = "qcom,slim-ngd-v2.1.0"; 4042 reg = <0 0x171c0000 0 0x2c000>; 4043 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 4044 4045 dmas = <&slimbam 3>, <&slimbam 4>; 4046 dma-names = "rx", "tx"; 4047 4048 iommus = <&apps_smmu 0x1806 0x0>; 4049 #address-cells = <1>; 4050 #size-cells = <0>; 4051 status = "disabled"; 4052 }; 4053 4054 lmh_cluster1: lmh@17d70800 { 4055 compatible = "qcom,sdm845-lmh"; 4056 reg = <0 0x17d70800 0 0x400>; 4057 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 4058 cpus = <&cpu4>; 4059 qcom,lmh-temp-arm-millicelsius = <65000>; 4060 qcom,lmh-temp-low-millicelsius = <94500>; 4061 qcom,lmh-temp-high-millicelsius = <95000>; 4062 interrupt-controller; 4063 #interrupt-cells = <1>; 4064 }; 4065 4066 lmh_cluster0: lmh@17d78800 { 4067 compatible = "qcom,sdm845-lmh"; 4068 reg = <0 0x17d78800 0 0x400>; 4069 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 4070 cpus = <&cpu0>; 4071 qcom,lmh-temp-arm-millicelsius = <65000>; 4072 qcom,lmh-temp-low-millicelsius = <94500>; 4073 qcom,lmh-temp-high-millicelsius = <95000>; 4074 interrupt-controller; 4075 #interrupt-cells = <1>; 4076 }; 4077 4078 usb_1_hsphy: phy@88e2000 { 4079 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 4080 reg = <0 0x088e2000 0 0x400>; 4081 status = "disabled"; 4082 #phy-cells = <0>; 4083 4084 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 4085 <&rpmhcc RPMH_CXO_CLK>; 4086 clock-names = "cfg_ahb", "ref"; 4087 4088 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 4089 4090 nvmem-cells = <&qusb2p_hstx_trim>; 4091 }; 4092 4093 usb_2_hsphy: phy@88e3000 { 4094 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 4095 reg = <0 0x088e3000 0 0x400>; 4096 status = "disabled"; 4097 #phy-cells = <0>; 4098 4099 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 4100 <&rpmhcc RPMH_CXO_CLK>; 4101 clock-names = "cfg_ahb", "ref"; 4102 4103 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 4104 4105 nvmem-cells = <&qusb2s_hstx_trim>; 4106 }; 4107 4108 usb_1_qmpphy: phy@88e8000 { 4109 compatible = "qcom,sdm845-qmp-usb3-dp-phy"; 4110 reg = <0 0x088e8000 0 0x3000>; 4111 status = "disabled"; 4112 4113 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4114 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 4115 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 4116 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, 4117 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 4118 clock-names = "aux", 4119 "ref", 4120 "com_aux", 4121 "usb3_pipe", 4122 "cfg_ahb"; 4123 4124 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 4125 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 4126 reset-names = "phy", "common"; 4127 4128 #clock-cells = <1>; 4129 #phy-cells = <1>; 4130 orientation-switch; 4131 4132 ports { 4133 #address-cells = <1>; 4134 #size-cells = <0>; 4135 4136 port@0 { 4137 reg = <0>; 4138 4139 usb_1_qmpphy_out: endpoint { 4140 }; 4141 }; 4142 4143 port@1 { 4144 reg = <1>; 4145 4146 usb_1_qmpphy_usb_ss_in: endpoint { 4147 remote-endpoint = <&usb_1_dwc3_ss>; 4148 }; 4149 }; 4150 4151 port@2 { 4152 reg = <2>; 4153 4154 usb_1_qmpphy_dp_in: endpoint { 4155 remote-endpoint = <&mdss_dp_out>; 4156 }; 4157 }; 4158 }; 4159 }; 4160 4161 usb_2_qmpphy: phy@88eb000 { 4162 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 4163 reg = <0 0x088eb000 0 0x1000>; 4164 4165 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 4166 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 4167 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 4168 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 4169 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 4170 clock-names = "aux", 4171 "cfg_ahb", 4172 "ref", 4173 "com_aux", 4174 "pipe"; 4175 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 4176 #clock-cells = <0>; 4177 #phy-cells = <0>; 4178 4179 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 4180 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 4181 reset-names = "phy", 4182 "phy_phy"; 4183 4184 status = "disabled"; 4185 }; 4186 4187 usb_1: usb@a6f8800 { 4188 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 4189 reg = <0 0x0a6f8800 0 0x400>; 4190 status = "disabled"; 4191 #address-cells = <2>; 4192 #size-cells = <2>; 4193 ranges; 4194 dma-ranges; 4195 4196 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4197 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4198 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4199 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4200 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4201 clock-names = "cfg_noc", 4202 "core", 4203 "iface", 4204 "sleep", 4205 "mock_utmi"; 4206 4207 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4208 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4209 assigned-clock-rates = <19200000>, <150000000>; 4210 4211 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4212 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4213 <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>, 4214 <&pdc_intc 8 IRQ_TYPE_EDGE_BOTH>, 4215 <&pdc_intc 6 IRQ_TYPE_LEVEL_HIGH>; 4216 interrupt-names = "pwr_event", 4217 "hs_phy_irq", 4218 "dp_hs_phy_irq", 4219 "dm_hs_phy_irq", 4220 "ss_phy_irq"; 4221 4222 power-domains = <&gcc USB30_PRIM_GDSC>; 4223 4224 resets = <&gcc GCC_USB30_PRIM_BCR>; 4225 4226 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>, 4227 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4228 interconnect-names = "usb-ddr", "apps-usb"; 4229 4230 usb_1_dwc3: usb@a600000 { 4231 compatible = "snps,dwc3"; 4232 reg = <0 0x0a600000 0 0xcd00>; 4233 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4234 iommus = <&apps_smmu 0x740 0>; 4235 snps,dis_u2_susphy_quirk; 4236 snps,dis_enblslpm_quirk; 4237 snps,parkmode-disable-ss-quirk; 4238 snps,dis-u1-entry-quirk; 4239 snps,dis-u2-entry-quirk; 4240 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4241 phy-names = "usb2-phy", "usb3-phy"; 4242 4243 ports { 4244 #address-cells = <1>; 4245 #size-cells = <0>; 4246 4247 port@0 { 4248 reg = <0>; 4249 4250 usb_1_dwc3_hs: endpoint { 4251 }; 4252 }; 4253 4254 port@1 { 4255 reg = <1>; 4256 4257 usb_1_dwc3_ss: endpoint { 4258 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 4259 }; 4260 }; 4261 }; 4262 }; 4263 }; 4264 4265 usb_2: usb@a8f8800 { 4266 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 4267 reg = <0 0x0a8f8800 0 0x400>; 4268 status = "disabled"; 4269 #address-cells = <2>; 4270 #size-cells = <2>; 4271 ranges; 4272 dma-ranges; 4273 4274 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4275 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4276 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4277 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4278 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 4279 clock-names = "cfg_noc", 4280 "core", 4281 "iface", 4282 "sleep", 4283 "mock_utmi"; 4284 4285 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4286 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4287 assigned-clock-rates = <19200000>, <150000000>; 4288 4289 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 4290 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 4291 <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>, 4292 <&pdc_intc 10 IRQ_TYPE_EDGE_BOTH>, 4293 <&pdc_intc 7 IRQ_TYPE_LEVEL_HIGH>; 4294 interrupt-names = "pwr_event", 4295 "hs_phy_irq", 4296 "dp_hs_phy_irq", 4297 "dm_hs_phy_irq", 4298 "ss_phy_irq"; 4299 4300 power-domains = <&gcc USB30_SEC_GDSC>; 4301 4302 resets = <&gcc GCC_USB30_SEC_BCR>; 4303 4304 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>, 4305 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 4306 interconnect-names = "usb-ddr", "apps-usb"; 4307 4308 usb_2_dwc3: usb@a800000 { 4309 compatible = "snps,dwc3"; 4310 reg = <0 0x0a800000 0 0xcd00>; 4311 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 4312 iommus = <&apps_smmu 0x760 0>; 4313 snps,dis_u2_susphy_quirk; 4314 snps,dis_enblslpm_quirk; 4315 snps,parkmode-disable-ss-quirk; 4316 snps,dis-u1-entry-quirk; 4317 snps,dis-u2-entry-quirk; 4318 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 4319 phy-names = "usb2-phy", "usb3-phy"; 4320 }; 4321 }; 4322 4323 venus: video-codec@aa00000 { 4324 compatible = "qcom,sdm845-venus-v2"; 4325 reg = <0 0x0aa00000 0 0xff000>; 4326 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4327 power-domains = <&videocc VENUS_GDSC>, 4328 <&videocc VCODEC0_GDSC>, 4329 <&videocc VCODEC1_GDSC>, 4330 <&rpmhpd SDM845_CX>; 4331 power-domain-names = "venus", "vcodec0", "vcodec1", "cx"; 4332 operating-points-v2 = <&venus_opp_table>; 4333 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 4334 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 4335 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 4336 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 4337 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>, 4338 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, 4339 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; 4340 clock-names = "core", "iface", "bus", 4341 "vcodec0_core", "vcodec0_bus", 4342 "vcodec1_core", "vcodec1_bus"; 4343 iommus = <&apps_smmu 0x10a0 0x8>, 4344 <&apps_smmu 0x10b0 0x0>; 4345 memory-region = <&venus_mem>; 4346 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>, 4347 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 4348 interconnect-names = "video-mem", "cpu-cfg"; 4349 4350 status = "disabled"; 4351 4352 venus_opp_table: opp-table { 4353 compatible = "operating-points-v2"; 4354 4355 opp-100000000 { 4356 opp-hz = /bits/ 64 <100000000>; 4357 required-opps = <&rpmhpd_opp_min_svs>; 4358 }; 4359 4360 opp-200000000 { 4361 opp-hz = /bits/ 64 <200000000>; 4362 required-opps = <&rpmhpd_opp_low_svs>; 4363 }; 4364 4365 opp-320000000 { 4366 opp-hz = /bits/ 64 <320000000>; 4367 required-opps = <&rpmhpd_opp_svs>; 4368 }; 4369 4370 opp-380000000 { 4371 opp-hz = /bits/ 64 <380000000>; 4372 required-opps = <&rpmhpd_opp_svs_l1>; 4373 }; 4374 4375 opp-444000000 { 4376 opp-hz = /bits/ 64 <444000000>; 4377 required-opps = <&rpmhpd_opp_nom>; 4378 }; 4379 4380 opp-533000097 { 4381 opp-hz = /bits/ 64 <533000097>; 4382 required-opps = <&rpmhpd_opp_turbo>; 4383 }; 4384 }; 4385 }; 4386 4387 videocc: clock-controller@ab00000 { 4388 compatible = "qcom,sdm845-videocc"; 4389 reg = <0 0x0ab00000 0 0x10000>; 4390 clocks = <&rpmhcc RPMH_CXO_CLK>; 4391 clock-names = "bi_tcxo"; 4392 #clock-cells = <1>; 4393 #power-domain-cells = <1>; 4394 #reset-cells = <1>; 4395 }; 4396 4397 camss: camss@acb3000 { 4398 compatible = "qcom,sdm845-camss"; 4399 4400 reg = <0 0x0acb3000 0 0x1000>, 4401 <0 0x0acba000 0 0x1000>, 4402 <0 0x0acc8000 0 0x1000>, 4403 <0 0x0ac65000 0 0x1000>, 4404 <0 0x0ac66000 0 0x1000>, 4405 <0 0x0ac67000 0 0x1000>, 4406 <0 0x0ac68000 0 0x1000>, 4407 <0 0x0acaf000 0 0x4000>, 4408 <0 0x0acb6000 0 0x4000>, 4409 <0 0x0acc4000 0 0x4000>; 4410 reg-names = "csid0", 4411 "csid1", 4412 "csid2", 4413 "csiphy0", 4414 "csiphy1", 4415 "csiphy2", 4416 "csiphy3", 4417 "vfe0", 4418 "vfe1", 4419 "vfe_lite"; 4420 4421 interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 4422 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, 4423 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 4424 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 4425 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 4426 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 4427 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 4428 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 4429 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 4430 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>; 4431 interrupt-names = "csid0", 4432 "csid1", 4433 "csid2", 4434 "csiphy0", 4435 "csiphy1", 4436 "csiphy2", 4437 "csiphy3", 4438 "vfe0", 4439 "vfe1", 4440 "vfe_lite"; 4441 4442 power-domains = <&clock_camcc IFE_0_GDSC>, 4443 <&clock_camcc IFE_1_GDSC>, 4444 <&clock_camcc TITAN_TOP_GDSC>; 4445 4446 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4447 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 4448 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, 4449 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, 4450 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, 4451 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, 4452 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, 4453 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, 4454 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, 4455 <&clock_camcc CAM_CC_CSIPHY0_CLK>, 4456 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, 4457 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, 4458 <&clock_camcc CAM_CC_CSIPHY1_CLK>, 4459 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, 4460 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, 4461 <&clock_camcc CAM_CC_CSIPHY2_CLK>, 4462 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, 4463 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, 4464 <&clock_camcc CAM_CC_CSIPHY3_CLK>, 4465 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, 4466 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, 4467 <&gcc GCC_CAMERA_AHB_CLK>, 4468 <&gcc GCC_CAMERA_AXI_CLK>, 4469 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4470 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4471 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, 4472 <&clock_camcc CAM_CC_IFE_0_CLK>, 4473 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4474 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, 4475 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, 4476 <&clock_camcc CAM_CC_IFE_1_CLK>, 4477 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4478 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, 4479 <&clock_camcc CAM_CC_IFE_LITE_CLK>, 4480 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4481 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>; 4482 clock-names = "camnoc_axi", 4483 "cpas_ahb", 4484 "cphy_rx_src", 4485 "csi0", 4486 "csi0_src", 4487 "csi1", 4488 "csi1_src", 4489 "csi2", 4490 "csi2_src", 4491 "csiphy0", 4492 "csiphy0_timer", 4493 "csiphy0_timer_src", 4494 "csiphy1", 4495 "csiphy1_timer", 4496 "csiphy1_timer_src", 4497 "csiphy2", 4498 "csiphy2_timer", 4499 "csiphy2_timer_src", 4500 "csiphy3", 4501 "csiphy3_timer", 4502 "csiphy3_timer_src", 4503 "gcc_camera_ahb", 4504 "gcc_camera_axi", 4505 "slow_ahb_src", 4506 "soc_ahb", 4507 "vfe0_axi", 4508 "vfe0", 4509 "vfe0_cphy_rx", 4510 "vfe0_src", 4511 "vfe1_axi", 4512 "vfe1", 4513 "vfe1_cphy_rx", 4514 "vfe1_src", 4515 "vfe_lite", 4516 "vfe_lite_cphy_rx", 4517 "vfe_lite_src"; 4518 4519 iommus = <&apps_smmu 0x0808 0x0>, 4520 <&apps_smmu 0x0810 0x8>, 4521 <&apps_smmu 0x0c08 0x0>, 4522 <&apps_smmu 0x0c10 0x8>; 4523 4524 status = "disabled"; 4525 4526 ports { 4527 #address-cells = <1>; 4528 #size-cells = <0>; 4529 4530 port@0 { 4531 reg = <0>; 4532 }; 4533 4534 port@1 { 4535 reg = <1>; 4536 }; 4537 4538 port@2 { 4539 reg = <2>; 4540 }; 4541 4542 port@3 { 4543 reg = <3>; 4544 }; 4545 }; 4546 }; 4547 4548 cci: cci@ac4a000 { 4549 compatible = "qcom,sdm845-cci", "qcom,msm8996-cci"; 4550 #address-cells = <1>; 4551 #size-cells = <0>; 4552 4553 reg = <0 0x0ac4a000 0 0x4000>; 4554 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4555 power-domains = <&clock_camcc TITAN_TOP_GDSC>; 4556 4557 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4558 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4559 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4560 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 4561 <&clock_camcc CAM_CC_CCI_CLK>, 4562 <&clock_camcc CAM_CC_CCI_CLK_SRC>; 4563 clock-names = "camnoc_axi", 4564 "soc_ahb", 4565 "slow_ahb_src", 4566 "cpas_ahb", 4567 "cci", 4568 "cci_src"; 4569 4570 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4571 <&clock_camcc CAM_CC_CCI_CLK>; 4572 assigned-clock-rates = <80000000>, <37500000>; 4573 4574 pinctrl-names = "default", "sleep"; 4575 pinctrl-0 = <&cci0_default &cci1_default>; 4576 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 4577 4578 status = "disabled"; 4579 4580 cci_i2c0: i2c-bus@0 { 4581 reg = <0>; 4582 clock-frequency = <1000000>; 4583 #address-cells = <1>; 4584 #size-cells = <0>; 4585 }; 4586 4587 cci_i2c1: i2c-bus@1 { 4588 reg = <1>; 4589 clock-frequency = <1000000>; 4590 #address-cells = <1>; 4591 #size-cells = <0>; 4592 }; 4593 }; 4594 4595 clock_camcc: clock-controller@ad00000 { 4596 compatible = "qcom,sdm845-camcc"; 4597 reg = <0 0x0ad00000 0 0x10000>; 4598 #clock-cells = <1>; 4599 #reset-cells = <1>; 4600 #power-domain-cells = <1>; 4601 clocks = <&rpmhcc RPMH_CXO_CLK>; 4602 clock-names = "bi_tcxo"; 4603 }; 4604 4605 mdss: display-subsystem@ae00000 { 4606 compatible = "qcom,sdm845-mdss"; 4607 reg = <0 0x0ae00000 0 0x1000>; 4608 reg-names = "mdss"; 4609 4610 power-domains = <&dispcc MDSS_GDSC>; 4611 4612 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4613 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4614 clock-names = "iface", "core"; 4615 4616 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4617 interrupt-controller; 4618 #interrupt-cells = <1>; 4619 4620 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>, 4621 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>; 4622 interconnect-names = "mdp0-mem", "mdp1-mem"; 4623 4624 iommus = <&apps_smmu 0x880 0x8>, 4625 <&apps_smmu 0xc80 0x8>; 4626 4627 status = "disabled"; 4628 4629 #address-cells = <2>; 4630 #size-cells = <2>; 4631 ranges; 4632 4633 mdss_mdp: display-controller@ae01000 { 4634 compatible = "qcom,sdm845-dpu"; 4635 reg = <0 0x0ae01000 0 0x8f000>, 4636 <0 0x0aeb0000 0 0x3000>; 4637 reg-names = "mdp", "vbif"; 4638 4639 clocks = <&gcc GCC_DISP_AXI_CLK>, 4640 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4641 <&dispcc DISP_CC_MDSS_AXI_CLK>, 4642 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4643 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4644 clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; 4645 4646 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4647 assigned-clock-rates = <19200000>; 4648 operating-points-v2 = <&mdp_opp_table>; 4649 power-domains = <&rpmhpd SDM845_CX>; 4650 4651 interrupt-parent = <&mdss>; 4652 interrupts = <0>; 4653 4654 ports { 4655 #address-cells = <1>; 4656 #size-cells = <0>; 4657 4658 port@0 { 4659 reg = <0>; 4660 dpu_intf0_out: endpoint { 4661 remote-endpoint = <&mdss_dp_in>; 4662 }; 4663 }; 4664 4665 port@1 { 4666 reg = <1>; 4667 dpu_intf1_out: endpoint { 4668 remote-endpoint = <&mdss_dsi0_in>; 4669 }; 4670 }; 4671 4672 port@2 { 4673 reg = <2>; 4674 dpu_intf2_out: endpoint { 4675 remote-endpoint = <&mdss_dsi1_in>; 4676 }; 4677 }; 4678 }; 4679 4680 mdp_opp_table: opp-table { 4681 compatible = "operating-points-v2"; 4682 4683 opp-19200000 { 4684 opp-hz = /bits/ 64 <19200000>; 4685 required-opps = <&rpmhpd_opp_min_svs>; 4686 }; 4687 4688 opp-171428571 { 4689 opp-hz = /bits/ 64 <171428571>; 4690 required-opps = <&rpmhpd_opp_low_svs>; 4691 }; 4692 4693 opp-344000000 { 4694 opp-hz = /bits/ 64 <344000000>; 4695 required-opps = <&rpmhpd_opp_svs_l1>; 4696 }; 4697 4698 opp-430000000 { 4699 opp-hz = /bits/ 64 <430000000>; 4700 required-opps = <&rpmhpd_opp_nom>; 4701 }; 4702 }; 4703 }; 4704 4705 mdss_dp: displayport-controller@ae90000 { 4706 status = "disabled"; 4707 compatible = "qcom,sdm845-dp"; 4708 4709 reg = <0 0x0ae90000 0 0x200>, 4710 <0 0x0ae90200 0 0x200>, 4711 <0 0x0ae90400 0 0x600>, 4712 <0 0x0ae90a00 0 0x600>, 4713 <0 0x0ae91000 0 0x600>; 4714 4715 interrupt-parent = <&mdss>; 4716 interrupts = <12>; 4717 4718 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4719 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4720 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4721 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4722 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, 4723 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; 4724 clock-names = "core_iface", 4725 "core_aux", 4726 "ctrl_link", 4727 "ctrl_link_iface", 4728 "stream_pixel", 4729 "stream_1_pixel"; 4730 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4731 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, 4732 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; 4733 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4734 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4735 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4736 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4737 phy-names = "dp"; 4738 4739 operating-points-v2 = <&dp_opp_table>; 4740 power-domains = <&rpmhpd SDM845_CX>; 4741 4742 ports { 4743 #address-cells = <1>; 4744 #size-cells = <0>; 4745 port@0 { 4746 reg = <0>; 4747 mdss_dp_in: endpoint { 4748 remote-endpoint = <&dpu_intf0_out>; 4749 }; 4750 }; 4751 4752 port@1 { 4753 reg = <1>; 4754 mdss_dp_out: endpoint { 4755 remote-endpoint = <&usb_1_qmpphy_dp_in>; 4756 }; 4757 }; 4758 }; 4759 4760 dp_opp_table: opp-table { 4761 compatible = "operating-points-v2"; 4762 4763 opp-162000000 { 4764 opp-hz = /bits/ 64 <162000000>; 4765 required-opps = <&rpmhpd_opp_low_svs>; 4766 }; 4767 4768 opp-270000000 { 4769 opp-hz = /bits/ 64 <270000000>; 4770 required-opps = <&rpmhpd_opp_svs>; 4771 }; 4772 4773 opp-540000000 { 4774 opp-hz = /bits/ 64 <540000000>; 4775 required-opps = <&rpmhpd_opp_svs_l1>; 4776 }; 4777 4778 opp-810000000 { 4779 opp-hz = /bits/ 64 <810000000>; 4780 required-opps = <&rpmhpd_opp_nom>; 4781 }; 4782 }; 4783 }; 4784 4785 mdss_dsi0: dsi@ae94000 { 4786 compatible = "qcom,sdm845-dsi-ctrl", 4787 "qcom,mdss-dsi-ctrl"; 4788 reg = <0 0x0ae94000 0 0x400>; 4789 reg-names = "dsi_ctrl"; 4790 4791 interrupt-parent = <&mdss>; 4792 interrupts = <4>; 4793 4794 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4795 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4796 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4797 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4798 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4799 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4800 clock-names = "byte", 4801 "byte_intf", 4802 "pixel", 4803 "core", 4804 "iface", 4805 "bus"; 4806 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 4807 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4808 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 4809 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 4810 4811 operating-points-v2 = <&dsi_opp_table>; 4812 power-domains = <&rpmhpd SDM845_CX>; 4813 4814 phys = <&mdss_dsi0_phy>; 4815 4816 refgen-supply = <&refgen>; 4817 4818 status = "disabled"; 4819 4820 #address-cells = <1>; 4821 #size-cells = <0>; 4822 4823 ports { 4824 #address-cells = <1>; 4825 #size-cells = <0>; 4826 4827 port@0 { 4828 reg = <0>; 4829 mdss_dsi0_in: endpoint { 4830 remote-endpoint = <&dpu_intf1_out>; 4831 }; 4832 }; 4833 4834 port@1 { 4835 reg = <1>; 4836 mdss_dsi0_out: endpoint { 4837 }; 4838 }; 4839 }; 4840 }; 4841 4842 mdss_dsi0_phy: phy@ae94400 { 4843 compatible = "qcom,dsi-phy-10nm"; 4844 reg = <0 0x0ae94400 0 0x200>, 4845 <0 0x0ae94600 0 0x280>, 4846 <0 0x0ae94a00 0 0x1e0>; 4847 reg-names = "dsi_phy", 4848 "dsi_phy_lane", 4849 "dsi_pll"; 4850 4851 #clock-cells = <1>; 4852 #phy-cells = <0>; 4853 4854 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4855 <&rpmhcc RPMH_CXO_CLK>; 4856 clock-names = "iface", "ref"; 4857 4858 status = "disabled"; 4859 }; 4860 4861 mdss_dsi1: dsi@ae96000 { 4862 compatible = "qcom,sdm845-dsi-ctrl", 4863 "qcom,mdss-dsi-ctrl"; 4864 reg = <0 0x0ae96000 0 0x400>; 4865 reg-names = "dsi_ctrl"; 4866 4867 interrupt-parent = <&mdss>; 4868 interrupts = <5>; 4869 4870 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4871 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4872 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4873 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4874 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4875 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4876 clock-names = "byte", 4877 "byte_intf", 4878 "pixel", 4879 "core", 4880 "iface", 4881 "bus"; 4882 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 4883 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4884 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 4885 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 4886 4887 operating-points-v2 = <&dsi_opp_table>; 4888 power-domains = <&rpmhpd SDM845_CX>; 4889 4890 phys = <&mdss_dsi1_phy>; 4891 4892 refgen-supply = <&refgen>; 4893 4894 status = "disabled"; 4895 4896 #address-cells = <1>; 4897 #size-cells = <0>; 4898 4899 ports { 4900 #address-cells = <1>; 4901 #size-cells = <0>; 4902 4903 port@0 { 4904 reg = <0>; 4905 mdss_dsi1_in: endpoint { 4906 remote-endpoint = <&dpu_intf2_out>; 4907 }; 4908 }; 4909 4910 port@1 { 4911 reg = <1>; 4912 mdss_dsi1_out: endpoint { 4913 }; 4914 }; 4915 }; 4916 }; 4917 4918 mdss_dsi1_phy: phy@ae96400 { 4919 compatible = "qcom,dsi-phy-10nm"; 4920 reg = <0 0x0ae96400 0 0x200>, 4921 <0 0x0ae96600 0 0x280>, 4922 <0 0x0ae96a00 0 0x10e>; 4923 reg-names = "dsi_phy", 4924 "dsi_phy_lane", 4925 "dsi_pll"; 4926 4927 #clock-cells = <1>; 4928 #phy-cells = <0>; 4929 4930 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4931 <&rpmhcc RPMH_CXO_CLK>; 4932 clock-names = "iface", "ref"; 4933 4934 status = "disabled"; 4935 }; 4936 }; 4937 4938 gpu: gpu@5000000 { 4939 compatible = "qcom,adreno-630.2", "qcom,adreno"; 4940 4941 reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>; 4942 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 4943 4944 /* 4945 * Look ma, no clocks! The GPU clocks and power are 4946 * controlled entirely by the GMU 4947 */ 4948 4949 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4950 4951 iommus = <&adreno_smmu 0>; 4952 4953 operating-points-v2 = <&gpu_opp_table>; 4954 4955 qcom,gmu = <&gmu>; 4956 #cooling-cells = <2>; 4957 4958 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; 4959 interconnect-names = "gfx-mem"; 4960 4961 status = "disabled"; 4962 4963 gpu_zap_shader: zap-shader { 4964 memory-region = <&gpu_mem>; 4965 }; 4966 4967 gpu_opp_table: opp-table { 4968 compatible = "operating-points-v2"; 4969 4970 opp-710000000 { 4971 opp-hz = /bits/ 64 <710000000>; 4972 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4973 opp-peak-kBps = <7216000>; 4974 }; 4975 4976 opp-675000000 { 4977 opp-hz = /bits/ 64 <675000000>; 4978 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4979 opp-peak-kBps = <7216000>; 4980 }; 4981 4982 opp-596000000 { 4983 opp-hz = /bits/ 64 <596000000>; 4984 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4985 opp-peak-kBps = <6220000>; 4986 }; 4987 4988 opp-520000000 { 4989 opp-hz = /bits/ 64 <520000000>; 4990 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4991 opp-peak-kBps = <6220000>; 4992 }; 4993 4994 opp-414000000 { 4995 opp-hz = /bits/ 64 <414000000>; 4996 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4997 opp-peak-kBps = <4068000>; 4998 }; 4999 5000 opp-342000000 { 5001 opp-hz = /bits/ 64 <342000000>; 5002 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5003 opp-peak-kBps = <2724000>; 5004 }; 5005 5006 opp-257000000 { 5007 opp-hz = /bits/ 64 <257000000>; 5008 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5009 opp-peak-kBps = <1648000>; 5010 }; 5011 }; 5012 }; 5013 5014 adreno_smmu: iommu@5040000 { 5015 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 5016 reg = <0 0x05040000 0 0x10000>; 5017 #iommu-cells = <1>; 5018 #global-interrupts = <2>; 5019 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 5020 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 5021 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 5022 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 5023 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 5024 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 5025 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 5026 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 5027 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 5028 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 5029 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 5030 <&gcc GCC_GPU_CFG_AHB_CLK>; 5031 clock-names = "bus", "iface"; 5032 5033 power-domains = <&gpucc GPU_CX_GDSC>; 5034 }; 5035 5036 gmu: gmu@506a000 { 5037 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 5038 5039 reg = <0 0x0506a000 0 0x30000>, 5040 <0 0x0b280000 0 0x10000>, 5041 <0 0x0b480000 0 0x10000>; 5042 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 5043 5044 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 5045 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 5046 interrupt-names = "hfi", "gmu"; 5047 5048 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 5049 <&gpucc GPU_CC_CXO_CLK>, 5050 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 5051 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 5052 clock-names = "gmu", "cxo", "axi", "memnoc"; 5053 5054 power-domains = <&gpucc GPU_CX_GDSC>, 5055 <&gpucc GPU_GX_GDSC>; 5056 power-domain-names = "cx", "gx"; 5057 5058 iommus = <&adreno_smmu 5>; 5059 5060 operating-points-v2 = <&gmu_opp_table>; 5061 5062 gmu_opp_table: opp-table { 5063 compatible = "operating-points-v2"; 5064 5065 opp-400000000 { 5066 opp-hz = /bits/ 64 <400000000>; 5067 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5068 }; 5069 5070 opp-200000000 { 5071 opp-hz = /bits/ 64 <200000000>; 5072 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5073 }; 5074 }; 5075 }; 5076 5077 dispcc: clock-controller@af00000 { 5078 compatible = "qcom,sdm845-dispcc"; 5079 reg = <0 0x0af00000 0 0x10000>; 5080 clocks = <&rpmhcc RPMH_CXO_CLK>, 5081 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 5082 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 5083 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 5084 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 5085 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 5086 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 5087 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5088 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5089 clock-names = "bi_tcxo", 5090 "gcc_disp_gpll0_clk_src", 5091 "gcc_disp_gpll0_div_clk_src", 5092 "dsi0_phy_pll_out_byteclk", 5093 "dsi0_phy_pll_out_dsiclk", 5094 "dsi1_phy_pll_out_byteclk", 5095 "dsi1_phy_pll_out_dsiclk", 5096 "dp_link_clk_divsel_ten", 5097 "dp_vco_divided_clk_src_mux"; 5098 #clock-cells = <1>; 5099 #reset-cells = <1>; 5100 #power-domain-cells = <1>; 5101 }; 5102 5103 pdc_intc: interrupt-controller@b220000 { 5104 compatible = "qcom,sdm845-pdc", "qcom,pdc"; 5105 reg = <0 0x0b220000 0 0x30000>; 5106 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; 5107 #interrupt-cells = <2>; 5108 interrupt-parent = <&intc>; 5109 interrupt-controller; 5110 }; 5111 5112 pdc_reset: reset-controller@b2e0000 { 5113 compatible = "qcom,sdm845-pdc-global"; 5114 reg = <0 0x0b2e0000 0 0x20000>; 5115 #reset-cells = <1>; 5116 }; 5117 5118 tsens0: thermal-sensor@c263000 { 5119 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 5120 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 5121 <0 0x0c222000 0 0x1ff>; /* SROT */ 5122 #qcom,sensors = <13>; 5123 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 5125 interrupt-names = "uplow", "critical"; 5126 #thermal-sensor-cells = <1>; 5127 }; 5128 5129 tsens1: thermal-sensor@c265000 { 5130 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 5131 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 5132 <0 0x0c223000 0 0x1ff>; /* SROT */ 5133 #qcom,sensors = <8>; 5134 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 5136 interrupt-names = "uplow", "critical"; 5137 #thermal-sensor-cells = <1>; 5138 }; 5139 5140 aoss_reset: reset-controller@c2a0000 { 5141 compatible = "qcom,sdm845-aoss-cc"; 5142 reg = <0 0x0c2a0000 0 0x31000>; 5143 #reset-cells = <1>; 5144 }; 5145 5146 aoss_qmp: power-management@c300000 { 5147 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; 5148 reg = <0 0x0c300000 0 0x400>; 5149 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 5150 mboxes = <&apss_shared 0>; 5151 5152 #clock-cells = <0>; 5153 5154 cx_cdev: cx { 5155 #cooling-cells = <2>; 5156 }; 5157 5158 ebi_cdev: ebi { 5159 #cooling-cells = <2>; 5160 }; 5161 }; 5162 5163 sram@c3f0000 { 5164 compatible = "qcom,sdm845-rpmh-stats"; 5165 reg = <0 0x0c3f0000 0 0x400>; 5166 }; 5167 5168 spmi_bus: spmi@c440000 { 5169 compatible = "qcom,spmi-pmic-arb"; 5170 reg = <0 0x0c440000 0 0x1100>, 5171 <0 0x0c600000 0 0x2000000>, 5172 <0 0x0e600000 0 0x100000>, 5173 <0 0x0e700000 0 0xa0000>, 5174 <0 0x0c40a000 0 0x26000>; 5175 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 5176 interrupt-names = "periph_irq"; 5177 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 5178 qcom,ee = <0>; 5179 qcom,channel = <0>; 5180 #address-cells = <2>; 5181 #size-cells = <0>; 5182 interrupt-controller; 5183 #interrupt-cells = <4>; 5184 }; 5185 5186 sram@14680000 { 5187 compatible = "qcom,sdm845-imem", "syscon", "simple-mfd"; 5188 reg = <0 0x14680000 0 0x40000>; 5189 5190 #address-cells = <1>; 5191 #size-cells = <1>; 5192 5193 ranges = <0 0 0x14680000 0x40000>; 5194 5195 ipa_modem_tables: modem-tables@3d000 { 5196 reg = <0x3d000 0x2000>; 5197 }; 5198 5199 pil-reloc@3f94c { 5200 compatible = "qcom,pil-reloc-info"; 5201 reg = <0x3f94c 0xc8>; 5202 }; 5203 }; 5204 5205 apps_smmu: iommu@15000000 { 5206 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; 5207 reg = <0 0x15000000 0 0x80000>; 5208 #iommu-cells = <2>; 5209 #global-interrupts = <1>; 5210 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5211 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5212 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5213 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5214 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5215 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5216 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5217 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5218 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5219 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5220 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5221 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5222 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5223 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5224 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5225 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5226 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5227 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5228 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5229 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5230 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5231 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5232 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5233 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5234 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5235 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5236 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5237 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5238 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5239 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5240 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5241 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5242 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5243 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5244 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5245 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5246 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5247 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5248 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5249 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5250 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5251 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5252 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5253 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5254 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5255 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5256 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5257 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5258 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5259 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5260 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5261 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5262 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5263 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5264 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5265 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5266 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5267 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5268 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5269 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5270 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5271 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5272 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5273 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5274 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 5275 }; 5276 5277 anoc_1_tbu: tbu@150c5000 { 5278 compatible = "qcom,sdm845-tbu"; 5279 reg = <0x0 0x150c5000 0x0 0x1000>; 5280 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY 5281 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5282 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC>; 5283 qcom,stream-id-range = <&apps_smmu 0x0 0x400>; 5284 }; 5285 5286 anoc_2_tbu: tbu@150c9000 { 5287 compatible = "qcom,sdm845-tbu"; 5288 reg = <0x0 0x150c9000 0x0 0x1000>; 5289 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY 5290 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5291 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC>; 5292 qcom,stream-id-range = <&apps_smmu 0x400 0x400>; 5293 }; 5294 5295 mnoc_hf_0_tbu: tbu@150cd000 { 5296 compatible = "qcom,sdm845-tbu"; 5297 reg = <0x0 0x150cd000 0x0 0x1000>; 5298 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY 5299 &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; 5300 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>; 5301 qcom,stream-id-range = <&apps_smmu 0x800 0x400>; 5302 }; 5303 5304 mnoc_hf_1_tbu: tbu@150d1000 { 5305 compatible = "qcom,sdm845-tbu"; 5306 reg = <0x0 0x150d1000 0x0 0x1000>; 5307 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY 5308 &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; 5309 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>; 5310 qcom,stream-id-range = <&apps_smmu 0xc00 0x400>; 5311 }; 5312 5313 mnoc_sf_0_tbu: tbu@150d5000 { 5314 compatible = "qcom,sdm845-tbu"; 5315 reg = <0x0 0x150d5000 0x0 0x1000>; 5316 interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY 5317 &mmss_noc SLAVE_MNOC_SF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; 5318 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC>; 5319 qcom,stream-id-range = <&apps_smmu 0x1000 0x400>; 5320 }; 5321 5322 compute_dsp_tbu: tbu@150d9000 { 5323 compatible = "qcom,sdm845-tbu"; 5324 reg = <0x0 0x150d9000 0x0 0x1000>; 5325 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY 5326 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5327 qcom,stream-id-range = <&apps_smmu 0x1400 0x400>; 5328 }; 5329 5330 adsp_tbu: tbu@150dd000 { 5331 compatible = "qcom,sdm845-tbu"; 5332 reg = <0x0 0x150dd000 0x0 0x1000>; 5333 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY 5334 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5335 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC>; 5336 qcom,stream-id-range = <&apps_smmu 0x1800 0x400>; 5337 }; 5338 5339 anoc_1_pcie_tbu: tbu@150e1000 { 5340 compatible = "qcom,sdm845-tbu"; 5341 reg = <0x0 0x150e1000 0x0 0x1000>; 5342 clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 5343 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY 5344 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5345 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>; 5346 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>; 5347 }; 5348 5349 lpasscc: clock-controller@17014000 { 5350 compatible = "qcom,sdm845-lpasscc"; 5351 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; 5352 reg-names = "cc", "qdsp6ss"; 5353 #clock-cells = <1>; 5354 status = "disabled"; 5355 }; 5356 5357 gladiator_noc: interconnect@17900000 { 5358 compatible = "qcom,sdm845-gladiator-noc"; 5359 reg = <0 0x17900000 0 0xd080>; 5360 #interconnect-cells = <2>; 5361 qcom,bcm-voters = <&apps_bcm_voter>; 5362 }; 5363 5364 watchdog@17980000 { 5365 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; 5366 reg = <0 0x17980000 0 0x1000>; 5367 clocks = <&sleep_clk>; 5368 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5369 }; 5370 5371 apss_shared: mailbox@17990000 { 5372 compatible = "qcom,sdm845-apss-shared"; 5373 reg = <0 0x17990000 0 0x1000>; 5374 #mbox-cells = <1>; 5375 }; 5376 5377 apps_rsc: rsc@179c0000 { 5378 compatible = "qcom,sdm845-rpmh-apps-rsc", "qcom,rpmh-rsc"; 5379 label = "apps_rsc"; 5380 reg = <0 0x179c0000 0 0x10000>, 5381 <0 0x179d0000 0 0x10000>, 5382 <0 0x179e0000 0 0x10000>; 5383 reg-names = "drv-0", "drv-1", "drv-2"; 5384 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5385 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5386 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5387 qcom,tcs-offset = <0xd00>; 5388 qcom,drv-id = <2>; 5389 qcom,tcs-config = <ACTIVE_TCS 2>, 5390 <SLEEP_TCS 3>, 5391 <WAKE_TCS 3>, 5392 <CONTROL_TCS 1>; 5393 power-domains = <&cluster_pd>; 5394 5395 apps_bcm_voter: bcm-voter { 5396 compatible = "qcom,bcm-voter"; 5397 }; 5398 5399 rpmhcc: clock-controller { 5400 compatible = "qcom,sdm845-rpmh-clk"; 5401 #clock-cells = <1>; 5402 clock-names = "xo"; 5403 clocks = <&xo_board>; 5404 }; 5405 5406 rpmhpd: power-controller { 5407 compatible = "qcom,sdm845-rpmhpd"; 5408 #power-domain-cells = <1>; 5409 operating-points-v2 = <&rpmhpd_opp_table>; 5410 5411 rpmhpd_opp_table: opp-table { 5412 compatible = "operating-points-v2"; 5413 5414 rpmhpd_opp_ret: opp1 { 5415 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5416 }; 5417 5418 rpmhpd_opp_min_svs: opp2 { 5419 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5420 }; 5421 5422 rpmhpd_opp_low_svs: opp3 { 5423 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5424 }; 5425 5426 rpmhpd_opp_svs: opp4 { 5427 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5428 }; 5429 5430 rpmhpd_opp_svs_l1: opp5 { 5431 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5432 }; 5433 5434 rpmhpd_opp_nom: opp6 { 5435 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5436 }; 5437 5438 rpmhpd_opp_nom_l1: opp7 { 5439 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5440 }; 5441 5442 rpmhpd_opp_nom_l2: opp8 { 5443 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5444 }; 5445 5446 rpmhpd_opp_turbo: opp9 { 5447 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5448 }; 5449 5450 rpmhpd_opp_turbo_l1: opp10 { 5451 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5452 }; 5453 }; 5454 }; 5455 }; 5456 5457 intc: interrupt-controller@17a00000 { 5458 compatible = "arm,gic-v3"; 5459 #address-cells = <2>; 5460 #size-cells = <2>; 5461 ranges; 5462 #interrupt-cells = <3>; 5463 interrupt-controller; 5464 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5465 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5466 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5467 5468 msi-controller@17a40000 { 5469 compatible = "arm,gic-v3-its"; 5470 msi-controller; 5471 #msi-cells = <1>; 5472 reg = <0 0x17a40000 0 0x20000>; 5473 status = "disabled"; 5474 }; 5475 }; 5476 5477 slimbam: dma-controller@17184000 { 5478 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 5479 qcom,controlled-remotely; 5480 reg = <0 0x17184000 0 0x2a000>; 5481 num-channels = <23>; 5482 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 5483 #dma-cells = <1>; 5484 qcom,ee = <1>; 5485 qcom,num-ees = <4>; 5486 iommus = <&apps_smmu 0x1806 0x0>; 5487 }; 5488 5489 timer@17c90000 { 5490 #address-cells = <1>; 5491 #size-cells = <1>; 5492 ranges = <0 0 0 0x20000000>; 5493 compatible = "arm,armv7-timer-mem"; 5494 reg = <0 0x17c90000 0 0x1000>; 5495 5496 frame@17ca0000 { 5497 frame-number = <0>; 5498 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 5499 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5500 reg = <0x17ca0000 0x1000>, 5501 <0x17cb0000 0x1000>; 5502 }; 5503 5504 frame@17cc0000 { 5505 frame-number = <1>; 5506 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 5507 reg = <0x17cc0000 0x1000>; 5508 status = "disabled"; 5509 }; 5510 5511 frame@17cd0000 { 5512 frame-number = <2>; 5513 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5514 reg = <0x17cd0000 0x1000>; 5515 status = "disabled"; 5516 }; 5517 5518 frame@17ce0000 { 5519 frame-number = <3>; 5520 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5521 reg = <0x17ce0000 0x1000>; 5522 status = "disabled"; 5523 }; 5524 5525 frame@17cf0000 { 5526 frame-number = <4>; 5527 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5528 reg = <0x17cf0000 0x1000>; 5529 status = "disabled"; 5530 }; 5531 5532 frame@17d00000 { 5533 frame-number = <5>; 5534 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5535 reg = <0x17d00000 0x1000>; 5536 status = "disabled"; 5537 }; 5538 5539 frame@17d10000 { 5540 frame-number = <6>; 5541 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5542 reg = <0x17d10000 0x1000>; 5543 status = "disabled"; 5544 }; 5545 }; 5546 5547 osm_l3: interconnect@17d41000 { 5548 compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3"; 5549 reg = <0 0x17d41000 0 0x1400>; 5550 5551 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5552 clock-names = "xo", "alternate"; 5553 5554 #interconnect-cells = <1>; 5555 }; 5556 5557 cpufreq_hw: cpufreq@17d43000 { 5558 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw"; 5559 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 5560 reg-names = "freq-domain0", "freq-domain1"; 5561 5562 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>; 5563 5564 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5565 clock-names = "xo", "alternate"; 5566 5567 #freq-domain-cells = <1>; 5568 #clock-cells = <1>; 5569 }; 5570 5571 wifi: wifi@18800000 { 5572 compatible = "qcom,wcn3990-wifi"; 5573 status = "disabled"; 5574 reg = <0 0x18800000 0 0x800000>; 5575 reg-names = "membase"; 5576 memory-region = <&wlan_msa_mem>; 5577 clock-names = "cxo_ref_clk_pin"; 5578 clocks = <&rpmhcc RPMH_RF_CLK2>; 5579 interrupts = 5580 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 5581 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 5582 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 5583 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 5584 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5585 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5586 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 5587 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5588 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 5589 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5590 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5591 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 5592 iommus = <&apps_smmu 0x0040 0x1>; 5593 }; 5594 }; 5595 5596 sound: sound { 5597 }; 5598 5599 thermal-zones { 5600 cpu0-thermal { 5601 polling-delay-passive = <250>; 5602 5603 thermal-sensors = <&tsens0 1>; 5604 5605 trips { 5606 cpu0_alert0: trip-point0 { 5607 temperature = <90000>; 5608 hysteresis = <2000>; 5609 type = "passive"; 5610 }; 5611 5612 cpu0_alert1: trip-point1 { 5613 temperature = <95000>; 5614 hysteresis = <2000>; 5615 type = "passive"; 5616 }; 5617 5618 cpu0_crit: cpu-crit { 5619 temperature = <110000>; 5620 hysteresis = <1000>; 5621 type = "critical"; 5622 }; 5623 }; 5624 }; 5625 5626 cpu1-thermal { 5627 polling-delay-passive = <250>; 5628 5629 thermal-sensors = <&tsens0 2>; 5630 5631 trips { 5632 cpu1_alert0: trip-point0 { 5633 temperature = <90000>; 5634 hysteresis = <2000>; 5635 type = "passive"; 5636 }; 5637 5638 cpu1_alert1: trip-point1 { 5639 temperature = <95000>; 5640 hysteresis = <2000>; 5641 type = "passive"; 5642 }; 5643 5644 cpu1_crit: cpu-crit { 5645 temperature = <110000>; 5646 hysteresis = <1000>; 5647 type = "critical"; 5648 }; 5649 }; 5650 }; 5651 5652 cpu2-thermal { 5653 polling-delay-passive = <250>; 5654 5655 thermal-sensors = <&tsens0 3>; 5656 5657 trips { 5658 cpu2_alert0: trip-point0 { 5659 temperature = <90000>; 5660 hysteresis = <2000>; 5661 type = "passive"; 5662 }; 5663 5664 cpu2_alert1: trip-point1 { 5665 temperature = <95000>; 5666 hysteresis = <2000>; 5667 type = "passive"; 5668 }; 5669 5670 cpu2_crit: cpu-crit { 5671 temperature = <110000>; 5672 hysteresis = <1000>; 5673 type = "critical"; 5674 }; 5675 }; 5676 }; 5677 5678 cpu3-thermal { 5679 polling-delay-passive = <250>; 5680 5681 thermal-sensors = <&tsens0 4>; 5682 5683 trips { 5684 cpu3_alert0: trip-point0 { 5685 temperature = <90000>; 5686 hysteresis = <2000>; 5687 type = "passive"; 5688 }; 5689 5690 cpu3_alert1: trip-point1 { 5691 temperature = <95000>; 5692 hysteresis = <2000>; 5693 type = "passive"; 5694 }; 5695 5696 cpu3_crit: cpu-crit { 5697 temperature = <110000>; 5698 hysteresis = <1000>; 5699 type = "critical"; 5700 }; 5701 }; 5702 }; 5703 5704 cpu4-thermal { 5705 polling-delay-passive = <250>; 5706 5707 thermal-sensors = <&tsens0 7>; 5708 5709 trips { 5710 cpu4_alert0: trip-point0 { 5711 temperature = <90000>; 5712 hysteresis = <2000>; 5713 type = "passive"; 5714 }; 5715 5716 cpu4_alert1: trip-point1 { 5717 temperature = <95000>; 5718 hysteresis = <2000>; 5719 type = "passive"; 5720 }; 5721 5722 cpu4_crit: cpu-crit { 5723 temperature = <110000>; 5724 hysteresis = <1000>; 5725 type = "critical"; 5726 }; 5727 }; 5728 }; 5729 5730 cpu5-thermal { 5731 polling-delay-passive = <250>; 5732 5733 thermal-sensors = <&tsens0 8>; 5734 5735 trips { 5736 cpu5_alert0: trip-point0 { 5737 temperature = <90000>; 5738 hysteresis = <2000>; 5739 type = "passive"; 5740 }; 5741 5742 cpu5_alert1: trip-point1 { 5743 temperature = <95000>; 5744 hysteresis = <2000>; 5745 type = "passive"; 5746 }; 5747 5748 cpu5_crit: cpu-crit { 5749 temperature = <110000>; 5750 hysteresis = <1000>; 5751 type = "critical"; 5752 }; 5753 }; 5754 }; 5755 5756 cpu6-thermal { 5757 polling-delay-passive = <250>; 5758 5759 thermal-sensors = <&tsens0 9>; 5760 5761 trips { 5762 cpu6_alert0: trip-point0 { 5763 temperature = <90000>; 5764 hysteresis = <2000>; 5765 type = "passive"; 5766 }; 5767 5768 cpu6_alert1: trip-point1 { 5769 temperature = <95000>; 5770 hysteresis = <2000>; 5771 type = "passive"; 5772 }; 5773 5774 cpu6_crit: cpu-crit { 5775 temperature = <110000>; 5776 hysteresis = <1000>; 5777 type = "critical"; 5778 }; 5779 }; 5780 }; 5781 5782 cpu7-thermal { 5783 polling-delay-passive = <250>; 5784 5785 thermal-sensors = <&tsens0 10>; 5786 5787 trips { 5788 cpu7_alert0: trip-point0 { 5789 temperature = <90000>; 5790 hysteresis = <2000>; 5791 type = "passive"; 5792 }; 5793 5794 cpu7_alert1: trip-point1 { 5795 temperature = <95000>; 5796 hysteresis = <2000>; 5797 type = "passive"; 5798 }; 5799 5800 cpu7_crit: cpu-crit { 5801 temperature = <110000>; 5802 hysteresis = <1000>; 5803 type = "critical"; 5804 }; 5805 }; 5806 }; 5807 5808 aoss0-thermal { 5809 polling-delay-passive = <250>; 5810 5811 thermal-sensors = <&tsens0 0>; 5812 5813 trips { 5814 aoss0_alert0: trip-point0 { 5815 temperature = <90000>; 5816 hysteresis = <2000>; 5817 type = "hot"; 5818 }; 5819 }; 5820 }; 5821 5822 cluster0-thermal { 5823 polling-delay-passive = <250>; 5824 5825 thermal-sensors = <&tsens0 5>; 5826 5827 trips { 5828 cluster0_alert0: trip-point0 { 5829 temperature = <90000>; 5830 hysteresis = <2000>; 5831 type = "hot"; 5832 }; 5833 cluster0_crit: cluster0-crit { 5834 temperature = <110000>; 5835 hysteresis = <2000>; 5836 type = "critical"; 5837 }; 5838 }; 5839 }; 5840 5841 cluster1-thermal { 5842 polling-delay-passive = <250>; 5843 5844 thermal-sensors = <&tsens0 6>; 5845 5846 trips { 5847 cluster1_alert0: trip-point0 { 5848 temperature = <90000>; 5849 hysteresis = <2000>; 5850 type = "hot"; 5851 }; 5852 cluster1_crit: cluster1-crit { 5853 temperature = <110000>; 5854 hysteresis = <2000>; 5855 type = "critical"; 5856 }; 5857 }; 5858 }; 5859 5860 gpu-top-thermal { 5861 polling-delay-passive = <250>; 5862 5863 thermal-sensors = <&tsens0 11>; 5864 5865 cooling-maps { 5866 map0 { 5867 trip = <&gpu_top_alert0>; 5868 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5869 }; 5870 }; 5871 5872 trips { 5873 gpu_top_alert0: trip-point0 { 5874 temperature = <85000>; 5875 hysteresis = <1000>; 5876 type = "passive"; 5877 }; 5878 5879 trip-point1 { 5880 temperature = <90000>; 5881 hysteresis = <1000>; 5882 type = "hot"; 5883 }; 5884 5885 trip-point2 { 5886 temperature = <110000>; 5887 hysteresis = <1000>; 5888 type = "critical"; 5889 }; 5890 }; 5891 }; 5892 5893 gpu-bottom-thermal { 5894 polling-delay-passive = <250>; 5895 5896 thermal-sensors = <&tsens0 12>; 5897 5898 cooling-maps { 5899 map0 { 5900 trip = <&gpu_bottom_alert0>; 5901 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5902 }; 5903 }; 5904 5905 trips { 5906 gpu_bottom_alert0: trip-point0 { 5907 temperature = <85000>; 5908 hysteresis = <1000>; 5909 type = "passive"; 5910 }; 5911 5912 trip-point1 { 5913 temperature = <90000>; 5914 hysteresis = <1000>; 5915 type = "hot"; 5916 }; 5917 5918 trip-point2 { 5919 temperature = <110000>; 5920 hysteresis = <1000>; 5921 type = "critical"; 5922 }; 5923 }; 5924 }; 5925 5926 aoss1-thermal { 5927 polling-delay-passive = <250>; 5928 5929 thermal-sensors = <&tsens1 0>; 5930 5931 trips { 5932 aoss1_alert0: trip-point0 { 5933 temperature = <90000>; 5934 hysteresis = <2000>; 5935 type = "hot"; 5936 }; 5937 }; 5938 }; 5939 5940 q6-modem-thermal { 5941 polling-delay-passive = <250>; 5942 5943 thermal-sensors = <&tsens1 1>; 5944 5945 trips { 5946 q6_modem_alert0: trip-point0 { 5947 temperature = <90000>; 5948 hysteresis = <2000>; 5949 type = "hot"; 5950 }; 5951 }; 5952 }; 5953 5954 mem-thermal { 5955 polling-delay-passive = <250>; 5956 5957 thermal-sensors = <&tsens1 2>; 5958 5959 trips { 5960 mem_alert0: trip-point0 { 5961 temperature = <90000>; 5962 hysteresis = <2000>; 5963 type = "hot"; 5964 }; 5965 }; 5966 }; 5967 5968 wlan-thermal { 5969 polling-delay-passive = <250>; 5970 5971 thermal-sensors = <&tsens1 3>; 5972 5973 trips { 5974 wlan_alert0: trip-point0 { 5975 temperature = <90000>; 5976 hysteresis = <2000>; 5977 type = "hot"; 5978 }; 5979 }; 5980 }; 5981 5982 q6-hvx-thermal { 5983 polling-delay-passive = <250>; 5984 5985 thermal-sensors = <&tsens1 4>; 5986 5987 trips { 5988 q6_hvx_alert0: trip-point0 { 5989 temperature = <90000>; 5990 hysteresis = <2000>; 5991 type = "hot"; 5992 }; 5993 }; 5994 }; 5995 5996 camera-thermal { 5997 polling-delay-passive = <250>; 5998 5999 thermal-sensors = <&tsens1 5>; 6000 6001 trips { 6002 camera_alert0: trip-point0 { 6003 temperature = <90000>; 6004 hysteresis = <2000>; 6005 type = "hot"; 6006 }; 6007 }; 6008 }; 6009 6010 video-thermal { 6011 polling-delay-passive = <250>; 6012 6013 thermal-sensors = <&tsens1 6>; 6014 6015 trips { 6016 video_alert0: trip-point0 { 6017 temperature = <90000>; 6018 hysteresis = <2000>; 6019 type = "hot"; 6020 }; 6021 }; 6022 }; 6023 6024 modem-thermal { 6025 polling-delay-passive = <250>; 6026 6027 thermal-sensors = <&tsens1 7>; 6028 6029 trips { 6030 modem_alert0: trip-point0 { 6031 temperature = <90000>; 6032 hysteresis = <2000>; 6033 type = "hot"; 6034 }; 6035 }; 6036 }; 6037 }; 6038 6039 timer { 6040 compatible = "arm,armv8-timer"; 6041 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 6042 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 6043 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 6044 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 6045 }; 6046}; 6047