1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,camcc-sdm845.h> 9#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 10#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 11#include <dt-bindings/clock/qcom,gcc-sdm845.h> 12#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 13#include <dt-bindings/clock/qcom,lpass-sdm845.h> 14#include <dt-bindings/clock/qcom,rpmh.h> 15#include <dt-bindings/clock/qcom,videocc-sdm845.h> 16#include <dt-bindings/dma/qcom-gpi.h> 17#include <dt-bindings/firmware/qcom,scm.h> 18#include <dt-bindings/gpio/gpio.h> 19#include <dt-bindings/interconnect/qcom,icc.h> 20#include <dt-bindings/interconnect/qcom,osm-l3.h> 21#include <dt-bindings/interconnect/qcom,sdm845.h> 22#include <dt-bindings/interrupt-controller/arm-gic.h> 23#include <dt-bindings/phy/phy-qcom-qmp.h> 24#include <dt-bindings/phy/phy-qcom-qusb2.h> 25#include <dt-bindings/power/qcom-rpmpd.h> 26#include <dt-bindings/reset/qcom,sdm845-aoss.h> 27#include <dt-bindings/reset/qcom,sdm845-pdc.h> 28#include <dt-bindings/soc/qcom,apr.h> 29#include <dt-bindings/soc/qcom,rpmh-rsc.h> 30#include <dt-bindings/clock/qcom,gcc-sdm845.h> 31#include <dt-bindings/thermal/thermal.h> 32 33/ { 34 interrupt-parent = <&intc>; 35 36 #address-cells = <2>; 37 #size-cells = <2>; 38 39 aliases { 40 i2c0 = &i2c0; 41 i2c1 = &i2c1; 42 i2c2 = &i2c2; 43 i2c3 = &i2c3; 44 i2c4 = &i2c4; 45 i2c5 = &i2c5; 46 i2c6 = &i2c6; 47 i2c7 = &i2c7; 48 i2c8 = &i2c8; 49 i2c9 = &i2c9; 50 i2c10 = &i2c10; 51 i2c11 = &i2c11; 52 i2c12 = &i2c12; 53 i2c13 = &i2c13; 54 i2c14 = &i2c14; 55 i2c15 = &i2c15; 56 spi0 = &spi0; 57 spi1 = &spi1; 58 spi2 = &spi2; 59 spi3 = &spi3; 60 spi4 = &spi4; 61 spi5 = &spi5; 62 spi6 = &spi6; 63 spi7 = &spi7; 64 spi8 = &spi8; 65 spi9 = &spi9; 66 spi10 = &spi10; 67 spi11 = &spi11; 68 spi12 = &spi12; 69 spi13 = &spi13; 70 spi14 = &spi14; 71 spi15 = &spi15; 72 }; 73 74 chosen { }; 75 76 clocks { 77 xo_board: xo-board { 78 compatible = "fixed-clock"; 79 #clock-cells = <0>; 80 clock-frequency = <38400000>; 81 clock-output-names = "xo_board"; 82 }; 83 84 sleep_clk: sleep-clk { 85 compatible = "fixed-clock"; 86 #clock-cells = <0>; 87 clock-frequency = <32764>; 88 }; 89 }; 90 91 cpus: cpus { 92 #address-cells = <2>; 93 #size-cells = <0>; 94 95 cpu0: cpu@0 { 96 device_type = "cpu"; 97 compatible = "qcom,kryo385"; 98 reg = <0x0 0x0>; 99 clocks = <&cpufreq_hw 0>; 100 enable-method = "psci"; 101 capacity-dmips-mhz = <611>; 102 dynamic-power-coefficient = <154>; 103 qcom,freq-domain = <&cpufreq_hw 0>; 104 operating-points-v2 = <&cpu0_opp_table>; 105 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 106 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 107 power-domains = <&cpu_pd0>; 108 power-domain-names = "psci"; 109 #cooling-cells = <2>; 110 next-level-cache = <&l2_0>; 111 l2_0: l2-cache { 112 compatible = "cache"; 113 cache-level = <2>; 114 cache-unified; 115 next-level-cache = <&l3_0>; 116 l3_0: l3-cache { 117 compatible = "cache"; 118 cache-level = <3>; 119 cache-unified; 120 }; 121 }; 122 }; 123 124 cpu1: cpu@100 { 125 device_type = "cpu"; 126 compatible = "qcom,kryo385"; 127 reg = <0x0 0x100>; 128 clocks = <&cpufreq_hw 0>; 129 enable-method = "psci"; 130 capacity-dmips-mhz = <611>; 131 dynamic-power-coefficient = <154>; 132 qcom,freq-domain = <&cpufreq_hw 0>; 133 operating-points-v2 = <&cpu0_opp_table>; 134 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 135 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 136 power-domains = <&cpu_pd1>; 137 power-domain-names = "psci"; 138 #cooling-cells = <2>; 139 next-level-cache = <&l2_100>; 140 l2_100: l2-cache { 141 compatible = "cache"; 142 cache-level = <2>; 143 cache-unified; 144 next-level-cache = <&l3_0>; 145 }; 146 }; 147 148 cpu2: cpu@200 { 149 device_type = "cpu"; 150 compatible = "qcom,kryo385"; 151 reg = <0x0 0x200>; 152 clocks = <&cpufreq_hw 0>; 153 enable-method = "psci"; 154 capacity-dmips-mhz = <611>; 155 dynamic-power-coefficient = <154>; 156 qcom,freq-domain = <&cpufreq_hw 0>; 157 operating-points-v2 = <&cpu0_opp_table>; 158 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 159 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 160 power-domains = <&cpu_pd2>; 161 power-domain-names = "psci"; 162 #cooling-cells = <2>; 163 next-level-cache = <&l2_200>; 164 l2_200: l2-cache { 165 compatible = "cache"; 166 cache-level = <2>; 167 cache-unified; 168 next-level-cache = <&l3_0>; 169 }; 170 }; 171 172 cpu3: cpu@300 { 173 device_type = "cpu"; 174 compatible = "qcom,kryo385"; 175 reg = <0x0 0x300>; 176 clocks = <&cpufreq_hw 0>; 177 enable-method = "psci"; 178 capacity-dmips-mhz = <611>; 179 dynamic-power-coefficient = <154>; 180 qcom,freq-domain = <&cpufreq_hw 0>; 181 operating-points-v2 = <&cpu0_opp_table>; 182 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 183 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 184 #cooling-cells = <2>; 185 power-domains = <&cpu_pd3>; 186 power-domain-names = "psci"; 187 next-level-cache = <&l2_300>; 188 l2_300: l2-cache { 189 compatible = "cache"; 190 cache-level = <2>; 191 cache-unified; 192 next-level-cache = <&l3_0>; 193 }; 194 }; 195 196 cpu4: cpu@400 { 197 device_type = "cpu"; 198 compatible = "qcom,kryo385"; 199 reg = <0x0 0x400>; 200 clocks = <&cpufreq_hw 1>; 201 enable-method = "psci"; 202 capacity-dmips-mhz = <1024>; 203 dynamic-power-coefficient = <442>; 204 qcom,freq-domain = <&cpufreq_hw 1>; 205 operating-points-v2 = <&cpu4_opp_table>; 206 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 207 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 208 power-domains = <&cpu_pd4>; 209 power-domain-names = "psci"; 210 #cooling-cells = <2>; 211 next-level-cache = <&l2_400>; 212 l2_400: l2-cache { 213 compatible = "cache"; 214 cache-level = <2>; 215 cache-unified; 216 next-level-cache = <&l3_0>; 217 }; 218 }; 219 220 cpu5: cpu@500 { 221 device_type = "cpu"; 222 compatible = "qcom,kryo385"; 223 reg = <0x0 0x500>; 224 clocks = <&cpufreq_hw 1>; 225 enable-method = "psci"; 226 capacity-dmips-mhz = <1024>; 227 dynamic-power-coefficient = <442>; 228 qcom,freq-domain = <&cpufreq_hw 1>; 229 operating-points-v2 = <&cpu4_opp_table>; 230 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 231 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 232 power-domains = <&cpu_pd5>; 233 power-domain-names = "psci"; 234 #cooling-cells = <2>; 235 next-level-cache = <&l2_500>; 236 l2_500: l2-cache { 237 compatible = "cache"; 238 cache-level = <2>; 239 cache-unified; 240 next-level-cache = <&l3_0>; 241 }; 242 }; 243 244 cpu6: cpu@600 { 245 device_type = "cpu"; 246 compatible = "qcom,kryo385"; 247 reg = <0x0 0x600>; 248 clocks = <&cpufreq_hw 1>; 249 enable-method = "psci"; 250 capacity-dmips-mhz = <1024>; 251 dynamic-power-coefficient = <442>; 252 qcom,freq-domain = <&cpufreq_hw 1>; 253 operating-points-v2 = <&cpu4_opp_table>; 254 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 255 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 256 power-domains = <&cpu_pd6>; 257 power-domain-names = "psci"; 258 #cooling-cells = <2>; 259 next-level-cache = <&l2_600>; 260 l2_600: l2-cache { 261 compatible = "cache"; 262 cache-level = <2>; 263 cache-unified; 264 next-level-cache = <&l3_0>; 265 }; 266 }; 267 268 cpu7: cpu@700 { 269 device_type = "cpu"; 270 compatible = "qcom,kryo385"; 271 reg = <0x0 0x700>; 272 clocks = <&cpufreq_hw 1>; 273 enable-method = "psci"; 274 capacity-dmips-mhz = <1024>; 275 dynamic-power-coefficient = <442>; 276 qcom,freq-domain = <&cpufreq_hw 1>; 277 operating-points-v2 = <&cpu4_opp_table>; 278 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 279 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 280 power-domains = <&cpu_pd7>; 281 power-domain-names = "psci"; 282 #cooling-cells = <2>; 283 next-level-cache = <&l2_700>; 284 l2_700: l2-cache { 285 compatible = "cache"; 286 cache-level = <2>; 287 cache-unified; 288 next-level-cache = <&l3_0>; 289 }; 290 }; 291 292 cpu-map { 293 cluster0 { 294 core0 { 295 cpu = <&cpu0>; 296 }; 297 298 core1 { 299 cpu = <&cpu1>; 300 }; 301 302 core2 { 303 cpu = <&cpu2>; 304 }; 305 306 core3 { 307 cpu = <&cpu3>; 308 }; 309 310 core4 { 311 cpu = <&cpu4>; 312 }; 313 314 core5 { 315 cpu = <&cpu5>; 316 }; 317 318 core6 { 319 cpu = <&cpu6>; 320 }; 321 322 core7 { 323 cpu = <&cpu7>; 324 }; 325 }; 326 }; 327 328 cpu_idle_states: idle-states { 329 entry-method = "psci"; 330 331 little_cpu_sleep_0: cpu-sleep-0-0 { 332 compatible = "arm,idle-state"; 333 idle-state-name = "little-rail-power-collapse"; 334 arm,psci-suspend-param = <0x40000004>; 335 entry-latency-us = <350>; 336 exit-latency-us = <461>; 337 min-residency-us = <1890>; 338 local-timer-stop; 339 }; 340 341 big_cpu_sleep_0: cpu-sleep-1-0 { 342 compatible = "arm,idle-state"; 343 idle-state-name = "big-rail-power-collapse"; 344 arm,psci-suspend-param = <0x40000004>; 345 entry-latency-us = <264>; 346 exit-latency-us = <621>; 347 min-residency-us = <952>; 348 local-timer-stop; 349 }; 350 }; 351 352 domain-idle-states { 353 cluster_sleep_0: cluster-sleep-0 { 354 compatible = "domain-idle-state"; 355 arm,psci-suspend-param = <0x4100c244>; 356 entry-latency-us = <3263>; 357 exit-latency-us = <6562>; 358 min-residency-us = <9987>; 359 }; 360 }; 361 }; 362 363 firmware { 364 scm { 365 compatible = "qcom,scm-sdm845", "qcom,scm"; 366 }; 367 }; 368 369 memory@80000000 { 370 device_type = "memory"; 371 /* We expect the bootloader to fill in the size */ 372 reg = <0 0x80000000 0 0>; 373 }; 374 375 cpu0_opp_table: opp-table-cpu0 { 376 compatible = "operating-points-v2"; 377 opp-shared; 378 379 cpu0_opp1: opp-300000000 { 380 opp-hz = /bits/ 64 <300000000>; 381 opp-peak-kBps = <800000 4800000>; 382 }; 383 384 cpu0_opp2: opp-403200000 { 385 opp-hz = /bits/ 64 <403200000>; 386 opp-peak-kBps = <800000 4800000>; 387 }; 388 389 cpu0_opp3: opp-480000000 { 390 opp-hz = /bits/ 64 <480000000>; 391 opp-peak-kBps = <800000 6451200>; 392 }; 393 394 cpu0_opp4: opp-576000000 { 395 opp-hz = /bits/ 64 <576000000>; 396 opp-peak-kBps = <800000 6451200>; 397 }; 398 399 cpu0_opp5: opp-652800000 { 400 opp-hz = /bits/ 64 <652800000>; 401 opp-peak-kBps = <800000 7680000>; 402 }; 403 404 cpu0_opp6: opp-748800000 { 405 opp-hz = /bits/ 64 <748800000>; 406 opp-peak-kBps = <1804000 9216000>; 407 }; 408 409 cpu0_opp7: opp-825600000 { 410 opp-hz = /bits/ 64 <825600000>; 411 opp-peak-kBps = <1804000 9216000>; 412 }; 413 414 cpu0_opp8: opp-902400000 { 415 opp-hz = /bits/ 64 <902400000>; 416 opp-peak-kBps = <1804000 10444800>; 417 }; 418 419 cpu0_opp9: opp-979200000 { 420 opp-hz = /bits/ 64 <979200000>; 421 opp-peak-kBps = <1804000 11980800>; 422 }; 423 424 cpu0_opp10: opp-1056000000 { 425 opp-hz = /bits/ 64 <1056000000>; 426 opp-peak-kBps = <1804000 11980800>; 427 }; 428 429 cpu0_opp11: opp-1132800000 { 430 opp-hz = /bits/ 64 <1132800000>; 431 opp-peak-kBps = <2188000 13516800>; 432 }; 433 434 cpu0_opp12: opp-1228800000 { 435 opp-hz = /bits/ 64 <1228800000>; 436 opp-peak-kBps = <2188000 15052800>; 437 }; 438 439 cpu0_opp13: opp-1324800000 { 440 opp-hz = /bits/ 64 <1324800000>; 441 opp-peak-kBps = <2188000 16588800>; 442 }; 443 444 cpu0_opp14: opp-1420800000 { 445 opp-hz = /bits/ 64 <1420800000>; 446 opp-peak-kBps = <3072000 18124800>; 447 }; 448 449 cpu0_opp15: opp-1516800000 { 450 opp-hz = /bits/ 64 <1516800000>; 451 opp-peak-kBps = <3072000 19353600>; 452 }; 453 454 cpu0_opp16: opp-1612800000 { 455 opp-hz = /bits/ 64 <1612800000>; 456 opp-peak-kBps = <4068000 19353600>; 457 }; 458 459 cpu0_opp17: opp-1689600000 { 460 opp-hz = /bits/ 64 <1689600000>; 461 opp-peak-kBps = <4068000 20889600>; 462 }; 463 464 cpu0_opp18: opp-1766400000 { 465 opp-hz = /bits/ 64 <1766400000>; 466 opp-peak-kBps = <4068000 22425600>; 467 }; 468 }; 469 470 cpu4_opp_table: opp-table-cpu4 { 471 compatible = "operating-points-v2"; 472 opp-shared; 473 474 cpu4_opp1: opp-300000000 { 475 opp-hz = /bits/ 64 <300000000>; 476 opp-peak-kBps = <800000 4800000>; 477 }; 478 479 cpu4_opp2: opp-403200000 { 480 opp-hz = /bits/ 64 <403200000>; 481 opp-peak-kBps = <800000 4800000>; 482 }; 483 484 cpu4_opp3: opp-480000000 { 485 opp-hz = /bits/ 64 <480000000>; 486 opp-peak-kBps = <1804000 4800000>; 487 }; 488 489 cpu4_opp4: opp-576000000 { 490 opp-hz = /bits/ 64 <576000000>; 491 opp-peak-kBps = <1804000 4800000>; 492 }; 493 494 cpu4_opp5: opp-652800000 { 495 opp-hz = /bits/ 64 <652800000>; 496 opp-peak-kBps = <1804000 4800000>; 497 }; 498 499 cpu4_opp6: opp-748800000 { 500 opp-hz = /bits/ 64 <748800000>; 501 opp-peak-kBps = <1804000 4800000>; 502 }; 503 504 cpu4_opp7: opp-825600000 { 505 opp-hz = /bits/ 64 <825600000>; 506 opp-peak-kBps = <2188000 9216000>; 507 }; 508 509 cpu4_opp8: opp-902400000 { 510 opp-hz = /bits/ 64 <902400000>; 511 opp-peak-kBps = <2188000 9216000>; 512 }; 513 514 cpu4_opp9: opp-979200000 { 515 opp-hz = /bits/ 64 <979200000>; 516 opp-peak-kBps = <2188000 9216000>; 517 }; 518 519 cpu4_opp10: opp-1056000000 { 520 opp-hz = /bits/ 64 <1056000000>; 521 opp-peak-kBps = <3072000 9216000>; 522 }; 523 524 cpu4_opp11: opp-1132800000 { 525 opp-hz = /bits/ 64 <1132800000>; 526 opp-peak-kBps = <3072000 11980800>; 527 }; 528 529 cpu4_opp12: opp-1209600000 { 530 opp-hz = /bits/ 64 <1209600000>; 531 opp-peak-kBps = <4068000 11980800>; 532 }; 533 534 cpu4_opp13: opp-1286400000 { 535 opp-hz = /bits/ 64 <1286400000>; 536 opp-peak-kBps = <4068000 11980800>; 537 }; 538 539 cpu4_opp14: opp-1363200000 { 540 opp-hz = /bits/ 64 <1363200000>; 541 opp-peak-kBps = <4068000 15052800>; 542 }; 543 544 cpu4_opp15: opp-1459200000 { 545 opp-hz = /bits/ 64 <1459200000>; 546 opp-peak-kBps = <4068000 15052800>; 547 }; 548 549 cpu4_opp16: opp-1536000000 { 550 opp-hz = /bits/ 64 <1536000000>; 551 opp-peak-kBps = <5412000 15052800>; 552 }; 553 554 cpu4_opp17: opp-1612800000 { 555 opp-hz = /bits/ 64 <1612800000>; 556 opp-peak-kBps = <5412000 15052800>; 557 }; 558 559 cpu4_opp18: opp-1689600000 { 560 opp-hz = /bits/ 64 <1689600000>; 561 opp-peak-kBps = <5412000 19353600>; 562 }; 563 564 cpu4_opp19: opp-1766400000 { 565 opp-hz = /bits/ 64 <1766400000>; 566 opp-peak-kBps = <6220000 19353600>; 567 }; 568 569 cpu4_opp20: opp-1843200000 { 570 opp-hz = /bits/ 64 <1843200000>; 571 opp-peak-kBps = <6220000 19353600>; 572 }; 573 574 cpu4_opp21: opp-1920000000 { 575 opp-hz = /bits/ 64 <1920000000>; 576 opp-peak-kBps = <7216000 19353600>; 577 }; 578 579 cpu4_opp22: opp-1996800000 { 580 opp-hz = /bits/ 64 <1996800000>; 581 opp-peak-kBps = <7216000 20889600>; 582 }; 583 584 cpu4_opp23: opp-2092800000 { 585 opp-hz = /bits/ 64 <2092800000>; 586 opp-peak-kBps = <7216000 20889600>; 587 }; 588 589 cpu4_opp24: opp-2169600000 { 590 opp-hz = /bits/ 64 <2169600000>; 591 opp-peak-kBps = <7216000 20889600>; 592 }; 593 594 cpu4_opp25: opp-2246400000 { 595 opp-hz = /bits/ 64 <2246400000>; 596 opp-peak-kBps = <7216000 20889600>; 597 }; 598 599 cpu4_opp26: opp-2323200000 { 600 opp-hz = /bits/ 64 <2323200000>; 601 opp-peak-kBps = <7216000 20889600>; 602 }; 603 604 cpu4_opp27: opp-2400000000 { 605 opp-hz = /bits/ 64 <2400000000>; 606 opp-peak-kBps = <7216000 22425600>; 607 }; 608 609 cpu4_opp28: opp-2476800000 { 610 opp-hz = /bits/ 64 <2476800000>; 611 opp-peak-kBps = <7216000 22425600>; 612 }; 613 614 cpu4_opp29: opp-2553600000 { 615 opp-hz = /bits/ 64 <2553600000>; 616 opp-peak-kBps = <7216000 22425600>; 617 }; 618 619 cpu4_opp30: opp-2649600000 { 620 opp-hz = /bits/ 64 <2649600000>; 621 opp-peak-kBps = <7216000 22425600>; 622 }; 623 624 cpu4_opp31: opp-2745600000 { 625 opp-hz = /bits/ 64 <2745600000>; 626 opp-peak-kBps = <7216000 25497600>; 627 }; 628 629 cpu4_opp32: opp-2803200000 { 630 opp-hz = /bits/ 64 <2803200000>; 631 opp-peak-kBps = <7216000 25497600>; 632 }; 633 }; 634 635 dsi_opp_table: opp-table-dsi { 636 compatible = "operating-points-v2"; 637 638 opp-19200000 { 639 opp-hz = /bits/ 64 <19200000>; 640 required-opps = <&rpmhpd_opp_min_svs>; 641 }; 642 643 opp-180000000 { 644 opp-hz = /bits/ 64 <180000000>; 645 required-opps = <&rpmhpd_opp_low_svs>; 646 }; 647 648 opp-275000000 { 649 opp-hz = /bits/ 64 <275000000>; 650 required-opps = <&rpmhpd_opp_svs>; 651 }; 652 653 opp-328580000 { 654 opp-hz = /bits/ 64 <328580000>; 655 required-opps = <&rpmhpd_opp_svs_l1>; 656 }; 657 658 opp-358000000 { 659 opp-hz = /bits/ 64 <358000000>; 660 required-opps = <&rpmhpd_opp_nom>; 661 }; 662 }; 663 664 qspi_opp_table: opp-table-qspi { 665 compatible = "operating-points-v2"; 666 667 opp-19200000 { 668 opp-hz = /bits/ 64 <19200000>; 669 required-opps = <&rpmhpd_opp_min_svs>; 670 }; 671 672 opp-100000000 { 673 opp-hz = /bits/ 64 <100000000>; 674 required-opps = <&rpmhpd_opp_low_svs>; 675 }; 676 677 opp-150000000 { 678 opp-hz = /bits/ 64 <150000000>; 679 required-opps = <&rpmhpd_opp_svs>; 680 }; 681 682 opp-300000000 { 683 opp-hz = /bits/ 64 <300000000>; 684 required-opps = <&rpmhpd_opp_nom>; 685 }; 686 }; 687 688 qup_opp_table: opp-table-qup { 689 compatible = "operating-points-v2"; 690 691 opp-50000000 { 692 opp-hz = /bits/ 64 <50000000>; 693 required-opps = <&rpmhpd_opp_min_svs>; 694 }; 695 696 opp-75000000 { 697 opp-hz = /bits/ 64 <75000000>; 698 required-opps = <&rpmhpd_opp_low_svs>; 699 }; 700 701 opp-100000000 { 702 opp-hz = /bits/ 64 <100000000>; 703 required-opps = <&rpmhpd_opp_svs>; 704 }; 705 706 opp-128000000 { 707 opp-hz = /bits/ 64 <128000000>; 708 required-opps = <&rpmhpd_opp_nom>; 709 }; 710 }; 711 712 pmu { 713 compatible = "arm,armv8-pmuv3"; 714 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 715 }; 716 717 psci: psci { 718 compatible = "arm,psci-1.0"; 719 method = "smc"; 720 721 cpu_pd0: power-domain-cpu0 { 722 #power-domain-cells = <0>; 723 power-domains = <&cluster_pd>; 724 domain-idle-states = <&little_cpu_sleep_0>; 725 }; 726 727 cpu_pd1: power-domain-cpu1 { 728 #power-domain-cells = <0>; 729 power-domains = <&cluster_pd>; 730 domain-idle-states = <&little_cpu_sleep_0>; 731 }; 732 733 cpu_pd2: power-domain-cpu2 { 734 #power-domain-cells = <0>; 735 power-domains = <&cluster_pd>; 736 domain-idle-states = <&little_cpu_sleep_0>; 737 }; 738 739 cpu_pd3: power-domain-cpu3 { 740 #power-domain-cells = <0>; 741 power-domains = <&cluster_pd>; 742 domain-idle-states = <&little_cpu_sleep_0>; 743 }; 744 745 cpu_pd4: power-domain-cpu4 { 746 #power-domain-cells = <0>; 747 power-domains = <&cluster_pd>; 748 domain-idle-states = <&big_cpu_sleep_0>; 749 }; 750 751 cpu_pd5: power-domain-cpu5 { 752 #power-domain-cells = <0>; 753 power-domains = <&cluster_pd>; 754 domain-idle-states = <&big_cpu_sleep_0>; 755 }; 756 757 cpu_pd6: power-domain-cpu6 { 758 #power-domain-cells = <0>; 759 power-domains = <&cluster_pd>; 760 domain-idle-states = <&big_cpu_sleep_0>; 761 }; 762 763 cpu_pd7: power-domain-cpu7 { 764 #power-domain-cells = <0>; 765 power-domains = <&cluster_pd>; 766 domain-idle-states = <&big_cpu_sleep_0>; 767 }; 768 769 cluster_pd: power-domain-cluster { 770 #power-domain-cells = <0>; 771 domain-idle-states = <&cluster_sleep_0>; 772 }; 773 }; 774 775 reserved-memory { 776 #address-cells = <2>; 777 #size-cells = <2>; 778 ranges; 779 780 hyp_mem: hyp-mem@85700000 { 781 reg = <0 0x85700000 0 0x600000>; 782 no-map; 783 }; 784 785 xbl_mem: xbl-mem@85e00000 { 786 reg = <0 0x85e00000 0 0x100000>; 787 no-map; 788 }; 789 790 aop_mem: aop-mem@85fc0000 { 791 reg = <0 0x85fc0000 0 0x20000>; 792 no-map; 793 }; 794 795 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { 796 compatible = "qcom,cmd-db"; 797 reg = <0x0 0x85fe0000 0 0x20000>; 798 no-map; 799 }; 800 801 smem@86000000 { 802 compatible = "qcom,smem"; 803 reg = <0x0 0x86000000 0 0x200000>; 804 no-map; 805 hwlocks = <&tcsr_mutex 3>; 806 }; 807 808 tz_mem: tz@86200000 { 809 reg = <0 0x86200000 0 0x2d00000>; 810 no-map; 811 }; 812 813 rmtfs_mem: rmtfs@88f00000 { 814 compatible = "qcom,rmtfs-mem"; 815 reg = <0 0x88f00000 0 0x200000>; 816 no-map; 817 818 qcom,client-id = <1>; 819 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 820 }; 821 822 qseecom_mem: qseecom@8ab00000 { 823 reg = <0 0x8ab00000 0 0x1400000>; 824 no-map; 825 }; 826 827 camera_mem: camera-mem@8bf00000 { 828 reg = <0 0x8bf00000 0 0x500000>; 829 no-map; 830 }; 831 832 ipa_fw_mem: ipa-fw@8c400000 { 833 reg = <0 0x8c400000 0 0x10000>; 834 no-map; 835 }; 836 837 ipa_gsi_mem: ipa-gsi@8c410000 { 838 reg = <0 0x8c410000 0 0x5000>; 839 no-map; 840 }; 841 842 gpu_mem: gpu@8c415000 { 843 reg = <0 0x8c415000 0 0x2000>; 844 no-map; 845 }; 846 847 adsp_mem: adsp@8c500000 { 848 reg = <0 0x8c500000 0 0x1a00000>; 849 no-map; 850 }; 851 852 wlan_msa_mem: wlan-msa@8df00000 { 853 reg = <0 0x8df00000 0 0x100000>; 854 no-map; 855 }; 856 857 mpss_region: mpss@8e000000 { 858 reg = <0 0x8e000000 0 0x7800000>; 859 no-map; 860 }; 861 862 venus_mem: venus@95800000 { 863 reg = <0 0x95800000 0 0x500000>; 864 no-map; 865 }; 866 867 cdsp_mem: cdsp@95d00000 { 868 reg = <0 0x95d00000 0 0x800000>; 869 no-map; 870 }; 871 872 mba_region: mba@96500000 { 873 reg = <0 0x96500000 0 0x200000>; 874 no-map; 875 }; 876 877 slpi_mem: slpi@96700000 { 878 reg = <0 0x96700000 0 0x1400000>; 879 no-map; 880 }; 881 882 spss_mem: spss@97b00000 { 883 reg = <0 0x97b00000 0 0x100000>; 884 no-map; 885 }; 886 887 mdata_mem: mpss-metadata { 888 alloc-ranges = <0 0xa0000000 0 0x20000000>; 889 size = <0 0x4000>; 890 no-map; 891 }; 892 893 fastrpc_mem: fastrpc { 894 compatible = "shared-dma-pool"; 895 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; 896 alignment = <0x0 0x400000>; 897 size = <0x0 0x1000000>; 898 reusable; 899 }; 900 }; 901 902 adsp_pas: remoteproc-adsp { 903 compatible = "qcom,sdm845-adsp-pas"; 904 905 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 906 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 907 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 908 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 909 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 910 interrupt-names = "wdog", "fatal", "ready", 911 "handover", "stop-ack"; 912 913 clocks = <&rpmhcc RPMH_CXO_CLK>; 914 clock-names = "xo"; 915 916 memory-region = <&adsp_mem>; 917 918 qcom,qmp = <&aoss_qmp>; 919 920 qcom,smem-states = <&adsp_smp2p_out 0>; 921 qcom,smem-state-names = "stop"; 922 923 status = "disabled"; 924 925 glink-edge { 926 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 927 label = "lpass"; 928 qcom,remote-pid = <2>; 929 mboxes = <&apss_shared 8>; 930 931 apr { 932 compatible = "qcom,apr-v2"; 933 qcom,glink-channels = "apr_audio_svc"; 934 qcom,domain = <APR_DOMAIN_ADSP>; 935 #address-cells = <1>; 936 #size-cells = <0>; 937 qcom,intents = <512 20>; 938 939 service@3 { 940 reg = <APR_SVC_ADSP_CORE>; 941 compatible = "qcom,q6core"; 942 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 943 }; 944 945 q6afe: service@4 { 946 compatible = "qcom,q6afe"; 947 reg = <APR_SVC_AFE>; 948 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 949 q6afedai: dais { 950 compatible = "qcom,q6afe-dais"; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 #sound-dai-cells = <1>; 954 }; 955 }; 956 957 q6asm: service@7 { 958 compatible = "qcom,q6asm"; 959 reg = <APR_SVC_ASM>; 960 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 961 q6asmdai: dais { 962 compatible = "qcom,q6asm-dais"; 963 #address-cells = <1>; 964 #size-cells = <0>; 965 #sound-dai-cells = <1>; 966 iommus = <&apps_smmu 0x1821 0x0>; 967 }; 968 }; 969 970 q6adm: service@8 { 971 compatible = "qcom,q6adm"; 972 reg = <APR_SVC_ADM>; 973 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 974 q6routing: routing { 975 compatible = "qcom,q6adm-routing"; 976 #sound-dai-cells = <0>; 977 }; 978 }; 979 }; 980 981 fastrpc { 982 compatible = "qcom,fastrpc"; 983 qcom,glink-channels = "fastrpcglink-apps-dsp"; 984 label = "adsp"; 985 qcom,non-secure-domain; 986 #address-cells = <1>; 987 #size-cells = <0>; 988 989 compute-cb@3 { 990 compatible = "qcom,fastrpc-compute-cb"; 991 reg = <3>; 992 iommus = <&apps_smmu 0x1823 0x0>; 993 }; 994 995 compute-cb@4 { 996 compatible = "qcom,fastrpc-compute-cb"; 997 reg = <4>; 998 iommus = <&apps_smmu 0x1824 0x0>; 999 }; 1000 }; 1001 }; 1002 }; 1003 1004 cdsp_pas: remoteproc-cdsp { 1005 compatible = "qcom,sdm845-cdsp-pas"; 1006 1007 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 1008 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1009 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1010 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1011 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1012 interrupt-names = "wdog", "fatal", "ready", 1013 "handover", "stop-ack"; 1014 1015 clocks = <&rpmhcc RPMH_CXO_CLK>; 1016 clock-names = "xo"; 1017 1018 memory-region = <&cdsp_mem>; 1019 1020 qcom,qmp = <&aoss_qmp>; 1021 1022 qcom,smem-states = <&cdsp_smp2p_out 0>; 1023 qcom,smem-state-names = "stop"; 1024 1025 status = "disabled"; 1026 1027 glink-edge { 1028 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 1029 label = "turing"; 1030 qcom,remote-pid = <5>; 1031 mboxes = <&apss_shared 4>; 1032 fastrpc { 1033 compatible = "qcom,fastrpc"; 1034 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1035 label = "cdsp"; 1036 qcom,non-secure-domain; 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 1040 compute-cb@1 { 1041 compatible = "qcom,fastrpc-compute-cb"; 1042 reg = <1>; 1043 iommus = <&apps_smmu 0x1401 0x30>; 1044 }; 1045 1046 compute-cb@2 { 1047 compatible = "qcom,fastrpc-compute-cb"; 1048 reg = <2>; 1049 iommus = <&apps_smmu 0x1402 0x30>; 1050 }; 1051 1052 compute-cb@3 { 1053 compatible = "qcom,fastrpc-compute-cb"; 1054 reg = <3>; 1055 iommus = <&apps_smmu 0x1403 0x30>; 1056 }; 1057 1058 compute-cb@4 { 1059 compatible = "qcom,fastrpc-compute-cb"; 1060 reg = <4>; 1061 iommus = <&apps_smmu 0x1404 0x30>; 1062 }; 1063 1064 compute-cb@5 { 1065 compatible = "qcom,fastrpc-compute-cb"; 1066 reg = <5>; 1067 iommus = <&apps_smmu 0x1405 0x30>; 1068 }; 1069 1070 compute-cb@6 { 1071 compatible = "qcom,fastrpc-compute-cb"; 1072 reg = <6>; 1073 iommus = <&apps_smmu 0x1406 0x30>; 1074 }; 1075 1076 compute-cb@7 { 1077 compatible = "qcom,fastrpc-compute-cb"; 1078 reg = <7>; 1079 iommus = <&apps_smmu 0x1407 0x30>; 1080 }; 1081 1082 compute-cb@8 { 1083 compatible = "qcom,fastrpc-compute-cb"; 1084 reg = <8>; 1085 iommus = <&apps_smmu 0x1408 0x30>; 1086 }; 1087 }; 1088 }; 1089 }; 1090 1091 smp2p-cdsp { 1092 compatible = "qcom,smp2p"; 1093 qcom,smem = <94>, <432>; 1094 1095 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 1096 1097 mboxes = <&apss_shared 6>; 1098 1099 qcom,local-pid = <0>; 1100 qcom,remote-pid = <5>; 1101 1102 cdsp_smp2p_out: master-kernel { 1103 qcom,entry-name = "master-kernel"; 1104 #qcom,smem-state-cells = <1>; 1105 }; 1106 1107 cdsp_smp2p_in: slave-kernel { 1108 qcom,entry-name = "slave-kernel"; 1109 1110 interrupt-controller; 1111 #interrupt-cells = <2>; 1112 }; 1113 }; 1114 1115 smp2p-lpass { 1116 compatible = "qcom,smp2p"; 1117 qcom,smem = <443>, <429>; 1118 1119 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 1120 1121 mboxes = <&apss_shared 10>; 1122 1123 qcom,local-pid = <0>; 1124 qcom,remote-pid = <2>; 1125 1126 adsp_smp2p_out: master-kernel { 1127 qcom,entry-name = "master-kernel"; 1128 #qcom,smem-state-cells = <1>; 1129 }; 1130 1131 adsp_smp2p_in: slave-kernel { 1132 qcom,entry-name = "slave-kernel"; 1133 1134 interrupt-controller; 1135 #interrupt-cells = <2>; 1136 }; 1137 }; 1138 1139 smp2p-mpss { 1140 compatible = "qcom,smp2p"; 1141 qcom,smem = <435>, <428>; 1142 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 1143 mboxes = <&apss_shared 14>; 1144 qcom,local-pid = <0>; 1145 qcom,remote-pid = <1>; 1146 1147 modem_smp2p_out: master-kernel { 1148 qcom,entry-name = "master-kernel"; 1149 #qcom,smem-state-cells = <1>; 1150 }; 1151 1152 modem_smp2p_in: slave-kernel { 1153 qcom,entry-name = "slave-kernel"; 1154 interrupt-controller; 1155 #interrupt-cells = <2>; 1156 }; 1157 1158 ipa_smp2p_out: ipa-ap-to-modem { 1159 qcom,entry-name = "ipa"; 1160 #qcom,smem-state-cells = <1>; 1161 }; 1162 1163 ipa_smp2p_in: ipa-modem-to-ap { 1164 qcom,entry-name = "ipa"; 1165 interrupt-controller; 1166 #interrupt-cells = <2>; 1167 }; 1168 }; 1169 1170 smp2p-slpi { 1171 compatible = "qcom,smp2p"; 1172 qcom,smem = <481>, <430>; 1173 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 1174 mboxes = <&apss_shared 26>; 1175 qcom,local-pid = <0>; 1176 qcom,remote-pid = <3>; 1177 1178 slpi_smp2p_out: master-kernel { 1179 qcom,entry-name = "master-kernel"; 1180 #qcom,smem-state-cells = <1>; 1181 }; 1182 1183 slpi_smp2p_in: slave-kernel { 1184 qcom,entry-name = "slave-kernel"; 1185 interrupt-controller; 1186 #interrupt-cells = <2>; 1187 }; 1188 }; 1189 1190 soc: soc@0 { 1191 #address-cells = <2>; 1192 #size-cells = <2>; 1193 ranges = <0 0 0 0 0x10 0>; 1194 dma-ranges = <0 0 0 0 0x10 0>; 1195 compatible = "simple-bus"; 1196 1197 gcc: clock-controller@100000 { 1198 compatible = "qcom,gcc-sdm845"; 1199 reg = <0 0x00100000 0 0x1f0000>; 1200 clocks = <&rpmhcc RPMH_CXO_CLK>, 1201 <&rpmhcc RPMH_CXO_CLK_A>, 1202 <&sleep_clk>, 1203 <&pcie0_phy>, 1204 <&pcie1_phy>; 1205 clock-names = "bi_tcxo", 1206 "bi_tcxo_ao", 1207 "sleep_clk", 1208 "pcie_0_pipe_clk", 1209 "pcie_1_pipe_clk"; 1210 #clock-cells = <1>; 1211 #reset-cells = <1>; 1212 #power-domain-cells = <1>; 1213 power-domains = <&rpmhpd SDM845_CX>; 1214 }; 1215 1216 qfprom@784000 { 1217 compatible = "qcom,sdm845-qfprom", "qcom,qfprom"; 1218 reg = <0 0x00784000 0 0x8ff>; 1219 #address-cells = <1>; 1220 #size-cells = <1>; 1221 1222 qusb2p_hstx_trim: hstx-trim-primary@1eb { 1223 reg = <0x1eb 0x1>; 1224 bits = <1 4>; 1225 }; 1226 1227 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 1228 reg = <0x1eb 0x2>; 1229 bits = <6 4>; 1230 }; 1231 }; 1232 1233 rng: rng@793000 { 1234 compatible = "qcom,prng-ee"; 1235 reg = <0 0x00793000 0 0x1000>; 1236 clocks = <&gcc GCC_PRNG_AHB_CLK>; 1237 clock-names = "core"; 1238 }; 1239 1240 gpi_dma0: dma-controller@800000 { 1241 #dma-cells = <3>; 1242 compatible = "qcom,sdm845-gpi-dma"; 1243 reg = <0 0x00800000 0 0x60000>; 1244 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1257 dma-channels = <13>; 1258 dma-channel-mask = <0xfa>; 1259 iommus = <&apps_smmu 0x0016 0x0>; 1260 status = "disabled"; 1261 }; 1262 1263 qupv3_id_0: geniqup@8c0000 { 1264 compatible = "qcom,geni-se-qup"; 1265 reg = <0 0x008c0000 0 0x6000>; 1266 clock-names = "m-ahb", "s-ahb"; 1267 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1268 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1269 iommus = <&apps_smmu 0x3 0x0>; 1270 #address-cells = <2>; 1271 #size-cells = <2>; 1272 ranges; 1273 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>; 1274 interconnect-names = "qup-core"; 1275 status = "disabled"; 1276 1277 i2c0: i2c@880000 { 1278 compatible = "qcom,geni-i2c"; 1279 reg = <0 0x00880000 0 0x4000>; 1280 clock-names = "se"; 1281 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1282 pinctrl-names = "default"; 1283 pinctrl-0 = <&qup_i2c0_default>; 1284 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1285 #address-cells = <1>; 1286 #size-cells = <0>; 1287 power-domains = <&rpmhpd SDM845_CX>; 1288 operating-points-v2 = <&qup_opp_table>; 1289 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1290 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1291 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1292 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1293 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1294 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1295 dma-names = "tx", "rx"; 1296 status = "disabled"; 1297 }; 1298 1299 spi0: spi@880000 { 1300 compatible = "qcom,geni-spi"; 1301 reg = <0 0x00880000 0 0x4000>; 1302 clock-names = "se"; 1303 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1304 pinctrl-names = "default"; 1305 pinctrl-0 = <&qup_spi0_default>; 1306 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1307 #address-cells = <1>; 1308 #size-cells = <0>; 1309 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1310 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1311 interconnect-names = "qup-core", "qup-config"; 1312 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1313 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1314 dma-names = "tx", "rx"; 1315 status = "disabled"; 1316 }; 1317 1318 uart0: serial@880000 { 1319 compatible = "qcom,geni-uart"; 1320 reg = <0 0x00880000 0 0x4000>; 1321 clock-names = "se"; 1322 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1323 pinctrl-names = "default"; 1324 pinctrl-0 = <&qup_uart0_default>; 1325 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1326 power-domains = <&rpmhpd SDM845_CX>; 1327 operating-points-v2 = <&qup_opp_table>; 1328 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1329 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1330 interconnect-names = "qup-core", "qup-config"; 1331 status = "disabled"; 1332 }; 1333 1334 i2c1: i2c@884000 { 1335 compatible = "qcom,geni-i2c"; 1336 reg = <0 0x00884000 0 0x4000>; 1337 clock-names = "se"; 1338 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1339 pinctrl-names = "default"; 1340 pinctrl-0 = <&qup_i2c1_default>; 1341 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1342 #address-cells = <1>; 1343 #size-cells = <0>; 1344 power-domains = <&rpmhpd SDM845_CX>; 1345 operating-points-v2 = <&qup_opp_table>; 1346 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1347 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1348 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1349 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1350 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1351 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1352 dma-names = "tx", "rx"; 1353 status = "disabled"; 1354 }; 1355 1356 spi1: spi@884000 { 1357 compatible = "qcom,geni-spi"; 1358 reg = <0 0x00884000 0 0x4000>; 1359 clock-names = "se"; 1360 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1361 pinctrl-names = "default"; 1362 pinctrl-0 = <&qup_spi1_default>; 1363 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1364 #address-cells = <1>; 1365 #size-cells = <0>; 1366 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1367 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1368 interconnect-names = "qup-core", "qup-config"; 1369 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1370 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1371 dma-names = "tx", "rx"; 1372 status = "disabled"; 1373 }; 1374 1375 uart1: serial@884000 { 1376 compatible = "qcom,geni-uart"; 1377 reg = <0 0x00884000 0 0x4000>; 1378 clock-names = "se"; 1379 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1380 pinctrl-names = "default"; 1381 pinctrl-0 = <&qup_uart1_default>; 1382 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1383 power-domains = <&rpmhpd SDM845_CX>; 1384 operating-points-v2 = <&qup_opp_table>; 1385 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1386 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1387 interconnect-names = "qup-core", "qup-config"; 1388 status = "disabled"; 1389 }; 1390 1391 i2c2: i2c@888000 { 1392 compatible = "qcom,geni-i2c"; 1393 reg = <0 0x00888000 0 0x4000>; 1394 clock-names = "se"; 1395 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1396 pinctrl-names = "default"; 1397 pinctrl-0 = <&qup_i2c2_default>; 1398 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1399 #address-cells = <1>; 1400 #size-cells = <0>; 1401 power-domains = <&rpmhpd SDM845_CX>; 1402 operating-points-v2 = <&qup_opp_table>; 1403 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1404 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1405 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1406 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1407 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1408 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1409 dma-names = "tx", "rx"; 1410 status = "disabled"; 1411 }; 1412 1413 spi2: spi@888000 { 1414 compatible = "qcom,geni-spi"; 1415 reg = <0 0x00888000 0 0x4000>; 1416 clock-names = "se"; 1417 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1418 pinctrl-names = "default"; 1419 pinctrl-0 = <&qup_spi2_default>; 1420 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1421 #address-cells = <1>; 1422 #size-cells = <0>; 1423 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1424 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1425 interconnect-names = "qup-core", "qup-config"; 1426 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1427 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1428 dma-names = "tx", "rx"; 1429 status = "disabled"; 1430 }; 1431 1432 uart2: serial@888000 { 1433 compatible = "qcom,geni-uart"; 1434 reg = <0 0x00888000 0 0x4000>; 1435 clock-names = "se"; 1436 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1437 pinctrl-names = "default"; 1438 pinctrl-0 = <&qup_uart2_default>; 1439 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1440 power-domains = <&rpmhpd SDM845_CX>; 1441 operating-points-v2 = <&qup_opp_table>; 1442 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1443 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1444 interconnect-names = "qup-core", "qup-config"; 1445 status = "disabled"; 1446 }; 1447 1448 i2c3: i2c@88c000 { 1449 compatible = "qcom,geni-i2c"; 1450 reg = <0 0x0088c000 0 0x4000>; 1451 clock-names = "se"; 1452 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1453 pinctrl-names = "default"; 1454 pinctrl-0 = <&qup_i2c3_default>; 1455 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1456 #address-cells = <1>; 1457 #size-cells = <0>; 1458 power-domains = <&rpmhpd SDM845_CX>; 1459 operating-points-v2 = <&qup_opp_table>; 1460 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1461 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1462 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1463 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1464 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1465 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1466 dma-names = "tx", "rx"; 1467 status = "disabled"; 1468 }; 1469 1470 spi3: spi@88c000 { 1471 compatible = "qcom,geni-spi"; 1472 reg = <0 0x0088c000 0 0x4000>; 1473 clock-names = "se"; 1474 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1475 pinctrl-names = "default"; 1476 pinctrl-0 = <&qup_spi3_default>; 1477 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1478 #address-cells = <1>; 1479 #size-cells = <0>; 1480 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1481 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1482 interconnect-names = "qup-core", "qup-config"; 1483 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1484 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1485 dma-names = "tx", "rx"; 1486 status = "disabled"; 1487 }; 1488 1489 uart3: serial@88c000 { 1490 compatible = "qcom,geni-uart"; 1491 reg = <0 0x0088c000 0 0x4000>; 1492 clock-names = "se"; 1493 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1494 pinctrl-names = "default"; 1495 pinctrl-0 = <&qup_uart3_default>; 1496 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1497 power-domains = <&rpmhpd SDM845_CX>; 1498 operating-points-v2 = <&qup_opp_table>; 1499 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1500 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1501 interconnect-names = "qup-core", "qup-config"; 1502 status = "disabled"; 1503 }; 1504 1505 i2c4: i2c@890000 { 1506 compatible = "qcom,geni-i2c"; 1507 reg = <0 0x00890000 0 0x4000>; 1508 clock-names = "se"; 1509 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1510 pinctrl-names = "default"; 1511 pinctrl-0 = <&qup_i2c4_default>; 1512 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1513 #address-cells = <1>; 1514 #size-cells = <0>; 1515 power-domains = <&rpmhpd SDM845_CX>; 1516 operating-points-v2 = <&qup_opp_table>; 1517 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1518 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1519 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1520 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1521 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1522 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1523 dma-names = "tx", "rx"; 1524 status = "disabled"; 1525 }; 1526 1527 spi4: spi@890000 { 1528 compatible = "qcom,geni-spi"; 1529 reg = <0 0x00890000 0 0x4000>; 1530 clock-names = "se"; 1531 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1532 pinctrl-names = "default"; 1533 pinctrl-0 = <&qup_spi4_default>; 1534 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1535 #address-cells = <1>; 1536 #size-cells = <0>; 1537 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1538 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1539 interconnect-names = "qup-core", "qup-config"; 1540 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1541 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1542 dma-names = "tx", "rx"; 1543 status = "disabled"; 1544 }; 1545 1546 uart4: serial@890000 { 1547 compatible = "qcom,geni-uart"; 1548 reg = <0 0x00890000 0 0x4000>; 1549 clock-names = "se"; 1550 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1551 pinctrl-names = "default"; 1552 pinctrl-0 = <&qup_uart4_default>; 1553 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1554 power-domains = <&rpmhpd SDM845_CX>; 1555 operating-points-v2 = <&qup_opp_table>; 1556 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1557 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1558 interconnect-names = "qup-core", "qup-config"; 1559 status = "disabled"; 1560 }; 1561 1562 i2c5: i2c@894000 { 1563 compatible = "qcom,geni-i2c"; 1564 reg = <0 0x00894000 0 0x4000>; 1565 clock-names = "se"; 1566 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1567 pinctrl-names = "default"; 1568 pinctrl-0 = <&qup_i2c5_default>; 1569 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1570 #address-cells = <1>; 1571 #size-cells = <0>; 1572 power-domains = <&rpmhpd SDM845_CX>; 1573 operating-points-v2 = <&qup_opp_table>; 1574 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1575 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1576 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1577 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1578 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1579 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1580 dma-names = "tx", "rx"; 1581 status = "disabled"; 1582 }; 1583 1584 spi5: spi@894000 { 1585 compatible = "qcom,geni-spi"; 1586 reg = <0 0x00894000 0 0x4000>; 1587 clock-names = "se"; 1588 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1589 pinctrl-names = "default"; 1590 pinctrl-0 = <&qup_spi5_default>; 1591 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1592 #address-cells = <1>; 1593 #size-cells = <0>; 1594 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1595 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1596 interconnect-names = "qup-core", "qup-config"; 1597 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1598 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1599 dma-names = "tx", "rx"; 1600 status = "disabled"; 1601 }; 1602 1603 uart5: serial@894000 { 1604 compatible = "qcom,geni-uart"; 1605 reg = <0 0x00894000 0 0x4000>; 1606 clock-names = "se"; 1607 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1608 pinctrl-names = "default"; 1609 pinctrl-0 = <&qup_uart5_default>; 1610 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1611 power-domains = <&rpmhpd SDM845_CX>; 1612 operating-points-v2 = <&qup_opp_table>; 1613 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1614 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1615 interconnect-names = "qup-core", "qup-config"; 1616 status = "disabled"; 1617 }; 1618 1619 i2c6: i2c@898000 { 1620 compatible = "qcom,geni-i2c"; 1621 reg = <0 0x00898000 0 0x4000>; 1622 clock-names = "se"; 1623 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1624 pinctrl-names = "default"; 1625 pinctrl-0 = <&qup_i2c6_default>; 1626 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 power-domains = <&rpmhpd SDM845_CX>; 1630 operating-points-v2 = <&qup_opp_table>; 1631 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1632 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1633 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1634 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1635 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1636 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1637 dma-names = "tx", "rx"; 1638 status = "disabled"; 1639 }; 1640 1641 spi6: spi@898000 { 1642 compatible = "qcom,geni-spi"; 1643 reg = <0 0x00898000 0 0x4000>; 1644 clock-names = "se"; 1645 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1646 pinctrl-names = "default"; 1647 pinctrl-0 = <&qup_spi6_default>; 1648 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1649 #address-cells = <1>; 1650 #size-cells = <0>; 1651 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1652 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1653 interconnect-names = "qup-core", "qup-config"; 1654 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1655 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1656 dma-names = "tx", "rx"; 1657 status = "disabled"; 1658 }; 1659 1660 uart6: serial@898000 { 1661 compatible = "qcom,geni-uart"; 1662 reg = <0 0x00898000 0 0x4000>; 1663 clock-names = "se"; 1664 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1665 pinctrl-names = "default"; 1666 pinctrl-0 = <&qup_uart6_default>; 1667 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1668 power-domains = <&rpmhpd SDM845_CX>; 1669 operating-points-v2 = <&qup_opp_table>; 1670 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1671 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1672 interconnect-names = "qup-core", "qup-config"; 1673 status = "disabled"; 1674 }; 1675 1676 i2c7: i2c@89c000 { 1677 compatible = "qcom,geni-i2c"; 1678 reg = <0 0x0089c000 0 0x4000>; 1679 clock-names = "se"; 1680 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1681 pinctrl-names = "default"; 1682 pinctrl-0 = <&qup_i2c7_default>; 1683 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1684 #address-cells = <1>; 1685 #size-cells = <0>; 1686 power-domains = <&rpmhpd SDM845_CX>; 1687 operating-points-v2 = <&qup_opp_table>; 1688 status = "disabled"; 1689 }; 1690 1691 spi7: spi@89c000 { 1692 compatible = "qcom,geni-spi"; 1693 reg = <0 0x0089c000 0 0x4000>; 1694 clock-names = "se"; 1695 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1696 pinctrl-names = "default"; 1697 pinctrl-0 = <&qup_spi7_default>; 1698 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1699 #address-cells = <1>; 1700 #size-cells = <0>; 1701 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1702 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1703 interconnect-names = "qup-core", "qup-config"; 1704 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1705 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1706 dma-names = "tx", "rx"; 1707 status = "disabled"; 1708 }; 1709 1710 uart7: serial@89c000 { 1711 compatible = "qcom,geni-uart"; 1712 reg = <0 0x0089c000 0 0x4000>; 1713 clock-names = "se"; 1714 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1715 pinctrl-names = "default"; 1716 pinctrl-0 = <&qup_uart7_default>; 1717 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1718 power-domains = <&rpmhpd SDM845_CX>; 1719 operating-points-v2 = <&qup_opp_table>; 1720 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1721 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1722 interconnect-names = "qup-core", "qup-config"; 1723 status = "disabled"; 1724 }; 1725 }; 1726 1727 gpi_dma1: dma-controller@a00000 { 1728 #dma-cells = <3>; 1729 compatible = "qcom,sdm845-gpi-dma"; 1730 reg = <0 0x00a00000 0 0x60000>; 1731 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1743 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1744 dma-channels = <13>; 1745 dma-channel-mask = <0xfa>; 1746 iommus = <&apps_smmu 0x06d6 0x0>; 1747 status = "disabled"; 1748 }; 1749 1750 qupv3_id_1: geniqup@ac0000 { 1751 compatible = "qcom,geni-se-qup"; 1752 reg = <0 0x00ac0000 0 0x6000>; 1753 clock-names = "m-ahb", "s-ahb"; 1754 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1755 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1756 iommus = <&apps_smmu 0x6c3 0x0>; 1757 #address-cells = <2>; 1758 #size-cells = <2>; 1759 ranges; 1760 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>; 1761 interconnect-names = "qup-core"; 1762 status = "disabled"; 1763 1764 i2c8: i2c@a80000 { 1765 compatible = "qcom,geni-i2c"; 1766 reg = <0 0x00a80000 0 0x4000>; 1767 clock-names = "se"; 1768 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1769 pinctrl-names = "default"; 1770 pinctrl-0 = <&qup_i2c8_default>; 1771 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1772 #address-cells = <1>; 1773 #size-cells = <0>; 1774 power-domains = <&rpmhpd SDM845_CX>; 1775 operating-points-v2 = <&qup_opp_table>; 1776 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1777 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1778 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1779 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1780 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1781 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1782 dma-names = "tx", "rx"; 1783 status = "disabled"; 1784 }; 1785 1786 spi8: spi@a80000 { 1787 compatible = "qcom,geni-spi"; 1788 reg = <0 0x00a80000 0 0x4000>; 1789 clock-names = "se"; 1790 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1791 pinctrl-names = "default"; 1792 pinctrl-0 = <&qup_spi8_default>; 1793 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1794 #address-cells = <1>; 1795 #size-cells = <0>; 1796 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1797 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1798 interconnect-names = "qup-core", "qup-config"; 1799 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1800 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1801 dma-names = "tx", "rx"; 1802 status = "disabled"; 1803 }; 1804 1805 uart8: serial@a80000 { 1806 compatible = "qcom,geni-uart"; 1807 reg = <0 0x00a80000 0 0x4000>; 1808 clock-names = "se"; 1809 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1810 pinctrl-names = "default"; 1811 pinctrl-0 = <&qup_uart8_default>; 1812 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1813 power-domains = <&rpmhpd SDM845_CX>; 1814 operating-points-v2 = <&qup_opp_table>; 1815 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1816 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1817 interconnect-names = "qup-core", "qup-config"; 1818 status = "disabled"; 1819 }; 1820 1821 i2c9: i2c@a84000 { 1822 compatible = "qcom,geni-i2c"; 1823 reg = <0 0x00a84000 0 0x4000>; 1824 clock-names = "se"; 1825 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1826 pinctrl-names = "default"; 1827 pinctrl-0 = <&qup_i2c9_default>; 1828 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1829 #address-cells = <1>; 1830 #size-cells = <0>; 1831 power-domains = <&rpmhpd SDM845_CX>; 1832 operating-points-v2 = <&qup_opp_table>; 1833 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1834 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1835 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1836 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1837 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1838 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1839 dma-names = "tx", "rx"; 1840 status = "disabled"; 1841 }; 1842 1843 spi9: spi@a84000 { 1844 compatible = "qcom,geni-spi"; 1845 reg = <0 0x00a84000 0 0x4000>; 1846 clock-names = "se"; 1847 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1848 pinctrl-names = "default"; 1849 pinctrl-0 = <&qup_spi9_default>; 1850 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1851 #address-cells = <1>; 1852 #size-cells = <0>; 1853 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1854 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1855 interconnect-names = "qup-core", "qup-config"; 1856 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1857 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1858 dma-names = "tx", "rx"; 1859 status = "disabled"; 1860 }; 1861 1862 uart9: serial@a84000 { 1863 compatible = "qcom,geni-debug-uart"; 1864 reg = <0 0x00a84000 0 0x4000>; 1865 clock-names = "se"; 1866 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1867 pinctrl-names = "default"; 1868 pinctrl-0 = <&qup_uart9_default>; 1869 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1870 power-domains = <&rpmhpd SDM845_CX>; 1871 operating-points-v2 = <&qup_opp_table>; 1872 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1873 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1874 interconnect-names = "qup-core", "qup-config"; 1875 status = "disabled"; 1876 }; 1877 1878 i2c10: i2c@a88000 { 1879 compatible = "qcom,geni-i2c"; 1880 reg = <0 0x00a88000 0 0x4000>; 1881 clock-names = "se"; 1882 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1883 pinctrl-names = "default"; 1884 pinctrl-0 = <&qup_i2c10_default>; 1885 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1886 #address-cells = <1>; 1887 #size-cells = <0>; 1888 power-domains = <&rpmhpd SDM845_CX>; 1889 operating-points-v2 = <&qup_opp_table>; 1890 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1891 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1892 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1893 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1894 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1895 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1896 dma-names = "tx", "rx"; 1897 status = "disabled"; 1898 }; 1899 1900 spi10: spi@a88000 { 1901 compatible = "qcom,geni-spi"; 1902 reg = <0 0x00a88000 0 0x4000>; 1903 clock-names = "se"; 1904 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1905 pinctrl-names = "default"; 1906 pinctrl-0 = <&qup_spi10_default>; 1907 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1908 #address-cells = <1>; 1909 #size-cells = <0>; 1910 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1911 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1912 interconnect-names = "qup-core", "qup-config"; 1913 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1914 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1915 dma-names = "tx", "rx"; 1916 status = "disabled"; 1917 }; 1918 1919 uart10: serial@a88000 { 1920 compatible = "qcom,geni-uart"; 1921 reg = <0 0x00a88000 0 0x4000>; 1922 clock-names = "se"; 1923 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1924 pinctrl-names = "default"; 1925 pinctrl-0 = <&qup_uart10_default>; 1926 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1927 power-domains = <&rpmhpd SDM845_CX>; 1928 operating-points-v2 = <&qup_opp_table>; 1929 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1930 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1931 interconnect-names = "qup-core", "qup-config"; 1932 status = "disabled"; 1933 }; 1934 1935 i2c11: i2c@a8c000 { 1936 compatible = "qcom,geni-i2c"; 1937 reg = <0 0x00a8c000 0 0x4000>; 1938 clock-names = "se"; 1939 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1940 pinctrl-names = "default"; 1941 pinctrl-0 = <&qup_i2c11_default>; 1942 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1943 #address-cells = <1>; 1944 #size-cells = <0>; 1945 power-domains = <&rpmhpd SDM845_CX>; 1946 operating-points-v2 = <&qup_opp_table>; 1947 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1948 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1949 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1950 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1951 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1952 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1953 dma-names = "tx", "rx"; 1954 status = "disabled"; 1955 }; 1956 1957 spi11: spi@a8c000 { 1958 compatible = "qcom,geni-spi"; 1959 reg = <0 0x00a8c000 0 0x4000>; 1960 clock-names = "se"; 1961 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1962 pinctrl-names = "default"; 1963 pinctrl-0 = <&qup_spi11_default>; 1964 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1965 #address-cells = <1>; 1966 #size-cells = <0>; 1967 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1968 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1969 interconnect-names = "qup-core", "qup-config"; 1970 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1971 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1972 dma-names = "tx", "rx"; 1973 status = "disabled"; 1974 }; 1975 1976 uart11: serial@a8c000 { 1977 compatible = "qcom,geni-uart"; 1978 reg = <0 0x00a8c000 0 0x4000>; 1979 clock-names = "se"; 1980 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1981 pinctrl-names = "default"; 1982 pinctrl-0 = <&qup_uart11_default>; 1983 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1984 power-domains = <&rpmhpd SDM845_CX>; 1985 operating-points-v2 = <&qup_opp_table>; 1986 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1987 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1988 interconnect-names = "qup-core", "qup-config"; 1989 status = "disabled"; 1990 }; 1991 1992 i2c12: i2c@a90000 { 1993 compatible = "qcom,geni-i2c"; 1994 reg = <0 0x00a90000 0 0x4000>; 1995 clock-names = "se"; 1996 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1997 pinctrl-names = "default"; 1998 pinctrl-0 = <&qup_i2c12_default>; 1999 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2000 #address-cells = <1>; 2001 #size-cells = <0>; 2002 power-domains = <&rpmhpd SDM845_CX>; 2003 operating-points-v2 = <&qup_opp_table>; 2004 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2005 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2006 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2007 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2008 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 2009 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 2010 dma-names = "tx", "rx"; 2011 status = "disabled"; 2012 }; 2013 2014 spi12: spi@a90000 { 2015 compatible = "qcom,geni-spi"; 2016 reg = <0 0x00a90000 0 0x4000>; 2017 clock-names = "se"; 2018 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2019 pinctrl-names = "default"; 2020 pinctrl-0 = <&qup_spi12_default>; 2021 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2022 #address-cells = <1>; 2023 #size-cells = <0>; 2024 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2025 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2026 interconnect-names = "qup-core", "qup-config"; 2027 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 2028 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2029 dma-names = "tx", "rx"; 2030 status = "disabled"; 2031 }; 2032 2033 uart12: serial@a90000 { 2034 compatible = "qcom,geni-uart"; 2035 reg = <0 0x00a90000 0 0x4000>; 2036 clock-names = "se"; 2037 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2038 pinctrl-names = "default"; 2039 pinctrl-0 = <&qup_uart12_default>; 2040 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2041 power-domains = <&rpmhpd SDM845_CX>; 2042 operating-points-v2 = <&qup_opp_table>; 2043 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2044 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2045 interconnect-names = "qup-core", "qup-config"; 2046 status = "disabled"; 2047 }; 2048 2049 i2c13: i2c@a94000 { 2050 compatible = "qcom,geni-i2c"; 2051 reg = <0 0x00a94000 0 0x4000>; 2052 clock-names = "se"; 2053 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2054 pinctrl-names = "default"; 2055 pinctrl-0 = <&qup_i2c13_default>; 2056 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2057 #address-cells = <1>; 2058 #size-cells = <0>; 2059 power-domains = <&rpmhpd SDM845_CX>; 2060 operating-points-v2 = <&qup_opp_table>; 2061 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2062 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2063 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2064 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2065 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2066 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2067 dma-names = "tx", "rx"; 2068 status = "disabled"; 2069 }; 2070 2071 spi13: spi@a94000 { 2072 compatible = "qcom,geni-spi"; 2073 reg = <0 0x00a94000 0 0x4000>; 2074 clock-names = "se"; 2075 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2076 pinctrl-names = "default"; 2077 pinctrl-0 = <&qup_spi13_default>; 2078 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2079 #address-cells = <1>; 2080 #size-cells = <0>; 2081 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2082 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2083 interconnect-names = "qup-core", "qup-config"; 2084 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2085 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2086 dma-names = "tx", "rx"; 2087 status = "disabled"; 2088 }; 2089 2090 uart13: serial@a94000 { 2091 compatible = "qcom,geni-uart"; 2092 reg = <0 0x00a94000 0 0x4000>; 2093 clock-names = "se"; 2094 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2095 pinctrl-names = "default"; 2096 pinctrl-0 = <&qup_uart13_default>; 2097 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2098 power-domains = <&rpmhpd SDM845_CX>; 2099 operating-points-v2 = <&qup_opp_table>; 2100 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2101 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2102 interconnect-names = "qup-core", "qup-config"; 2103 status = "disabled"; 2104 }; 2105 2106 i2c14: i2c@a98000 { 2107 compatible = "qcom,geni-i2c"; 2108 reg = <0 0x00a98000 0 0x4000>; 2109 clock-names = "se"; 2110 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2111 pinctrl-names = "default"; 2112 pinctrl-0 = <&qup_i2c14_default>; 2113 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2114 #address-cells = <1>; 2115 #size-cells = <0>; 2116 power-domains = <&rpmhpd SDM845_CX>; 2117 operating-points-v2 = <&qup_opp_table>; 2118 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2119 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2120 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2121 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2122 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2123 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2124 dma-names = "tx", "rx"; 2125 status = "disabled"; 2126 }; 2127 2128 spi14: spi@a98000 { 2129 compatible = "qcom,geni-spi"; 2130 reg = <0 0x00a98000 0 0x4000>; 2131 clock-names = "se"; 2132 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2133 pinctrl-names = "default"; 2134 pinctrl-0 = <&qup_spi14_default>; 2135 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2136 #address-cells = <1>; 2137 #size-cells = <0>; 2138 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2139 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2140 interconnect-names = "qup-core", "qup-config"; 2141 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2142 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2143 dma-names = "tx", "rx"; 2144 status = "disabled"; 2145 }; 2146 2147 uart14: serial@a98000 { 2148 compatible = "qcom,geni-uart"; 2149 reg = <0 0x00a98000 0 0x4000>; 2150 clock-names = "se"; 2151 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2152 pinctrl-names = "default"; 2153 pinctrl-0 = <&qup_uart14_default>; 2154 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2155 power-domains = <&rpmhpd SDM845_CX>; 2156 operating-points-v2 = <&qup_opp_table>; 2157 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2158 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2159 interconnect-names = "qup-core", "qup-config"; 2160 status = "disabled"; 2161 }; 2162 2163 i2c15: i2c@a9c000 { 2164 compatible = "qcom,geni-i2c"; 2165 reg = <0 0x00a9c000 0 0x4000>; 2166 clock-names = "se"; 2167 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2168 pinctrl-names = "default"; 2169 pinctrl-0 = <&qup_i2c15_default>; 2170 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2171 #address-cells = <1>; 2172 #size-cells = <0>; 2173 power-domains = <&rpmhpd SDM845_CX>; 2174 operating-points-v2 = <&qup_opp_table>; 2175 status = "disabled"; 2176 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2177 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2178 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2179 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2180 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2181 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2182 dma-names = "tx", "rx"; 2183 }; 2184 2185 spi15: spi@a9c000 { 2186 compatible = "qcom,geni-spi"; 2187 reg = <0 0x00a9c000 0 0x4000>; 2188 clock-names = "se"; 2189 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2190 pinctrl-names = "default"; 2191 pinctrl-0 = <&qup_spi15_default>; 2192 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2193 #address-cells = <1>; 2194 #size-cells = <0>; 2195 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2196 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2197 interconnect-names = "qup-core", "qup-config"; 2198 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2199 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2200 dma-names = "tx", "rx"; 2201 status = "disabled"; 2202 }; 2203 2204 uart15: serial@a9c000 { 2205 compatible = "qcom,geni-uart"; 2206 reg = <0 0x00a9c000 0 0x4000>; 2207 clock-names = "se"; 2208 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2209 pinctrl-names = "default"; 2210 pinctrl-0 = <&qup_uart15_default>; 2211 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2212 power-domains = <&rpmhpd SDM845_CX>; 2213 operating-points-v2 = <&qup_opp_table>; 2214 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2215 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2216 interconnect-names = "qup-core", "qup-config"; 2217 status = "disabled"; 2218 }; 2219 }; 2220 2221 llcc: system-cache-controller@1100000 { 2222 compatible = "qcom,sdm845-llcc"; 2223 reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>, 2224 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, 2225 <0 0x01300000 0 0x50000>; 2226 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2227 "llcc3_base", "llcc_broadcast_base"; 2228 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2229 }; 2230 2231 dma@10a2000 { 2232 compatible = "qcom,sdm845-dcc", "qcom,dcc"; 2233 reg = <0x0 0x010a2000 0x0 0x1000>, 2234 <0x0 0x010ae000 0x0 0x2000>; 2235 }; 2236 2237 pmu@114a000 { 2238 compatible = "qcom,sdm845-llcc-bwmon"; 2239 reg = <0 0x0114a000 0 0x1000>; 2240 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 2241 interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>; 2242 2243 operating-points-v2 = <&llcc_bwmon_opp_table>; 2244 2245 llcc_bwmon_opp_table: opp-table { 2246 compatible = "operating-points-v2"; 2247 2248 /* 2249 * The interconnect path bandwidth taken from 2250 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc 2251 * interconnect. This also matches the 2252 * bandwidth table of qcom,llccbw (qcom,bw-tbl, 2253 * bus width: 4 bytes) from msm-4.9 downstream 2254 * kernel. 2255 */ 2256 opp-0 { 2257 opp-peak-kBps = <800000>; 2258 }; 2259 opp-1 { 2260 opp-peak-kBps = <1804000>; 2261 }; 2262 opp-2 { 2263 opp-peak-kBps = <3072000>; 2264 }; 2265 opp-3 { 2266 opp-peak-kBps = <5412000>; 2267 }; 2268 opp-4 { 2269 opp-peak-kBps = <7216000>; 2270 }; 2271 }; 2272 }; 2273 2274 pmu@1436400 { 2275 compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon"; 2276 reg = <0 0x01436400 0 0x600>; 2277 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 2278 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>; 2279 2280 operating-points-v2 = <&cpu_bwmon_opp_table>; 2281 2282 cpu_bwmon_opp_table: opp-table { 2283 compatible = "operating-points-v2"; 2284 2285 /* 2286 * The interconnect path bandwidth taken from 2287 * cpu4_opp_table bandwidth for OSM L3 2288 * interconnect. This also matches the OSM L3 2289 * from bandwidth table of qcom,cpu4-l3lat-mon 2290 * (qcom,core-dev-table, bus width: 16 bytes) 2291 * from msm-4.9 downstream kernel. 2292 */ 2293 opp-0 { 2294 opp-peak-kBps = <4800000>; 2295 }; 2296 opp-1 { 2297 opp-peak-kBps = <9216000>; 2298 }; 2299 opp-2 { 2300 opp-peak-kBps = <15052800>; 2301 }; 2302 opp-3 { 2303 opp-peak-kBps = <20889600>; 2304 }; 2305 opp-4 { 2306 opp-peak-kBps = <25497600>; 2307 }; 2308 }; 2309 }; 2310 2311 pcie0: pcie@1c00000 { 2312 compatible = "qcom,pcie-sdm845"; 2313 reg = <0 0x01c00000 0 0x2000>, 2314 <0 0x60000000 0 0xf1d>, 2315 <0 0x60000f20 0 0xa8>, 2316 <0 0x60100000 0 0x100000>, 2317 <0 0x01c07000 0 0x1000>; 2318 reg-names = "parf", "dbi", "elbi", "config", "mhi"; 2319 device_type = "pci"; 2320 linux,pci-domain = <0>; 2321 bus-range = <0x00 0xff>; 2322 num-lanes = <1>; 2323 2324 #address-cells = <3>; 2325 #size-cells = <2>; 2326 2327 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 2328 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>; 2329 2330 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 2331 interrupt-names = "msi"; 2332 #interrupt-cells = <1>; 2333 interrupt-map-mask = <0 0 0 0x7>; 2334 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2335 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2336 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2337 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2338 2339 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2340 <&gcc GCC_PCIE_0_AUX_CLK>, 2341 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2342 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2343 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2344 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2345 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2346 clock-names = "pipe", 2347 "aux", 2348 "cfg", 2349 "bus_master", 2350 "bus_slave", 2351 "slave_q2a", 2352 "tbu"; 2353 2354 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, 2355 <0x100 &apps_smmu 0x1c11 0x1>, 2356 <0x200 &apps_smmu 0x1c12 0x1>, 2357 <0x300 &apps_smmu 0x1c13 0x1>, 2358 <0x400 &apps_smmu 0x1c14 0x1>, 2359 <0x500 &apps_smmu 0x1c15 0x1>, 2360 <0x600 &apps_smmu 0x1c16 0x1>, 2361 <0x700 &apps_smmu 0x1c17 0x1>, 2362 <0x800 &apps_smmu 0x1c18 0x1>, 2363 <0x900 &apps_smmu 0x1c19 0x1>, 2364 <0xa00 &apps_smmu 0x1c1a 0x1>, 2365 <0xb00 &apps_smmu 0x1c1b 0x1>, 2366 <0xc00 &apps_smmu 0x1c1c 0x1>, 2367 <0xd00 &apps_smmu 0x1c1d 0x1>, 2368 <0xe00 &apps_smmu 0x1c1e 0x1>, 2369 <0xf00 &apps_smmu 0x1c1f 0x1>; 2370 2371 resets = <&gcc GCC_PCIE_0_BCR>; 2372 reset-names = "pci"; 2373 2374 power-domains = <&gcc PCIE_0_GDSC>; 2375 2376 phys = <&pcie0_phy>; 2377 phy-names = "pciephy"; 2378 2379 status = "disabled"; 2380 2381 pcie@0 { 2382 device_type = "pci"; 2383 reg = <0x0 0x0 0x0 0x0 0x0>; 2384 bus-range = <0x01 0xff>; 2385 2386 #address-cells = <3>; 2387 #size-cells = <2>; 2388 ranges; 2389 }; 2390 }; 2391 2392 pcie0_phy: phy@1c06000 { 2393 compatible = "qcom,sdm845-qmp-pcie-phy"; 2394 reg = <0 0x01c06000 0 0x1000>; 2395 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2396 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2397 <&gcc GCC_PCIE_0_CLKREF_CLK>, 2398 <&gcc GCC_PCIE_PHY_REFGEN_CLK>, 2399 <&gcc GCC_PCIE_0_PIPE_CLK>; 2400 clock-names = "aux", 2401 "cfg_ahb", 2402 "ref", 2403 "refgen", 2404 "pipe"; 2405 2406 clock-output-names = "pcie_0_pipe_clk"; 2407 #clock-cells = <0>; 2408 2409 #phy-cells = <0>; 2410 2411 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2412 reset-names = "phy"; 2413 2414 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2415 assigned-clock-rates = <100000000>; 2416 2417 status = "disabled"; 2418 }; 2419 2420 pcie1: pcie@1c08000 { 2421 compatible = "qcom,pcie-sdm845"; 2422 reg = <0 0x01c08000 0 0x2000>, 2423 <0 0x40000000 0 0xf1d>, 2424 <0 0x40000f20 0 0xa8>, 2425 <0 0x40100000 0 0x100000>, 2426 <0 0x01c0c000 0 0x1000>; 2427 reg-names = "parf", "dbi", "elbi", "config", "mhi"; 2428 device_type = "pci"; 2429 linux,pci-domain = <1>; 2430 bus-range = <0x00 0xff>; 2431 num-lanes = <1>; 2432 2433 #address-cells = <3>; 2434 #size-cells = <2>; 2435 2436 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2437 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2438 2439 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 2440 interrupt-names = "msi"; 2441 #interrupt-cells = <1>; 2442 interrupt-map-mask = <0 0 0 0x7>; 2443 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2444 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2445 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2446 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2447 2448 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2449 <&gcc GCC_PCIE_1_AUX_CLK>, 2450 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2451 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2452 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2453 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2454 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2455 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2456 clock-names = "pipe", 2457 "aux", 2458 "cfg", 2459 "bus_master", 2460 "bus_slave", 2461 "slave_q2a", 2462 "ref", 2463 "tbu"; 2464 2465 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2466 assigned-clock-rates = <19200000>; 2467 2468 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2469 <0x100 &apps_smmu 0x1c01 0x1>, 2470 <0x200 &apps_smmu 0x1c02 0x1>, 2471 <0x300 &apps_smmu 0x1c03 0x1>, 2472 <0x400 &apps_smmu 0x1c04 0x1>, 2473 <0x500 &apps_smmu 0x1c05 0x1>, 2474 <0x600 &apps_smmu 0x1c06 0x1>, 2475 <0x700 &apps_smmu 0x1c07 0x1>, 2476 <0x800 &apps_smmu 0x1c08 0x1>, 2477 <0x900 &apps_smmu 0x1c09 0x1>, 2478 <0xa00 &apps_smmu 0x1c0a 0x1>, 2479 <0xb00 &apps_smmu 0x1c0b 0x1>, 2480 <0xc00 &apps_smmu 0x1c0c 0x1>, 2481 <0xd00 &apps_smmu 0x1c0d 0x1>, 2482 <0xe00 &apps_smmu 0x1c0e 0x1>, 2483 <0xf00 &apps_smmu 0x1c0f 0x1>; 2484 2485 resets = <&gcc GCC_PCIE_1_BCR>; 2486 reset-names = "pci"; 2487 2488 power-domains = <&gcc PCIE_1_GDSC>; 2489 2490 phys = <&pcie1_phy>; 2491 phy-names = "pciephy"; 2492 2493 status = "disabled"; 2494 2495 pcie@0 { 2496 device_type = "pci"; 2497 reg = <0x0 0x0 0x0 0x0 0x0>; 2498 bus-range = <0x01 0xff>; 2499 2500 #address-cells = <3>; 2501 #size-cells = <2>; 2502 ranges; 2503 }; 2504 }; 2505 2506 pcie1_phy: phy@1c0a000 { 2507 compatible = "qcom,sdm845-qhp-pcie-phy"; 2508 reg = <0 0x01c0a000 0 0x2000>; 2509 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2510 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2511 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2512 <&gcc GCC_PCIE_PHY_REFGEN_CLK>, 2513 <&gcc GCC_PCIE_1_PIPE_CLK>; 2514 clock-names = "aux", 2515 "cfg_ahb", 2516 "ref", 2517 "refgen", 2518 "pipe"; 2519 2520 clock-output-names = "pcie_1_pipe_clk"; 2521 #clock-cells = <0>; 2522 2523 #phy-cells = <0>; 2524 2525 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2526 reset-names = "phy"; 2527 2528 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2529 assigned-clock-rates = <100000000>; 2530 2531 status = "disabled"; 2532 }; 2533 2534 mem_noc: interconnect@1380000 { 2535 compatible = "qcom,sdm845-mem-noc"; 2536 reg = <0 0x01380000 0 0x27200>; 2537 #interconnect-cells = <2>; 2538 qcom,bcm-voters = <&apps_bcm_voter>; 2539 }; 2540 2541 dc_noc: interconnect@14e0000 { 2542 compatible = "qcom,sdm845-dc-noc"; 2543 reg = <0 0x014e0000 0 0x400>; 2544 #interconnect-cells = <2>; 2545 qcom,bcm-voters = <&apps_bcm_voter>; 2546 }; 2547 2548 config_noc: interconnect@1500000 { 2549 compatible = "qcom,sdm845-config-noc"; 2550 reg = <0 0x01500000 0 0x5080>; 2551 #interconnect-cells = <2>; 2552 qcom,bcm-voters = <&apps_bcm_voter>; 2553 }; 2554 2555 system_noc: interconnect@1620000 { 2556 compatible = "qcom,sdm845-system-noc"; 2557 reg = <0 0x01620000 0 0x18080>; 2558 #interconnect-cells = <2>; 2559 qcom,bcm-voters = <&apps_bcm_voter>; 2560 }; 2561 2562 aggre1_noc: interconnect@16e0000 { 2563 compatible = "qcom,sdm845-aggre1-noc"; 2564 reg = <0 0x016e0000 0 0x15080>; 2565 #interconnect-cells = <2>; 2566 qcom,bcm-voters = <&apps_bcm_voter>; 2567 }; 2568 2569 aggre2_noc: interconnect@1700000 { 2570 compatible = "qcom,sdm845-aggre2-noc"; 2571 reg = <0 0x01700000 0 0x1f300>; 2572 #interconnect-cells = <2>; 2573 qcom,bcm-voters = <&apps_bcm_voter>; 2574 }; 2575 2576 mmss_noc: interconnect@1740000 { 2577 compatible = "qcom,sdm845-mmss-noc"; 2578 reg = <0 0x01740000 0 0x1c100>; 2579 #interconnect-cells = <2>; 2580 qcom,bcm-voters = <&apps_bcm_voter>; 2581 }; 2582 2583 ufs_mem_hc: ufshc@1d84000 { 2584 compatible = "qcom,sdm845-ufshc", "qcom,ufshc", 2585 "jedec,ufs-2.0"; 2586 reg = <0 0x01d84000 0 0x2500>, 2587 <0 0x01d90000 0 0x8000>; 2588 reg-names = "std", "ice"; 2589 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2590 phys = <&ufs_mem_phy>; 2591 phy-names = "ufsphy"; 2592 lanes-per-direction = <2>; 2593 power-domains = <&gcc UFS_PHY_GDSC>; 2594 #reset-cells = <1>; 2595 resets = <&gcc GCC_UFS_PHY_BCR>; 2596 reset-names = "rst"; 2597 2598 iommus = <&apps_smmu 0x100 0xf>; 2599 2600 clock-names = 2601 "core_clk", 2602 "bus_aggr_clk", 2603 "iface_clk", 2604 "core_clk_unipro", 2605 "ref_clk", 2606 "tx_lane0_sync_clk", 2607 "rx_lane0_sync_clk", 2608 "rx_lane1_sync_clk", 2609 "ice_core_clk"; 2610 clocks = 2611 <&gcc GCC_UFS_PHY_AXI_CLK>, 2612 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2613 <&gcc GCC_UFS_PHY_AHB_CLK>, 2614 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2615 <&rpmhcc RPMH_CXO_CLK>, 2616 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2617 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2618 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2619 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2620 2621 operating-points-v2 = <&ufs_opp_table>; 2622 2623 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>, 2624 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 2625 interconnect-names = "ufs-ddr", "cpu-ufs"; 2626 2627 status = "disabled"; 2628 2629 ufs_opp_table: opp-table { 2630 compatible = "operating-points-v2"; 2631 2632 opp-50000000 { 2633 opp-hz = /bits/ 64 <50000000>, 2634 /bits/ 64 <0>, 2635 /bits/ 64 <0>, 2636 /bits/ 64 <37500000>, 2637 /bits/ 64 <0>, 2638 /bits/ 64 <0>, 2639 /bits/ 64 <0>, 2640 /bits/ 64 <0>, 2641 /bits/ 64 <75000000>; 2642 required-opps = <&rpmhpd_opp_low_svs>; 2643 }; 2644 2645 opp-200000000 { 2646 opp-hz = /bits/ 64 <200000000>, 2647 /bits/ 64 <0>, 2648 /bits/ 64 <0>, 2649 /bits/ 64 <150000000>, 2650 /bits/ 64 <0>, 2651 /bits/ 64 <0>, 2652 /bits/ 64 <0>, 2653 /bits/ 64 <0>, 2654 /bits/ 64 <300000000>; 2655 required-opps = <&rpmhpd_opp_nom>; 2656 }; 2657 }; 2658 }; 2659 2660 ufs_mem_phy: phy@1d87000 { 2661 compatible = "qcom,sdm845-qmp-ufs-phy"; 2662 reg = <0 0x01d87000 0 0x1000>; 2663 2664 clocks = <&rpmhcc RPMH_CXO_CLK>, 2665 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2666 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 2667 clock-names = "ref", 2668 "ref_aux", 2669 "qref"; 2670 2671 power-domains = <&gcc UFS_PHY_GDSC>; 2672 2673 resets = <&ufs_mem_hc 0>; 2674 reset-names = "ufsphy"; 2675 2676 #phy-cells = <0>; 2677 status = "disabled"; 2678 }; 2679 2680 cryptobam: dma-controller@1dc4000 { 2681 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2682 reg = <0 0x01dc4000 0 0x24000>; 2683 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2684 clocks = <&rpmhcc RPMH_CE_CLK>; 2685 clock-names = "bam_clk"; 2686 #dma-cells = <1>; 2687 qcom,ee = <0>; 2688 qcom,controlled-remotely; 2689 iommus = <&apps_smmu 0x704 0x1>, 2690 <&apps_smmu 0x706 0x1>, 2691 <&apps_smmu 0x714 0x1>, 2692 <&apps_smmu 0x716 0x1>; 2693 }; 2694 2695 crypto: crypto@1dfa000 { 2696 compatible = "qcom,crypto-v5.4"; 2697 reg = <0 0x01dfa000 0 0x6000>; 2698 clocks = <&gcc GCC_CE1_AHB_CLK>, 2699 <&gcc GCC_CE1_AXI_CLK>, 2700 <&rpmhcc RPMH_CE_CLK>; 2701 clock-names = "iface", "bus", "core"; 2702 dmas = <&cryptobam 6>, <&cryptobam 7>; 2703 dma-names = "rx", "tx"; 2704 iommus = <&apps_smmu 0x704 0x1>, 2705 <&apps_smmu 0x706 0x1>, 2706 <&apps_smmu 0x714 0x1>, 2707 <&apps_smmu 0x716 0x1>; 2708 }; 2709 2710 ipa: ipa@1e40000 { 2711 compatible = "qcom,sdm845-ipa"; 2712 2713 iommus = <&apps_smmu 0x720 0x0>, 2714 <&apps_smmu 0x722 0x0>; 2715 reg = <0 0x01e40000 0 0x7000>, 2716 <0 0x01e47000 0 0x2000>, 2717 <0 0x01e04000 0 0x2c000>; 2718 reg-names = "ipa-reg", 2719 "ipa-shared", 2720 "gsi"; 2721 2722 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 2723 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2724 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2725 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2726 interrupt-names = "ipa", 2727 "gsi", 2728 "ipa-clock-query", 2729 "ipa-setup-ready"; 2730 2731 clocks = <&rpmhcc RPMH_IPA_CLK>; 2732 clock-names = "core"; 2733 2734 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>, 2735 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 2736 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2737 interconnect-names = "memory", 2738 "imem", 2739 "config"; 2740 2741 qcom,smem-states = <&ipa_smp2p_out 0>, 2742 <&ipa_smp2p_out 1>; 2743 qcom,smem-state-names = "ipa-clock-enabled-valid", 2744 "ipa-clock-enabled"; 2745 2746 status = "disabled"; 2747 }; 2748 2749 tcsr_mutex: hwlock@1f40000 { 2750 compatible = "qcom,tcsr-mutex"; 2751 reg = <0 0x01f40000 0 0x20000>; 2752 #hwlock-cells = <1>; 2753 }; 2754 2755 tcsr_regs_1: syscon@1f60000 { 2756 compatible = "qcom,sdm845-tcsr", "syscon"; 2757 reg = <0 0x01f60000 0 0x20000>; 2758 }; 2759 2760 tlmm: pinctrl@3400000 { 2761 compatible = "qcom,sdm845-pinctrl"; 2762 reg = <0 0x03400000 0 0xc00000>; 2763 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2764 gpio-controller; 2765 #gpio-cells = <2>; 2766 interrupt-controller; 2767 #interrupt-cells = <2>; 2768 gpio-ranges = <&tlmm 0 0 151>; 2769 wakeup-parent = <&pdc_intc>; 2770 2771 cci0_default: cci0-default-state { 2772 /* SDA, SCL */ 2773 pins = "gpio17", "gpio18"; 2774 function = "cci_i2c"; 2775 2776 bias-pull-up; 2777 drive-strength = <2>; /* 2 mA */ 2778 }; 2779 2780 cci0_sleep: cci0-sleep-state { 2781 /* SDA, SCL */ 2782 pins = "gpio17", "gpio18"; 2783 function = "cci_i2c"; 2784 2785 drive-strength = <2>; /* 2 mA */ 2786 bias-pull-down; 2787 }; 2788 2789 cci1_default: cci1-default-state { 2790 /* SDA, SCL */ 2791 pins = "gpio19", "gpio20"; 2792 function = "cci_i2c"; 2793 2794 bias-pull-up; 2795 drive-strength = <2>; /* 2 mA */ 2796 }; 2797 2798 cci1_sleep: cci1-sleep-state { 2799 /* SDA, SCL */ 2800 pins = "gpio19", "gpio20"; 2801 function = "cci_i2c"; 2802 2803 drive-strength = <2>; /* 2 mA */ 2804 bias-pull-down; 2805 }; 2806 2807 qspi_clk: qspi-clk-state { 2808 pins = "gpio95"; 2809 function = "qspi_clk"; 2810 }; 2811 2812 qspi_cs0: qspi-cs0-state { 2813 pins = "gpio90"; 2814 function = "qspi_cs"; 2815 }; 2816 2817 qspi_cs1: qspi-cs1-state { 2818 pins = "gpio89"; 2819 function = "qspi_cs"; 2820 }; 2821 2822 qspi_data0: qspi-data0-state { 2823 pins = "gpio91"; 2824 function = "qspi_data"; 2825 }; 2826 2827 qspi_data1: qspi-data1-state { 2828 pins = "gpio92"; 2829 function = "qspi_data"; 2830 }; 2831 2832 qspi_data23: qspi-data23-state { 2833 pins = "gpio93", "gpio94"; 2834 function = "qspi_data"; 2835 }; 2836 2837 qup_i2c0_default: qup-i2c0-default-state { 2838 pins = "gpio0", "gpio1"; 2839 function = "qup0"; 2840 }; 2841 2842 qup_i2c1_default: qup-i2c1-default-state { 2843 pins = "gpio17", "gpio18"; 2844 function = "qup1"; 2845 }; 2846 2847 qup_i2c2_default: qup-i2c2-default-state { 2848 pins = "gpio27", "gpio28"; 2849 function = "qup2"; 2850 }; 2851 2852 qup_i2c3_default: qup-i2c3-default-state { 2853 pins = "gpio41", "gpio42"; 2854 function = "qup3"; 2855 }; 2856 2857 qup_i2c4_default: qup-i2c4-default-state { 2858 pins = "gpio89", "gpio90"; 2859 function = "qup4"; 2860 }; 2861 2862 qup_i2c5_default: qup-i2c5-default-state { 2863 pins = "gpio85", "gpio86"; 2864 function = "qup5"; 2865 }; 2866 2867 qup_i2c6_default: qup-i2c6-default-state { 2868 pins = "gpio45", "gpio46"; 2869 function = "qup6"; 2870 }; 2871 2872 qup_i2c7_default: qup-i2c7-default-state { 2873 pins = "gpio93", "gpio94"; 2874 function = "qup7"; 2875 }; 2876 2877 qup_i2c8_default: qup-i2c8-default-state { 2878 pins = "gpio65", "gpio66"; 2879 function = "qup8"; 2880 }; 2881 2882 qup_i2c9_default: qup-i2c9-default-state { 2883 pins = "gpio6", "gpio7"; 2884 function = "qup9"; 2885 }; 2886 2887 qup_i2c10_default: qup-i2c10-default-state { 2888 pins = "gpio55", "gpio56"; 2889 function = "qup10"; 2890 }; 2891 2892 qup_i2c11_default: qup-i2c11-default-state { 2893 pins = "gpio31", "gpio32"; 2894 function = "qup11"; 2895 }; 2896 2897 qup_i2c12_default: qup-i2c12-default-state { 2898 pins = "gpio49", "gpio50"; 2899 function = "qup12"; 2900 }; 2901 2902 qup_i2c13_default: qup-i2c13-default-state { 2903 pins = "gpio105", "gpio106"; 2904 function = "qup13"; 2905 }; 2906 2907 qup_i2c14_default: qup-i2c14-default-state { 2908 pins = "gpio33", "gpio34"; 2909 function = "qup14"; 2910 }; 2911 2912 qup_i2c15_default: qup-i2c15-default-state { 2913 pins = "gpio81", "gpio82"; 2914 function = "qup15"; 2915 }; 2916 2917 qup_spi0_default: qup-spi0-default-state { 2918 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2919 function = "qup0"; 2920 }; 2921 2922 qup_spi1_default: qup-spi1-default-state { 2923 pins = "gpio17", "gpio18", "gpio19", "gpio20"; 2924 function = "qup1"; 2925 }; 2926 2927 qup_spi2_default: qup-spi2-default-state { 2928 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2929 function = "qup2"; 2930 }; 2931 2932 qup_spi3_default: qup-spi3-default-state { 2933 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 2934 function = "qup3"; 2935 }; 2936 2937 qup_spi4_default: qup-spi4-default-state { 2938 pins = "gpio89", "gpio90", "gpio91", "gpio92"; 2939 function = "qup4"; 2940 }; 2941 2942 qup_spi5_default: qup-spi5-default-state { 2943 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 2944 function = "qup5"; 2945 }; 2946 2947 qup_spi6_default: qup-spi6-default-state { 2948 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 2949 function = "qup6"; 2950 }; 2951 2952 qup_spi7_default: qup-spi7-default-state { 2953 pins = "gpio93", "gpio94", "gpio95", "gpio96"; 2954 function = "qup7"; 2955 }; 2956 2957 qup_spi8_default: qup-spi8-default-state { 2958 pins = "gpio65", "gpio66", "gpio67", "gpio68"; 2959 function = "qup8"; 2960 }; 2961 2962 qup_spi9_default: qup-spi9-default-state { 2963 pins = "gpio6", "gpio7", "gpio4", "gpio5"; 2964 function = "qup9"; 2965 }; 2966 2967 qup_spi10_default: qup-spi10-default-state { 2968 pins = "gpio55", "gpio56", "gpio53", "gpio54"; 2969 function = "qup10"; 2970 }; 2971 2972 qup_spi11_default: qup-spi11-default-state { 2973 pins = "gpio31", "gpio32", "gpio33", "gpio34"; 2974 function = "qup11"; 2975 }; 2976 2977 qup_spi12_default: qup-spi12-default-state { 2978 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 2979 function = "qup12"; 2980 }; 2981 2982 qup_spi13_default: qup-spi13-default-state { 2983 pins = "gpio105", "gpio106", "gpio107", "gpio108"; 2984 function = "qup13"; 2985 }; 2986 2987 qup_spi14_default: qup-spi14-default-state { 2988 pins = "gpio33", "gpio34", "gpio31", "gpio32"; 2989 function = "qup14"; 2990 }; 2991 2992 qup_spi15_default: qup-spi15-default-state { 2993 pins = "gpio81", "gpio82", "gpio83", "gpio84"; 2994 function = "qup15"; 2995 }; 2996 2997 qup_uart0_default: qup-uart0-default-state { 2998 qup_uart0_tx: tx-pins { 2999 pins = "gpio2"; 3000 function = "qup0"; 3001 }; 3002 3003 qup_uart0_rx: rx-pins { 3004 pins = "gpio3"; 3005 function = "qup0"; 3006 }; 3007 }; 3008 3009 qup_uart1_default: qup-uart1-default-state { 3010 qup_uart1_tx: tx-pins { 3011 pins = "gpio19"; 3012 function = "qup1"; 3013 }; 3014 3015 qup_uart1_rx: rx-pins { 3016 pins = "gpio20"; 3017 function = "qup1"; 3018 }; 3019 }; 3020 3021 qup_uart2_default: qup-uart2-default-state { 3022 qup_uart2_tx: tx-pins { 3023 pins = "gpio29"; 3024 function = "qup2"; 3025 }; 3026 3027 qup_uart2_rx: rx-pins { 3028 pins = "gpio30"; 3029 function = "qup2"; 3030 }; 3031 }; 3032 3033 qup_uart3_default: qup-uart3-default-state { 3034 qup_uart3_tx: tx-pins { 3035 pins = "gpio43"; 3036 function = "qup3"; 3037 }; 3038 3039 qup_uart3_rx: rx-pins { 3040 pins = "gpio44"; 3041 function = "qup3"; 3042 }; 3043 }; 3044 3045 qup_uart3_4pin: qup-uart3-4pin-state { 3046 qup_uart3_4pin_cts: cts-pins { 3047 pins = "gpio41"; 3048 function = "qup3"; 3049 }; 3050 3051 qup_uart3_4pin_rts_tx: rts-tx-pins { 3052 pins = "gpio42", "gpio43"; 3053 function = "qup3"; 3054 }; 3055 3056 qup_uart3_4pin_rx: rx-pins { 3057 pins = "gpio44"; 3058 function = "qup3"; 3059 }; 3060 }; 3061 3062 qup_uart4_default: qup-uart4-default-state { 3063 qup_uart4_tx: tx-pins { 3064 pins = "gpio91"; 3065 function = "qup4"; 3066 }; 3067 3068 qup_uart4_rx: rx-pins { 3069 pins = "gpio92"; 3070 function = "qup4"; 3071 }; 3072 }; 3073 3074 qup_uart5_default: qup-uart5-default-state { 3075 qup_uart5_tx: tx-pins { 3076 pins = "gpio87"; 3077 function = "qup5"; 3078 }; 3079 3080 qup_uart5_rx: rx-pins { 3081 pins = "gpio88"; 3082 function = "qup5"; 3083 }; 3084 }; 3085 3086 qup_uart6_default: qup-uart6-default-state { 3087 qup_uart6_tx: tx-pins { 3088 pins = "gpio47"; 3089 function = "qup6"; 3090 }; 3091 3092 qup_uart6_rx: rx-pins { 3093 pins = "gpio48"; 3094 function = "qup6"; 3095 }; 3096 }; 3097 3098 qup_uart6_4pin: qup-uart6-4pin-state { 3099 qup_uart6_4pin_cts: cts-pins { 3100 pins = "gpio45"; 3101 function = "qup6"; 3102 bias-pull-down; 3103 }; 3104 3105 qup_uart6_4pin_rts_tx: rts-tx-pins { 3106 pins = "gpio46", "gpio47"; 3107 function = "qup6"; 3108 drive-strength = <2>; 3109 bias-disable; 3110 }; 3111 3112 qup_uart6_4pin_rx: rx-pins { 3113 pins = "gpio48"; 3114 function = "qup6"; 3115 bias-pull-up; 3116 }; 3117 }; 3118 3119 qup_uart7_default: qup-uart7-default-state { 3120 qup_uart7_tx: tx-pins { 3121 pins = "gpio95"; 3122 function = "qup7"; 3123 }; 3124 3125 qup_uart7_rx: rx-pins { 3126 pins = "gpio96"; 3127 function = "qup7"; 3128 }; 3129 }; 3130 3131 qup_uart8_default: qup-uart8-default-state { 3132 qup_uart8_tx: tx-pins { 3133 pins = "gpio67"; 3134 function = "qup8"; 3135 }; 3136 3137 qup_uart8_rx: rx-pins { 3138 pins = "gpio68"; 3139 function = "qup8"; 3140 }; 3141 }; 3142 3143 qup_uart9_default: qup-uart9-default-state { 3144 qup_uart9_tx: tx-pins { 3145 pins = "gpio4"; 3146 function = "qup9"; 3147 }; 3148 3149 qup_uart9_rx: rx-pins { 3150 pins = "gpio5"; 3151 function = "qup9"; 3152 }; 3153 }; 3154 3155 qup_uart10_default: qup-uart10-default-state { 3156 qup_uart10_tx: tx-pins { 3157 pins = "gpio53"; 3158 function = "qup10"; 3159 }; 3160 3161 qup_uart10_rx: rx-pins { 3162 pins = "gpio54"; 3163 function = "qup10"; 3164 }; 3165 }; 3166 3167 qup_uart11_default: qup-uart11-default-state { 3168 qup_uart11_tx: tx-pins { 3169 pins = "gpio33"; 3170 function = "qup11"; 3171 }; 3172 3173 qup_uart11_rx: rx-pins { 3174 pins = "gpio34"; 3175 function = "qup11"; 3176 }; 3177 }; 3178 3179 qup_uart12_default: qup-uart12-default-state { 3180 qup_uart12_tx: tx-pins { 3181 pins = "gpio51"; 3182 function = "qup0"; 3183 }; 3184 3185 qup_uart12_rx: rx-pins { 3186 pins = "gpio52"; 3187 function = "qup0"; 3188 }; 3189 }; 3190 3191 qup_uart13_default: qup-uart13-default-state { 3192 qup_uart13_tx: tx-pins { 3193 pins = "gpio107"; 3194 function = "qup13"; 3195 }; 3196 3197 qup_uart13_rx: rx-pins { 3198 pins = "gpio108"; 3199 function = "qup13"; 3200 }; 3201 }; 3202 3203 qup_uart14_default: qup-uart14-default-state { 3204 qup_uart14_tx: tx-pins { 3205 pins = "gpio31"; 3206 function = "qup14"; 3207 }; 3208 3209 qup_uart14_rx: rx-pins { 3210 pins = "gpio32"; 3211 function = "qup14"; 3212 }; 3213 }; 3214 3215 qup_uart15_default: qup-uart15-default-state { 3216 qup_uart15_tx: tx-pins { 3217 pins = "gpio83"; 3218 function = "qup15"; 3219 }; 3220 3221 qup_uart15_rx: rx-pins { 3222 pins = "gpio84"; 3223 function = "qup15"; 3224 }; 3225 }; 3226 3227 quat_mi2s_sleep: quat-mi2s-sleep-state { 3228 pins = "gpio58", "gpio59"; 3229 function = "gpio"; 3230 drive-strength = <2>; 3231 bias-pull-down; 3232 }; 3233 3234 quat_mi2s_active: quat-mi2s-active-state { 3235 pins = "gpio58", "gpio59"; 3236 function = "qua_mi2s"; 3237 drive-strength = <8>; 3238 bias-disable; 3239 output-high; 3240 }; 3241 3242 quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state { 3243 pins = "gpio60"; 3244 function = "gpio"; 3245 drive-strength = <2>; 3246 bias-pull-down; 3247 }; 3248 3249 quat_mi2s_sd0_active: quat-mi2s-sd0-active-state { 3250 pins = "gpio60"; 3251 function = "qua_mi2s"; 3252 drive-strength = <8>; 3253 bias-disable; 3254 }; 3255 3256 quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state { 3257 pins = "gpio61"; 3258 function = "gpio"; 3259 drive-strength = <2>; 3260 bias-pull-down; 3261 }; 3262 3263 quat_mi2s_sd1_active: quat-mi2s-sd1-active-state { 3264 pins = "gpio61"; 3265 function = "qua_mi2s"; 3266 drive-strength = <8>; 3267 bias-disable; 3268 }; 3269 3270 quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state { 3271 pins = "gpio62"; 3272 function = "gpio"; 3273 drive-strength = <2>; 3274 bias-pull-down; 3275 }; 3276 3277 quat_mi2s_sd2_active: quat-mi2s-sd2-active-state { 3278 pins = "gpio62"; 3279 function = "qua_mi2s"; 3280 drive-strength = <8>; 3281 bias-disable; 3282 }; 3283 3284 quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state { 3285 pins = "gpio63"; 3286 function = "gpio"; 3287 drive-strength = <2>; 3288 bias-pull-down; 3289 }; 3290 3291 quat_mi2s_sd3_active: quat-mi2s-sd3-active-state { 3292 pins = "gpio63"; 3293 function = "qua_mi2s"; 3294 drive-strength = <8>; 3295 bias-disable; 3296 }; 3297 }; 3298 3299 mss_pil: remoteproc@4080000 { 3300 compatible = "qcom,sdm845-mss-pil"; 3301 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; 3302 reg-names = "qdsp6", "rmb"; 3303 3304 interrupts-extended = 3305 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 3306 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3307 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3308 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3309 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3310 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3311 interrupt-names = "wdog", "fatal", "ready", 3312 "handover", "stop-ack", 3313 "shutdown-ack"; 3314 3315 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 3316 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 3317 <&gcc GCC_BOOT_ROM_AHB_CLK>, 3318 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 3319 <&gcc GCC_MSS_SNOC_AXI_CLK>, 3320 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 3321 <&gcc GCC_PRNG_AHB_CLK>, 3322 <&rpmhcc RPMH_CXO_CLK>; 3323 clock-names = "iface", "bus", "mem", "gpll0_mss", 3324 "snoc_axi", "mnoc_axi", "prng", "xo"; 3325 3326 qcom,qmp = <&aoss_qmp>; 3327 3328 qcom,smem-states = <&modem_smp2p_out 0>; 3329 qcom,smem-state-names = "stop"; 3330 3331 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 3332 <&pdc_reset PDC_MODEM_SYNC_RESET>; 3333 reset-names = "mss_restart", "pdc_reset"; 3334 3335 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 3336 3337 power-domains = <&rpmhpd SDM845_CX>, 3338 <&rpmhpd SDM845_MX>, 3339 <&rpmhpd SDM845_MSS>; 3340 power-domain-names = "cx", "mx", "mss"; 3341 3342 status = "disabled"; 3343 3344 mba { 3345 memory-region = <&mba_region>; 3346 }; 3347 3348 mpss { 3349 memory-region = <&mpss_region>; 3350 }; 3351 3352 metadata { 3353 memory-region = <&mdata_mem>; 3354 }; 3355 3356 glink-edge { 3357 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 3358 label = "modem"; 3359 qcom,remote-pid = <1>; 3360 mboxes = <&apss_shared 12>; 3361 }; 3362 }; 3363 3364 gpucc: clock-controller@5090000 { 3365 compatible = "qcom,sdm845-gpucc"; 3366 reg = <0 0x05090000 0 0x9000>; 3367 #clock-cells = <1>; 3368 #reset-cells = <1>; 3369 #power-domain-cells = <1>; 3370 clocks = <&rpmhcc RPMH_CXO_CLK>, 3371 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3372 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3373 clock-names = "bi_tcxo", 3374 "gcc_gpu_gpll0_clk_src", 3375 "gcc_gpu_gpll0_div_clk_src"; 3376 }; 3377 3378 slpi_pas: remoteproc@5c00000 { 3379 compatible = "qcom,sdm845-slpi-pas"; 3380 reg = <0 0x5c00000 0 0x4000>; 3381 3382 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 3383 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3384 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3385 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3386 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3387 interrupt-names = "wdog", "fatal", "ready", 3388 "handover", "stop-ack"; 3389 3390 clocks = <&rpmhcc RPMH_CXO_CLK>; 3391 clock-names = "xo"; 3392 3393 qcom,qmp = <&aoss_qmp>; 3394 3395 power-domains = <&rpmhpd SDM845_LCX>, 3396 <&rpmhpd SDM845_LMX>; 3397 power-domain-names = "lcx", "lmx"; 3398 3399 memory-region = <&slpi_mem>; 3400 3401 qcom,smem-states = <&slpi_smp2p_out 0>; 3402 qcom,smem-state-names = "stop"; 3403 3404 status = "disabled"; 3405 3406 glink-edge { 3407 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 3408 label = "dsps"; 3409 qcom,remote-pid = <3>; 3410 mboxes = <&apss_shared 24>; 3411 3412 fastrpc { 3413 compatible = "qcom,fastrpc"; 3414 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3415 label = "sdsp"; 3416 qcom,non-secure-domain; 3417 qcom,vmids = <QCOM_SCM_VMID_HLOS QCOM_SCM_VMID_MSS_MSA 3418 QCOM_SCM_VMID_SSC_Q6 QCOM_SCM_VMID_ADSP_Q6>; 3419 memory-region = <&fastrpc_mem>; 3420 #address-cells = <1>; 3421 #size-cells = <0>; 3422 3423 compute-cb@0 { 3424 compatible = "qcom,fastrpc-compute-cb"; 3425 reg = <0>; 3426 }; 3427 }; 3428 }; 3429 }; 3430 3431 stm@6002000 { 3432 compatible = "arm,coresight-stm", "arm,primecell"; 3433 reg = <0 0x06002000 0 0x1000>, 3434 <0 0x16280000 0 0x180000>; 3435 reg-names = "stm-base", "stm-stimulus-base"; 3436 3437 clocks = <&aoss_qmp>; 3438 clock-names = "apb_pclk"; 3439 3440 out-ports { 3441 port { 3442 stm_out: endpoint { 3443 remote-endpoint = 3444 <&funnel0_in7>; 3445 }; 3446 }; 3447 }; 3448 }; 3449 3450 funnel@6041000 { 3451 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3452 reg = <0 0x06041000 0 0x1000>; 3453 3454 clocks = <&aoss_qmp>; 3455 clock-names = "apb_pclk"; 3456 3457 out-ports { 3458 port { 3459 funnel0_out: endpoint { 3460 remote-endpoint = 3461 <&merge_funnel_in0>; 3462 }; 3463 }; 3464 }; 3465 3466 in-ports { 3467 #address-cells = <1>; 3468 #size-cells = <0>; 3469 3470 port@7 { 3471 reg = <7>; 3472 funnel0_in7: endpoint { 3473 remote-endpoint = <&stm_out>; 3474 }; 3475 }; 3476 }; 3477 }; 3478 3479 funnel@6043000 { 3480 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3481 reg = <0 0x06043000 0 0x1000>; 3482 3483 clocks = <&aoss_qmp>; 3484 clock-names = "apb_pclk"; 3485 3486 out-ports { 3487 port { 3488 funnel2_out: endpoint { 3489 remote-endpoint = 3490 <&merge_funnel_in2>; 3491 }; 3492 }; 3493 }; 3494 3495 in-ports { 3496 #address-cells = <1>; 3497 #size-cells = <0>; 3498 3499 port@5 { 3500 reg = <5>; 3501 funnel2_in5: endpoint { 3502 remote-endpoint = 3503 <&apss_merge_funnel_out>; 3504 }; 3505 }; 3506 }; 3507 }; 3508 3509 funnel@6045000 { 3510 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3511 reg = <0 0x06045000 0 0x1000>; 3512 3513 clocks = <&aoss_qmp>; 3514 clock-names = "apb_pclk"; 3515 3516 out-ports { 3517 port { 3518 merge_funnel_out: endpoint { 3519 remote-endpoint = <&etf_in>; 3520 }; 3521 }; 3522 }; 3523 3524 in-ports { 3525 #address-cells = <1>; 3526 #size-cells = <0>; 3527 3528 port@0 { 3529 reg = <0>; 3530 merge_funnel_in0: endpoint { 3531 remote-endpoint = 3532 <&funnel0_out>; 3533 }; 3534 }; 3535 3536 port@2 { 3537 reg = <2>; 3538 merge_funnel_in2: endpoint { 3539 remote-endpoint = 3540 <&funnel2_out>; 3541 }; 3542 }; 3543 }; 3544 }; 3545 3546 replicator@6046000 { 3547 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3548 reg = <0 0x06046000 0 0x1000>; 3549 3550 clocks = <&aoss_qmp>; 3551 clock-names = "apb_pclk"; 3552 3553 out-ports { 3554 port { 3555 replicator_out: endpoint { 3556 remote-endpoint = <&etr_in>; 3557 }; 3558 }; 3559 }; 3560 3561 in-ports { 3562 port { 3563 replicator_in: endpoint { 3564 remote-endpoint = <&etf_out>; 3565 }; 3566 }; 3567 }; 3568 }; 3569 3570 etf@6047000 { 3571 compatible = "arm,coresight-tmc", "arm,primecell"; 3572 reg = <0 0x06047000 0 0x1000>; 3573 3574 clocks = <&aoss_qmp>; 3575 clock-names = "apb_pclk"; 3576 3577 out-ports { 3578 port { 3579 etf_out: endpoint { 3580 remote-endpoint = 3581 <&replicator_in>; 3582 }; 3583 }; 3584 }; 3585 3586 in-ports { 3587 3588 port { 3589 etf_in: endpoint { 3590 remote-endpoint = 3591 <&merge_funnel_out>; 3592 }; 3593 }; 3594 }; 3595 }; 3596 3597 etr@6048000 { 3598 compatible = "arm,coresight-tmc", "arm,primecell"; 3599 reg = <0 0x06048000 0 0x1000>; 3600 3601 clocks = <&aoss_qmp>; 3602 clock-names = "apb_pclk"; 3603 arm,scatter-gather; 3604 3605 in-ports { 3606 port { 3607 etr_in: endpoint { 3608 remote-endpoint = 3609 <&replicator_out>; 3610 }; 3611 }; 3612 }; 3613 }; 3614 3615 etm@7040000 { 3616 compatible = "arm,coresight-etm4x", "arm,primecell"; 3617 reg = <0 0x07040000 0 0x1000>; 3618 3619 cpu = <&cpu0>; 3620 3621 clocks = <&aoss_qmp>; 3622 clock-names = "apb_pclk"; 3623 arm,coresight-loses-context-with-cpu; 3624 3625 out-ports { 3626 port { 3627 etm0_out: endpoint { 3628 remote-endpoint = 3629 <&apss_funnel_in0>; 3630 }; 3631 }; 3632 }; 3633 }; 3634 3635 etm@7140000 { 3636 compatible = "arm,coresight-etm4x", "arm,primecell"; 3637 reg = <0 0x07140000 0 0x1000>; 3638 3639 cpu = <&cpu1>; 3640 3641 clocks = <&aoss_qmp>; 3642 clock-names = "apb_pclk"; 3643 arm,coresight-loses-context-with-cpu; 3644 3645 out-ports { 3646 port { 3647 etm1_out: endpoint { 3648 remote-endpoint = 3649 <&apss_funnel_in1>; 3650 }; 3651 }; 3652 }; 3653 }; 3654 3655 etm@7240000 { 3656 compatible = "arm,coresight-etm4x", "arm,primecell"; 3657 reg = <0 0x07240000 0 0x1000>; 3658 3659 cpu = <&cpu2>; 3660 3661 clocks = <&aoss_qmp>; 3662 clock-names = "apb_pclk"; 3663 arm,coresight-loses-context-with-cpu; 3664 3665 out-ports { 3666 port { 3667 etm2_out: endpoint { 3668 remote-endpoint = 3669 <&apss_funnel_in2>; 3670 }; 3671 }; 3672 }; 3673 }; 3674 3675 etm@7340000 { 3676 compatible = "arm,coresight-etm4x", "arm,primecell"; 3677 reg = <0 0x07340000 0 0x1000>; 3678 3679 cpu = <&cpu3>; 3680 3681 clocks = <&aoss_qmp>; 3682 clock-names = "apb_pclk"; 3683 arm,coresight-loses-context-with-cpu; 3684 3685 out-ports { 3686 port { 3687 etm3_out: endpoint { 3688 remote-endpoint = 3689 <&apss_funnel_in3>; 3690 }; 3691 }; 3692 }; 3693 }; 3694 3695 etm@7440000 { 3696 compatible = "arm,coresight-etm4x", "arm,primecell"; 3697 reg = <0 0x07440000 0 0x1000>; 3698 3699 cpu = <&cpu4>; 3700 3701 clocks = <&aoss_qmp>; 3702 clock-names = "apb_pclk"; 3703 arm,coresight-loses-context-with-cpu; 3704 3705 out-ports { 3706 port { 3707 etm4_out: endpoint { 3708 remote-endpoint = 3709 <&apss_funnel_in4>; 3710 }; 3711 }; 3712 }; 3713 }; 3714 3715 etm@7540000 { 3716 compatible = "arm,coresight-etm4x", "arm,primecell"; 3717 reg = <0 0x07540000 0 0x1000>; 3718 3719 cpu = <&cpu5>; 3720 3721 clocks = <&aoss_qmp>; 3722 clock-names = "apb_pclk"; 3723 arm,coresight-loses-context-with-cpu; 3724 3725 out-ports { 3726 port { 3727 etm5_out: endpoint { 3728 remote-endpoint = 3729 <&apss_funnel_in5>; 3730 }; 3731 }; 3732 }; 3733 }; 3734 3735 etm@7640000 { 3736 compatible = "arm,coresight-etm4x", "arm,primecell"; 3737 reg = <0 0x07640000 0 0x1000>; 3738 3739 cpu = <&cpu6>; 3740 3741 clocks = <&aoss_qmp>; 3742 clock-names = "apb_pclk"; 3743 arm,coresight-loses-context-with-cpu; 3744 3745 out-ports { 3746 port { 3747 etm6_out: endpoint { 3748 remote-endpoint = 3749 <&apss_funnel_in6>; 3750 }; 3751 }; 3752 }; 3753 }; 3754 3755 etm@7740000 { 3756 compatible = "arm,coresight-etm4x", "arm,primecell"; 3757 reg = <0 0x07740000 0 0x1000>; 3758 3759 cpu = <&cpu7>; 3760 3761 clocks = <&aoss_qmp>; 3762 clock-names = "apb_pclk"; 3763 arm,coresight-loses-context-with-cpu; 3764 3765 out-ports { 3766 port { 3767 etm7_out: endpoint { 3768 remote-endpoint = 3769 <&apss_funnel_in7>; 3770 }; 3771 }; 3772 }; 3773 }; 3774 3775 funnel@7800000 { /* APSS Funnel */ 3776 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3777 reg = <0 0x07800000 0 0x1000>; 3778 3779 clocks = <&aoss_qmp>; 3780 clock-names = "apb_pclk"; 3781 3782 out-ports { 3783 port { 3784 apss_funnel_out: endpoint { 3785 remote-endpoint = 3786 <&apss_merge_funnel_in>; 3787 }; 3788 }; 3789 }; 3790 3791 in-ports { 3792 #address-cells = <1>; 3793 #size-cells = <0>; 3794 3795 port@0 { 3796 reg = <0>; 3797 apss_funnel_in0: endpoint { 3798 remote-endpoint = 3799 <&etm0_out>; 3800 }; 3801 }; 3802 3803 port@1 { 3804 reg = <1>; 3805 apss_funnel_in1: endpoint { 3806 remote-endpoint = 3807 <&etm1_out>; 3808 }; 3809 }; 3810 3811 port@2 { 3812 reg = <2>; 3813 apss_funnel_in2: endpoint { 3814 remote-endpoint = 3815 <&etm2_out>; 3816 }; 3817 }; 3818 3819 port@3 { 3820 reg = <3>; 3821 apss_funnel_in3: endpoint { 3822 remote-endpoint = 3823 <&etm3_out>; 3824 }; 3825 }; 3826 3827 port@4 { 3828 reg = <4>; 3829 apss_funnel_in4: endpoint { 3830 remote-endpoint = 3831 <&etm4_out>; 3832 }; 3833 }; 3834 3835 port@5 { 3836 reg = <5>; 3837 apss_funnel_in5: endpoint { 3838 remote-endpoint = 3839 <&etm5_out>; 3840 }; 3841 }; 3842 3843 port@6 { 3844 reg = <6>; 3845 apss_funnel_in6: endpoint { 3846 remote-endpoint = 3847 <&etm6_out>; 3848 }; 3849 }; 3850 3851 port@7 { 3852 reg = <7>; 3853 apss_funnel_in7: endpoint { 3854 remote-endpoint = 3855 <&etm7_out>; 3856 }; 3857 }; 3858 }; 3859 }; 3860 3861 funnel@7810000 { 3862 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3863 reg = <0 0x07810000 0 0x1000>; 3864 3865 clocks = <&aoss_qmp>; 3866 clock-names = "apb_pclk"; 3867 3868 out-ports { 3869 port { 3870 apss_merge_funnel_out: endpoint { 3871 remote-endpoint = 3872 <&funnel2_in5>; 3873 }; 3874 }; 3875 }; 3876 3877 in-ports { 3878 port { 3879 apss_merge_funnel_in: endpoint { 3880 remote-endpoint = 3881 <&apss_funnel_out>; 3882 }; 3883 }; 3884 }; 3885 }; 3886 3887 sdhc_2: mmc@8804000 { 3888 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 3889 reg = <0 0x08804000 0 0x1000>; 3890 3891 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3892 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3893 interrupt-names = "hc_irq", "pwr_irq"; 3894 3895 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3896 <&gcc GCC_SDCC2_APPS_CLK>, 3897 <&rpmhcc RPMH_CXO_CLK>; 3898 clock-names = "iface", "core", "xo"; 3899 iommus = <&apps_smmu 0xa0 0xf>; 3900 power-domains = <&rpmhpd SDM845_CX>; 3901 operating-points-v2 = <&sdhc2_opp_table>; 3902 3903 status = "disabled"; 3904 3905 sdhc2_opp_table: opp-table { 3906 compatible = "operating-points-v2"; 3907 3908 opp-9600000 { 3909 opp-hz = /bits/ 64 <9600000>; 3910 required-opps = <&rpmhpd_opp_min_svs>; 3911 }; 3912 3913 opp-19200000 { 3914 opp-hz = /bits/ 64 <19200000>; 3915 required-opps = <&rpmhpd_opp_low_svs>; 3916 }; 3917 3918 opp-100000000 { 3919 opp-hz = /bits/ 64 <100000000>; 3920 required-opps = <&rpmhpd_opp_svs>; 3921 }; 3922 3923 opp-201500000 { 3924 opp-hz = /bits/ 64 <201500000>; 3925 required-opps = <&rpmhpd_opp_svs_l1>; 3926 }; 3927 }; 3928 }; 3929 3930 qspi: spi@88df000 { 3931 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 3932 reg = <0 0x088df000 0 0x600>; 3933 iommus = <&apps_smmu 0x160 0x0>; 3934 #address-cells = <1>; 3935 #size-cells = <0>; 3936 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3937 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3938 <&gcc GCC_QSPI_CORE_CLK>; 3939 clock-names = "iface", "core"; 3940 power-domains = <&rpmhpd SDM845_CX>; 3941 operating-points-v2 = <&qspi_opp_table>; 3942 status = "disabled"; 3943 }; 3944 3945 slim: slim-ngd@171c0000 { 3946 compatible = "qcom,slim-ngd-v2.1.0"; 3947 reg = <0 0x171c0000 0 0x2c000>; 3948 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 3949 3950 dmas = <&slimbam 3>, <&slimbam 4>; 3951 dma-names = "rx", "tx"; 3952 3953 iommus = <&apps_smmu 0x1806 0x0>; 3954 #address-cells = <1>; 3955 #size-cells = <0>; 3956 status = "disabled"; 3957 }; 3958 3959 lmh_cluster1: lmh@17d70800 { 3960 compatible = "qcom,sdm845-lmh"; 3961 reg = <0 0x17d70800 0 0x400>; 3962 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3963 cpus = <&cpu4>; 3964 qcom,lmh-temp-arm-millicelsius = <65000>; 3965 qcom,lmh-temp-low-millicelsius = <94500>; 3966 qcom,lmh-temp-high-millicelsius = <95000>; 3967 interrupt-controller; 3968 #interrupt-cells = <1>; 3969 }; 3970 3971 lmh_cluster0: lmh@17d78800 { 3972 compatible = "qcom,sdm845-lmh"; 3973 reg = <0 0x17d78800 0 0x400>; 3974 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3975 cpus = <&cpu0>; 3976 qcom,lmh-temp-arm-millicelsius = <65000>; 3977 qcom,lmh-temp-low-millicelsius = <94500>; 3978 qcom,lmh-temp-high-millicelsius = <95000>; 3979 interrupt-controller; 3980 #interrupt-cells = <1>; 3981 }; 3982 3983 usb_1_hsphy: phy@88e2000 { 3984 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3985 reg = <0 0x088e2000 0 0x400>; 3986 status = "disabled"; 3987 #phy-cells = <0>; 3988 3989 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3990 <&rpmhcc RPMH_CXO_CLK>; 3991 clock-names = "cfg_ahb", "ref"; 3992 3993 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3994 3995 nvmem-cells = <&qusb2p_hstx_trim>; 3996 }; 3997 3998 usb_2_hsphy: phy@88e3000 { 3999 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 4000 reg = <0 0x088e3000 0 0x400>; 4001 status = "disabled"; 4002 #phy-cells = <0>; 4003 4004 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 4005 <&rpmhcc RPMH_CXO_CLK>; 4006 clock-names = "cfg_ahb", "ref"; 4007 4008 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 4009 4010 nvmem-cells = <&qusb2s_hstx_trim>; 4011 }; 4012 4013 usb_1_qmpphy: phy@88e8000 { 4014 compatible = "qcom,sdm845-qmp-usb3-dp-phy"; 4015 reg = <0 0x088e8000 0 0x3000>; 4016 status = "disabled"; 4017 4018 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4019 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 4020 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 4021 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, 4022 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 4023 clock-names = "aux", 4024 "ref", 4025 "com_aux", 4026 "usb3_pipe", 4027 "cfg_ahb"; 4028 4029 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 4030 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 4031 reset-names = "phy", "common"; 4032 4033 #clock-cells = <1>; 4034 #phy-cells = <1>; 4035 orientation-switch; 4036 4037 ports { 4038 #address-cells = <1>; 4039 #size-cells = <0>; 4040 4041 port@0 { 4042 reg = <0>; 4043 4044 usb_1_qmpphy_out: endpoint { 4045 }; 4046 }; 4047 4048 port@1 { 4049 reg = <1>; 4050 4051 usb_1_qmpphy_usb_ss_in: endpoint { 4052 remote-endpoint = <&usb_1_dwc3_ss>; 4053 }; 4054 }; 4055 4056 port@2 { 4057 reg = <2>; 4058 4059 usb_1_qmpphy_dp_in: endpoint { 4060 remote-endpoint = <&dp_out>; 4061 }; 4062 }; 4063 }; 4064 }; 4065 4066 usb_2_qmpphy: phy@88eb000 { 4067 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 4068 reg = <0 0x088eb000 0 0x1000>; 4069 4070 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 4071 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 4072 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 4073 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 4074 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 4075 clock-names = "aux", 4076 "cfg_ahb", 4077 "ref", 4078 "com_aux", 4079 "pipe"; 4080 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 4081 #clock-cells = <0>; 4082 #phy-cells = <0>; 4083 4084 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 4085 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 4086 reset-names = "phy", 4087 "phy_phy"; 4088 4089 status = "disabled"; 4090 }; 4091 4092 usb_1: usb@a6f8800 { 4093 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 4094 reg = <0 0x0a6f8800 0 0x400>; 4095 status = "disabled"; 4096 #address-cells = <2>; 4097 #size-cells = <2>; 4098 ranges; 4099 dma-ranges; 4100 4101 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4102 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4103 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4104 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4105 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4106 clock-names = "cfg_noc", 4107 "core", 4108 "iface", 4109 "sleep", 4110 "mock_utmi"; 4111 4112 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4113 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4114 assigned-clock-rates = <19200000>, <150000000>; 4115 4116 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4117 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4118 <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>, 4119 <&pdc_intc 8 IRQ_TYPE_EDGE_BOTH>, 4120 <&pdc_intc 6 IRQ_TYPE_LEVEL_HIGH>; 4121 interrupt-names = "pwr_event", 4122 "hs_phy_irq", 4123 "dp_hs_phy_irq", 4124 "dm_hs_phy_irq", 4125 "ss_phy_irq"; 4126 4127 power-domains = <&gcc USB30_PRIM_GDSC>; 4128 4129 resets = <&gcc GCC_USB30_PRIM_BCR>; 4130 4131 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>, 4132 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4133 interconnect-names = "usb-ddr", "apps-usb"; 4134 4135 usb_1_dwc3: usb@a600000 { 4136 compatible = "snps,dwc3"; 4137 reg = <0 0x0a600000 0 0xcd00>; 4138 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4139 iommus = <&apps_smmu 0x740 0>; 4140 snps,dis_u2_susphy_quirk; 4141 snps,dis_enblslpm_quirk; 4142 snps,parkmode-disable-ss-quirk; 4143 snps,dis-u1-entry-quirk; 4144 snps,dis-u2-entry-quirk; 4145 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4146 phy-names = "usb2-phy", "usb3-phy"; 4147 4148 ports { 4149 #address-cells = <1>; 4150 #size-cells = <0>; 4151 4152 port@0 { 4153 reg = <0>; 4154 4155 usb_1_dwc3_hs: endpoint { 4156 }; 4157 }; 4158 4159 port@1 { 4160 reg = <1>; 4161 4162 usb_1_dwc3_ss: endpoint { 4163 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 4164 }; 4165 }; 4166 }; 4167 }; 4168 }; 4169 4170 usb_2: usb@a8f8800 { 4171 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 4172 reg = <0 0x0a8f8800 0 0x400>; 4173 status = "disabled"; 4174 #address-cells = <2>; 4175 #size-cells = <2>; 4176 ranges; 4177 dma-ranges; 4178 4179 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4180 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4181 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4182 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4183 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 4184 clock-names = "cfg_noc", 4185 "core", 4186 "iface", 4187 "sleep", 4188 "mock_utmi"; 4189 4190 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4191 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4192 assigned-clock-rates = <19200000>, <150000000>; 4193 4194 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 4195 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 4196 <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>, 4197 <&pdc_intc 10 IRQ_TYPE_EDGE_BOTH>, 4198 <&pdc_intc 7 IRQ_TYPE_LEVEL_HIGH>; 4199 interrupt-names = "pwr_event", 4200 "hs_phy_irq", 4201 "dp_hs_phy_irq", 4202 "dm_hs_phy_irq", 4203 "ss_phy_irq"; 4204 4205 power-domains = <&gcc USB30_SEC_GDSC>; 4206 4207 resets = <&gcc GCC_USB30_SEC_BCR>; 4208 4209 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>, 4210 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 4211 interconnect-names = "usb-ddr", "apps-usb"; 4212 4213 usb_2_dwc3: usb@a800000 { 4214 compatible = "snps,dwc3"; 4215 reg = <0 0x0a800000 0 0xcd00>; 4216 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 4217 iommus = <&apps_smmu 0x760 0>; 4218 snps,dis_u2_susphy_quirk; 4219 snps,dis_enblslpm_quirk; 4220 snps,parkmode-disable-ss-quirk; 4221 snps,dis-u1-entry-quirk; 4222 snps,dis-u2-entry-quirk; 4223 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 4224 phy-names = "usb2-phy", "usb3-phy"; 4225 }; 4226 }; 4227 4228 venus: video-codec@aa00000 { 4229 compatible = "qcom,sdm845-venus-v2"; 4230 reg = <0 0x0aa00000 0 0xff000>; 4231 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4232 power-domains = <&videocc VENUS_GDSC>, 4233 <&videocc VCODEC0_GDSC>, 4234 <&videocc VCODEC1_GDSC>, 4235 <&rpmhpd SDM845_CX>; 4236 power-domain-names = "venus", "vcodec0", "vcodec1", "cx"; 4237 operating-points-v2 = <&venus_opp_table>; 4238 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 4239 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 4240 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 4241 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 4242 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>, 4243 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, 4244 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; 4245 clock-names = "core", "iface", "bus", 4246 "vcodec0_core", "vcodec0_bus", 4247 "vcodec1_core", "vcodec1_bus"; 4248 iommus = <&apps_smmu 0x10a0 0x8>, 4249 <&apps_smmu 0x10b0 0x0>; 4250 memory-region = <&venus_mem>; 4251 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>, 4252 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 4253 interconnect-names = "video-mem", "cpu-cfg"; 4254 4255 status = "disabled"; 4256 4257 video-core0 { 4258 compatible = "venus-decoder"; 4259 }; 4260 4261 video-core1 { 4262 compatible = "venus-encoder"; 4263 }; 4264 4265 venus_opp_table: opp-table { 4266 compatible = "operating-points-v2"; 4267 4268 opp-100000000 { 4269 opp-hz = /bits/ 64 <100000000>; 4270 required-opps = <&rpmhpd_opp_min_svs>; 4271 }; 4272 4273 opp-200000000 { 4274 opp-hz = /bits/ 64 <200000000>; 4275 required-opps = <&rpmhpd_opp_low_svs>; 4276 }; 4277 4278 opp-320000000 { 4279 opp-hz = /bits/ 64 <320000000>; 4280 required-opps = <&rpmhpd_opp_svs>; 4281 }; 4282 4283 opp-380000000 { 4284 opp-hz = /bits/ 64 <380000000>; 4285 required-opps = <&rpmhpd_opp_svs_l1>; 4286 }; 4287 4288 opp-444000000 { 4289 opp-hz = /bits/ 64 <444000000>; 4290 required-opps = <&rpmhpd_opp_nom>; 4291 }; 4292 4293 opp-533000097 { 4294 opp-hz = /bits/ 64 <533000097>; 4295 required-opps = <&rpmhpd_opp_turbo>; 4296 }; 4297 }; 4298 }; 4299 4300 videocc: clock-controller@ab00000 { 4301 compatible = "qcom,sdm845-videocc"; 4302 reg = <0 0x0ab00000 0 0x10000>; 4303 clocks = <&rpmhcc RPMH_CXO_CLK>; 4304 clock-names = "bi_tcxo"; 4305 #clock-cells = <1>; 4306 #power-domain-cells = <1>; 4307 #reset-cells = <1>; 4308 }; 4309 4310 camss: camss@acb3000 { 4311 compatible = "qcom,sdm845-camss"; 4312 4313 reg = <0 0x0acb3000 0 0x1000>, 4314 <0 0x0acba000 0 0x1000>, 4315 <0 0x0acc8000 0 0x1000>, 4316 <0 0x0ac65000 0 0x1000>, 4317 <0 0x0ac66000 0 0x1000>, 4318 <0 0x0ac67000 0 0x1000>, 4319 <0 0x0ac68000 0 0x1000>, 4320 <0 0x0acaf000 0 0x4000>, 4321 <0 0x0acb6000 0 0x4000>, 4322 <0 0x0acc4000 0 0x4000>; 4323 reg-names = "csid0", 4324 "csid1", 4325 "csid2", 4326 "csiphy0", 4327 "csiphy1", 4328 "csiphy2", 4329 "csiphy3", 4330 "vfe0", 4331 "vfe1", 4332 "vfe_lite"; 4333 4334 interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 4335 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, 4336 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 4337 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 4338 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 4339 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 4340 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 4341 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 4342 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 4343 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>; 4344 interrupt-names = "csid0", 4345 "csid1", 4346 "csid2", 4347 "csiphy0", 4348 "csiphy1", 4349 "csiphy2", 4350 "csiphy3", 4351 "vfe0", 4352 "vfe1", 4353 "vfe_lite"; 4354 4355 power-domains = <&clock_camcc IFE_0_GDSC>, 4356 <&clock_camcc IFE_1_GDSC>, 4357 <&clock_camcc TITAN_TOP_GDSC>; 4358 4359 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4360 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 4361 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, 4362 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, 4363 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, 4364 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, 4365 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, 4366 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, 4367 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, 4368 <&clock_camcc CAM_CC_CSIPHY0_CLK>, 4369 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, 4370 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, 4371 <&clock_camcc CAM_CC_CSIPHY1_CLK>, 4372 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, 4373 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, 4374 <&clock_camcc CAM_CC_CSIPHY2_CLK>, 4375 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, 4376 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, 4377 <&clock_camcc CAM_CC_CSIPHY3_CLK>, 4378 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, 4379 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, 4380 <&gcc GCC_CAMERA_AHB_CLK>, 4381 <&gcc GCC_CAMERA_AXI_CLK>, 4382 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4383 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4384 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, 4385 <&clock_camcc CAM_CC_IFE_0_CLK>, 4386 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4387 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, 4388 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, 4389 <&clock_camcc CAM_CC_IFE_1_CLK>, 4390 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4391 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, 4392 <&clock_camcc CAM_CC_IFE_LITE_CLK>, 4393 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4394 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>; 4395 clock-names = "camnoc_axi", 4396 "cpas_ahb", 4397 "cphy_rx_src", 4398 "csi0", 4399 "csi0_src", 4400 "csi1", 4401 "csi1_src", 4402 "csi2", 4403 "csi2_src", 4404 "csiphy0", 4405 "csiphy0_timer", 4406 "csiphy0_timer_src", 4407 "csiphy1", 4408 "csiphy1_timer", 4409 "csiphy1_timer_src", 4410 "csiphy2", 4411 "csiphy2_timer", 4412 "csiphy2_timer_src", 4413 "csiphy3", 4414 "csiphy3_timer", 4415 "csiphy3_timer_src", 4416 "gcc_camera_ahb", 4417 "gcc_camera_axi", 4418 "slow_ahb_src", 4419 "soc_ahb", 4420 "vfe0_axi", 4421 "vfe0", 4422 "vfe0_cphy_rx", 4423 "vfe0_src", 4424 "vfe1_axi", 4425 "vfe1", 4426 "vfe1_cphy_rx", 4427 "vfe1_src", 4428 "vfe_lite", 4429 "vfe_lite_cphy_rx", 4430 "vfe_lite_src"; 4431 4432 iommus = <&apps_smmu 0x0808 0x0>, 4433 <&apps_smmu 0x0810 0x8>, 4434 <&apps_smmu 0x0c08 0x0>, 4435 <&apps_smmu 0x0c10 0x8>; 4436 4437 status = "disabled"; 4438 4439 ports { 4440 #address-cells = <1>; 4441 #size-cells = <0>; 4442 4443 port@0 { 4444 reg = <0>; 4445 }; 4446 4447 port@1 { 4448 reg = <1>; 4449 }; 4450 4451 port@2 { 4452 reg = <2>; 4453 }; 4454 4455 port@3 { 4456 reg = <3>; 4457 }; 4458 }; 4459 }; 4460 4461 cci: cci@ac4a000 { 4462 compatible = "qcom,sdm845-cci", "qcom,msm8996-cci"; 4463 #address-cells = <1>; 4464 #size-cells = <0>; 4465 4466 reg = <0 0x0ac4a000 0 0x4000>; 4467 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4468 power-domains = <&clock_camcc TITAN_TOP_GDSC>; 4469 4470 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4471 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4472 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4473 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 4474 <&clock_camcc CAM_CC_CCI_CLK>, 4475 <&clock_camcc CAM_CC_CCI_CLK_SRC>; 4476 clock-names = "camnoc_axi", 4477 "soc_ahb", 4478 "slow_ahb_src", 4479 "cpas_ahb", 4480 "cci", 4481 "cci_src"; 4482 4483 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4484 <&clock_camcc CAM_CC_CCI_CLK>; 4485 assigned-clock-rates = <80000000>, <37500000>; 4486 4487 pinctrl-names = "default", "sleep"; 4488 pinctrl-0 = <&cci0_default &cci1_default>; 4489 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 4490 4491 status = "disabled"; 4492 4493 cci_i2c0: i2c-bus@0 { 4494 reg = <0>; 4495 clock-frequency = <1000000>; 4496 #address-cells = <1>; 4497 #size-cells = <0>; 4498 }; 4499 4500 cci_i2c1: i2c-bus@1 { 4501 reg = <1>; 4502 clock-frequency = <1000000>; 4503 #address-cells = <1>; 4504 #size-cells = <0>; 4505 }; 4506 }; 4507 4508 clock_camcc: clock-controller@ad00000 { 4509 compatible = "qcom,sdm845-camcc"; 4510 reg = <0 0x0ad00000 0 0x10000>; 4511 #clock-cells = <1>; 4512 #reset-cells = <1>; 4513 #power-domain-cells = <1>; 4514 clocks = <&rpmhcc RPMH_CXO_CLK>; 4515 clock-names = "bi_tcxo"; 4516 }; 4517 4518 mdss: display-subsystem@ae00000 { 4519 compatible = "qcom,sdm845-mdss"; 4520 reg = <0 0x0ae00000 0 0x1000>; 4521 reg-names = "mdss"; 4522 4523 power-domains = <&dispcc MDSS_GDSC>; 4524 4525 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4526 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4527 clock-names = "iface", "core"; 4528 4529 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4530 interrupt-controller; 4531 #interrupt-cells = <1>; 4532 4533 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>, 4534 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>; 4535 interconnect-names = "mdp0-mem", "mdp1-mem"; 4536 4537 iommus = <&apps_smmu 0x880 0x8>, 4538 <&apps_smmu 0xc80 0x8>; 4539 4540 status = "disabled"; 4541 4542 #address-cells = <2>; 4543 #size-cells = <2>; 4544 ranges; 4545 4546 mdss_mdp: display-controller@ae01000 { 4547 compatible = "qcom,sdm845-dpu"; 4548 reg = <0 0x0ae01000 0 0x8f000>, 4549 <0 0x0aeb0000 0 0x3000>; 4550 reg-names = "mdp", "vbif"; 4551 4552 clocks = <&gcc GCC_DISP_AXI_CLK>, 4553 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4554 <&dispcc DISP_CC_MDSS_AXI_CLK>, 4555 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4556 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4557 clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; 4558 4559 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4560 assigned-clock-rates = <19200000>; 4561 operating-points-v2 = <&mdp_opp_table>; 4562 power-domains = <&rpmhpd SDM845_CX>; 4563 4564 interrupt-parent = <&mdss>; 4565 interrupts = <0>; 4566 4567 ports { 4568 #address-cells = <1>; 4569 #size-cells = <0>; 4570 4571 port@0 { 4572 reg = <0>; 4573 dpu_intf0_out: endpoint { 4574 remote-endpoint = <&dp_in>; 4575 }; 4576 }; 4577 4578 port@1 { 4579 reg = <1>; 4580 dpu_intf1_out: endpoint { 4581 remote-endpoint = <&mdss_dsi0_in>; 4582 }; 4583 }; 4584 4585 port@2 { 4586 reg = <2>; 4587 dpu_intf2_out: endpoint { 4588 remote-endpoint = <&mdss_dsi1_in>; 4589 }; 4590 }; 4591 }; 4592 4593 mdp_opp_table: opp-table { 4594 compatible = "operating-points-v2"; 4595 4596 opp-19200000 { 4597 opp-hz = /bits/ 64 <19200000>; 4598 required-opps = <&rpmhpd_opp_min_svs>; 4599 }; 4600 4601 opp-171428571 { 4602 opp-hz = /bits/ 64 <171428571>; 4603 required-opps = <&rpmhpd_opp_low_svs>; 4604 }; 4605 4606 opp-344000000 { 4607 opp-hz = /bits/ 64 <344000000>; 4608 required-opps = <&rpmhpd_opp_svs_l1>; 4609 }; 4610 4611 opp-430000000 { 4612 opp-hz = /bits/ 64 <430000000>; 4613 required-opps = <&rpmhpd_opp_nom>; 4614 }; 4615 }; 4616 }; 4617 4618 mdss_dp: displayport-controller@ae90000 { 4619 status = "disabled"; 4620 compatible = "qcom,sdm845-dp"; 4621 4622 reg = <0 0x0ae90000 0 0x200>, 4623 <0 0x0ae90200 0 0x200>, 4624 <0 0x0ae90400 0 0x600>, 4625 <0 0x0ae90a00 0 0x600>, 4626 <0 0x0ae91000 0 0x600>; 4627 4628 interrupt-parent = <&mdss>; 4629 interrupts = <12>; 4630 4631 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4632 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4633 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4634 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4635 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4636 clock-names = "core_iface", "core_aux", "ctrl_link", 4637 "ctrl_link_iface", "stream_pixel"; 4638 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4639 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4640 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4641 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4642 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4643 phy-names = "dp"; 4644 4645 operating-points-v2 = <&dp_opp_table>; 4646 power-domains = <&rpmhpd SDM845_CX>; 4647 4648 ports { 4649 #address-cells = <1>; 4650 #size-cells = <0>; 4651 port@0 { 4652 reg = <0>; 4653 dp_in: endpoint { 4654 remote-endpoint = <&dpu_intf0_out>; 4655 }; 4656 }; 4657 4658 port@1 { 4659 reg = <1>; 4660 dp_out: endpoint { 4661 remote-endpoint = <&usb_1_qmpphy_dp_in>; 4662 }; 4663 }; 4664 }; 4665 4666 dp_opp_table: opp-table { 4667 compatible = "operating-points-v2"; 4668 4669 opp-162000000 { 4670 opp-hz = /bits/ 64 <162000000>; 4671 required-opps = <&rpmhpd_opp_low_svs>; 4672 }; 4673 4674 opp-270000000 { 4675 opp-hz = /bits/ 64 <270000000>; 4676 required-opps = <&rpmhpd_opp_svs>; 4677 }; 4678 4679 opp-540000000 { 4680 opp-hz = /bits/ 64 <540000000>; 4681 required-opps = <&rpmhpd_opp_svs_l1>; 4682 }; 4683 4684 opp-810000000 { 4685 opp-hz = /bits/ 64 <810000000>; 4686 required-opps = <&rpmhpd_opp_nom>; 4687 }; 4688 }; 4689 }; 4690 4691 mdss_dsi0: dsi@ae94000 { 4692 compatible = "qcom,sdm845-dsi-ctrl", 4693 "qcom,mdss-dsi-ctrl"; 4694 reg = <0 0x0ae94000 0 0x400>; 4695 reg-names = "dsi_ctrl"; 4696 4697 interrupt-parent = <&mdss>; 4698 interrupts = <4>; 4699 4700 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4701 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4702 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4703 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4704 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4705 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4706 clock-names = "byte", 4707 "byte_intf", 4708 "pixel", 4709 "core", 4710 "iface", 4711 "bus"; 4712 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 4713 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4714 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 4715 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 4716 4717 operating-points-v2 = <&dsi_opp_table>; 4718 power-domains = <&rpmhpd SDM845_CX>; 4719 4720 phys = <&mdss_dsi0_phy>; 4721 4722 status = "disabled"; 4723 4724 #address-cells = <1>; 4725 #size-cells = <0>; 4726 4727 ports { 4728 #address-cells = <1>; 4729 #size-cells = <0>; 4730 4731 port@0 { 4732 reg = <0>; 4733 mdss_dsi0_in: endpoint { 4734 remote-endpoint = <&dpu_intf1_out>; 4735 }; 4736 }; 4737 4738 port@1 { 4739 reg = <1>; 4740 mdss_dsi0_out: endpoint { 4741 }; 4742 }; 4743 }; 4744 }; 4745 4746 mdss_dsi0_phy: phy@ae94400 { 4747 compatible = "qcom,dsi-phy-10nm"; 4748 reg = <0 0x0ae94400 0 0x200>, 4749 <0 0x0ae94600 0 0x280>, 4750 <0 0x0ae94a00 0 0x1e0>; 4751 reg-names = "dsi_phy", 4752 "dsi_phy_lane", 4753 "dsi_pll"; 4754 4755 #clock-cells = <1>; 4756 #phy-cells = <0>; 4757 4758 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4759 <&rpmhcc RPMH_CXO_CLK>; 4760 clock-names = "iface", "ref"; 4761 4762 status = "disabled"; 4763 }; 4764 4765 mdss_dsi1: dsi@ae96000 { 4766 compatible = "qcom,sdm845-dsi-ctrl", 4767 "qcom,mdss-dsi-ctrl"; 4768 reg = <0 0x0ae96000 0 0x400>; 4769 reg-names = "dsi_ctrl"; 4770 4771 interrupt-parent = <&mdss>; 4772 interrupts = <5>; 4773 4774 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4775 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4776 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4777 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4778 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4779 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4780 clock-names = "byte", 4781 "byte_intf", 4782 "pixel", 4783 "core", 4784 "iface", 4785 "bus"; 4786 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 4787 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4788 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 4789 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 4790 4791 operating-points-v2 = <&dsi_opp_table>; 4792 power-domains = <&rpmhpd SDM845_CX>; 4793 4794 phys = <&mdss_dsi1_phy>; 4795 4796 status = "disabled"; 4797 4798 #address-cells = <1>; 4799 #size-cells = <0>; 4800 4801 ports { 4802 #address-cells = <1>; 4803 #size-cells = <0>; 4804 4805 port@0 { 4806 reg = <0>; 4807 mdss_dsi1_in: endpoint { 4808 remote-endpoint = <&dpu_intf2_out>; 4809 }; 4810 }; 4811 4812 port@1 { 4813 reg = <1>; 4814 mdss_dsi1_out: endpoint { 4815 }; 4816 }; 4817 }; 4818 }; 4819 4820 mdss_dsi1_phy: phy@ae96400 { 4821 compatible = "qcom,dsi-phy-10nm"; 4822 reg = <0 0x0ae96400 0 0x200>, 4823 <0 0x0ae96600 0 0x280>, 4824 <0 0x0ae96a00 0 0x10e>; 4825 reg-names = "dsi_phy", 4826 "dsi_phy_lane", 4827 "dsi_pll"; 4828 4829 #clock-cells = <1>; 4830 #phy-cells = <0>; 4831 4832 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4833 <&rpmhcc RPMH_CXO_CLK>; 4834 clock-names = "iface", "ref"; 4835 4836 status = "disabled"; 4837 }; 4838 }; 4839 4840 gpu: gpu@5000000 { 4841 compatible = "qcom,adreno-630.2", "qcom,adreno"; 4842 4843 reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>; 4844 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 4845 4846 /* 4847 * Look ma, no clocks! The GPU clocks and power are 4848 * controlled entirely by the GMU 4849 */ 4850 4851 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4852 4853 iommus = <&adreno_smmu 0>; 4854 4855 operating-points-v2 = <&gpu_opp_table>; 4856 4857 qcom,gmu = <&gmu>; 4858 #cooling-cells = <2>; 4859 4860 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; 4861 interconnect-names = "gfx-mem"; 4862 4863 status = "disabled"; 4864 4865 gpu_opp_table: opp-table { 4866 compatible = "operating-points-v2"; 4867 4868 opp-710000000 { 4869 opp-hz = /bits/ 64 <710000000>; 4870 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4871 opp-peak-kBps = <7216000>; 4872 }; 4873 4874 opp-675000000 { 4875 opp-hz = /bits/ 64 <675000000>; 4876 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4877 opp-peak-kBps = <7216000>; 4878 }; 4879 4880 opp-596000000 { 4881 opp-hz = /bits/ 64 <596000000>; 4882 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4883 opp-peak-kBps = <6220000>; 4884 }; 4885 4886 opp-520000000 { 4887 opp-hz = /bits/ 64 <520000000>; 4888 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4889 opp-peak-kBps = <6220000>; 4890 }; 4891 4892 opp-414000000 { 4893 opp-hz = /bits/ 64 <414000000>; 4894 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4895 opp-peak-kBps = <4068000>; 4896 }; 4897 4898 opp-342000000 { 4899 opp-hz = /bits/ 64 <342000000>; 4900 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4901 opp-peak-kBps = <2724000>; 4902 }; 4903 4904 opp-257000000 { 4905 opp-hz = /bits/ 64 <257000000>; 4906 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4907 opp-peak-kBps = <1648000>; 4908 }; 4909 }; 4910 }; 4911 4912 adreno_smmu: iommu@5040000 { 4913 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 4914 reg = <0 0x05040000 0 0x10000>; 4915 #iommu-cells = <1>; 4916 #global-interrupts = <2>; 4917 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 4918 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 4919 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 4920 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 4921 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 4922 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 4923 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 4924 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 4925 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 4926 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 4927 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4928 <&gcc GCC_GPU_CFG_AHB_CLK>; 4929 clock-names = "bus", "iface"; 4930 4931 power-domains = <&gpucc GPU_CX_GDSC>; 4932 }; 4933 4934 gmu: gmu@506a000 { 4935 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 4936 4937 reg = <0 0x0506a000 0 0x30000>, 4938 <0 0x0b280000 0 0x10000>, 4939 <0 0x0b480000 0 0x10000>; 4940 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 4941 4942 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4943 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4944 interrupt-names = "hfi", "gmu"; 4945 4946 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 4947 <&gpucc GPU_CC_CXO_CLK>, 4948 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4949 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 4950 clock-names = "gmu", "cxo", "axi", "memnoc"; 4951 4952 power-domains = <&gpucc GPU_CX_GDSC>, 4953 <&gpucc GPU_GX_GDSC>; 4954 power-domain-names = "cx", "gx"; 4955 4956 iommus = <&adreno_smmu 5>; 4957 4958 operating-points-v2 = <&gmu_opp_table>; 4959 4960 gmu_opp_table: opp-table { 4961 compatible = "operating-points-v2"; 4962 4963 opp-400000000 { 4964 opp-hz = /bits/ 64 <400000000>; 4965 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4966 }; 4967 4968 opp-200000000 { 4969 opp-hz = /bits/ 64 <200000000>; 4970 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4971 }; 4972 }; 4973 }; 4974 4975 dispcc: clock-controller@af00000 { 4976 compatible = "qcom,sdm845-dispcc"; 4977 reg = <0 0x0af00000 0 0x10000>; 4978 clocks = <&rpmhcc RPMH_CXO_CLK>, 4979 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 4980 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 4981 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 4982 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 4983 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 4984 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 4985 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4986 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4987 clock-names = "bi_tcxo", 4988 "gcc_disp_gpll0_clk_src", 4989 "gcc_disp_gpll0_div_clk_src", 4990 "dsi0_phy_pll_out_byteclk", 4991 "dsi0_phy_pll_out_dsiclk", 4992 "dsi1_phy_pll_out_byteclk", 4993 "dsi1_phy_pll_out_dsiclk", 4994 "dp_link_clk_divsel_ten", 4995 "dp_vco_divided_clk_src_mux"; 4996 #clock-cells = <1>; 4997 #reset-cells = <1>; 4998 #power-domain-cells = <1>; 4999 }; 5000 5001 pdc_intc: interrupt-controller@b220000 { 5002 compatible = "qcom,sdm845-pdc", "qcom,pdc"; 5003 reg = <0 0x0b220000 0 0x30000>; 5004 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; 5005 #interrupt-cells = <2>; 5006 interrupt-parent = <&intc>; 5007 interrupt-controller; 5008 }; 5009 5010 pdc_reset: reset-controller@b2e0000 { 5011 compatible = "qcom,sdm845-pdc-global"; 5012 reg = <0 0x0b2e0000 0 0x20000>; 5013 #reset-cells = <1>; 5014 }; 5015 5016 tsens0: thermal-sensor@c263000 { 5017 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 5018 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 5019 <0 0x0c222000 0 0x1ff>; /* SROT */ 5020 #qcom,sensors = <13>; 5021 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 5022 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 5023 interrupt-names = "uplow", "critical"; 5024 #thermal-sensor-cells = <1>; 5025 }; 5026 5027 tsens1: thermal-sensor@c265000 { 5028 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 5029 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 5030 <0 0x0c223000 0 0x1ff>; /* SROT */ 5031 #qcom,sensors = <8>; 5032 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 5033 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 5034 interrupt-names = "uplow", "critical"; 5035 #thermal-sensor-cells = <1>; 5036 }; 5037 5038 aoss_reset: reset-controller@c2a0000 { 5039 compatible = "qcom,sdm845-aoss-cc"; 5040 reg = <0 0x0c2a0000 0 0x31000>; 5041 #reset-cells = <1>; 5042 }; 5043 5044 aoss_qmp: power-management@c300000 { 5045 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; 5046 reg = <0 0x0c300000 0 0x400>; 5047 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 5048 mboxes = <&apss_shared 0>; 5049 5050 #clock-cells = <0>; 5051 5052 cx_cdev: cx { 5053 #cooling-cells = <2>; 5054 }; 5055 5056 ebi_cdev: ebi { 5057 #cooling-cells = <2>; 5058 }; 5059 }; 5060 5061 sram@c3f0000 { 5062 compatible = "qcom,sdm845-rpmh-stats"; 5063 reg = <0 0x0c3f0000 0 0x400>; 5064 }; 5065 5066 spmi_bus: spmi@c440000 { 5067 compatible = "qcom,spmi-pmic-arb"; 5068 reg = <0 0x0c440000 0 0x1100>, 5069 <0 0x0c600000 0 0x2000000>, 5070 <0 0x0e600000 0 0x100000>, 5071 <0 0x0e700000 0 0xa0000>, 5072 <0 0x0c40a000 0 0x26000>; 5073 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 5074 interrupt-names = "periph_irq"; 5075 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 5076 qcom,ee = <0>; 5077 qcom,channel = <0>; 5078 #address-cells = <2>; 5079 #size-cells = <0>; 5080 interrupt-controller; 5081 #interrupt-cells = <4>; 5082 }; 5083 5084 sram@146bf000 { 5085 compatible = "qcom,sdm845-imem", "syscon", "simple-mfd"; 5086 reg = <0 0x146bf000 0 0x1000>; 5087 5088 #address-cells = <1>; 5089 #size-cells = <1>; 5090 5091 ranges = <0 0 0x146bf000 0x1000>; 5092 5093 pil-reloc@94c { 5094 compatible = "qcom,pil-reloc-info"; 5095 reg = <0x94c 0xc8>; 5096 }; 5097 }; 5098 5099 apps_smmu: iommu@15000000 { 5100 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; 5101 reg = <0 0x15000000 0 0x80000>; 5102 #iommu-cells = <2>; 5103 #global-interrupts = <1>; 5104 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5167 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5168 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 5169 }; 5170 5171 anoc_1_tbu: tbu@150c5000 { 5172 compatible = "qcom,sdm845-tbu"; 5173 reg = <0x0 0x150c5000 0x0 0x1000>; 5174 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY 5175 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5176 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC>; 5177 qcom,stream-id-range = <&apps_smmu 0x0 0x400>; 5178 }; 5179 5180 anoc_2_tbu: tbu@150c9000 { 5181 compatible = "qcom,sdm845-tbu"; 5182 reg = <0x0 0x150c9000 0x0 0x1000>; 5183 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY 5184 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5185 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC>; 5186 qcom,stream-id-range = <&apps_smmu 0x400 0x400>; 5187 }; 5188 5189 mnoc_hf_0_tbu: tbu@150cd000 { 5190 compatible = "qcom,sdm845-tbu"; 5191 reg = <0x0 0x150cd000 0x0 0x1000>; 5192 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY 5193 &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; 5194 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>; 5195 qcom,stream-id-range = <&apps_smmu 0x800 0x400>; 5196 }; 5197 5198 mnoc_hf_1_tbu: tbu@150d1000 { 5199 compatible = "qcom,sdm845-tbu"; 5200 reg = <0x0 0x150d1000 0x0 0x1000>; 5201 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY 5202 &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; 5203 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>; 5204 qcom,stream-id-range = <&apps_smmu 0xc00 0x400>; 5205 }; 5206 5207 mnoc_sf_0_tbu: tbu@150d5000 { 5208 compatible = "qcom,sdm845-tbu"; 5209 reg = <0x0 0x150d5000 0x0 0x1000>; 5210 interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY 5211 &mmss_noc SLAVE_MNOC_SF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; 5212 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC>; 5213 qcom,stream-id-range = <&apps_smmu 0x1000 0x400>; 5214 }; 5215 5216 compute_dsp_tbu: tbu@150d9000 { 5217 compatible = "qcom,sdm845-tbu"; 5218 reg = <0x0 0x150d9000 0x0 0x1000>; 5219 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY 5220 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5221 qcom,stream-id-range = <&apps_smmu 0x1400 0x400>; 5222 }; 5223 5224 adsp_tbu: tbu@150dd000 { 5225 compatible = "qcom,sdm845-tbu"; 5226 reg = <0x0 0x150dd000 0x0 0x1000>; 5227 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY 5228 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5229 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC>; 5230 qcom,stream-id-range = <&apps_smmu 0x1800 0x400>; 5231 }; 5232 5233 anoc_1_pcie_tbu: tbu@150e1000 { 5234 compatible = "qcom,sdm845-tbu"; 5235 reg = <0x0 0x150e1000 0x0 0x1000>; 5236 clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 5237 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY 5238 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5239 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>; 5240 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>; 5241 }; 5242 5243 lpasscc: clock-controller@17014000 { 5244 compatible = "qcom,sdm845-lpasscc"; 5245 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; 5246 reg-names = "cc", "qdsp6ss"; 5247 #clock-cells = <1>; 5248 status = "disabled"; 5249 }; 5250 5251 gladiator_noc: interconnect@17900000 { 5252 compatible = "qcom,sdm845-gladiator-noc"; 5253 reg = <0 0x17900000 0 0xd080>; 5254 #interconnect-cells = <2>; 5255 qcom,bcm-voters = <&apps_bcm_voter>; 5256 }; 5257 5258 watchdog@17980000 { 5259 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; 5260 reg = <0 0x17980000 0 0x1000>; 5261 clocks = <&sleep_clk>; 5262 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5263 }; 5264 5265 apss_shared: mailbox@17990000 { 5266 compatible = "qcom,sdm845-apss-shared"; 5267 reg = <0 0x17990000 0 0x1000>; 5268 #mbox-cells = <1>; 5269 }; 5270 5271 apps_rsc: rsc@179c0000 { 5272 compatible = "qcom,sdm845-rpmh-apps-rsc", "qcom,rpmh-rsc"; 5273 label = "apps_rsc"; 5274 reg = <0 0x179c0000 0 0x10000>, 5275 <0 0x179d0000 0 0x10000>, 5276 <0 0x179e0000 0 0x10000>; 5277 reg-names = "drv-0", "drv-1", "drv-2"; 5278 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5279 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5280 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5281 qcom,tcs-offset = <0xd00>; 5282 qcom,drv-id = <2>; 5283 qcom,tcs-config = <ACTIVE_TCS 2>, 5284 <SLEEP_TCS 3>, 5285 <WAKE_TCS 3>, 5286 <CONTROL_TCS 1>; 5287 power-domains = <&cluster_pd>; 5288 5289 apps_bcm_voter: bcm-voter { 5290 compatible = "qcom,bcm-voter"; 5291 }; 5292 5293 rpmhcc: clock-controller { 5294 compatible = "qcom,sdm845-rpmh-clk"; 5295 #clock-cells = <1>; 5296 clock-names = "xo"; 5297 clocks = <&xo_board>; 5298 }; 5299 5300 rpmhpd: power-controller { 5301 compatible = "qcom,sdm845-rpmhpd"; 5302 #power-domain-cells = <1>; 5303 operating-points-v2 = <&rpmhpd_opp_table>; 5304 5305 rpmhpd_opp_table: opp-table { 5306 compatible = "operating-points-v2"; 5307 5308 rpmhpd_opp_ret: opp1 { 5309 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5310 }; 5311 5312 rpmhpd_opp_min_svs: opp2 { 5313 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5314 }; 5315 5316 rpmhpd_opp_low_svs: opp3 { 5317 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5318 }; 5319 5320 rpmhpd_opp_svs: opp4 { 5321 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5322 }; 5323 5324 rpmhpd_opp_svs_l1: opp5 { 5325 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5326 }; 5327 5328 rpmhpd_opp_nom: opp6 { 5329 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5330 }; 5331 5332 rpmhpd_opp_nom_l1: opp7 { 5333 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5334 }; 5335 5336 rpmhpd_opp_nom_l2: opp8 { 5337 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5338 }; 5339 5340 rpmhpd_opp_turbo: opp9 { 5341 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5342 }; 5343 5344 rpmhpd_opp_turbo_l1: opp10 { 5345 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5346 }; 5347 }; 5348 }; 5349 }; 5350 5351 intc: interrupt-controller@17a00000 { 5352 compatible = "arm,gic-v3"; 5353 #address-cells = <2>; 5354 #size-cells = <2>; 5355 ranges; 5356 #interrupt-cells = <3>; 5357 interrupt-controller; 5358 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5359 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5360 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5361 5362 msi-controller@17a40000 { 5363 compatible = "arm,gic-v3-its"; 5364 msi-controller; 5365 #msi-cells = <1>; 5366 reg = <0 0x17a40000 0 0x20000>; 5367 status = "disabled"; 5368 }; 5369 }; 5370 5371 slimbam: dma-controller@17184000 { 5372 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 5373 qcom,controlled-remotely; 5374 reg = <0 0x17184000 0 0x2a000>; 5375 num-channels = <31>; 5376 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 5377 #dma-cells = <1>; 5378 qcom,ee = <1>; 5379 qcom,num-ees = <2>; 5380 iommus = <&apps_smmu 0x1806 0x0>; 5381 }; 5382 5383 timer@17c90000 { 5384 #address-cells = <1>; 5385 #size-cells = <1>; 5386 ranges = <0 0 0 0x20000000>; 5387 compatible = "arm,armv7-timer-mem"; 5388 reg = <0 0x17c90000 0 0x1000>; 5389 5390 frame@17ca0000 { 5391 frame-number = <0>; 5392 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 5393 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5394 reg = <0x17ca0000 0x1000>, 5395 <0x17cb0000 0x1000>; 5396 }; 5397 5398 frame@17cc0000 { 5399 frame-number = <1>; 5400 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 5401 reg = <0x17cc0000 0x1000>; 5402 status = "disabled"; 5403 }; 5404 5405 frame@17cd0000 { 5406 frame-number = <2>; 5407 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5408 reg = <0x17cd0000 0x1000>; 5409 status = "disabled"; 5410 }; 5411 5412 frame@17ce0000 { 5413 frame-number = <3>; 5414 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5415 reg = <0x17ce0000 0x1000>; 5416 status = "disabled"; 5417 }; 5418 5419 frame@17cf0000 { 5420 frame-number = <4>; 5421 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5422 reg = <0x17cf0000 0x1000>; 5423 status = "disabled"; 5424 }; 5425 5426 frame@17d00000 { 5427 frame-number = <5>; 5428 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5429 reg = <0x17d00000 0x1000>; 5430 status = "disabled"; 5431 }; 5432 5433 frame@17d10000 { 5434 frame-number = <6>; 5435 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5436 reg = <0x17d10000 0x1000>; 5437 status = "disabled"; 5438 }; 5439 }; 5440 5441 osm_l3: interconnect@17d41000 { 5442 compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3"; 5443 reg = <0 0x17d41000 0 0x1400>; 5444 5445 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5446 clock-names = "xo", "alternate"; 5447 5448 #interconnect-cells = <1>; 5449 }; 5450 5451 cpufreq_hw: cpufreq@17d43000 { 5452 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw"; 5453 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 5454 reg-names = "freq-domain0", "freq-domain1"; 5455 5456 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>; 5457 5458 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5459 clock-names = "xo", "alternate"; 5460 5461 #freq-domain-cells = <1>; 5462 #clock-cells = <1>; 5463 }; 5464 5465 wifi: wifi@18800000 { 5466 compatible = "qcom,wcn3990-wifi"; 5467 status = "disabled"; 5468 reg = <0 0x18800000 0 0x800000>; 5469 reg-names = "membase"; 5470 memory-region = <&wlan_msa_mem>; 5471 clock-names = "cxo_ref_clk_pin"; 5472 clocks = <&rpmhcc RPMH_RF_CLK2>; 5473 interrupts = 5474 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 5475 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 5476 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 5477 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 5478 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5479 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5480 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 5481 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5482 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 5483 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5484 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5485 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 5486 iommus = <&apps_smmu 0x0040 0x1>; 5487 }; 5488 }; 5489 5490 sound: sound { 5491 }; 5492 5493 thermal-zones { 5494 cpu0-thermal { 5495 polling-delay-passive = <250>; 5496 5497 thermal-sensors = <&tsens0 1>; 5498 5499 trips { 5500 cpu0_alert0: trip-point0 { 5501 temperature = <90000>; 5502 hysteresis = <2000>; 5503 type = "passive"; 5504 }; 5505 5506 cpu0_alert1: trip-point1 { 5507 temperature = <95000>; 5508 hysteresis = <2000>; 5509 type = "passive"; 5510 }; 5511 5512 cpu0_crit: cpu-crit { 5513 temperature = <110000>; 5514 hysteresis = <1000>; 5515 type = "critical"; 5516 }; 5517 }; 5518 }; 5519 5520 cpu1-thermal { 5521 polling-delay-passive = <250>; 5522 5523 thermal-sensors = <&tsens0 2>; 5524 5525 trips { 5526 cpu1_alert0: trip-point0 { 5527 temperature = <90000>; 5528 hysteresis = <2000>; 5529 type = "passive"; 5530 }; 5531 5532 cpu1_alert1: trip-point1 { 5533 temperature = <95000>; 5534 hysteresis = <2000>; 5535 type = "passive"; 5536 }; 5537 5538 cpu1_crit: cpu-crit { 5539 temperature = <110000>; 5540 hysteresis = <1000>; 5541 type = "critical"; 5542 }; 5543 }; 5544 }; 5545 5546 cpu2-thermal { 5547 polling-delay-passive = <250>; 5548 5549 thermal-sensors = <&tsens0 3>; 5550 5551 trips { 5552 cpu2_alert0: trip-point0 { 5553 temperature = <90000>; 5554 hysteresis = <2000>; 5555 type = "passive"; 5556 }; 5557 5558 cpu2_alert1: trip-point1 { 5559 temperature = <95000>; 5560 hysteresis = <2000>; 5561 type = "passive"; 5562 }; 5563 5564 cpu2_crit: cpu-crit { 5565 temperature = <110000>; 5566 hysteresis = <1000>; 5567 type = "critical"; 5568 }; 5569 }; 5570 }; 5571 5572 cpu3-thermal { 5573 polling-delay-passive = <250>; 5574 5575 thermal-sensors = <&tsens0 4>; 5576 5577 trips { 5578 cpu3_alert0: trip-point0 { 5579 temperature = <90000>; 5580 hysteresis = <2000>; 5581 type = "passive"; 5582 }; 5583 5584 cpu3_alert1: trip-point1 { 5585 temperature = <95000>; 5586 hysteresis = <2000>; 5587 type = "passive"; 5588 }; 5589 5590 cpu3_crit: cpu-crit { 5591 temperature = <110000>; 5592 hysteresis = <1000>; 5593 type = "critical"; 5594 }; 5595 }; 5596 }; 5597 5598 cpu4-thermal { 5599 polling-delay-passive = <250>; 5600 5601 thermal-sensors = <&tsens0 7>; 5602 5603 trips { 5604 cpu4_alert0: trip-point0 { 5605 temperature = <90000>; 5606 hysteresis = <2000>; 5607 type = "passive"; 5608 }; 5609 5610 cpu4_alert1: trip-point1 { 5611 temperature = <95000>; 5612 hysteresis = <2000>; 5613 type = "passive"; 5614 }; 5615 5616 cpu4_crit: cpu-crit { 5617 temperature = <110000>; 5618 hysteresis = <1000>; 5619 type = "critical"; 5620 }; 5621 }; 5622 }; 5623 5624 cpu5-thermal { 5625 polling-delay-passive = <250>; 5626 5627 thermal-sensors = <&tsens0 8>; 5628 5629 trips { 5630 cpu5_alert0: trip-point0 { 5631 temperature = <90000>; 5632 hysteresis = <2000>; 5633 type = "passive"; 5634 }; 5635 5636 cpu5_alert1: trip-point1 { 5637 temperature = <95000>; 5638 hysteresis = <2000>; 5639 type = "passive"; 5640 }; 5641 5642 cpu5_crit: cpu-crit { 5643 temperature = <110000>; 5644 hysteresis = <1000>; 5645 type = "critical"; 5646 }; 5647 }; 5648 }; 5649 5650 cpu6-thermal { 5651 polling-delay-passive = <250>; 5652 5653 thermal-sensors = <&tsens0 9>; 5654 5655 trips { 5656 cpu6_alert0: trip-point0 { 5657 temperature = <90000>; 5658 hysteresis = <2000>; 5659 type = "passive"; 5660 }; 5661 5662 cpu6_alert1: trip-point1 { 5663 temperature = <95000>; 5664 hysteresis = <2000>; 5665 type = "passive"; 5666 }; 5667 5668 cpu6_crit: cpu-crit { 5669 temperature = <110000>; 5670 hysteresis = <1000>; 5671 type = "critical"; 5672 }; 5673 }; 5674 }; 5675 5676 cpu7-thermal { 5677 polling-delay-passive = <250>; 5678 5679 thermal-sensors = <&tsens0 10>; 5680 5681 trips { 5682 cpu7_alert0: trip-point0 { 5683 temperature = <90000>; 5684 hysteresis = <2000>; 5685 type = "passive"; 5686 }; 5687 5688 cpu7_alert1: trip-point1 { 5689 temperature = <95000>; 5690 hysteresis = <2000>; 5691 type = "passive"; 5692 }; 5693 5694 cpu7_crit: cpu-crit { 5695 temperature = <110000>; 5696 hysteresis = <1000>; 5697 type = "critical"; 5698 }; 5699 }; 5700 }; 5701 5702 aoss0-thermal { 5703 polling-delay-passive = <250>; 5704 5705 thermal-sensors = <&tsens0 0>; 5706 5707 trips { 5708 aoss0_alert0: trip-point0 { 5709 temperature = <90000>; 5710 hysteresis = <2000>; 5711 type = "hot"; 5712 }; 5713 }; 5714 }; 5715 5716 cluster0-thermal { 5717 polling-delay-passive = <250>; 5718 5719 thermal-sensors = <&tsens0 5>; 5720 5721 trips { 5722 cluster0_alert0: trip-point0 { 5723 temperature = <90000>; 5724 hysteresis = <2000>; 5725 type = "hot"; 5726 }; 5727 cluster0_crit: cluster0-crit { 5728 temperature = <110000>; 5729 hysteresis = <2000>; 5730 type = "critical"; 5731 }; 5732 }; 5733 }; 5734 5735 cluster1-thermal { 5736 polling-delay-passive = <250>; 5737 5738 thermal-sensors = <&tsens0 6>; 5739 5740 trips { 5741 cluster1_alert0: trip-point0 { 5742 temperature = <90000>; 5743 hysteresis = <2000>; 5744 type = "hot"; 5745 }; 5746 cluster1_crit: cluster1-crit { 5747 temperature = <110000>; 5748 hysteresis = <2000>; 5749 type = "critical"; 5750 }; 5751 }; 5752 }; 5753 5754 gpu-top-thermal { 5755 polling-delay-passive = <250>; 5756 5757 thermal-sensors = <&tsens0 11>; 5758 5759 cooling-maps { 5760 map0 { 5761 trip = <&gpu_top_alert0>; 5762 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5763 }; 5764 }; 5765 5766 trips { 5767 gpu_top_alert0: trip-point0 { 5768 temperature = <85000>; 5769 hysteresis = <1000>; 5770 type = "passive"; 5771 }; 5772 5773 trip-point1 { 5774 temperature = <90000>; 5775 hysteresis = <1000>; 5776 type = "hot"; 5777 }; 5778 5779 trip-point2 { 5780 temperature = <110000>; 5781 hysteresis = <1000>; 5782 type = "critical"; 5783 }; 5784 }; 5785 }; 5786 5787 gpu-bottom-thermal { 5788 polling-delay-passive = <250>; 5789 5790 thermal-sensors = <&tsens0 12>; 5791 5792 cooling-maps { 5793 map0 { 5794 trip = <&gpu_bottom_alert0>; 5795 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5796 }; 5797 }; 5798 5799 trips { 5800 gpu_bottom_alert0: trip-point0 { 5801 temperature = <85000>; 5802 hysteresis = <1000>; 5803 type = "passive"; 5804 }; 5805 5806 trip-point1 { 5807 temperature = <90000>; 5808 hysteresis = <1000>; 5809 type = "hot"; 5810 }; 5811 5812 trip-point2 { 5813 temperature = <110000>; 5814 hysteresis = <1000>; 5815 type = "critical"; 5816 }; 5817 }; 5818 }; 5819 5820 aoss1-thermal { 5821 polling-delay-passive = <250>; 5822 5823 thermal-sensors = <&tsens1 0>; 5824 5825 trips { 5826 aoss1_alert0: trip-point0 { 5827 temperature = <90000>; 5828 hysteresis = <2000>; 5829 type = "hot"; 5830 }; 5831 }; 5832 }; 5833 5834 q6-modem-thermal { 5835 polling-delay-passive = <250>; 5836 5837 thermal-sensors = <&tsens1 1>; 5838 5839 trips { 5840 q6_modem_alert0: trip-point0 { 5841 temperature = <90000>; 5842 hysteresis = <2000>; 5843 type = "hot"; 5844 }; 5845 }; 5846 }; 5847 5848 mem-thermal { 5849 polling-delay-passive = <250>; 5850 5851 thermal-sensors = <&tsens1 2>; 5852 5853 trips { 5854 mem_alert0: trip-point0 { 5855 temperature = <90000>; 5856 hysteresis = <2000>; 5857 type = "hot"; 5858 }; 5859 }; 5860 }; 5861 5862 wlan-thermal { 5863 polling-delay-passive = <250>; 5864 5865 thermal-sensors = <&tsens1 3>; 5866 5867 trips { 5868 wlan_alert0: trip-point0 { 5869 temperature = <90000>; 5870 hysteresis = <2000>; 5871 type = "hot"; 5872 }; 5873 }; 5874 }; 5875 5876 q6-hvx-thermal { 5877 polling-delay-passive = <250>; 5878 5879 thermal-sensors = <&tsens1 4>; 5880 5881 trips { 5882 q6_hvx_alert0: trip-point0 { 5883 temperature = <90000>; 5884 hysteresis = <2000>; 5885 type = "hot"; 5886 }; 5887 }; 5888 }; 5889 5890 camera-thermal { 5891 polling-delay-passive = <250>; 5892 5893 thermal-sensors = <&tsens1 5>; 5894 5895 trips { 5896 camera_alert0: trip-point0 { 5897 temperature = <90000>; 5898 hysteresis = <2000>; 5899 type = "hot"; 5900 }; 5901 }; 5902 }; 5903 5904 video-thermal { 5905 polling-delay-passive = <250>; 5906 5907 thermal-sensors = <&tsens1 6>; 5908 5909 trips { 5910 video_alert0: trip-point0 { 5911 temperature = <90000>; 5912 hysteresis = <2000>; 5913 type = "hot"; 5914 }; 5915 }; 5916 }; 5917 5918 modem-thermal { 5919 polling-delay-passive = <250>; 5920 5921 thermal-sensors = <&tsens1 7>; 5922 5923 trips { 5924 modem_alert0: trip-point0 { 5925 temperature = <90000>; 5926 hysteresis = <2000>; 5927 type = "hot"; 5928 }; 5929 }; 5930 }; 5931 }; 5932 5933 timer { 5934 compatible = "arm,armv8-timer"; 5935 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 5936 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 5937 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 5938 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 5939 }; 5940}; 5941