1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,camcc-sdm845.h> 9#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 10#include <dt-bindings/clock/qcom,gcc-sdm845.h> 11#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 12#include <dt-bindings/clock/qcom,lpass-sdm845.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sdm845.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/firmware/qcom,scm.h> 17#include <dt-bindings/gpio/gpio.h> 18#include <dt-bindings/interconnect/qcom,osm-l3.h> 19#include <dt-bindings/interconnect/qcom,sdm845.h> 20#include <dt-bindings/interrupt-controller/arm-gic.h> 21#include <dt-bindings/phy/phy-qcom-qusb2.h> 22#include <dt-bindings/power/qcom-rpmpd.h> 23#include <dt-bindings/reset/qcom,sdm845-aoss.h> 24#include <dt-bindings/reset/qcom,sdm845-pdc.h> 25#include <dt-bindings/soc/qcom,apr.h> 26#include <dt-bindings/soc/qcom,rpmh-rsc.h> 27#include <dt-bindings/clock/qcom,gcc-sdm845.h> 28#include <dt-bindings/thermal/thermal.h> 29 30/ { 31 interrupt-parent = <&intc>; 32 33 #address-cells = <2>; 34 #size-cells = <2>; 35 36 aliases { 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 i2c6 = &i2c6; 44 i2c7 = &i2c7; 45 i2c8 = &i2c8; 46 i2c9 = &i2c9; 47 i2c10 = &i2c10; 48 i2c11 = &i2c11; 49 i2c12 = &i2c12; 50 i2c13 = &i2c13; 51 i2c14 = &i2c14; 52 i2c15 = &i2c15; 53 spi0 = &spi0; 54 spi1 = &spi1; 55 spi2 = &spi2; 56 spi3 = &spi3; 57 spi4 = &spi4; 58 spi5 = &spi5; 59 spi6 = &spi6; 60 spi7 = &spi7; 61 spi8 = &spi8; 62 spi9 = &spi9; 63 spi10 = &spi10; 64 spi11 = &spi11; 65 spi12 = &spi12; 66 spi13 = &spi13; 67 spi14 = &spi14; 68 spi15 = &spi15; 69 }; 70 71 chosen { }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 #clock-cells = <0>; 77 clock-frequency = <38400000>; 78 clock-output-names = "xo_board"; 79 }; 80 81 sleep_clk: sleep-clk { 82 compatible = "fixed-clock"; 83 #clock-cells = <0>; 84 clock-frequency = <32764>; 85 }; 86 }; 87 88 cpus: cpus { 89 #address-cells = <2>; 90 #size-cells = <0>; 91 92 CPU0: cpu@0 { 93 device_type = "cpu"; 94 compatible = "qcom,kryo385"; 95 reg = <0x0 0x0>; 96 clocks = <&cpufreq_hw 0>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <611>; 99 dynamic-power-coefficient = <154>; 100 qcom,freq-domain = <&cpufreq_hw 0>; 101 operating-points-v2 = <&cpu0_opp_table>; 102 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 103 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 104 power-domains = <&CPU_PD0>; 105 power-domain-names = "psci"; 106 #cooling-cells = <2>; 107 next-level-cache = <&L2_0>; 108 L2_0: l2-cache { 109 compatible = "cache"; 110 cache-level = <2>; 111 cache-unified; 112 next-level-cache = <&L3_0>; 113 L3_0: l3-cache { 114 compatible = "cache"; 115 cache-level = <3>; 116 cache-unified; 117 }; 118 }; 119 }; 120 121 CPU1: cpu@100 { 122 device_type = "cpu"; 123 compatible = "qcom,kryo385"; 124 reg = <0x0 0x100>; 125 clocks = <&cpufreq_hw 0>; 126 enable-method = "psci"; 127 capacity-dmips-mhz = <611>; 128 dynamic-power-coefficient = <154>; 129 qcom,freq-domain = <&cpufreq_hw 0>; 130 operating-points-v2 = <&cpu0_opp_table>; 131 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 132 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 133 power-domains = <&CPU_PD1>; 134 power-domain-names = "psci"; 135 #cooling-cells = <2>; 136 next-level-cache = <&L2_100>; 137 L2_100: l2-cache { 138 compatible = "cache"; 139 cache-level = <2>; 140 cache-unified; 141 next-level-cache = <&L3_0>; 142 }; 143 }; 144 145 CPU2: cpu@200 { 146 device_type = "cpu"; 147 compatible = "qcom,kryo385"; 148 reg = <0x0 0x200>; 149 clocks = <&cpufreq_hw 0>; 150 enable-method = "psci"; 151 capacity-dmips-mhz = <611>; 152 dynamic-power-coefficient = <154>; 153 qcom,freq-domain = <&cpufreq_hw 0>; 154 operating-points-v2 = <&cpu0_opp_table>; 155 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 156 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 157 power-domains = <&CPU_PD2>; 158 power-domain-names = "psci"; 159 #cooling-cells = <2>; 160 next-level-cache = <&L2_200>; 161 L2_200: l2-cache { 162 compatible = "cache"; 163 cache-level = <2>; 164 cache-unified; 165 next-level-cache = <&L3_0>; 166 }; 167 }; 168 169 CPU3: cpu@300 { 170 device_type = "cpu"; 171 compatible = "qcom,kryo385"; 172 reg = <0x0 0x300>; 173 clocks = <&cpufreq_hw 0>; 174 enable-method = "psci"; 175 capacity-dmips-mhz = <611>; 176 dynamic-power-coefficient = <154>; 177 qcom,freq-domain = <&cpufreq_hw 0>; 178 operating-points-v2 = <&cpu0_opp_table>; 179 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 180 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 181 #cooling-cells = <2>; 182 power-domains = <&CPU_PD3>; 183 power-domain-names = "psci"; 184 next-level-cache = <&L2_300>; 185 L2_300: l2-cache { 186 compatible = "cache"; 187 cache-level = <2>; 188 cache-unified; 189 next-level-cache = <&L3_0>; 190 }; 191 }; 192 193 CPU4: cpu@400 { 194 device_type = "cpu"; 195 compatible = "qcom,kryo385"; 196 reg = <0x0 0x400>; 197 clocks = <&cpufreq_hw 1>; 198 enable-method = "psci"; 199 capacity-dmips-mhz = <1024>; 200 dynamic-power-coefficient = <442>; 201 qcom,freq-domain = <&cpufreq_hw 1>; 202 operating-points-v2 = <&cpu4_opp_table>; 203 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 204 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 205 power-domains = <&CPU_PD4>; 206 power-domain-names = "psci"; 207 #cooling-cells = <2>; 208 next-level-cache = <&L2_400>; 209 L2_400: l2-cache { 210 compatible = "cache"; 211 cache-level = <2>; 212 cache-unified; 213 next-level-cache = <&L3_0>; 214 }; 215 }; 216 217 CPU5: cpu@500 { 218 device_type = "cpu"; 219 compatible = "qcom,kryo385"; 220 reg = <0x0 0x500>; 221 clocks = <&cpufreq_hw 1>; 222 enable-method = "psci"; 223 capacity-dmips-mhz = <1024>; 224 dynamic-power-coefficient = <442>; 225 qcom,freq-domain = <&cpufreq_hw 1>; 226 operating-points-v2 = <&cpu4_opp_table>; 227 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 228 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 229 power-domains = <&CPU_PD5>; 230 power-domain-names = "psci"; 231 #cooling-cells = <2>; 232 next-level-cache = <&L2_500>; 233 L2_500: l2-cache { 234 compatible = "cache"; 235 cache-level = <2>; 236 cache-unified; 237 next-level-cache = <&L3_0>; 238 }; 239 }; 240 241 CPU6: cpu@600 { 242 device_type = "cpu"; 243 compatible = "qcom,kryo385"; 244 reg = <0x0 0x600>; 245 clocks = <&cpufreq_hw 1>; 246 enable-method = "psci"; 247 capacity-dmips-mhz = <1024>; 248 dynamic-power-coefficient = <442>; 249 qcom,freq-domain = <&cpufreq_hw 1>; 250 operating-points-v2 = <&cpu4_opp_table>; 251 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 252 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 253 power-domains = <&CPU_PD6>; 254 power-domain-names = "psci"; 255 #cooling-cells = <2>; 256 next-level-cache = <&L2_600>; 257 L2_600: l2-cache { 258 compatible = "cache"; 259 cache-level = <2>; 260 cache-unified; 261 next-level-cache = <&L3_0>; 262 }; 263 }; 264 265 CPU7: cpu@700 { 266 device_type = "cpu"; 267 compatible = "qcom,kryo385"; 268 reg = <0x0 0x700>; 269 clocks = <&cpufreq_hw 1>; 270 enable-method = "psci"; 271 capacity-dmips-mhz = <1024>; 272 dynamic-power-coefficient = <442>; 273 qcom,freq-domain = <&cpufreq_hw 1>; 274 operating-points-v2 = <&cpu4_opp_table>; 275 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 276 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 277 power-domains = <&CPU_PD7>; 278 power-domain-names = "psci"; 279 #cooling-cells = <2>; 280 next-level-cache = <&L2_700>; 281 L2_700: l2-cache { 282 compatible = "cache"; 283 cache-level = <2>; 284 cache-unified; 285 next-level-cache = <&L3_0>; 286 }; 287 }; 288 289 cpu-map { 290 cluster0 { 291 core0 { 292 cpu = <&CPU0>; 293 }; 294 295 core1 { 296 cpu = <&CPU1>; 297 }; 298 299 core2 { 300 cpu = <&CPU2>; 301 }; 302 303 core3 { 304 cpu = <&CPU3>; 305 }; 306 307 core4 { 308 cpu = <&CPU4>; 309 }; 310 311 core5 { 312 cpu = <&CPU5>; 313 }; 314 315 core6 { 316 cpu = <&CPU6>; 317 }; 318 319 core7 { 320 cpu = <&CPU7>; 321 }; 322 }; 323 }; 324 325 cpu_idle_states: idle-states { 326 entry-method = "psci"; 327 328 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 329 compatible = "arm,idle-state"; 330 idle-state-name = "little-rail-power-collapse"; 331 arm,psci-suspend-param = <0x40000004>; 332 entry-latency-us = <350>; 333 exit-latency-us = <461>; 334 min-residency-us = <1890>; 335 local-timer-stop; 336 }; 337 338 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 339 compatible = "arm,idle-state"; 340 idle-state-name = "big-rail-power-collapse"; 341 arm,psci-suspend-param = <0x40000004>; 342 entry-latency-us = <264>; 343 exit-latency-us = <621>; 344 min-residency-us = <952>; 345 local-timer-stop; 346 }; 347 }; 348 349 domain-idle-states { 350 CLUSTER_SLEEP_0: cluster-sleep-0 { 351 compatible = "domain-idle-state"; 352 arm,psci-suspend-param = <0x4100c244>; 353 entry-latency-us = <3263>; 354 exit-latency-us = <6562>; 355 min-residency-us = <9987>; 356 }; 357 }; 358 }; 359 360 firmware { 361 scm { 362 compatible = "qcom,scm-sdm845", "qcom,scm"; 363 }; 364 }; 365 366 memory@80000000 { 367 device_type = "memory"; 368 /* We expect the bootloader to fill in the size */ 369 reg = <0 0x80000000 0 0>; 370 }; 371 372 cpu0_opp_table: opp-table-cpu0 { 373 compatible = "operating-points-v2"; 374 opp-shared; 375 376 cpu0_opp1: opp-300000000 { 377 opp-hz = /bits/ 64 <300000000>; 378 opp-peak-kBps = <800000 4800000>; 379 }; 380 381 cpu0_opp2: opp-403200000 { 382 opp-hz = /bits/ 64 <403200000>; 383 opp-peak-kBps = <800000 4800000>; 384 }; 385 386 cpu0_opp3: opp-480000000 { 387 opp-hz = /bits/ 64 <480000000>; 388 opp-peak-kBps = <800000 6451200>; 389 }; 390 391 cpu0_opp4: opp-576000000 { 392 opp-hz = /bits/ 64 <576000000>; 393 opp-peak-kBps = <800000 6451200>; 394 }; 395 396 cpu0_opp5: opp-652800000 { 397 opp-hz = /bits/ 64 <652800000>; 398 opp-peak-kBps = <800000 7680000>; 399 }; 400 401 cpu0_opp6: opp-748800000 { 402 opp-hz = /bits/ 64 <748800000>; 403 opp-peak-kBps = <1804000 9216000>; 404 }; 405 406 cpu0_opp7: opp-825600000 { 407 opp-hz = /bits/ 64 <825600000>; 408 opp-peak-kBps = <1804000 9216000>; 409 }; 410 411 cpu0_opp8: opp-902400000 { 412 opp-hz = /bits/ 64 <902400000>; 413 opp-peak-kBps = <1804000 10444800>; 414 }; 415 416 cpu0_opp9: opp-979200000 { 417 opp-hz = /bits/ 64 <979200000>; 418 opp-peak-kBps = <1804000 11980800>; 419 }; 420 421 cpu0_opp10: opp-1056000000 { 422 opp-hz = /bits/ 64 <1056000000>; 423 opp-peak-kBps = <1804000 11980800>; 424 }; 425 426 cpu0_opp11: opp-1132800000 { 427 opp-hz = /bits/ 64 <1132800000>; 428 opp-peak-kBps = <2188000 13516800>; 429 }; 430 431 cpu0_opp12: opp-1228800000 { 432 opp-hz = /bits/ 64 <1228800000>; 433 opp-peak-kBps = <2188000 15052800>; 434 }; 435 436 cpu0_opp13: opp-1324800000 { 437 opp-hz = /bits/ 64 <1324800000>; 438 opp-peak-kBps = <2188000 16588800>; 439 }; 440 441 cpu0_opp14: opp-1420800000 { 442 opp-hz = /bits/ 64 <1420800000>; 443 opp-peak-kBps = <3072000 18124800>; 444 }; 445 446 cpu0_opp15: opp-1516800000 { 447 opp-hz = /bits/ 64 <1516800000>; 448 opp-peak-kBps = <3072000 19353600>; 449 }; 450 451 cpu0_opp16: opp-1612800000 { 452 opp-hz = /bits/ 64 <1612800000>; 453 opp-peak-kBps = <4068000 19353600>; 454 }; 455 456 cpu0_opp17: opp-1689600000 { 457 opp-hz = /bits/ 64 <1689600000>; 458 opp-peak-kBps = <4068000 20889600>; 459 }; 460 461 cpu0_opp18: opp-1766400000 { 462 opp-hz = /bits/ 64 <1766400000>; 463 opp-peak-kBps = <4068000 22425600>; 464 }; 465 }; 466 467 cpu4_opp_table: opp-table-cpu4 { 468 compatible = "operating-points-v2"; 469 opp-shared; 470 471 cpu4_opp1: opp-300000000 { 472 opp-hz = /bits/ 64 <300000000>; 473 opp-peak-kBps = <800000 4800000>; 474 }; 475 476 cpu4_opp2: opp-403200000 { 477 opp-hz = /bits/ 64 <403200000>; 478 opp-peak-kBps = <800000 4800000>; 479 }; 480 481 cpu4_opp3: opp-480000000 { 482 opp-hz = /bits/ 64 <480000000>; 483 opp-peak-kBps = <1804000 4800000>; 484 }; 485 486 cpu4_opp4: opp-576000000 { 487 opp-hz = /bits/ 64 <576000000>; 488 opp-peak-kBps = <1804000 4800000>; 489 }; 490 491 cpu4_opp5: opp-652800000 { 492 opp-hz = /bits/ 64 <652800000>; 493 opp-peak-kBps = <1804000 4800000>; 494 }; 495 496 cpu4_opp6: opp-748800000 { 497 opp-hz = /bits/ 64 <748800000>; 498 opp-peak-kBps = <1804000 4800000>; 499 }; 500 501 cpu4_opp7: opp-825600000 { 502 opp-hz = /bits/ 64 <825600000>; 503 opp-peak-kBps = <2188000 9216000>; 504 }; 505 506 cpu4_opp8: opp-902400000 { 507 opp-hz = /bits/ 64 <902400000>; 508 opp-peak-kBps = <2188000 9216000>; 509 }; 510 511 cpu4_opp9: opp-979200000 { 512 opp-hz = /bits/ 64 <979200000>; 513 opp-peak-kBps = <2188000 9216000>; 514 }; 515 516 cpu4_opp10: opp-1056000000 { 517 opp-hz = /bits/ 64 <1056000000>; 518 opp-peak-kBps = <3072000 9216000>; 519 }; 520 521 cpu4_opp11: opp-1132800000 { 522 opp-hz = /bits/ 64 <1132800000>; 523 opp-peak-kBps = <3072000 11980800>; 524 }; 525 526 cpu4_opp12: opp-1209600000 { 527 opp-hz = /bits/ 64 <1209600000>; 528 opp-peak-kBps = <4068000 11980800>; 529 }; 530 531 cpu4_opp13: opp-1286400000 { 532 opp-hz = /bits/ 64 <1286400000>; 533 opp-peak-kBps = <4068000 11980800>; 534 }; 535 536 cpu4_opp14: opp-1363200000 { 537 opp-hz = /bits/ 64 <1363200000>; 538 opp-peak-kBps = <4068000 15052800>; 539 }; 540 541 cpu4_opp15: opp-1459200000 { 542 opp-hz = /bits/ 64 <1459200000>; 543 opp-peak-kBps = <4068000 15052800>; 544 }; 545 546 cpu4_opp16: opp-1536000000 { 547 opp-hz = /bits/ 64 <1536000000>; 548 opp-peak-kBps = <5412000 15052800>; 549 }; 550 551 cpu4_opp17: opp-1612800000 { 552 opp-hz = /bits/ 64 <1612800000>; 553 opp-peak-kBps = <5412000 15052800>; 554 }; 555 556 cpu4_opp18: opp-1689600000 { 557 opp-hz = /bits/ 64 <1689600000>; 558 opp-peak-kBps = <5412000 19353600>; 559 }; 560 561 cpu4_opp19: opp-1766400000 { 562 opp-hz = /bits/ 64 <1766400000>; 563 opp-peak-kBps = <6220000 19353600>; 564 }; 565 566 cpu4_opp20: opp-1843200000 { 567 opp-hz = /bits/ 64 <1843200000>; 568 opp-peak-kBps = <6220000 19353600>; 569 }; 570 571 cpu4_opp21: opp-1920000000 { 572 opp-hz = /bits/ 64 <1920000000>; 573 opp-peak-kBps = <7216000 19353600>; 574 }; 575 576 cpu4_opp22: opp-1996800000 { 577 opp-hz = /bits/ 64 <1996800000>; 578 opp-peak-kBps = <7216000 20889600>; 579 }; 580 581 cpu4_opp23: opp-2092800000 { 582 opp-hz = /bits/ 64 <2092800000>; 583 opp-peak-kBps = <7216000 20889600>; 584 }; 585 586 cpu4_opp24: opp-2169600000 { 587 opp-hz = /bits/ 64 <2169600000>; 588 opp-peak-kBps = <7216000 20889600>; 589 }; 590 591 cpu4_opp25: opp-2246400000 { 592 opp-hz = /bits/ 64 <2246400000>; 593 opp-peak-kBps = <7216000 20889600>; 594 }; 595 596 cpu4_opp26: opp-2323200000 { 597 opp-hz = /bits/ 64 <2323200000>; 598 opp-peak-kBps = <7216000 20889600>; 599 }; 600 601 cpu4_opp27: opp-2400000000 { 602 opp-hz = /bits/ 64 <2400000000>; 603 opp-peak-kBps = <7216000 22425600>; 604 }; 605 606 cpu4_opp28: opp-2476800000 { 607 opp-hz = /bits/ 64 <2476800000>; 608 opp-peak-kBps = <7216000 22425600>; 609 }; 610 611 cpu4_opp29: opp-2553600000 { 612 opp-hz = /bits/ 64 <2553600000>; 613 opp-peak-kBps = <7216000 22425600>; 614 }; 615 616 cpu4_opp30: opp-2649600000 { 617 opp-hz = /bits/ 64 <2649600000>; 618 opp-peak-kBps = <7216000 22425600>; 619 }; 620 621 cpu4_opp31: opp-2745600000 { 622 opp-hz = /bits/ 64 <2745600000>; 623 opp-peak-kBps = <7216000 25497600>; 624 }; 625 626 cpu4_opp32: opp-2803200000 { 627 opp-hz = /bits/ 64 <2803200000>; 628 opp-peak-kBps = <7216000 25497600>; 629 }; 630 }; 631 632 dsi_opp_table: opp-table-dsi { 633 compatible = "operating-points-v2"; 634 635 opp-19200000 { 636 opp-hz = /bits/ 64 <19200000>; 637 required-opps = <&rpmhpd_opp_min_svs>; 638 }; 639 640 opp-180000000 { 641 opp-hz = /bits/ 64 <180000000>; 642 required-opps = <&rpmhpd_opp_low_svs>; 643 }; 644 645 opp-275000000 { 646 opp-hz = /bits/ 64 <275000000>; 647 required-opps = <&rpmhpd_opp_svs>; 648 }; 649 650 opp-328580000 { 651 opp-hz = /bits/ 64 <328580000>; 652 required-opps = <&rpmhpd_opp_svs_l1>; 653 }; 654 655 opp-358000000 { 656 opp-hz = /bits/ 64 <358000000>; 657 required-opps = <&rpmhpd_opp_nom>; 658 }; 659 }; 660 661 qspi_opp_table: opp-table-qspi { 662 compatible = "operating-points-v2"; 663 664 opp-19200000 { 665 opp-hz = /bits/ 64 <19200000>; 666 required-opps = <&rpmhpd_opp_min_svs>; 667 }; 668 669 opp-100000000 { 670 opp-hz = /bits/ 64 <100000000>; 671 required-opps = <&rpmhpd_opp_low_svs>; 672 }; 673 674 opp-150000000 { 675 opp-hz = /bits/ 64 <150000000>; 676 required-opps = <&rpmhpd_opp_svs>; 677 }; 678 679 opp-300000000 { 680 opp-hz = /bits/ 64 <300000000>; 681 required-opps = <&rpmhpd_opp_nom>; 682 }; 683 }; 684 685 qup_opp_table: opp-table-qup { 686 compatible = "operating-points-v2"; 687 688 opp-50000000 { 689 opp-hz = /bits/ 64 <50000000>; 690 required-opps = <&rpmhpd_opp_min_svs>; 691 }; 692 693 opp-75000000 { 694 opp-hz = /bits/ 64 <75000000>; 695 required-opps = <&rpmhpd_opp_low_svs>; 696 }; 697 698 opp-100000000 { 699 opp-hz = /bits/ 64 <100000000>; 700 required-opps = <&rpmhpd_opp_svs>; 701 }; 702 703 opp-128000000 { 704 opp-hz = /bits/ 64 <128000000>; 705 required-opps = <&rpmhpd_opp_nom>; 706 }; 707 }; 708 709 pmu { 710 compatible = "arm,armv8-pmuv3"; 711 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 712 }; 713 714 psci: psci { 715 compatible = "arm,psci-1.0"; 716 method = "smc"; 717 718 CPU_PD0: power-domain-cpu0 { 719 #power-domain-cells = <0>; 720 power-domains = <&CLUSTER_PD>; 721 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 722 }; 723 724 CPU_PD1: power-domain-cpu1 { 725 #power-domain-cells = <0>; 726 power-domains = <&CLUSTER_PD>; 727 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 728 }; 729 730 CPU_PD2: power-domain-cpu2 { 731 #power-domain-cells = <0>; 732 power-domains = <&CLUSTER_PD>; 733 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 734 }; 735 736 CPU_PD3: power-domain-cpu3 { 737 #power-domain-cells = <0>; 738 power-domains = <&CLUSTER_PD>; 739 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 740 }; 741 742 CPU_PD4: power-domain-cpu4 { 743 #power-domain-cells = <0>; 744 power-domains = <&CLUSTER_PD>; 745 domain-idle-states = <&BIG_CPU_SLEEP_0>; 746 }; 747 748 CPU_PD5: power-domain-cpu5 { 749 #power-domain-cells = <0>; 750 power-domains = <&CLUSTER_PD>; 751 domain-idle-states = <&BIG_CPU_SLEEP_0>; 752 }; 753 754 CPU_PD6: power-domain-cpu6 { 755 #power-domain-cells = <0>; 756 power-domains = <&CLUSTER_PD>; 757 domain-idle-states = <&BIG_CPU_SLEEP_0>; 758 }; 759 760 CPU_PD7: power-domain-cpu7 { 761 #power-domain-cells = <0>; 762 power-domains = <&CLUSTER_PD>; 763 domain-idle-states = <&BIG_CPU_SLEEP_0>; 764 }; 765 766 CLUSTER_PD: power-domain-cluster { 767 #power-domain-cells = <0>; 768 domain-idle-states = <&CLUSTER_SLEEP_0>; 769 }; 770 }; 771 772 reserved-memory { 773 #address-cells = <2>; 774 #size-cells = <2>; 775 ranges; 776 777 hyp_mem: hyp-mem@85700000 { 778 reg = <0 0x85700000 0 0x600000>; 779 no-map; 780 }; 781 782 xbl_mem: xbl-mem@85e00000 { 783 reg = <0 0x85e00000 0 0x100000>; 784 no-map; 785 }; 786 787 aop_mem: aop-mem@85fc0000 { 788 reg = <0 0x85fc0000 0 0x20000>; 789 no-map; 790 }; 791 792 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { 793 compatible = "qcom,cmd-db"; 794 reg = <0x0 0x85fe0000 0 0x20000>; 795 no-map; 796 }; 797 798 smem@86000000 { 799 compatible = "qcom,smem"; 800 reg = <0x0 0x86000000 0 0x200000>; 801 no-map; 802 hwlocks = <&tcsr_mutex 3>; 803 }; 804 805 tz_mem: tz@86200000 { 806 reg = <0 0x86200000 0 0x2d00000>; 807 no-map; 808 }; 809 810 rmtfs_mem: rmtfs@88f00000 { 811 compatible = "qcom,rmtfs-mem"; 812 reg = <0 0x88f00000 0 0x200000>; 813 no-map; 814 815 qcom,client-id = <1>; 816 qcom,vmid = <15>; 817 }; 818 819 qseecom_mem: qseecom@8ab00000 { 820 reg = <0 0x8ab00000 0 0x1400000>; 821 no-map; 822 }; 823 824 camera_mem: camera-mem@8bf00000 { 825 reg = <0 0x8bf00000 0 0x500000>; 826 no-map; 827 }; 828 829 ipa_fw_mem: ipa-fw@8c400000 { 830 reg = <0 0x8c400000 0 0x10000>; 831 no-map; 832 }; 833 834 ipa_gsi_mem: ipa-gsi@8c410000 { 835 reg = <0 0x8c410000 0 0x5000>; 836 no-map; 837 }; 838 839 gpu_mem: gpu@8c415000 { 840 reg = <0 0x8c415000 0 0x2000>; 841 no-map; 842 }; 843 844 adsp_mem: adsp@8c500000 { 845 reg = <0 0x8c500000 0 0x1a00000>; 846 no-map; 847 }; 848 849 wlan_msa_mem: wlan-msa@8df00000 { 850 reg = <0 0x8df00000 0 0x100000>; 851 no-map; 852 }; 853 854 mpss_region: mpss@8e000000 { 855 reg = <0 0x8e000000 0 0x7800000>; 856 no-map; 857 }; 858 859 venus_mem: venus@95800000 { 860 reg = <0 0x95800000 0 0x500000>; 861 no-map; 862 }; 863 864 cdsp_mem: cdsp@95d00000 { 865 reg = <0 0x95d00000 0 0x800000>; 866 no-map; 867 }; 868 869 mba_region: mba@96500000 { 870 reg = <0 0x96500000 0 0x200000>; 871 no-map; 872 }; 873 874 slpi_mem: slpi@96700000 { 875 reg = <0 0x96700000 0 0x1400000>; 876 no-map; 877 }; 878 879 spss_mem: spss@97b00000 { 880 reg = <0 0x97b00000 0 0x100000>; 881 no-map; 882 }; 883 884 mdata_mem: mpss-metadata { 885 alloc-ranges = <0 0xa0000000 0 0x20000000>; 886 size = <0 0x4000>; 887 no-map; 888 }; 889 890 fastrpc_mem: fastrpc { 891 compatible = "shared-dma-pool"; 892 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; 893 alignment = <0x0 0x400000>; 894 size = <0x0 0x1000000>; 895 reusable; 896 }; 897 }; 898 899 adsp_pas: remoteproc-adsp { 900 compatible = "qcom,sdm845-adsp-pas"; 901 902 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 903 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 904 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 905 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 906 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 907 interrupt-names = "wdog", "fatal", "ready", 908 "handover", "stop-ack"; 909 910 clocks = <&rpmhcc RPMH_CXO_CLK>; 911 clock-names = "xo"; 912 913 memory-region = <&adsp_mem>; 914 915 qcom,qmp = <&aoss_qmp>; 916 917 qcom,smem-states = <&adsp_smp2p_out 0>; 918 qcom,smem-state-names = "stop"; 919 920 status = "disabled"; 921 922 glink-edge { 923 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 924 label = "lpass"; 925 qcom,remote-pid = <2>; 926 mboxes = <&apss_shared 8>; 927 928 apr { 929 compatible = "qcom,apr-v2"; 930 qcom,glink-channels = "apr_audio_svc"; 931 qcom,domain = <APR_DOMAIN_ADSP>; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 qcom,intents = <512 20>; 935 936 service@3 { 937 reg = <APR_SVC_ADSP_CORE>; 938 compatible = "qcom,q6core"; 939 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 940 }; 941 942 q6afe: service@4 { 943 compatible = "qcom,q6afe"; 944 reg = <APR_SVC_AFE>; 945 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 946 q6afedai: dais { 947 compatible = "qcom,q6afe-dais"; 948 #address-cells = <1>; 949 #size-cells = <0>; 950 #sound-dai-cells = <1>; 951 }; 952 }; 953 954 q6asm: service@7 { 955 compatible = "qcom,q6asm"; 956 reg = <APR_SVC_ASM>; 957 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 958 q6asmdai: dais { 959 compatible = "qcom,q6asm-dais"; 960 #address-cells = <1>; 961 #size-cells = <0>; 962 #sound-dai-cells = <1>; 963 iommus = <&apps_smmu 0x1821 0x0>; 964 }; 965 }; 966 967 q6adm: service@8 { 968 compatible = "qcom,q6adm"; 969 reg = <APR_SVC_ADM>; 970 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 971 q6routing: routing { 972 compatible = "qcom,q6adm-routing"; 973 #sound-dai-cells = <0>; 974 }; 975 }; 976 }; 977 978 fastrpc { 979 compatible = "qcom,fastrpc"; 980 qcom,glink-channels = "fastrpcglink-apps-dsp"; 981 label = "adsp"; 982 qcom,non-secure-domain; 983 #address-cells = <1>; 984 #size-cells = <0>; 985 986 compute-cb@3 { 987 compatible = "qcom,fastrpc-compute-cb"; 988 reg = <3>; 989 iommus = <&apps_smmu 0x1823 0x0>; 990 }; 991 992 compute-cb@4 { 993 compatible = "qcom,fastrpc-compute-cb"; 994 reg = <4>; 995 iommus = <&apps_smmu 0x1824 0x0>; 996 }; 997 }; 998 }; 999 }; 1000 1001 cdsp_pas: remoteproc-cdsp { 1002 compatible = "qcom,sdm845-cdsp-pas"; 1003 1004 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 1005 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1006 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1007 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1008 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1009 interrupt-names = "wdog", "fatal", "ready", 1010 "handover", "stop-ack"; 1011 1012 clocks = <&rpmhcc RPMH_CXO_CLK>; 1013 clock-names = "xo"; 1014 1015 memory-region = <&cdsp_mem>; 1016 1017 qcom,qmp = <&aoss_qmp>; 1018 1019 qcom,smem-states = <&cdsp_smp2p_out 0>; 1020 qcom,smem-state-names = "stop"; 1021 1022 status = "disabled"; 1023 1024 glink-edge { 1025 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 1026 label = "turing"; 1027 qcom,remote-pid = <5>; 1028 mboxes = <&apss_shared 4>; 1029 fastrpc { 1030 compatible = "qcom,fastrpc"; 1031 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1032 label = "cdsp"; 1033 qcom,non-secure-domain; 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 1037 compute-cb@1 { 1038 compatible = "qcom,fastrpc-compute-cb"; 1039 reg = <1>; 1040 iommus = <&apps_smmu 0x1401 0x30>; 1041 }; 1042 1043 compute-cb@2 { 1044 compatible = "qcom,fastrpc-compute-cb"; 1045 reg = <2>; 1046 iommus = <&apps_smmu 0x1402 0x30>; 1047 }; 1048 1049 compute-cb@3 { 1050 compatible = "qcom,fastrpc-compute-cb"; 1051 reg = <3>; 1052 iommus = <&apps_smmu 0x1403 0x30>; 1053 }; 1054 1055 compute-cb@4 { 1056 compatible = "qcom,fastrpc-compute-cb"; 1057 reg = <4>; 1058 iommus = <&apps_smmu 0x1404 0x30>; 1059 }; 1060 1061 compute-cb@5 { 1062 compatible = "qcom,fastrpc-compute-cb"; 1063 reg = <5>; 1064 iommus = <&apps_smmu 0x1405 0x30>; 1065 }; 1066 1067 compute-cb@6 { 1068 compatible = "qcom,fastrpc-compute-cb"; 1069 reg = <6>; 1070 iommus = <&apps_smmu 0x1406 0x30>; 1071 }; 1072 1073 compute-cb@7 { 1074 compatible = "qcom,fastrpc-compute-cb"; 1075 reg = <7>; 1076 iommus = <&apps_smmu 0x1407 0x30>; 1077 }; 1078 1079 compute-cb@8 { 1080 compatible = "qcom,fastrpc-compute-cb"; 1081 reg = <8>; 1082 iommus = <&apps_smmu 0x1408 0x30>; 1083 }; 1084 }; 1085 }; 1086 }; 1087 1088 smp2p-cdsp { 1089 compatible = "qcom,smp2p"; 1090 qcom,smem = <94>, <432>; 1091 1092 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 1093 1094 mboxes = <&apss_shared 6>; 1095 1096 qcom,local-pid = <0>; 1097 qcom,remote-pid = <5>; 1098 1099 cdsp_smp2p_out: master-kernel { 1100 qcom,entry-name = "master-kernel"; 1101 #qcom,smem-state-cells = <1>; 1102 }; 1103 1104 cdsp_smp2p_in: slave-kernel { 1105 qcom,entry-name = "slave-kernel"; 1106 1107 interrupt-controller; 1108 #interrupt-cells = <2>; 1109 }; 1110 }; 1111 1112 smp2p-lpass { 1113 compatible = "qcom,smp2p"; 1114 qcom,smem = <443>, <429>; 1115 1116 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 1117 1118 mboxes = <&apss_shared 10>; 1119 1120 qcom,local-pid = <0>; 1121 qcom,remote-pid = <2>; 1122 1123 adsp_smp2p_out: master-kernel { 1124 qcom,entry-name = "master-kernel"; 1125 #qcom,smem-state-cells = <1>; 1126 }; 1127 1128 adsp_smp2p_in: slave-kernel { 1129 qcom,entry-name = "slave-kernel"; 1130 1131 interrupt-controller; 1132 #interrupt-cells = <2>; 1133 }; 1134 }; 1135 1136 smp2p-mpss { 1137 compatible = "qcom,smp2p"; 1138 qcom,smem = <435>, <428>; 1139 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 1140 mboxes = <&apss_shared 14>; 1141 qcom,local-pid = <0>; 1142 qcom,remote-pid = <1>; 1143 1144 modem_smp2p_out: master-kernel { 1145 qcom,entry-name = "master-kernel"; 1146 #qcom,smem-state-cells = <1>; 1147 }; 1148 1149 modem_smp2p_in: slave-kernel { 1150 qcom,entry-name = "slave-kernel"; 1151 interrupt-controller; 1152 #interrupt-cells = <2>; 1153 }; 1154 1155 ipa_smp2p_out: ipa-ap-to-modem { 1156 qcom,entry-name = "ipa"; 1157 #qcom,smem-state-cells = <1>; 1158 }; 1159 1160 ipa_smp2p_in: ipa-modem-to-ap { 1161 qcom,entry-name = "ipa"; 1162 interrupt-controller; 1163 #interrupt-cells = <2>; 1164 }; 1165 }; 1166 1167 smp2p-slpi { 1168 compatible = "qcom,smp2p"; 1169 qcom,smem = <481>, <430>; 1170 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 1171 mboxes = <&apss_shared 26>; 1172 qcom,local-pid = <0>; 1173 qcom,remote-pid = <3>; 1174 1175 slpi_smp2p_out: master-kernel { 1176 qcom,entry-name = "master-kernel"; 1177 #qcom,smem-state-cells = <1>; 1178 }; 1179 1180 slpi_smp2p_in: slave-kernel { 1181 qcom,entry-name = "slave-kernel"; 1182 interrupt-controller; 1183 #interrupt-cells = <2>; 1184 }; 1185 }; 1186 1187 soc: soc@0 { 1188 #address-cells = <2>; 1189 #size-cells = <2>; 1190 ranges = <0 0 0 0 0x10 0>; 1191 dma-ranges = <0 0 0 0 0x10 0>; 1192 compatible = "simple-bus"; 1193 1194 gcc: clock-controller@100000 { 1195 compatible = "qcom,gcc-sdm845"; 1196 reg = <0 0x00100000 0 0x1f0000>; 1197 clocks = <&rpmhcc RPMH_CXO_CLK>, 1198 <&rpmhcc RPMH_CXO_CLK_A>, 1199 <&sleep_clk>, 1200 <&pcie0_lane>, 1201 <&pcie1_lane>; 1202 clock-names = "bi_tcxo", 1203 "bi_tcxo_ao", 1204 "sleep_clk", 1205 "pcie_0_pipe_clk", 1206 "pcie_1_pipe_clk"; 1207 #clock-cells = <1>; 1208 #reset-cells = <1>; 1209 #power-domain-cells = <1>; 1210 power-domains = <&rpmhpd SDM845_CX>; 1211 }; 1212 1213 qfprom@784000 { 1214 compatible = "qcom,sdm845-qfprom", "qcom,qfprom"; 1215 reg = <0 0x00784000 0 0x8ff>; 1216 #address-cells = <1>; 1217 #size-cells = <1>; 1218 1219 qusb2p_hstx_trim: hstx-trim-primary@1eb { 1220 reg = <0x1eb 0x1>; 1221 bits = <1 4>; 1222 }; 1223 1224 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 1225 reg = <0x1eb 0x2>; 1226 bits = <6 4>; 1227 }; 1228 }; 1229 1230 rng: rng@793000 { 1231 compatible = "qcom,prng-ee"; 1232 reg = <0 0x00793000 0 0x1000>; 1233 clocks = <&gcc GCC_PRNG_AHB_CLK>; 1234 clock-names = "core"; 1235 }; 1236 1237 gpi_dma0: dma-controller@800000 { 1238 #dma-cells = <3>; 1239 compatible = "qcom,sdm845-gpi-dma"; 1240 reg = <0 0x00800000 0 0x60000>; 1241 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1254 dma-channels = <13>; 1255 dma-channel-mask = <0xfa>; 1256 iommus = <&apps_smmu 0x0016 0x0>; 1257 status = "disabled"; 1258 }; 1259 1260 qupv3_id_0: geniqup@8c0000 { 1261 compatible = "qcom,geni-se-qup"; 1262 reg = <0 0x008c0000 0 0x6000>; 1263 clock-names = "m-ahb", "s-ahb"; 1264 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1265 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1266 iommus = <&apps_smmu 0x3 0x0>; 1267 #address-cells = <2>; 1268 #size-cells = <2>; 1269 ranges; 1270 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>; 1271 interconnect-names = "qup-core"; 1272 status = "disabled"; 1273 1274 i2c0: i2c@880000 { 1275 compatible = "qcom,geni-i2c"; 1276 reg = <0 0x00880000 0 0x4000>; 1277 clock-names = "se"; 1278 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1279 pinctrl-names = "default"; 1280 pinctrl-0 = <&qup_i2c0_default>; 1281 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 power-domains = <&rpmhpd SDM845_CX>; 1285 operating-points-v2 = <&qup_opp_table>; 1286 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1287 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1288 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1289 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1290 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1291 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1292 dma-names = "tx", "rx"; 1293 status = "disabled"; 1294 }; 1295 1296 spi0: spi@880000 { 1297 compatible = "qcom,geni-spi"; 1298 reg = <0 0x00880000 0 0x4000>; 1299 clock-names = "se"; 1300 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1301 pinctrl-names = "default"; 1302 pinctrl-0 = <&qup_spi0_default>; 1303 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1307 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1308 interconnect-names = "qup-core", "qup-config"; 1309 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1310 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1311 dma-names = "tx", "rx"; 1312 status = "disabled"; 1313 }; 1314 1315 uart0: serial@880000 { 1316 compatible = "qcom,geni-uart"; 1317 reg = <0 0x00880000 0 0x4000>; 1318 clock-names = "se"; 1319 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1320 pinctrl-names = "default"; 1321 pinctrl-0 = <&qup_uart0_default>; 1322 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1323 power-domains = <&rpmhpd SDM845_CX>; 1324 operating-points-v2 = <&qup_opp_table>; 1325 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1326 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1327 interconnect-names = "qup-core", "qup-config"; 1328 status = "disabled"; 1329 }; 1330 1331 i2c1: i2c@884000 { 1332 compatible = "qcom,geni-i2c"; 1333 reg = <0 0x00884000 0 0x4000>; 1334 clock-names = "se"; 1335 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1336 pinctrl-names = "default"; 1337 pinctrl-0 = <&qup_i2c1_default>; 1338 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1339 #address-cells = <1>; 1340 #size-cells = <0>; 1341 power-domains = <&rpmhpd SDM845_CX>; 1342 operating-points-v2 = <&qup_opp_table>; 1343 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1344 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1345 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1346 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1347 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1348 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1349 dma-names = "tx", "rx"; 1350 status = "disabled"; 1351 }; 1352 1353 spi1: spi@884000 { 1354 compatible = "qcom,geni-spi"; 1355 reg = <0 0x00884000 0 0x4000>; 1356 clock-names = "se"; 1357 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1358 pinctrl-names = "default"; 1359 pinctrl-0 = <&qup_spi1_default>; 1360 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1361 #address-cells = <1>; 1362 #size-cells = <0>; 1363 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1364 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1365 interconnect-names = "qup-core", "qup-config"; 1366 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1367 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1368 dma-names = "tx", "rx"; 1369 status = "disabled"; 1370 }; 1371 1372 uart1: serial@884000 { 1373 compatible = "qcom,geni-uart"; 1374 reg = <0 0x00884000 0 0x4000>; 1375 clock-names = "se"; 1376 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1377 pinctrl-names = "default"; 1378 pinctrl-0 = <&qup_uart1_default>; 1379 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1380 power-domains = <&rpmhpd SDM845_CX>; 1381 operating-points-v2 = <&qup_opp_table>; 1382 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1383 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1384 interconnect-names = "qup-core", "qup-config"; 1385 status = "disabled"; 1386 }; 1387 1388 i2c2: i2c@888000 { 1389 compatible = "qcom,geni-i2c"; 1390 reg = <0 0x00888000 0 0x4000>; 1391 clock-names = "se"; 1392 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1393 pinctrl-names = "default"; 1394 pinctrl-0 = <&qup_i2c2_default>; 1395 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1396 #address-cells = <1>; 1397 #size-cells = <0>; 1398 power-domains = <&rpmhpd SDM845_CX>; 1399 operating-points-v2 = <&qup_opp_table>; 1400 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1401 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1402 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1403 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1404 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1405 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1406 dma-names = "tx", "rx"; 1407 status = "disabled"; 1408 }; 1409 1410 spi2: spi@888000 { 1411 compatible = "qcom,geni-spi"; 1412 reg = <0 0x00888000 0 0x4000>; 1413 clock-names = "se"; 1414 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1415 pinctrl-names = "default"; 1416 pinctrl-0 = <&qup_spi2_default>; 1417 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1418 #address-cells = <1>; 1419 #size-cells = <0>; 1420 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1421 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1422 interconnect-names = "qup-core", "qup-config"; 1423 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1424 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1425 dma-names = "tx", "rx"; 1426 status = "disabled"; 1427 }; 1428 1429 uart2: serial@888000 { 1430 compatible = "qcom,geni-uart"; 1431 reg = <0 0x00888000 0 0x4000>; 1432 clock-names = "se"; 1433 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1434 pinctrl-names = "default"; 1435 pinctrl-0 = <&qup_uart2_default>; 1436 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1437 power-domains = <&rpmhpd SDM845_CX>; 1438 operating-points-v2 = <&qup_opp_table>; 1439 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1440 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1441 interconnect-names = "qup-core", "qup-config"; 1442 status = "disabled"; 1443 }; 1444 1445 i2c3: i2c@88c000 { 1446 compatible = "qcom,geni-i2c"; 1447 reg = <0 0x0088c000 0 0x4000>; 1448 clock-names = "se"; 1449 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1450 pinctrl-names = "default"; 1451 pinctrl-0 = <&qup_i2c3_default>; 1452 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1453 #address-cells = <1>; 1454 #size-cells = <0>; 1455 power-domains = <&rpmhpd SDM845_CX>; 1456 operating-points-v2 = <&qup_opp_table>; 1457 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1458 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1459 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1460 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1461 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1462 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1463 dma-names = "tx", "rx"; 1464 status = "disabled"; 1465 }; 1466 1467 spi3: spi@88c000 { 1468 compatible = "qcom,geni-spi"; 1469 reg = <0 0x0088c000 0 0x4000>; 1470 clock-names = "se"; 1471 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1472 pinctrl-names = "default"; 1473 pinctrl-0 = <&qup_spi3_default>; 1474 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1475 #address-cells = <1>; 1476 #size-cells = <0>; 1477 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1478 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1479 interconnect-names = "qup-core", "qup-config"; 1480 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1481 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1482 dma-names = "tx", "rx"; 1483 status = "disabled"; 1484 }; 1485 1486 uart3: serial@88c000 { 1487 compatible = "qcom,geni-uart"; 1488 reg = <0 0x0088c000 0 0x4000>; 1489 clock-names = "se"; 1490 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1491 pinctrl-names = "default"; 1492 pinctrl-0 = <&qup_uart3_default>; 1493 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1494 power-domains = <&rpmhpd SDM845_CX>; 1495 operating-points-v2 = <&qup_opp_table>; 1496 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1497 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1498 interconnect-names = "qup-core", "qup-config"; 1499 status = "disabled"; 1500 }; 1501 1502 i2c4: i2c@890000 { 1503 compatible = "qcom,geni-i2c"; 1504 reg = <0 0x00890000 0 0x4000>; 1505 clock-names = "se"; 1506 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1507 pinctrl-names = "default"; 1508 pinctrl-0 = <&qup_i2c4_default>; 1509 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1510 #address-cells = <1>; 1511 #size-cells = <0>; 1512 power-domains = <&rpmhpd SDM845_CX>; 1513 operating-points-v2 = <&qup_opp_table>; 1514 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1515 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1516 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1517 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1518 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1519 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1520 dma-names = "tx", "rx"; 1521 status = "disabled"; 1522 }; 1523 1524 spi4: spi@890000 { 1525 compatible = "qcom,geni-spi"; 1526 reg = <0 0x00890000 0 0x4000>; 1527 clock-names = "se"; 1528 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1529 pinctrl-names = "default"; 1530 pinctrl-0 = <&qup_spi4_default>; 1531 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1532 #address-cells = <1>; 1533 #size-cells = <0>; 1534 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1535 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1536 interconnect-names = "qup-core", "qup-config"; 1537 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1538 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1539 dma-names = "tx", "rx"; 1540 status = "disabled"; 1541 }; 1542 1543 uart4: serial@890000 { 1544 compatible = "qcom,geni-uart"; 1545 reg = <0 0x00890000 0 0x4000>; 1546 clock-names = "se"; 1547 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1548 pinctrl-names = "default"; 1549 pinctrl-0 = <&qup_uart4_default>; 1550 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1551 power-domains = <&rpmhpd SDM845_CX>; 1552 operating-points-v2 = <&qup_opp_table>; 1553 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1554 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1555 interconnect-names = "qup-core", "qup-config"; 1556 status = "disabled"; 1557 }; 1558 1559 i2c5: i2c@894000 { 1560 compatible = "qcom,geni-i2c"; 1561 reg = <0 0x00894000 0 0x4000>; 1562 clock-names = "se"; 1563 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1564 pinctrl-names = "default"; 1565 pinctrl-0 = <&qup_i2c5_default>; 1566 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1567 #address-cells = <1>; 1568 #size-cells = <0>; 1569 power-domains = <&rpmhpd SDM845_CX>; 1570 operating-points-v2 = <&qup_opp_table>; 1571 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1572 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1573 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1574 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1575 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1576 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1577 dma-names = "tx", "rx"; 1578 status = "disabled"; 1579 }; 1580 1581 spi5: spi@894000 { 1582 compatible = "qcom,geni-spi"; 1583 reg = <0 0x00894000 0 0x4000>; 1584 clock-names = "se"; 1585 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1586 pinctrl-names = "default"; 1587 pinctrl-0 = <&qup_spi5_default>; 1588 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1589 #address-cells = <1>; 1590 #size-cells = <0>; 1591 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1592 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1593 interconnect-names = "qup-core", "qup-config"; 1594 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1595 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1596 dma-names = "tx", "rx"; 1597 status = "disabled"; 1598 }; 1599 1600 uart5: serial@894000 { 1601 compatible = "qcom,geni-uart"; 1602 reg = <0 0x00894000 0 0x4000>; 1603 clock-names = "se"; 1604 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1605 pinctrl-names = "default"; 1606 pinctrl-0 = <&qup_uart5_default>; 1607 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1608 power-domains = <&rpmhpd SDM845_CX>; 1609 operating-points-v2 = <&qup_opp_table>; 1610 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1611 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1612 interconnect-names = "qup-core", "qup-config"; 1613 status = "disabled"; 1614 }; 1615 1616 i2c6: i2c@898000 { 1617 compatible = "qcom,geni-i2c"; 1618 reg = <0 0x00898000 0 0x4000>; 1619 clock-names = "se"; 1620 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1621 pinctrl-names = "default"; 1622 pinctrl-0 = <&qup_i2c6_default>; 1623 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1624 #address-cells = <1>; 1625 #size-cells = <0>; 1626 power-domains = <&rpmhpd SDM845_CX>; 1627 operating-points-v2 = <&qup_opp_table>; 1628 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1629 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1630 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1631 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1632 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1633 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1634 dma-names = "tx", "rx"; 1635 status = "disabled"; 1636 }; 1637 1638 spi6: spi@898000 { 1639 compatible = "qcom,geni-spi"; 1640 reg = <0 0x00898000 0 0x4000>; 1641 clock-names = "se"; 1642 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1643 pinctrl-names = "default"; 1644 pinctrl-0 = <&qup_spi6_default>; 1645 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1646 #address-cells = <1>; 1647 #size-cells = <0>; 1648 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1649 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1650 interconnect-names = "qup-core", "qup-config"; 1651 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1652 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1653 dma-names = "tx", "rx"; 1654 status = "disabled"; 1655 }; 1656 1657 uart6: serial@898000 { 1658 compatible = "qcom,geni-uart"; 1659 reg = <0 0x00898000 0 0x4000>; 1660 clock-names = "se"; 1661 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1662 pinctrl-names = "default"; 1663 pinctrl-0 = <&qup_uart6_default>; 1664 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1665 power-domains = <&rpmhpd SDM845_CX>; 1666 operating-points-v2 = <&qup_opp_table>; 1667 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1668 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1669 interconnect-names = "qup-core", "qup-config"; 1670 status = "disabled"; 1671 }; 1672 1673 i2c7: i2c@89c000 { 1674 compatible = "qcom,geni-i2c"; 1675 reg = <0 0x0089c000 0 0x4000>; 1676 clock-names = "se"; 1677 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1678 pinctrl-names = "default"; 1679 pinctrl-0 = <&qup_i2c7_default>; 1680 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1681 #address-cells = <1>; 1682 #size-cells = <0>; 1683 power-domains = <&rpmhpd SDM845_CX>; 1684 operating-points-v2 = <&qup_opp_table>; 1685 status = "disabled"; 1686 }; 1687 1688 spi7: spi@89c000 { 1689 compatible = "qcom,geni-spi"; 1690 reg = <0 0x0089c000 0 0x4000>; 1691 clock-names = "se"; 1692 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1693 pinctrl-names = "default"; 1694 pinctrl-0 = <&qup_spi7_default>; 1695 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1696 #address-cells = <1>; 1697 #size-cells = <0>; 1698 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1699 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1700 interconnect-names = "qup-core", "qup-config"; 1701 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1702 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1703 dma-names = "tx", "rx"; 1704 status = "disabled"; 1705 }; 1706 1707 uart7: serial@89c000 { 1708 compatible = "qcom,geni-uart"; 1709 reg = <0 0x0089c000 0 0x4000>; 1710 clock-names = "se"; 1711 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1712 pinctrl-names = "default"; 1713 pinctrl-0 = <&qup_uart7_default>; 1714 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1715 power-domains = <&rpmhpd SDM845_CX>; 1716 operating-points-v2 = <&qup_opp_table>; 1717 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1718 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1719 interconnect-names = "qup-core", "qup-config"; 1720 status = "disabled"; 1721 }; 1722 }; 1723 1724 gpi_dma1: dma-controller@a00000 { 1725 #dma-cells = <3>; 1726 compatible = "qcom,sdm845-gpi-dma"; 1727 reg = <0 0x00a00000 0 0x60000>; 1728 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1741 dma-channels = <13>; 1742 dma-channel-mask = <0xfa>; 1743 iommus = <&apps_smmu 0x06d6 0x0>; 1744 status = "disabled"; 1745 }; 1746 1747 qupv3_id_1: geniqup@ac0000 { 1748 compatible = "qcom,geni-se-qup"; 1749 reg = <0 0x00ac0000 0 0x6000>; 1750 clock-names = "m-ahb", "s-ahb"; 1751 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1752 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1753 iommus = <&apps_smmu 0x6c3 0x0>; 1754 #address-cells = <2>; 1755 #size-cells = <2>; 1756 ranges; 1757 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>; 1758 interconnect-names = "qup-core"; 1759 status = "disabled"; 1760 1761 i2c8: i2c@a80000 { 1762 compatible = "qcom,geni-i2c"; 1763 reg = <0 0x00a80000 0 0x4000>; 1764 clock-names = "se"; 1765 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1766 pinctrl-names = "default"; 1767 pinctrl-0 = <&qup_i2c8_default>; 1768 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1769 #address-cells = <1>; 1770 #size-cells = <0>; 1771 power-domains = <&rpmhpd SDM845_CX>; 1772 operating-points-v2 = <&qup_opp_table>; 1773 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1774 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1775 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1776 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1777 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1778 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1779 dma-names = "tx", "rx"; 1780 status = "disabled"; 1781 }; 1782 1783 spi8: spi@a80000 { 1784 compatible = "qcom,geni-spi"; 1785 reg = <0 0x00a80000 0 0x4000>; 1786 clock-names = "se"; 1787 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1788 pinctrl-names = "default"; 1789 pinctrl-0 = <&qup_spi8_default>; 1790 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1791 #address-cells = <1>; 1792 #size-cells = <0>; 1793 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1794 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1795 interconnect-names = "qup-core", "qup-config"; 1796 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1797 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1798 dma-names = "tx", "rx"; 1799 status = "disabled"; 1800 }; 1801 1802 uart8: serial@a80000 { 1803 compatible = "qcom,geni-uart"; 1804 reg = <0 0x00a80000 0 0x4000>; 1805 clock-names = "se"; 1806 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1807 pinctrl-names = "default"; 1808 pinctrl-0 = <&qup_uart8_default>; 1809 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1810 power-domains = <&rpmhpd SDM845_CX>; 1811 operating-points-v2 = <&qup_opp_table>; 1812 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1813 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1814 interconnect-names = "qup-core", "qup-config"; 1815 status = "disabled"; 1816 }; 1817 1818 i2c9: i2c@a84000 { 1819 compatible = "qcom,geni-i2c"; 1820 reg = <0 0x00a84000 0 0x4000>; 1821 clock-names = "se"; 1822 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1823 pinctrl-names = "default"; 1824 pinctrl-0 = <&qup_i2c9_default>; 1825 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1826 #address-cells = <1>; 1827 #size-cells = <0>; 1828 power-domains = <&rpmhpd SDM845_CX>; 1829 operating-points-v2 = <&qup_opp_table>; 1830 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1831 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1832 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1833 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1834 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1835 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1836 dma-names = "tx", "rx"; 1837 status = "disabled"; 1838 }; 1839 1840 spi9: spi@a84000 { 1841 compatible = "qcom,geni-spi"; 1842 reg = <0 0x00a84000 0 0x4000>; 1843 clock-names = "se"; 1844 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1845 pinctrl-names = "default"; 1846 pinctrl-0 = <&qup_spi9_default>; 1847 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1848 #address-cells = <1>; 1849 #size-cells = <0>; 1850 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1851 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1852 interconnect-names = "qup-core", "qup-config"; 1853 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1854 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1855 dma-names = "tx", "rx"; 1856 status = "disabled"; 1857 }; 1858 1859 uart9: serial@a84000 { 1860 compatible = "qcom,geni-debug-uart"; 1861 reg = <0 0x00a84000 0 0x4000>; 1862 clock-names = "se"; 1863 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1864 pinctrl-names = "default"; 1865 pinctrl-0 = <&qup_uart9_default>; 1866 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1867 power-domains = <&rpmhpd SDM845_CX>; 1868 operating-points-v2 = <&qup_opp_table>; 1869 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1870 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1871 interconnect-names = "qup-core", "qup-config"; 1872 status = "disabled"; 1873 }; 1874 1875 i2c10: i2c@a88000 { 1876 compatible = "qcom,geni-i2c"; 1877 reg = <0 0x00a88000 0 0x4000>; 1878 clock-names = "se"; 1879 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1880 pinctrl-names = "default"; 1881 pinctrl-0 = <&qup_i2c10_default>; 1882 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1883 #address-cells = <1>; 1884 #size-cells = <0>; 1885 power-domains = <&rpmhpd SDM845_CX>; 1886 operating-points-v2 = <&qup_opp_table>; 1887 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1888 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1889 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1890 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1891 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1892 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1893 dma-names = "tx", "rx"; 1894 status = "disabled"; 1895 }; 1896 1897 spi10: spi@a88000 { 1898 compatible = "qcom,geni-spi"; 1899 reg = <0 0x00a88000 0 0x4000>; 1900 clock-names = "se"; 1901 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1902 pinctrl-names = "default"; 1903 pinctrl-0 = <&qup_spi10_default>; 1904 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1905 #address-cells = <1>; 1906 #size-cells = <0>; 1907 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1908 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1909 interconnect-names = "qup-core", "qup-config"; 1910 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1911 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1912 dma-names = "tx", "rx"; 1913 status = "disabled"; 1914 }; 1915 1916 uart10: serial@a88000 { 1917 compatible = "qcom,geni-uart"; 1918 reg = <0 0x00a88000 0 0x4000>; 1919 clock-names = "se"; 1920 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1921 pinctrl-names = "default"; 1922 pinctrl-0 = <&qup_uart10_default>; 1923 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1924 power-domains = <&rpmhpd SDM845_CX>; 1925 operating-points-v2 = <&qup_opp_table>; 1926 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1927 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1928 interconnect-names = "qup-core", "qup-config"; 1929 status = "disabled"; 1930 }; 1931 1932 i2c11: i2c@a8c000 { 1933 compatible = "qcom,geni-i2c"; 1934 reg = <0 0x00a8c000 0 0x4000>; 1935 clock-names = "se"; 1936 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1937 pinctrl-names = "default"; 1938 pinctrl-0 = <&qup_i2c11_default>; 1939 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1940 #address-cells = <1>; 1941 #size-cells = <0>; 1942 power-domains = <&rpmhpd SDM845_CX>; 1943 operating-points-v2 = <&qup_opp_table>; 1944 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1945 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1946 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1947 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1948 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1949 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1950 dma-names = "tx", "rx"; 1951 status = "disabled"; 1952 }; 1953 1954 spi11: spi@a8c000 { 1955 compatible = "qcom,geni-spi"; 1956 reg = <0 0x00a8c000 0 0x4000>; 1957 clock-names = "se"; 1958 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1959 pinctrl-names = "default"; 1960 pinctrl-0 = <&qup_spi11_default>; 1961 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1962 #address-cells = <1>; 1963 #size-cells = <0>; 1964 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1965 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1966 interconnect-names = "qup-core", "qup-config"; 1967 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1968 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1969 dma-names = "tx", "rx"; 1970 status = "disabled"; 1971 }; 1972 1973 uart11: serial@a8c000 { 1974 compatible = "qcom,geni-uart"; 1975 reg = <0 0x00a8c000 0 0x4000>; 1976 clock-names = "se"; 1977 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1978 pinctrl-names = "default"; 1979 pinctrl-0 = <&qup_uart11_default>; 1980 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1981 power-domains = <&rpmhpd SDM845_CX>; 1982 operating-points-v2 = <&qup_opp_table>; 1983 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1984 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1985 interconnect-names = "qup-core", "qup-config"; 1986 status = "disabled"; 1987 }; 1988 1989 i2c12: i2c@a90000 { 1990 compatible = "qcom,geni-i2c"; 1991 reg = <0 0x00a90000 0 0x4000>; 1992 clock-names = "se"; 1993 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1994 pinctrl-names = "default"; 1995 pinctrl-0 = <&qup_i2c12_default>; 1996 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1997 #address-cells = <1>; 1998 #size-cells = <0>; 1999 power-domains = <&rpmhpd SDM845_CX>; 2000 operating-points-v2 = <&qup_opp_table>; 2001 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2002 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2003 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2004 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2005 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 2006 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 2007 dma-names = "tx", "rx"; 2008 status = "disabled"; 2009 }; 2010 2011 spi12: spi@a90000 { 2012 compatible = "qcom,geni-spi"; 2013 reg = <0 0x00a90000 0 0x4000>; 2014 clock-names = "se"; 2015 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2016 pinctrl-names = "default"; 2017 pinctrl-0 = <&qup_spi12_default>; 2018 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2019 #address-cells = <1>; 2020 #size-cells = <0>; 2021 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2022 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2023 interconnect-names = "qup-core", "qup-config"; 2024 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 2025 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2026 dma-names = "tx", "rx"; 2027 status = "disabled"; 2028 }; 2029 2030 uart12: serial@a90000 { 2031 compatible = "qcom,geni-uart"; 2032 reg = <0 0x00a90000 0 0x4000>; 2033 clock-names = "se"; 2034 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2035 pinctrl-names = "default"; 2036 pinctrl-0 = <&qup_uart12_default>; 2037 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2038 power-domains = <&rpmhpd SDM845_CX>; 2039 operating-points-v2 = <&qup_opp_table>; 2040 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2041 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2042 interconnect-names = "qup-core", "qup-config"; 2043 status = "disabled"; 2044 }; 2045 2046 i2c13: i2c@a94000 { 2047 compatible = "qcom,geni-i2c"; 2048 reg = <0 0x00a94000 0 0x4000>; 2049 clock-names = "se"; 2050 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2051 pinctrl-names = "default"; 2052 pinctrl-0 = <&qup_i2c13_default>; 2053 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2054 #address-cells = <1>; 2055 #size-cells = <0>; 2056 power-domains = <&rpmhpd SDM845_CX>; 2057 operating-points-v2 = <&qup_opp_table>; 2058 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2059 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2060 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2061 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2062 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2063 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2064 dma-names = "tx", "rx"; 2065 status = "disabled"; 2066 }; 2067 2068 spi13: spi@a94000 { 2069 compatible = "qcom,geni-spi"; 2070 reg = <0 0x00a94000 0 0x4000>; 2071 clock-names = "se"; 2072 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2073 pinctrl-names = "default"; 2074 pinctrl-0 = <&qup_spi13_default>; 2075 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2076 #address-cells = <1>; 2077 #size-cells = <0>; 2078 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2079 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2080 interconnect-names = "qup-core", "qup-config"; 2081 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2082 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2083 dma-names = "tx", "rx"; 2084 status = "disabled"; 2085 }; 2086 2087 uart13: serial@a94000 { 2088 compatible = "qcom,geni-uart"; 2089 reg = <0 0x00a94000 0 0x4000>; 2090 clock-names = "se"; 2091 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2092 pinctrl-names = "default"; 2093 pinctrl-0 = <&qup_uart13_default>; 2094 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2095 power-domains = <&rpmhpd SDM845_CX>; 2096 operating-points-v2 = <&qup_opp_table>; 2097 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2098 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2099 interconnect-names = "qup-core", "qup-config"; 2100 status = "disabled"; 2101 }; 2102 2103 i2c14: i2c@a98000 { 2104 compatible = "qcom,geni-i2c"; 2105 reg = <0 0x00a98000 0 0x4000>; 2106 clock-names = "se"; 2107 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2108 pinctrl-names = "default"; 2109 pinctrl-0 = <&qup_i2c14_default>; 2110 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2111 #address-cells = <1>; 2112 #size-cells = <0>; 2113 power-domains = <&rpmhpd SDM845_CX>; 2114 operating-points-v2 = <&qup_opp_table>; 2115 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2116 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2117 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2118 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2119 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2120 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2121 dma-names = "tx", "rx"; 2122 status = "disabled"; 2123 }; 2124 2125 spi14: spi@a98000 { 2126 compatible = "qcom,geni-spi"; 2127 reg = <0 0x00a98000 0 0x4000>; 2128 clock-names = "se"; 2129 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2130 pinctrl-names = "default"; 2131 pinctrl-0 = <&qup_spi14_default>; 2132 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2133 #address-cells = <1>; 2134 #size-cells = <0>; 2135 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2136 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2137 interconnect-names = "qup-core", "qup-config"; 2138 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2139 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2140 dma-names = "tx", "rx"; 2141 status = "disabled"; 2142 }; 2143 2144 uart14: serial@a98000 { 2145 compatible = "qcom,geni-uart"; 2146 reg = <0 0x00a98000 0 0x4000>; 2147 clock-names = "se"; 2148 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2149 pinctrl-names = "default"; 2150 pinctrl-0 = <&qup_uart14_default>; 2151 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2152 power-domains = <&rpmhpd SDM845_CX>; 2153 operating-points-v2 = <&qup_opp_table>; 2154 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2155 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2156 interconnect-names = "qup-core", "qup-config"; 2157 status = "disabled"; 2158 }; 2159 2160 i2c15: i2c@a9c000 { 2161 compatible = "qcom,geni-i2c"; 2162 reg = <0 0x00a9c000 0 0x4000>; 2163 clock-names = "se"; 2164 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2165 pinctrl-names = "default"; 2166 pinctrl-0 = <&qup_i2c15_default>; 2167 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2168 #address-cells = <1>; 2169 #size-cells = <0>; 2170 power-domains = <&rpmhpd SDM845_CX>; 2171 operating-points-v2 = <&qup_opp_table>; 2172 status = "disabled"; 2173 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2174 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2175 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2176 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2177 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2178 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2179 dma-names = "tx", "rx"; 2180 }; 2181 2182 spi15: spi@a9c000 { 2183 compatible = "qcom,geni-spi"; 2184 reg = <0 0x00a9c000 0 0x4000>; 2185 clock-names = "se"; 2186 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2187 pinctrl-names = "default"; 2188 pinctrl-0 = <&qup_spi15_default>; 2189 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2190 #address-cells = <1>; 2191 #size-cells = <0>; 2192 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2193 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2194 interconnect-names = "qup-core", "qup-config"; 2195 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2196 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2197 dma-names = "tx", "rx"; 2198 status = "disabled"; 2199 }; 2200 2201 uart15: serial@a9c000 { 2202 compatible = "qcom,geni-uart"; 2203 reg = <0 0x00a9c000 0 0x4000>; 2204 clock-names = "se"; 2205 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2206 pinctrl-names = "default"; 2207 pinctrl-0 = <&qup_uart15_default>; 2208 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2209 power-domains = <&rpmhpd SDM845_CX>; 2210 operating-points-v2 = <&qup_opp_table>; 2211 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2212 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2213 interconnect-names = "qup-core", "qup-config"; 2214 status = "disabled"; 2215 }; 2216 }; 2217 2218 llcc: system-cache-controller@1100000 { 2219 compatible = "qcom,sdm845-llcc"; 2220 reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>, 2221 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, 2222 <0 0x01300000 0 0x50000>; 2223 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2224 "llcc3_base", "llcc_broadcast_base"; 2225 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2226 }; 2227 2228 dma@10a2000 { 2229 compatible = "qcom,sdm845-dcc", "qcom,dcc"; 2230 reg = <0x0 0x010a2000 0x0 0x1000>, 2231 <0x0 0x010ae000 0x0 0x2000>; 2232 }; 2233 2234 pmu@114a000 { 2235 compatible = "qcom,sdm845-llcc-bwmon"; 2236 reg = <0 0x0114a000 0 0x1000>; 2237 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 2238 interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>; 2239 2240 operating-points-v2 = <&llcc_bwmon_opp_table>; 2241 2242 llcc_bwmon_opp_table: opp-table { 2243 compatible = "operating-points-v2"; 2244 2245 /* 2246 * The interconnect path bandwidth taken from 2247 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc 2248 * interconnect. This also matches the 2249 * bandwidth table of qcom,llccbw (qcom,bw-tbl, 2250 * bus width: 4 bytes) from msm-4.9 downstream 2251 * kernel. 2252 */ 2253 opp-0 { 2254 opp-peak-kBps = <800000>; 2255 }; 2256 opp-1 { 2257 opp-peak-kBps = <1804000>; 2258 }; 2259 opp-2 { 2260 opp-peak-kBps = <3072000>; 2261 }; 2262 opp-3 { 2263 opp-peak-kBps = <5412000>; 2264 }; 2265 opp-4 { 2266 opp-peak-kBps = <7216000>; 2267 }; 2268 }; 2269 }; 2270 2271 pmu@1436400 { 2272 compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon"; 2273 reg = <0 0x01436400 0 0x600>; 2274 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 2275 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>; 2276 2277 operating-points-v2 = <&cpu_bwmon_opp_table>; 2278 2279 cpu_bwmon_opp_table: opp-table { 2280 compatible = "operating-points-v2"; 2281 2282 /* 2283 * The interconnect path bandwidth taken from 2284 * cpu4_opp_table bandwidth for OSM L3 2285 * interconnect. This also matches the OSM L3 2286 * from bandwidth table of qcom,cpu4-l3lat-mon 2287 * (qcom,core-dev-table, bus width: 16 bytes) 2288 * from msm-4.9 downstream kernel. 2289 */ 2290 opp-0 { 2291 opp-peak-kBps = <4800000>; 2292 }; 2293 opp-1 { 2294 opp-peak-kBps = <9216000>; 2295 }; 2296 opp-2 { 2297 opp-peak-kBps = <15052800>; 2298 }; 2299 opp-3 { 2300 opp-peak-kBps = <20889600>; 2301 }; 2302 opp-4 { 2303 opp-peak-kBps = <25497600>; 2304 }; 2305 }; 2306 }; 2307 2308 pcie0: pci@1c00000 { 2309 compatible = "qcom,pcie-sdm845"; 2310 reg = <0 0x01c00000 0 0x2000>, 2311 <0 0x60000000 0 0xf1d>, 2312 <0 0x60000f20 0 0xa8>, 2313 <0 0x60100000 0 0x100000>, 2314 <0 0x01c07000 0 0x1000>; 2315 reg-names = "parf", "dbi", "elbi", "config", "mhi"; 2316 device_type = "pci"; 2317 linux,pci-domain = <0>; 2318 bus-range = <0x00 0xff>; 2319 num-lanes = <1>; 2320 2321 #address-cells = <3>; 2322 #size-cells = <2>; 2323 2324 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 2325 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>; 2326 2327 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 2328 interrupt-names = "msi"; 2329 #interrupt-cells = <1>; 2330 interrupt-map-mask = <0 0 0 0x7>; 2331 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2332 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2333 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2334 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2335 2336 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2337 <&gcc GCC_PCIE_0_AUX_CLK>, 2338 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2339 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2340 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2341 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2342 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2343 clock-names = "pipe", 2344 "aux", 2345 "cfg", 2346 "bus_master", 2347 "bus_slave", 2348 "slave_q2a", 2349 "tbu"; 2350 2351 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, 2352 <0x100 &apps_smmu 0x1c11 0x1>, 2353 <0x200 &apps_smmu 0x1c12 0x1>, 2354 <0x300 &apps_smmu 0x1c13 0x1>, 2355 <0x400 &apps_smmu 0x1c14 0x1>, 2356 <0x500 &apps_smmu 0x1c15 0x1>, 2357 <0x600 &apps_smmu 0x1c16 0x1>, 2358 <0x700 &apps_smmu 0x1c17 0x1>, 2359 <0x800 &apps_smmu 0x1c18 0x1>, 2360 <0x900 &apps_smmu 0x1c19 0x1>, 2361 <0xa00 &apps_smmu 0x1c1a 0x1>, 2362 <0xb00 &apps_smmu 0x1c1b 0x1>, 2363 <0xc00 &apps_smmu 0x1c1c 0x1>, 2364 <0xd00 &apps_smmu 0x1c1d 0x1>, 2365 <0xe00 &apps_smmu 0x1c1e 0x1>, 2366 <0xf00 &apps_smmu 0x1c1f 0x1>; 2367 2368 resets = <&gcc GCC_PCIE_0_BCR>; 2369 reset-names = "pci"; 2370 2371 power-domains = <&gcc PCIE_0_GDSC>; 2372 2373 phys = <&pcie0_lane>; 2374 phy-names = "pciephy"; 2375 2376 status = "disabled"; 2377 }; 2378 2379 pcie0_phy: phy@1c06000 { 2380 compatible = "qcom,sdm845-qmp-pcie-phy"; 2381 reg = <0 0x01c06000 0 0x18c>; 2382 #address-cells = <2>; 2383 #size-cells = <2>; 2384 ranges; 2385 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2386 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2387 <&gcc GCC_PCIE_0_CLKREF_CLK>, 2388 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2389 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2390 2391 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2392 reset-names = "phy"; 2393 2394 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2395 assigned-clock-rates = <100000000>; 2396 2397 status = "disabled"; 2398 2399 pcie0_lane: phy@1c06200 { 2400 reg = <0 0x01c06200 0 0x128>, 2401 <0 0x01c06400 0 0x1fc>, 2402 <0 0x01c06800 0 0x218>, 2403 <0 0x01c06600 0 0x70>; 2404 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 2405 clock-names = "pipe0"; 2406 2407 #clock-cells = <0>; 2408 #phy-cells = <0>; 2409 clock-output-names = "pcie_0_pipe_clk"; 2410 }; 2411 }; 2412 2413 pcie1: pci@1c08000 { 2414 compatible = "qcom,pcie-sdm845"; 2415 reg = <0 0x01c08000 0 0x2000>, 2416 <0 0x40000000 0 0xf1d>, 2417 <0 0x40000f20 0 0xa8>, 2418 <0 0x40100000 0 0x100000>, 2419 <0 0x01c0c000 0 0x1000>; 2420 reg-names = "parf", "dbi", "elbi", "config", "mhi"; 2421 device_type = "pci"; 2422 linux,pci-domain = <1>; 2423 bus-range = <0x00 0xff>; 2424 num-lanes = <1>; 2425 2426 #address-cells = <3>; 2427 #size-cells = <2>; 2428 2429 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2430 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2431 2432 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 2433 interrupt-names = "msi"; 2434 #interrupt-cells = <1>; 2435 interrupt-map-mask = <0 0 0 0x7>; 2436 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2437 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2438 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2439 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2440 2441 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2442 <&gcc GCC_PCIE_1_AUX_CLK>, 2443 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2444 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2445 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2446 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2447 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2448 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2449 clock-names = "pipe", 2450 "aux", 2451 "cfg", 2452 "bus_master", 2453 "bus_slave", 2454 "slave_q2a", 2455 "ref", 2456 "tbu"; 2457 2458 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2459 assigned-clock-rates = <19200000>; 2460 2461 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2462 <0x100 &apps_smmu 0x1c01 0x1>, 2463 <0x200 &apps_smmu 0x1c02 0x1>, 2464 <0x300 &apps_smmu 0x1c03 0x1>, 2465 <0x400 &apps_smmu 0x1c04 0x1>, 2466 <0x500 &apps_smmu 0x1c05 0x1>, 2467 <0x600 &apps_smmu 0x1c06 0x1>, 2468 <0x700 &apps_smmu 0x1c07 0x1>, 2469 <0x800 &apps_smmu 0x1c08 0x1>, 2470 <0x900 &apps_smmu 0x1c09 0x1>, 2471 <0xa00 &apps_smmu 0x1c0a 0x1>, 2472 <0xb00 &apps_smmu 0x1c0b 0x1>, 2473 <0xc00 &apps_smmu 0x1c0c 0x1>, 2474 <0xd00 &apps_smmu 0x1c0d 0x1>, 2475 <0xe00 &apps_smmu 0x1c0e 0x1>, 2476 <0xf00 &apps_smmu 0x1c0f 0x1>; 2477 2478 resets = <&gcc GCC_PCIE_1_BCR>; 2479 reset-names = "pci"; 2480 2481 power-domains = <&gcc PCIE_1_GDSC>; 2482 2483 phys = <&pcie1_lane>; 2484 phy-names = "pciephy"; 2485 2486 status = "disabled"; 2487 }; 2488 2489 pcie1_phy: phy@1c0a000 { 2490 compatible = "qcom,sdm845-qhp-pcie-phy"; 2491 reg = <0 0x01c0a000 0 0x800>; 2492 #address-cells = <2>; 2493 #size-cells = <2>; 2494 ranges; 2495 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2496 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2497 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2498 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2499 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2500 2501 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2502 reset-names = "phy"; 2503 2504 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2505 assigned-clock-rates = <100000000>; 2506 2507 status = "disabled"; 2508 2509 pcie1_lane: phy@1c06200 { 2510 reg = <0 0x01c0a800 0 0x800>, 2511 <0 0x01c0a800 0 0x800>, 2512 <0 0x01c0b800 0 0x400>; 2513 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2514 clock-names = "pipe0"; 2515 2516 #clock-cells = <0>; 2517 #phy-cells = <0>; 2518 clock-output-names = "pcie_1_pipe_clk"; 2519 }; 2520 }; 2521 2522 mem_noc: interconnect@1380000 { 2523 compatible = "qcom,sdm845-mem-noc"; 2524 reg = <0 0x01380000 0 0x27200>; 2525 #interconnect-cells = <2>; 2526 qcom,bcm-voters = <&apps_bcm_voter>; 2527 }; 2528 2529 dc_noc: interconnect@14e0000 { 2530 compatible = "qcom,sdm845-dc-noc"; 2531 reg = <0 0x014e0000 0 0x400>; 2532 #interconnect-cells = <2>; 2533 qcom,bcm-voters = <&apps_bcm_voter>; 2534 }; 2535 2536 config_noc: interconnect@1500000 { 2537 compatible = "qcom,sdm845-config-noc"; 2538 reg = <0 0x01500000 0 0x5080>; 2539 #interconnect-cells = <2>; 2540 qcom,bcm-voters = <&apps_bcm_voter>; 2541 }; 2542 2543 system_noc: interconnect@1620000 { 2544 compatible = "qcom,sdm845-system-noc"; 2545 reg = <0 0x01620000 0 0x18080>; 2546 #interconnect-cells = <2>; 2547 qcom,bcm-voters = <&apps_bcm_voter>; 2548 }; 2549 2550 aggre1_noc: interconnect@16e0000 { 2551 compatible = "qcom,sdm845-aggre1-noc"; 2552 reg = <0 0x016e0000 0 0x15080>; 2553 #interconnect-cells = <2>; 2554 qcom,bcm-voters = <&apps_bcm_voter>; 2555 }; 2556 2557 aggre2_noc: interconnect@1700000 { 2558 compatible = "qcom,sdm845-aggre2-noc"; 2559 reg = <0 0x01700000 0 0x1f300>; 2560 #interconnect-cells = <2>; 2561 qcom,bcm-voters = <&apps_bcm_voter>; 2562 }; 2563 2564 mmss_noc: interconnect@1740000 { 2565 compatible = "qcom,sdm845-mmss-noc"; 2566 reg = <0 0x01740000 0 0x1c100>; 2567 #interconnect-cells = <2>; 2568 qcom,bcm-voters = <&apps_bcm_voter>; 2569 }; 2570 2571 ufs_mem_hc: ufshc@1d84000 { 2572 compatible = "qcom,sdm845-ufshc", "qcom,ufshc", 2573 "jedec,ufs-2.0"; 2574 reg = <0 0x01d84000 0 0x2500>, 2575 <0 0x01d90000 0 0x8000>; 2576 reg-names = "std", "ice"; 2577 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2578 phys = <&ufs_mem_phy_lanes>; 2579 phy-names = "ufsphy"; 2580 lanes-per-direction = <2>; 2581 power-domains = <&gcc UFS_PHY_GDSC>; 2582 #reset-cells = <1>; 2583 resets = <&gcc GCC_UFS_PHY_BCR>; 2584 reset-names = "rst"; 2585 2586 iommus = <&apps_smmu 0x100 0xf>; 2587 2588 clock-names = 2589 "core_clk", 2590 "bus_aggr_clk", 2591 "iface_clk", 2592 "core_clk_unipro", 2593 "ref_clk", 2594 "tx_lane0_sync_clk", 2595 "rx_lane0_sync_clk", 2596 "rx_lane1_sync_clk", 2597 "ice_core_clk"; 2598 clocks = 2599 <&gcc GCC_UFS_PHY_AXI_CLK>, 2600 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2601 <&gcc GCC_UFS_PHY_AHB_CLK>, 2602 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2603 <&rpmhcc RPMH_CXO_CLK>, 2604 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2605 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2606 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2607 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2608 freq-table-hz = 2609 <50000000 200000000>, 2610 <0 0>, 2611 <0 0>, 2612 <37500000 150000000>, 2613 <0 0>, 2614 <0 0>, 2615 <0 0>, 2616 <0 0>, 2617 <75000000 300000000>; 2618 2619 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>, 2620 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 2621 interconnect-names = "ufs-ddr", "cpu-ufs"; 2622 2623 status = "disabled"; 2624 }; 2625 2626 ufs_mem_phy: phy@1d87000 { 2627 compatible = "qcom,sdm845-qmp-ufs-phy"; 2628 reg = <0 0x01d87000 0 0x18c>; 2629 #address-cells = <2>; 2630 #size-cells = <2>; 2631 ranges; 2632 clock-names = "ref", 2633 "ref_aux"; 2634 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 2635 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2636 2637 resets = <&ufs_mem_hc 0>; 2638 reset-names = "ufsphy"; 2639 status = "disabled"; 2640 2641 ufs_mem_phy_lanes: phy@1d87400 { 2642 reg = <0 0x01d87400 0 0x108>, 2643 <0 0x01d87600 0 0x1e0>, 2644 <0 0x01d87c00 0 0x1dc>, 2645 <0 0x01d87800 0 0x108>, 2646 <0 0x01d87a00 0 0x1e0>; 2647 #phy-cells = <0>; 2648 }; 2649 }; 2650 2651 cryptobam: dma-controller@1dc4000 { 2652 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2653 reg = <0 0x01dc4000 0 0x24000>; 2654 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2655 clocks = <&rpmhcc RPMH_CE_CLK>; 2656 clock-names = "bam_clk"; 2657 #dma-cells = <1>; 2658 qcom,ee = <0>; 2659 qcom,controlled-remotely; 2660 iommus = <&apps_smmu 0x704 0x1>, 2661 <&apps_smmu 0x706 0x1>, 2662 <&apps_smmu 0x714 0x1>, 2663 <&apps_smmu 0x716 0x1>; 2664 }; 2665 2666 crypto: crypto@1dfa000 { 2667 compatible = "qcom,crypto-v5.4"; 2668 reg = <0 0x01dfa000 0 0x6000>; 2669 clocks = <&gcc GCC_CE1_AHB_CLK>, 2670 <&gcc GCC_CE1_AXI_CLK>, 2671 <&rpmhcc RPMH_CE_CLK>; 2672 clock-names = "iface", "bus", "core"; 2673 dmas = <&cryptobam 6>, <&cryptobam 7>; 2674 dma-names = "rx", "tx"; 2675 iommus = <&apps_smmu 0x704 0x1>, 2676 <&apps_smmu 0x706 0x1>, 2677 <&apps_smmu 0x714 0x1>, 2678 <&apps_smmu 0x716 0x1>; 2679 }; 2680 2681 ipa: ipa@1e40000 { 2682 compatible = "qcom,sdm845-ipa"; 2683 2684 iommus = <&apps_smmu 0x720 0x0>, 2685 <&apps_smmu 0x722 0x0>; 2686 reg = <0 0x01e40000 0 0x7000>, 2687 <0 0x01e47000 0 0x2000>, 2688 <0 0x01e04000 0 0x2c000>; 2689 reg-names = "ipa-reg", 2690 "ipa-shared", 2691 "gsi"; 2692 2693 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 2694 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2695 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2696 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2697 interrupt-names = "ipa", 2698 "gsi", 2699 "ipa-clock-query", 2700 "ipa-setup-ready"; 2701 2702 clocks = <&rpmhcc RPMH_IPA_CLK>; 2703 clock-names = "core"; 2704 2705 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>, 2706 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 2707 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2708 interconnect-names = "memory", 2709 "imem", 2710 "config"; 2711 2712 qcom,smem-states = <&ipa_smp2p_out 0>, 2713 <&ipa_smp2p_out 1>; 2714 qcom,smem-state-names = "ipa-clock-enabled-valid", 2715 "ipa-clock-enabled"; 2716 2717 status = "disabled"; 2718 }; 2719 2720 tcsr_mutex: hwlock@1f40000 { 2721 compatible = "qcom,tcsr-mutex"; 2722 reg = <0 0x01f40000 0 0x20000>; 2723 #hwlock-cells = <1>; 2724 }; 2725 2726 tcsr_regs_1: syscon@1f60000 { 2727 compatible = "qcom,sdm845-tcsr", "syscon"; 2728 reg = <0 0x01f60000 0 0x20000>; 2729 }; 2730 2731 tlmm: pinctrl@3400000 { 2732 compatible = "qcom,sdm845-pinctrl"; 2733 reg = <0 0x03400000 0 0xc00000>; 2734 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2735 gpio-controller; 2736 #gpio-cells = <2>; 2737 interrupt-controller; 2738 #interrupt-cells = <2>; 2739 gpio-ranges = <&tlmm 0 0 151>; 2740 wakeup-parent = <&pdc_intc>; 2741 2742 cci0_default: cci0-default-state { 2743 /* SDA, SCL */ 2744 pins = "gpio17", "gpio18"; 2745 function = "cci_i2c"; 2746 2747 bias-pull-up; 2748 drive-strength = <2>; /* 2 mA */ 2749 }; 2750 2751 cci0_sleep: cci0-sleep-state { 2752 /* SDA, SCL */ 2753 pins = "gpio17", "gpio18"; 2754 function = "cci_i2c"; 2755 2756 drive-strength = <2>; /* 2 mA */ 2757 bias-pull-down; 2758 }; 2759 2760 cci1_default: cci1-default-state { 2761 /* SDA, SCL */ 2762 pins = "gpio19", "gpio20"; 2763 function = "cci_i2c"; 2764 2765 bias-pull-up; 2766 drive-strength = <2>; /* 2 mA */ 2767 }; 2768 2769 cci1_sleep: cci1-sleep-state { 2770 /* SDA, SCL */ 2771 pins = "gpio19", "gpio20"; 2772 function = "cci_i2c"; 2773 2774 drive-strength = <2>; /* 2 mA */ 2775 bias-pull-down; 2776 }; 2777 2778 qspi_clk: qspi-clk-state { 2779 pins = "gpio95"; 2780 function = "qspi_clk"; 2781 }; 2782 2783 qspi_cs0: qspi-cs0-state { 2784 pins = "gpio90"; 2785 function = "qspi_cs"; 2786 }; 2787 2788 qspi_cs1: qspi-cs1-state { 2789 pins = "gpio89"; 2790 function = "qspi_cs"; 2791 }; 2792 2793 qspi_data0: qspi-data0-state { 2794 pins = "gpio91"; 2795 function = "qspi_data"; 2796 }; 2797 2798 qspi_data1: qspi-data1-state { 2799 pins = "gpio92"; 2800 function = "qspi_data"; 2801 }; 2802 2803 qspi_data23: qspi-data23-state { 2804 pins = "gpio93", "gpio94"; 2805 function = "qspi_data"; 2806 }; 2807 2808 qup_i2c0_default: qup-i2c0-default-state { 2809 pins = "gpio0", "gpio1"; 2810 function = "qup0"; 2811 }; 2812 2813 qup_i2c1_default: qup-i2c1-default-state { 2814 pins = "gpio17", "gpio18"; 2815 function = "qup1"; 2816 }; 2817 2818 qup_i2c2_default: qup-i2c2-default-state { 2819 pins = "gpio27", "gpio28"; 2820 function = "qup2"; 2821 }; 2822 2823 qup_i2c3_default: qup-i2c3-default-state { 2824 pins = "gpio41", "gpio42"; 2825 function = "qup3"; 2826 }; 2827 2828 qup_i2c4_default: qup-i2c4-default-state { 2829 pins = "gpio89", "gpio90"; 2830 function = "qup4"; 2831 }; 2832 2833 qup_i2c5_default: qup-i2c5-default-state { 2834 pins = "gpio85", "gpio86"; 2835 function = "qup5"; 2836 }; 2837 2838 qup_i2c6_default: qup-i2c6-default-state { 2839 pins = "gpio45", "gpio46"; 2840 function = "qup6"; 2841 }; 2842 2843 qup_i2c7_default: qup-i2c7-default-state { 2844 pins = "gpio93", "gpio94"; 2845 function = "qup7"; 2846 }; 2847 2848 qup_i2c8_default: qup-i2c8-default-state { 2849 pins = "gpio65", "gpio66"; 2850 function = "qup8"; 2851 }; 2852 2853 qup_i2c9_default: qup-i2c9-default-state { 2854 pins = "gpio6", "gpio7"; 2855 function = "qup9"; 2856 }; 2857 2858 qup_i2c10_default: qup-i2c10-default-state { 2859 pins = "gpio55", "gpio56"; 2860 function = "qup10"; 2861 }; 2862 2863 qup_i2c11_default: qup-i2c11-default-state { 2864 pins = "gpio31", "gpio32"; 2865 function = "qup11"; 2866 }; 2867 2868 qup_i2c12_default: qup-i2c12-default-state { 2869 pins = "gpio49", "gpio50"; 2870 function = "qup12"; 2871 }; 2872 2873 qup_i2c13_default: qup-i2c13-default-state { 2874 pins = "gpio105", "gpio106"; 2875 function = "qup13"; 2876 }; 2877 2878 qup_i2c14_default: qup-i2c14-default-state { 2879 pins = "gpio33", "gpio34"; 2880 function = "qup14"; 2881 }; 2882 2883 qup_i2c15_default: qup-i2c15-default-state { 2884 pins = "gpio81", "gpio82"; 2885 function = "qup15"; 2886 }; 2887 2888 qup_spi0_default: qup-spi0-default-state { 2889 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2890 function = "qup0"; 2891 }; 2892 2893 qup_spi1_default: qup-spi1-default-state { 2894 pins = "gpio17", "gpio18", "gpio19", "gpio20"; 2895 function = "qup1"; 2896 }; 2897 2898 qup_spi2_default: qup-spi2-default-state { 2899 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2900 function = "qup2"; 2901 }; 2902 2903 qup_spi3_default: qup-spi3-default-state { 2904 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 2905 function = "qup3"; 2906 }; 2907 2908 qup_spi4_default: qup-spi4-default-state { 2909 pins = "gpio89", "gpio90", "gpio91", "gpio92"; 2910 function = "qup4"; 2911 }; 2912 2913 qup_spi5_default: qup-spi5-default-state { 2914 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 2915 function = "qup5"; 2916 }; 2917 2918 qup_spi6_default: qup-spi6-default-state { 2919 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 2920 function = "qup6"; 2921 }; 2922 2923 qup_spi7_default: qup-spi7-default-state { 2924 pins = "gpio93", "gpio94", "gpio95", "gpio96"; 2925 function = "qup7"; 2926 }; 2927 2928 qup_spi8_default: qup-spi8-default-state { 2929 pins = "gpio65", "gpio66", "gpio67", "gpio68"; 2930 function = "qup8"; 2931 }; 2932 2933 qup_spi9_default: qup-spi9-default-state { 2934 pins = "gpio6", "gpio7", "gpio4", "gpio5"; 2935 function = "qup9"; 2936 }; 2937 2938 qup_spi10_default: qup-spi10-default-state { 2939 pins = "gpio55", "gpio56", "gpio53", "gpio54"; 2940 function = "qup10"; 2941 }; 2942 2943 qup_spi11_default: qup-spi11-default-state { 2944 pins = "gpio31", "gpio32", "gpio33", "gpio34"; 2945 function = "qup11"; 2946 }; 2947 2948 qup_spi12_default: qup-spi12-default-state { 2949 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 2950 function = "qup12"; 2951 }; 2952 2953 qup_spi13_default: qup-spi13-default-state { 2954 pins = "gpio105", "gpio106", "gpio107", "gpio108"; 2955 function = "qup13"; 2956 }; 2957 2958 qup_spi14_default: qup-spi14-default-state { 2959 pins = "gpio33", "gpio34", "gpio31", "gpio32"; 2960 function = "qup14"; 2961 }; 2962 2963 qup_spi15_default: qup-spi15-default-state { 2964 pins = "gpio81", "gpio82", "gpio83", "gpio84"; 2965 function = "qup15"; 2966 }; 2967 2968 qup_uart0_default: qup-uart0-default-state { 2969 qup_uart0_tx: tx-pins { 2970 pins = "gpio2"; 2971 function = "qup0"; 2972 }; 2973 2974 qup_uart0_rx: rx-pins { 2975 pins = "gpio3"; 2976 function = "qup0"; 2977 }; 2978 }; 2979 2980 qup_uart1_default: qup-uart1-default-state { 2981 qup_uart1_tx: tx-pins { 2982 pins = "gpio19"; 2983 function = "qup1"; 2984 }; 2985 2986 qup_uart1_rx: rx-pins { 2987 pins = "gpio20"; 2988 function = "qup1"; 2989 }; 2990 }; 2991 2992 qup_uart2_default: qup-uart2-default-state { 2993 qup_uart2_tx: tx-pins { 2994 pins = "gpio29"; 2995 function = "qup2"; 2996 }; 2997 2998 qup_uart2_rx: rx-pins { 2999 pins = "gpio30"; 3000 function = "qup2"; 3001 }; 3002 }; 3003 3004 qup_uart3_default: qup-uart3-default-state { 3005 qup_uart3_tx: tx-pins { 3006 pins = "gpio43"; 3007 function = "qup3"; 3008 }; 3009 3010 qup_uart3_rx: rx-pins { 3011 pins = "gpio44"; 3012 function = "qup3"; 3013 }; 3014 }; 3015 3016 qup_uart3_4pin: qup-uart3-4pin-state { 3017 qup_uart3_4pin_cts: cts-pins { 3018 pins = "gpio41"; 3019 function = "qup3"; 3020 }; 3021 3022 qup_uart3_4pin_rts_tx: rts-tx-pins { 3023 pins = "gpio42", "gpio43"; 3024 function = "qup3"; 3025 }; 3026 3027 qup_uart3_4pin_rx: rx-pins { 3028 pins = "gpio44"; 3029 function = "qup3"; 3030 }; 3031 }; 3032 3033 qup_uart4_default: qup-uart4-default-state { 3034 qup_uart4_tx: tx-pins { 3035 pins = "gpio91"; 3036 function = "qup4"; 3037 }; 3038 3039 qup_uart4_rx: rx-pins { 3040 pins = "gpio92"; 3041 function = "qup4"; 3042 }; 3043 }; 3044 3045 qup_uart5_default: qup-uart5-default-state { 3046 qup_uart5_tx: tx-pins { 3047 pins = "gpio87"; 3048 function = "qup5"; 3049 }; 3050 3051 qup_uart5_rx: rx-pins { 3052 pins = "gpio88"; 3053 function = "qup5"; 3054 }; 3055 }; 3056 3057 qup_uart6_default: qup-uart6-default-state { 3058 qup_uart6_tx: tx-pins { 3059 pins = "gpio47"; 3060 function = "qup6"; 3061 }; 3062 3063 qup_uart6_rx: rx-pins { 3064 pins = "gpio48"; 3065 function = "qup6"; 3066 }; 3067 }; 3068 3069 qup_uart6_4pin: qup-uart6-4pin-state { 3070 qup_uart6_4pin_cts: cts-pins { 3071 pins = "gpio45"; 3072 function = "qup6"; 3073 bias-pull-down; 3074 }; 3075 3076 qup_uart6_4pin_rts_tx: rts-tx-pins { 3077 pins = "gpio46", "gpio47"; 3078 function = "qup6"; 3079 drive-strength = <2>; 3080 bias-disable; 3081 }; 3082 3083 qup_uart6_4pin_rx: rx-pins { 3084 pins = "gpio48"; 3085 function = "qup6"; 3086 bias-pull-up; 3087 }; 3088 }; 3089 3090 qup_uart7_default: qup-uart7-default-state { 3091 qup_uart7_tx: tx-pins { 3092 pins = "gpio95"; 3093 function = "qup7"; 3094 }; 3095 3096 qup_uart7_rx: rx-pins { 3097 pins = "gpio96"; 3098 function = "qup7"; 3099 }; 3100 }; 3101 3102 qup_uart8_default: qup-uart8-default-state { 3103 qup_uart8_tx: tx-pins { 3104 pins = "gpio67"; 3105 function = "qup8"; 3106 }; 3107 3108 qup_uart8_rx: rx-pins { 3109 pins = "gpio68"; 3110 function = "qup8"; 3111 }; 3112 }; 3113 3114 qup_uart9_default: qup-uart9-default-state { 3115 qup_uart9_tx: tx-pins { 3116 pins = "gpio4"; 3117 function = "qup9"; 3118 }; 3119 3120 qup_uart9_rx: rx-pins { 3121 pins = "gpio5"; 3122 function = "qup9"; 3123 }; 3124 }; 3125 3126 qup_uart10_default: qup-uart10-default-state { 3127 qup_uart10_tx: tx-pins { 3128 pins = "gpio53"; 3129 function = "qup10"; 3130 }; 3131 3132 qup_uart10_rx: rx-pins { 3133 pins = "gpio54"; 3134 function = "qup10"; 3135 }; 3136 }; 3137 3138 qup_uart11_default: qup-uart11-default-state { 3139 qup_uart11_tx: tx-pins { 3140 pins = "gpio33"; 3141 function = "qup11"; 3142 }; 3143 3144 qup_uart11_rx: rx-pins { 3145 pins = "gpio34"; 3146 function = "qup11"; 3147 }; 3148 }; 3149 3150 qup_uart12_default: qup-uart12-default-state { 3151 qup_uart12_tx: tx-pins { 3152 pins = "gpio51"; 3153 function = "qup0"; 3154 }; 3155 3156 qup_uart12_rx: rx-pins { 3157 pins = "gpio52"; 3158 function = "qup0"; 3159 }; 3160 }; 3161 3162 qup_uart13_default: qup-uart13-default-state { 3163 qup_uart13_tx: tx-pins { 3164 pins = "gpio107"; 3165 function = "qup13"; 3166 }; 3167 3168 qup_uart13_rx: rx-pins { 3169 pins = "gpio108"; 3170 function = "qup13"; 3171 }; 3172 }; 3173 3174 qup_uart14_default: qup-uart14-default-state { 3175 qup_uart14_tx: tx-pins { 3176 pins = "gpio31"; 3177 function = "qup14"; 3178 }; 3179 3180 qup_uart14_rx: rx-pins { 3181 pins = "gpio32"; 3182 function = "qup14"; 3183 }; 3184 }; 3185 3186 qup_uart15_default: qup-uart15-default-state { 3187 qup_uart15_tx: tx-pins { 3188 pins = "gpio83"; 3189 function = "qup15"; 3190 }; 3191 3192 qup_uart15_rx: rx-pins { 3193 pins = "gpio84"; 3194 function = "qup15"; 3195 }; 3196 }; 3197 3198 quat_mi2s_sleep: quat-mi2s-sleep-state { 3199 pins = "gpio58", "gpio59"; 3200 function = "gpio"; 3201 drive-strength = <2>; 3202 bias-pull-down; 3203 }; 3204 3205 quat_mi2s_active: quat-mi2s-active-state { 3206 pins = "gpio58", "gpio59"; 3207 function = "qua_mi2s"; 3208 drive-strength = <8>; 3209 bias-disable; 3210 output-high; 3211 }; 3212 3213 quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state { 3214 pins = "gpio60"; 3215 function = "gpio"; 3216 drive-strength = <2>; 3217 bias-pull-down; 3218 }; 3219 3220 quat_mi2s_sd0_active: quat-mi2s-sd0-active-state { 3221 pins = "gpio60"; 3222 function = "qua_mi2s"; 3223 drive-strength = <8>; 3224 bias-disable; 3225 }; 3226 3227 quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state { 3228 pins = "gpio61"; 3229 function = "gpio"; 3230 drive-strength = <2>; 3231 bias-pull-down; 3232 }; 3233 3234 quat_mi2s_sd1_active: quat-mi2s-sd1-active-state { 3235 pins = "gpio61"; 3236 function = "qua_mi2s"; 3237 drive-strength = <8>; 3238 bias-disable; 3239 }; 3240 3241 quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state { 3242 pins = "gpio62"; 3243 function = "gpio"; 3244 drive-strength = <2>; 3245 bias-pull-down; 3246 }; 3247 3248 quat_mi2s_sd2_active: quat-mi2s-sd2-active-state { 3249 pins = "gpio62"; 3250 function = "qua_mi2s"; 3251 drive-strength = <8>; 3252 bias-disable; 3253 }; 3254 3255 quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state { 3256 pins = "gpio63"; 3257 function = "gpio"; 3258 drive-strength = <2>; 3259 bias-pull-down; 3260 }; 3261 3262 quat_mi2s_sd3_active: quat-mi2s-sd3-active-state { 3263 pins = "gpio63"; 3264 function = "qua_mi2s"; 3265 drive-strength = <8>; 3266 bias-disable; 3267 }; 3268 }; 3269 3270 mss_pil: remoteproc@4080000 { 3271 compatible = "qcom,sdm845-mss-pil"; 3272 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; 3273 reg-names = "qdsp6", "rmb"; 3274 3275 interrupts-extended = 3276 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 3277 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3278 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3279 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3280 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3281 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3282 interrupt-names = "wdog", "fatal", "ready", 3283 "handover", "stop-ack", 3284 "shutdown-ack"; 3285 3286 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 3287 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 3288 <&gcc GCC_BOOT_ROM_AHB_CLK>, 3289 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 3290 <&gcc GCC_MSS_SNOC_AXI_CLK>, 3291 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 3292 <&gcc GCC_PRNG_AHB_CLK>, 3293 <&rpmhcc RPMH_CXO_CLK>; 3294 clock-names = "iface", "bus", "mem", "gpll0_mss", 3295 "snoc_axi", "mnoc_axi", "prng", "xo"; 3296 3297 qcom,qmp = <&aoss_qmp>; 3298 3299 qcom,smem-states = <&modem_smp2p_out 0>; 3300 qcom,smem-state-names = "stop"; 3301 3302 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 3303 <&pdc_reset PDC_MODEM_SYNC_RESET>; 3304 reset-names = "mss_restart", "pdc_reset"; 3305 3306 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 3307 3308 power-domains = <&rpmhpd SDM845_CX>, 3309 <&rpmhpd SDM845_MX>, 3310 <&rpmhpd SDM845_MSS>; 3311 power-domain-names = "cx", "mx", "mss"; 3312 3313 status = "disabled"; 3314 3315 mba { 3316 memory-region = <&mba_region>; 3317 }; 3318 3319 mpss { 3320 memory-region = <&mpss_region>; 3321 }; 3322 3323 metadata { 3324 memory-region = <&mdata_mem>; 3325 }; 3326 3327 glink-edge { 3328 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 3329 label = "modem"; 3330 qcom,remote-pid = <1>; 3331 mboxes = <&apss_shared 12>; 3332 }; 3333 }; 3334 3335 gpucc: clock-controller@5090000 { 3336 compatible = "qcom,sdm845-gpucc"; 3337 reg = <0 0x05090000 0 0x9000>; 3338 #clock-cells = <1>; 3339 #reset-cells = <1>; 3340 #power-domain-cells = <1>; 3341 clocks = <&rpmhcc RPMH_CXO_CLK>, 3342 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3343 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3344 clock-names = "bi_tcxo", 3345 "gcc_gpu_gpll0_clk_src", 3346 "gcc_gpu_gpll0_div_clk_src"; 3347 }; 3348 3349 slpi_pas: remoteproc@5c00000 { 3350 compatible = "qcom,sdm845-slpi-pas"; 3351 reg = <0 0x5c00000 0 0x4000>; 3352 3353 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 3354 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3355 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3356 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3357 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3358 interrupt-names = "wdog", "fatal", "ready", 3359 "handover", "stop-ack"; 3360 3361 clocks = <&rpmhcc RPMH_CXO_CLK>; 3362 clock-names = "xo"; 3363 3364 qcom,qmp = <&aoss_qmp>; 3365 3366 power-domains = <&rpmhpd SDM845_CX>, 3367 <&rpmhpd SDM845_MX>; 3368 power-domain-names = "lcx", "lmx"; 3369 3370 memory-region = <&slpi_mem>; 3371 3372 qcom,smem-states = <&slpi_smp2p_out 0>; 3373 qcom,smem-state-names = "stop"; 3374 3375 status = "disabled"; 3376 3377 glink-edge { 3378 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 3379 label = "dsps"; 3380 qcom,remote-pid = <3>; 3381 mboxes = <&apss_shared 24>; 3382 3383 fastrpc { 3384 compatible = "qcom,fastrpc"; 3385 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3386 label = "sdsp"; 3387 qcom,non-secure-domain; 3388 qcom,vmids = <QCOM_SCM_VMID_HLOS QCOM_SCM_VMID_MSS_MSA 3389 QCOM_SCM_VMID_SSC_Q6 QCOM_SCM_VMID_ADSP_Q6>; 3390 memory-region = <&fastrpc_mem>; 3391 #address-cells = <1>; 3392 #size-cells = <0>; 3393 3394 compute-cb@0 { 3395 compatible = "qcom,fastrpc-compute-cb"; 3396 reg = <0>; 3397 }; 3398 }; 3399 }; 3400 }; 3401 3402 stm@6002000 { 3403 compatible = "arm,coresight-stm", "arm,primecell"; 3404 reg = <0 0x06002000 0 0x1000>, 3405 <0 0x16280000 0 0x180000>; 3406 reg-names = "stm-base", "stm-stimulus-base"; 3407 3408 clocks = <&aoss_qmp>; 3409 clock-names = "apb_pclk"; 3410 3411 out-ports { 3412 port { 3413 stm_out: endpoint { 3414 remote-endpoint = 3415 <&funnel0_in7>; 3416 }; 3417 }; 3418 }; 3419 }; 3420 3421 funnel@6041000 { 3422 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3423 reg = <0 0x06041000 0 0x1000>; 3424 3425 clocks = <&aoss_qmp>; 3426 clock-names = "apb_pclk"; 3427 3428 out-ports { 3429 port { 3430 funnel0_out: endpoint { 3431 remote-endpoint = 3432 <&merge_funnel_in0>; 3433 }; 3434 }; 3435 }; 3436 3437 in-ports { 3438 #address-cells = <1>; 3439 #size-cells = <0>; 3440 3441 port@7 { 3442 reg = <7>; 3443 funnel0_in7: endpoint { 3444 remote-endpoint = <&stm_out>; 3445 }; 3446 }; 3447 }; 3448 }; 3449 3450 funnel@6043000 { 3451 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3452 reg = <0 0x06043000 0 0x1000>; 3453 3454 clocks = <&aoss_qmp>; 3455 clock-names = "apb_pclk"; 3456 3457 out-ports { 3458 port { 3459 funnel2_out: endpoint { 3460 remote-endpoint = 3461 <&merge_funnel_in2>; 3462 }; 3463 }; 3464 }; 3465 3466 in-ports { 3467 #address-cells = <1>; 3468 #size-cells = <0>; 3469 3470 port@5 { 3471 reg = <5>; 3472 funnel2_in5: endpoint { 3473 remote-endpoint = 3474 <&apss_merge_funnel_out>; 3475 }; 3476 }; 3477 }; 3478 }; 3479 3480 funnel@6045000 { 3481 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3482 reg = <0 0x06045000 0 0x1000>; 3483 3484 clocks = <&aoss_qmp>; 3485 clock-names = "apb_pclk"; 3486 3487 out-ports { 3488 port { 3489 merge_funnel_out: endpoint { 3490 remote-endpoint = <&etf_in>; 3491 }; 3492 }; 3493 }; 3494 3495 in-ports { 3496 #address-cells = <1>; 3497 #size-cells = <0>; 3498 3499 port@0 { 3500 reg = <0>; 3501 merge_funnel_in0: endpoint { 3502 remote-endpoint = 3503 <&funnel0_out>; 3504 }; 3505 }; 3506 3507 port@2 { 3508 reg = <2>; 3509 merge_funnel_in2: endpoint { 3510 remote-endpoint = 3511 <&funnel2_out>; 3512 }; 3513 }; 3514 }; 3515 }; 3516 3517 replicator@6046000 { 3518 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3519 reg = <0 0x06046000 0 0x1000>; 3520 3521 clocks = <&aoss_qmp>; 3522 clock-names = "apb_pclk"; 3523 3524 out-ports { 3525 port { 3526 replicator_out: endpoint { 3527 remote-endpoint = <&etr_in>; 3528 }; 3529 }; 3530 }; 3531 3532 in-ports { 3533 port { 3534 replicator_in: endpoint { 3535 remote-endpoint = <&etf_out>; 3536 }; 3537 }; 3538 }; 3539 }; 3540 3541 etf@6047000 { 3542 compatible = "arm,coresight-tmc", "arm,primecell"; 3543 reg = <0 0x06047000 0 0x1000>; 3544 3545 clocks = <&aoss_qmp>; 3546 clock-names = "apb_pclk"; 3547 3548 out-ports { 3549 port { 3550 etf_out: endpoint { 3551 remote-endpoint = 3552 <&replicator_in>; 3553 }; 3554 }; 3555 }; 3556 3557 in-ports { 3558 #address-cells = <1>; 3559 #size-cells = <0>; 3560 3561 port@1 { 3562 reg = <1>; 3563 etf_in: endpoint { 3564 remote-endpoint = 3565 <&merge_funnel_out>; 3566 }; 3567 }; 3568 }; 3569 }; 3570 3571 etr@6048000 { 3572 compatible = "arm,coresight-tmc", "arm,primecell"; 3573 reg = <0 0x06048000 0 0x1000>; 3574 3575 clocks = <&aoss_qmp>; 3576 clock-names = "apb_pclk"; 3577 arm,scatter-gather; 3578 3579 in-ports { 3580 port { 3581 etr_in: endpoint { 3582 remote-endpoint = 3583 <&replicator_out>; 3584 }; 3585 }; 3586 }; 3587 }; 3588 3589 etm@7040000 { 3590 compatible = "arm,coresight-etm4x", "arm,primecell"; 3591 reg = <0 0x07040000 0 0x1000>; 3592 3593 cpu = <&CPU0>; 3594 3595 clocks = <&aoss_qmp>; 3596 clock-names = "apb_pclk"; 3597 arm,coresight-loses-context-with-cpu; 3598 3599 out-ports { 3600 port { 3601 etm0_out: endpoint { 3602 remote-endpoint = 3603 <&apss_funnel_in0>; 3604 }; 3605 }; 3606 }; 3607 }; 3608 3609 etm@7140000 { 3610 compatible = "arm,coresight-etm4x", "arm,primecell"; 3611 reg = <0 0x07140000 0 0x1000>; 3612 3613 cpu = <&CPU1>; 3614 3615 clocks = <&aoss_qmp>; 3616 clock-names = "apb_pclk"; 3617 arm,coresight-loses-context-with-cpu; 3618 3619 out-ports { 3620 port { 3621 etm1_out: endpoint { 3622 remote-endpoint = 3623 <&apss_funnel_in1>; 3624 }; 3625 }; 3626 }; 3627 }; 3628 3629 etm@7240000 { 3630 compatible = "arm,coresight-etm4x", "arm,primecell"; 3631 reg = <0 0x07240000 0 0x1000>; 3632 3633 cpu = <&CPU2>; 3634 3635 clocks = <&aoss_qmp>; 3636 clock-names = "apb_pclk"; 3637 arm,coresight-loses-context-with-cpu; 3638 3639 out-ports { 3640 port { 3641 etm2_out: endpoint { 3642 remote-endpoint = 3643 <&apss_funnel_in2>; 3644 }; 3645 }; 3646 }; 3647 }; 3648 3649 etm@7340000 { 3650 compatible = "arm,coresight-etm4x", "arm,primecell"; 3651 reg = <0 0x07340000 0 0x1000>; 3652 3653 cpu = <&CPU3>; 3654 3655 clocks = <&aoss_qmp>; 3656 clock-names = "apb_pclk"; 3657 arm,coresight-loses-context-with-cpu; 3658 3659 out-ports { 3660 port { 3661 etm3_out: endpoint { 3662 remote-endpoint = 3663 <&apss_funnel_in3>; 3664 }; 3665 }; 3666 }; 3667 }; 3668 3669 etm@7440000 { 3670 compatible = "arm,coresight-etm4x", "arm,primecell"; 3671 reg = <0 0x07440000 0 0x1000>; 3672 3673 cpu = <&CPU4>; 3674 3675 clocks = <&aoss_qmp>; 3676 clock-names = "apb_pclk"; 3677 arm,coresight-loses-context-with-cpu; 3678 3679 out-ports { 3680 port { 3681 etm4_out: endpoint { 3682 remote-endpoint = 3683 <&apss_funnel_in4>; 3684 }; 3685 }; 3686 }; 3687 }; 3688 3689 etm@7540000 { 3690 compatible = "arm,coresight-etm4x", "arm,primecell"; 3691 reg = <0 0x07540000 0 0x1000>; 3692 3693 cpu = <&CPU5>; 3694 3695 clocks = <&aoss_qmp>; 3696 clock-names = "apb_pclk"; 3697 arm,coresight-loses-context-with-cpu; 3698 3699 out-ports { 3700 port { 3701 etm5_out: endpoint { 3702 remote-endpoint = 3703 <&apss_funnel_in5>; 3704 }; 3705 }; 3706 }; 3707 }; 3708 3709 etm@7640000 { 3710 compatible = "arm,coresight-etm4x", "arm,primecell"; 3711 reg = <0 0x07640000 0 0x1000>; 3712 3713 cpu = <&CPU6>; 3714 3715 clocks = <&aoss_qmp>; 3716 clock-names = "apb_pclk"; 3717 arm,coresight-loses-context-with-cpu; 3718 3719 out-ports { 3720 port { 3721 etm6_out: endpoint { 3722 remote-endpoint = 3723 <&apss_funnel_in6>; 3724 }; 3725 }; 3726 }; 3727 }; 3728 3729 etm@7740000 { 3730 compatible = "arm,coresight-etm4x", "arm,primecell"; 3731 reg = <0 0x07740000 0 0x1000>; 3732 3733 cpu = <&CPU7>; 3734 3735 clocks = <&aoss_qmp>; 3736 clock-names = "apb_pclk"; 3737 arm,coresight-loses-context-with-cpu; 3738 3739 out-ports { 3740 port { 3741 etm7_out: endpoint { 3742 remote-endpoint = 3743 <&apss_funnel_in7>; 3744 }; 3745 }; 3746 }; 3747 }; 3748 3749 funnel@7800000 { /* APSS Funnel */ 3750 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3751 reg = <0 0x07800000 0 0x1000>; 3752 3753 clocks = <&aoss_qmp>; 3754 clock-names = "apb_pclk"; 3755 3756 out-ports { 3757 port { 3758 apss_funnel_out: endpoint { 3759 remote-endpoint = 3760 <&apss_merge_funnel_in>; 3761 }; 3762 }; 3763 }; 3764 3765 in-ports { 3766 #address-cells = <1>; 3767 #size-cells = <0>; 3768 3769 port@0 { 3770 reg = <0>; 3771 apss_funnel_in0: endpoint { 3772 remote-endpoint = 3773 <&etm0_out>; 3774 }; 3775 }; 3776 3777 port@1 { 3778 reg = <1>; 3779 apss_funnel_in1: endpoint { 3780 remote-endpoint = 3781 <&etm1_out>; 3782 }; 3783 }; 3784 3785 port@2 { 3786 reg = <2>; 3787 apss_funnel_in2: endpoint { 3788 remote-endpoint = 3789 <&etm2_out>; 3790 }; 3791 }; 3792 3793 port@3 { 3794 reg = <3>; 3795 apss_funnel_in3: endpoint { 3796 remote-endpoint = 3797 <&etm3_out>; 3798 }; 3799 }; 3800 3801 port@4 { 3802 reg = <4>; 3803 apss_funnel_in4: endpoint { 3804 remote-endpoint = 3805 <&etm4_out>; 3806 }; 3807 }; 3808 3809 port@5 { 3810 reg = <5>; 3811 apss_funnel_in5: endpoint { 3812 remote-endpoint = 3813 <&etm5_out>; 3814 }; 3815 }; 3816 3817 port@6 { 3818 reg = <6>; 3819 apss_funnel_in6: endpoint { 3820 remote-endpoint = 3821 <&etm6_out>; 3822 }; 3823 }; 3824 3825 port@7 { 3826 reg = <7>; 3827 apss_funnel_in7: endpoint { 3828 remote-endpoint = 3829 <&etm7_out>; 3830 }; 3831 }; 3832 }; 3833 }; 3834 3835 funnel@7810000 { 3836 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3837 reg = <0 0x07810000 0 0x1000>; 3838 3839 clocks = <&aoss_qmp>; 3840 clock-names = "apb_pclk"; 3841 3842 out-ports { 3843 port { 3844 apss_merge_funnel_out: endpoint { 3845 remote-endpoint = 3846 <&funnel2_in5>; 3847 }; 3848 }; 3849 }; 3850 3851 in-ports { 3852 port { 3853 apss_merge_funnel_in: endpoint { 3854 remote-endpoint = 3855 <&apss_funnel_out>; 3856 }; 3857 }; 3858 }; 3859 }; 3860 3861 sdhc_2: mmc@8804000 { 3862 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 3863 reg = <0 0x08804000 0 0x1000>; 3864 3865 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3866 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3867 interrupt-names = "hc_irq", "pwr_irq"; 3868 3869 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3870 <&gcc GCC_SDCC2_APPS_CLK>, 3871 <&rpmhcc RPMH_CXO_CLK>; 3872 clock-names = "iface", "core", "xo"; 3873 iommus = <&apps_smmu 0xa0 0xf>; 3874 power-domains = <&rpmhpd SDM845_CX>; 3875 operating-points-v2 = <&sdhc2_opp_table>; 3876 3877 status = "disabled"; 3878 3879 sdhc2_opp_table: opp-table { 3880 compatible = "operating-points-v2"; 3881 3882 opp-9600000 { 3883 opp-hz = /bits/ 64 <9600000>; 3884 required-opps = <&rpmhpd_opp_min_svs>; 3885 }; 3886 3887 opp-19200000 { 3888 opp-hz = /bits/ 64 <19200000>; 3889 required-opps = <&rpmhpd_opp_low_svs>; 3890 }; 3891 3892 opp-100000000 { 3893 opp-hz = /bits/ 64 <100000000>; 3894 required-opps = <&rpmhpd_opp_svs>; 3895 }; 3896 3897 opp-201500000 { 3898 opp-hz = /bits/ 64 <201500000>; 3899 required-opps = <&rpmhpd_opp_svs_l1>; 3900 }; 3901 }; 3902 }; 3903 3904 qspi: spi@88df000 { 3905 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 3906 reg = <0 0x088df000 0 0x600>; 3907 iommus = <&apps_smmu 0x160 0x0>; 3908 #address-cells = <1>; 3909 #size-cells = <0>; 3910 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3911 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3912 <&gcc GCC_QSPI_CORE_CLK>; 3913 clock-names = "iface", "core"; 3914 power-domains = <&rpmhpd SDM845_CX>; 3915 operating-points-v2 = <&qspi_opp_table>; 3916 status = "disabled"; 3917 }; 3918 3919 slim: slim-ngd@171c0000 { 3920 compatible = "qcom,slim-ngd-v2.1.0"; 3921 reg = <0 0x171c0000 0 0x2c000>; 3922 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 3923 3924 dmas = <&slimbam 3>, <&slimbam 4>; 3925 dma-names = "rx", "tx"; 3926 3927 iommus = <&apps_smmu 0x1806 0x0>; 3928 #address-cells = <1>; 3929 #size-cells = <0>; 3930 status = "disabled"; 3931 }; 3932 3933 lmh_cluster1: lmh@17d70800 { 3934 compatible = "qcom,sdm845-lmh"; 3935 reg = <0 0x17d70800 0 0x400>; 3936 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3937 cpus = <&CPU4>; 3938 qcom,lmh-temp-arm-millicelsius = <65000>; 3939 qcom,lmh-temp-low-millicelsius = <94500>; 3940 qcom,lmh-temp-high-millicelsius = <95000>; 3941 interrupt-controller; 3942 #interrupt-cells = <1>; 3943 }; 3944 3945 lmh_cluster0: lmh@17d78800 { 3946 compatible = "qcom,sdm845-lmh"; 3947 reg = <0 0x17d78800 0 0x400>; 3948 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3949 cpus = <&CPU0>; 3950 qcom,lmh-temp-arm-millicelsius = <65000>; 3951 qcom,lmh-temp-low-millicelsius = <94500>; 3952 qcom,lmh-temp-high-millicelsius = <95000>; 3953 interrupt-controller; 3954 #interrupt-cells = <1>; 3955 }; 3956 3957 usb_1_hsphy: phy@88e2000 { 3958 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3959 reg = <0 0x088e2000 0 0x400>; 3960 status = "disabled"; 3961 #phy-cells = <0>; 3962 3963 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3964 <&rpmhcc RPMH_CXO_CLK>; 3965 clock-names = "cfg_ahb", "ref"; 3966 3967 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3968 3969 nvmem-cells = <&qusb2p_hstx_trim>; 3970 }; 3971 3972 usb_2_hsphy: phy@88e3000 { 3973 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3974 reg = <0 0x088e3000 0 0x400>; 3975 status = "disabled"; 3976 #phy-cells = <0>; 3977 3978 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3979 <&rpmhcc RPMH_CXO_CLK>; 3980 clock-names = "cfg_ahb", "ref"; 3981 3982 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3983 3984 nvmem-cells = <&qusb2s_hstx_trim>; 3985 }; 3986 3987 usb_1_qmpphy: phy@88e9000 { 3988 compatible = "qcom,sdm845-qmp-usb3-dp-phy"; 3989 reg = <0 0x088e9000 0 0x18c>, 3990 <0 0x088e8000 0 0x38>, 3991 <0 0x088ea000 0 0x40>; 3992 status = "disabled"; 3993 #address-cells = <2>; 3994 #size-cells = <2>; 3995 ranges; 3996 3997 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3998 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3999 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 4000 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 4001 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 4002 4003 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 4004 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 4005 reset-names = "phy", "common"; 4006 4007 usb_1_ssphy: usb3-phy@88e9200 { 4008 reg = <0 0x088e9200 0 0x128>, 4009 <0 0x088e9400 0 0x200>, 4010 <0 0x088e9c00 0 0x218>, 4011 <0 0x088e9600 0 0x128>, 4012 <0 0x088e9800 0 0x200>, 4013 <0 0x088e9a00 0 0x100>; 4014 #clock-cells = <0>; 4015 #phy-cells = <0>; 4016 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4017 clock-names = "pipe0"; 4018 clock-output-names = "usb3_phy_pipe_clk_src"; 4019 }; 4020 4021 dp_phy: dp-phy@88ea200 { 4022 reg = <0 0x088ea200 0 0x200>, 4023 <0 0x088ea400 0 0x200>, 4024 <0 0x088eaa00 0 0x200>, 4025 <0 0x088ea600 0 0x200>, 4026 <0 0x088ea800 0 0x200>; 4027 #clock-cells = <1>; 4028 #phy-cells = <0>; 4029 }; 4030 }; 4031 4032 usb_2_qmpphy: phy@88eb000 { 4033 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 4034 reg = <0 0x088eb000 0 0x18c>; 4035 status = "disabled"; 4036 #address-cells = <2>; 4037 #size-cells = <2>; 4038 ranges; 4039 4040 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 4041 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 4042 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 4043 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 4044 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 4045 4046 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 4047 <&gcc GCC_USB3_PHY_SEC_BCR>; 4048 reset-names = "phy", "common"; 4049 4050 usb_2_ssphy: phy@88eb200 { 4051 reg = <0 0x088eb200 0 0x128>, 4052 <0 0x088eb400 0 0x1fc>, 4053 <0 0x088eb800 0 0x218>, 4054 <0 0x088eb600 0 0x70>; 4055 #clock-cells = <0>; 4056 #phy-cells = <0>; 4057 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 4058 clock-names = "pipe0"; 4059 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 4060 }; 4061 }; 4062 4063 usb_1: usb@a6f8800 { 4064 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 4065 reg = <0 0x0a6f8800 0 0x400>; 4066 status = "disabled"; 4067 #address-cells = <2>; 4068 #size-cells = <2>; 4069 ranges; 4070 dma-ranges; 4071 4072 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4073 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4074 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4075 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4076 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4077 clock-names = "cfg_noc", 4078 "core", 4079 "iface", 4080 "sleep", 4081 "mock_utmi"; 4082 4083 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4084 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4085 assigned-clock-rates = <19200000>, <150000000>; 4086 4087 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4088 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 4089 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 4090 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 4091 interrupt-names = "hs_phy_irq", "ss_phy_irq", 4092 "dm_hs_phy_irq", "dp_hs_phy_irq"; 4093 4094 power-domains = <&gcc USB30_PRIM_GDSC>; 4095 4096 resets = <&gcc GCC_USB30_PRIM_BCR>; 4097 4098 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>, 4099 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4100 interconnect-names = "usb-ddr", "apps-usb"; 4101 4102 usb_1_dwc3: usb@a600000 { 4103 compatible = "snps,dwc3"; 4104 reg = <0 0x0a600000 0 0xcd00>; 4105 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4106 iommus = <&apps_smmu 0x740 0>; 4107 snps,dis_u2_susphy_quirk; 4108 snps,dis_enblslpm_quirk; 4109 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 4110 phy-names = "usb2-phy", "usb3-phy"; 4111 }; 4112 }; 4113 4114 usb_2: usb@a8f8800 { 4115 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 4116 reg = <0 0x0a8f8800 0 0x400>; 4117 status = "disabled"; 4118 #address-cells = <2>; 4119 #size-cells = <2>; 4120 ranges; 4121 dma-ranges; 4122 4123 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4124 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4125 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4126 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4127 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 4128 clock-names = "cfg_noc", 4129 "core", 4130 "iface", 4131 "sleep", 4132 "mock_utmi"; 4133 4134 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4135 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4136 assigned-clock-rates = <19200000>, <150000000>; 4137 4138 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 4139 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 4140 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 4141 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 4142 interrupt-names = "hs_phy_irq", "ss_phy_irq", 4143 "dm_hs_phy_irq", "dp_hs_phy_irq"; 4144 4145 power-domains = <&gcc USB30_SEC_GDSC>; 4146 4147 resets = <&gcc GCC_USB30_SEC_BCR>; 4148 4149 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>, 4150 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 4151 interconnect-names = "usb-ddr", "apps-usb"; 4152 4153 usb_2_dwc3: usb@a800000 { 4154 compatible = "snps,dwc3"; 4155 reg = <0 0x0a800000 0 0xcd00>; 4156 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 4157 iommus = <&apps_smmu 0x760 0>; 4158 snps,dis_u2_susphy_quirk; 4159 snps,dis_enblslpm_quirk; 4160 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 4161 phy-names = "usb2-phy", "usb3-phy"; 4162 }; 4163 }; 4164 4165 venus: video-codec@aa00000 { 4166 compatible = "qcom,sdm845-venus-v2"; 4167 reg = <0 0x0aa00000 0 0xff000>; 4168 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4169 power-domains = <&videocc VENUS_GDSC>, 4170 <&videocc VCODEC0_GDSC>, 4171 <&videocc VCODEC1_GDSC>, 4172 <&rpmhpd SDM845_CX>; 4173 power-domain-names = "venus", "vcodec0", "vcodec1", "cx"; 4174 operating-points-v2 = <&venus_opp_table>; 4175 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 4176 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 4177 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 4178 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 4179 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>, 4180 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, 4181 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; 4182 clock-names = "core", "iface", "bus", 4183 "vcodec0_core", "vcodec0_bus", 4184 "vcodec1_core", "vcodec1_bus"; 4185 iommus = <&apps_smmu 0x10a0 0x8>, 4186 <&apps_smmu 0x10b0 0x0>; 4187 memory-region = <&venus_mem>; 4188 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>, 4189 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 4190 interconnect-names = "video-mem", "cpu-cfg"; 4191 4192 status = "disabled"; 4193 4194 video-core0 { 4195 compatible = "venus-decoder"; 4196 }; 4197 4198 video-core1 { 4199 compatible = "venus-encoder"; 4200 }; 4201 4202 venus_opp_table: opp-table { 4203 compatible = "operating-points-v2"; 4204 4205 opp-100000000 { 4206 opp-hz = /bits/ 64 <100000000>; 4207 required-opps = <&rpmhpd_opp_min_svs>; 4208 }; 4209 4210 opp-200000000 { 4211 opp-hz = /bits/ 64 <200000000>; 4212 required-opps = <&rpmhpd_opp_low_svs>; 4213 }; 4214 4215 opp-320000000 { 4216 opp-hz = /bits/ 64 <320000000>; 4217 required-opps = <&rpmhpd_opp_svs>; 4218 }; 4219 4220 opp-380000000 { 4221 opp-hz = /bits/ 64 <380000000>; 4222 required-opps = <&rpmhpd_opp_svs_l1>; 4223 }; 4224 4225 opp-444000000 { 4226 opp-hz = /bits/ 64 <444000000>; 4227 required-opps = <&rpmhpd_opp_nom>; 4228 }; 4229 4230 opp-533000097 { 4231 opp-hz = /bits/ 64 <533000097>; 4232 required-opps = <&rpmhpd_opp_turbo>; 4233 }; 4234 }; 4235 }; 4236 4237 videocc: clock-controller@ab00000 { 4238 compatible = "qcom,sdm845-videocc"; 4239 reg = <0 0x0ab00000 0 0x10000>; 4240 clocks = <&rpmhcc RPMH_CXO_CLK>; 4241 clock-names = "bi_tcxo"; 4242 #clock-cells = <1>; 4243 #power-domain-cells = <1>; 4244 #reset-cells = <1>; 4245 }; 4246 4247 camss: camss@acb3000 { 4248 compatible = "qcom,sdm845-camss"; 4249 4250 reg = <0 0x0acb3000 0 0x1000>, 4251 <0 0x0acba000 0 0x1000>, 4252 <0 0x0acc8000 0 0x1000>, 4253 <0 0x0ac65000 0 0x1000>, 4254 <0 0x0ac66000 0 0x1000>, 4255 <0 0x0ac67000 0 0x1000>, 4256 <0 0x0ac68000 0 0x1000>, 4257 <0 0x0acaf000 0 0x4000>, 4258 <0 0x0acb6000 0 0x4000>, 4259 <0 0x0acc4000 0 0x4000>; 4260 reg-names = "csid0", 4261 "csid1", 4262 "csid2", 4263 "csiphy0", 4264 "csiphy1", 4265 "csiphy2", 4266 "csiphy3", 4267 "vfe0", 4268 "vfe1", 4269 "vfe_lite"; 4270 4271 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 4272 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 4273 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 4274 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 4275 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 4276 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 4277 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 4278 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 4279 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 4280 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 4281 interrupt-names = "csid0", 4282 "csid1", 4283 "csid2", 4284 "csiphy0", 4285 "csiphy1", 4286 "csiphy2", 4287 "csiphy3", 4288 "vfe0", 4289 "vfe1", 4290 "vfe_lite"; 4291 4292 power-domains = <&clock_camcc IFE_0_GDSC>, 4293 <&clock_camcc IFE_1_GDSC>, 4294 <&clock_camcc TITAN_TOP_GDSC>; 4295 4296 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4297 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 4298 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, 4299 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, 4300 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, 4301 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, 4302 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, 4303 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, 4304 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, 4305 <&clock_camcc CAM_CC_CSIPHY0_CLK>, 4306 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, 4307 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, 4308 <&clock_camcc CAM_CC_CSIPHY1_CLK>, 4309 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, 4310 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, 4311 <&clock_camcc CAM_CC_CSIPHY2_CLK>, 4312 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, 4313 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, 4314 <&clock_camcc CAM_CC_CSIPHY3_CLK>, 4315 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, 4316 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, 4317 <&gcc GCC_CAMERA_AHB_CLK>, 4318 <&gcc GCC_CAMERA_AXI_CLK>, 4319 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4320 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4321 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, 4322 <&clock_camcc CAM_CC_IFE_0_CLK>, 4323 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4324 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, 4325 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, 4326 <&clock_camcc CAM_CC_IFE_1_CLK>, 4327 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4328 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, 4329 <&clock_camcc CAM_CC_IFE_LITE_CLK>, 4330 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4331 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>; 4332 clock-names = "camnoc_axi", 4333 "cpas_ahb", 4334 "cphy_rx_src", 4335 "csi0", 4336 "csi0_src", 4337 "csi1", 4338 "csi1_src", 4339 "csi2", 4340 "csi2_src", 4341 "csiphy0", 4342 "csiphy0_timer", 4343 "csiphy0_timer_src", 4344 "csiphy1", 4345 "csiphy1_timer", 4346 "csiphy1_timer_src", 4347 "csiphy2", 4348 "csiphy2_timer", 4349 "csiphy2_timer_src", 4350 "csiphy3", 4351 "csiphy3_timer", 4352 "csiphy3_timer_src", 4353 "gcc_camera_ahb", 4354 "gcc_camera_axi", 4355 "slow_ahb_src", 4356 "soc_ahb", 4357 "vfe0_axi", 4358 "vfe0", 4359 "vfe0_cphy_rx", 4360 "vfe0_src", 4361 "vfe1_axi", 4362 "vfe1", 4363 "vfe1_cphy_rx", 4364 "vfe1_src", 4365 "vfe_lite", 4366 "vfe_lite_cphy_rx", 4367 "vfe_lite_src"; 4368 4369 iommus = <&apps_smmu 0x0808 0x0>, 4370 <&apps_smmu 0x0810 0x8>, 4371 <&apps_smmu 0x0c08 0x0>, 4372 <&apps_smmu 0x0c10 0x8>; 4373 4374 status = "disabled"; 4375 4376 ports { 4377 #address-cells = <1>; 4378 #size-cells = <0>; 4379 4380 port@0 { 4381 reg = <0>; 4382 }; 4383 4384 port@1 { 4385 reg = <1>; 4386 }; 4387 4388 port@2 { 4389 reg = <2>; 4390 }; 4391 4392 port@3 { 4393 reg = <3>; 4394 }; 4395 }; 4396 }; 4397 4398 cci: cci@ac4a000 { 4399 compatible = "qcom,sdm845-cci", "qcom,msm8996-cci"; 4400 #address-cells = <1>; 4401 #size-cells = <0>; 4402 4403 reg = <0 0x0ac4a000 0 0x4000>; 4404 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4405 power-domains = <&clock_camcc TITAN_TOP_GDSC>; 4406 4407 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4408 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4409 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4410 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 4411 <&clock_camcc CAM_CC_CCI_CLK>, 4412 <&clock_camcc CAM_CC_CCI_CLK_SRC>; 4413 clock-names = "camnoc_axi", 4414 "soc_ahb", 4415 "slow_ahb_src", 4416 "cpas_ahb", 4417 "cci", 4418 "cci_src"; 4419 4420 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4421 <&clock_camcc CAM_CC_CCI_CLK>; 4422 assigned-clock-rates = <80000000>, <37500000>; 4423 4424 pinctrl-names = "default", "sleep"; 4425 pinctrl-0 = <&cci0_default &cci1_default>; 4426 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 4427 4428 status = "disabled"; 4429 4430 cci_i2c0: i2c-bus@0 { 4431 reg = <0>; 4432 clock-frequency = <1000000>; 4433 #address-cells = <1>; 4434 #size-cells = <0>; 4435 }; 4436 4437 cci_i2c1: i2c-bus@1 { 4438 reg = <1>; 4439 clock-frequency = <1000000>; 4440 #address-cells = <1>; 4441 #size-cells = <0>; 4442 }; 4443 }; 4444 4445 clock_camcc: clock-controller@ad00000 { 4446 compatible = "qcom,sdm845-camcc"; 4447 reg = <0 0x0ad00000 0 0x10000>; 4448 #clock-cells = <1>; 4449 #reset-cells = <1>; 4450 #power-domain-cells = <1>; 4451 clocks = <&rpmhcc RPMH_CXO_CLK>; 4452 clock-names = "bi_tcxo"; 4453 }; 4454 4455 mdss: display-subsystem@ae00000 { 4456 compatible = "qcom,sdm845-mdss"; 4457 reg = <0 0x0ae00000 0 0x1000>; 4458 reg-names = "mdss"; 4459 4460 power-domains = <&dispcc MDSS_GDSC>; 4461 4462 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4463 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4464 clock-names = "iface", "core"; 4465 4466 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4467 interrupt-controller; 4468 #interrupt-cells = <1>; 4469 4470 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>, 4471 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>; 4472 interconnect-names = "mdp0-mem", "mdp1-mem"; 4473 4474 iommus = <&apps_smmu 0x880 0x8>, 4475 <&apps_smmu 0xc80 0x8>; 4476 4477 status = "disabled"; 4478 4479 #address-cells = <2>; 4480 #size-cells = <2>; 4481 ranges; 4482 4483 mdss_mdp: display-controller@ae01000 { 4484 compatible = "qcom,sdm845-dpu"; 4485 reg = <0 0x0ae01000 0 0x8f000>, 4486 <0 0x0aeb0000 0 0x2008>; 4487 reg-names = "mdp", "vbif"; 4488 4489 clocks = <&gcc GCC_DISP_AXI_CLK>, 4490 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4491 <&dispcc DISP_CC_MDSS_AXI_CLK>, 4492 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4493 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4494 clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; 4495 4496 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4497 assigned-clock-rates = <19200000>; 4498 operating-points-v2 = <&mdp_opp_table>; 4499 power-domains = <&rpmhpd SDM845_CX>; 4500 4501 interrupt-parent = <&mdss>; 4502 interrupts = <0>; 4503 4504 ports { 4505 #address-cells = <1>; 4506 #size-cells = <0>; 4507 4508 port@0 { 4509 reg = <0>; 4510 dpu_intf0_out: endpoint { 4511 remote-endpoint = <&dp_in>; 4512 }; 4513 }; 4514 4515 port@1 { 4516 reg = <1>; 4517 dpu_intf1_out: endpoint { 4518 remote-endpoint = <&mdss_dsi0_in>; 4519 }; 4520 }; 4521 4522 port@2 { 4523 reg = <2>; 4524 dpu_intf2_out: endpoint { 4525 remote-endpoint = <&mdss_dsi1_in>; 4526 }; 4527 }; 4528 }; 4529 4530 mdp_opp_table: opp-table { 4531 compatible = "operating-points-v2"; 4532 4533 opp-19200000 { 4534 opp-hz = /bits/ 64 <19200000>; 4535 required-opps = <&rpmhpd_opp_min_svs>; 4536 }; 4537 4538 opp-171428571 { 4539 opp-hz = /bits/ 64 <171428571>; 4540 required-opps = <&rpmhpd_opp_low_svs>; 4541 }; 4542 4543 opp-344000000 { 4544 opp-hz = /bits/ 64 <344000000>; 4545 required-opps = <&rpmhpd_opp_svs_l1>; 4546 }; 4547 4548 opp-430000000 { 4549 opp-hz = /bits/ 64 <430000000>; 4550 required-opps = <&rpmhpd_opp_nom>; 4551 }; 4552 }; 4553 }; 4554 4555 mdss_dp: displayport-controller@ae90000 { 4556 status = "disabled"; 4557 compatible = "qcom,sdm845-dp"; 4558 4559 reg = <0 0x0ae90000 0 0x200>, 4560 <0 0x0ae90200 0 0x200>, 4561 <0 0x0ae90400 0 0x600>, 4562 <0 0x0ae90a00 0 0x600>, 4563 <0 0x0ae91000 0 0x600>; 4564 4565 interrupt-parent = <&mdss>; 4566 interrupts = <12>; 4567 4568 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4569 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4570 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4571 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4572 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4573 clock-names = "core_iface", "core_aux", "ctrl_link", 4574 "ctrl_link_iface", "stream_pixel"; 4575 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4576 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4577 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4578 phys = <&dp_phy>; 4579 phy-names = "dp"; 4580 4581 operating-points-v2 = <&dp_opp_table>; 4582 power-domains = <&rpmhpd SDM845_CX>; 4583 4584 ports { 4585 #address-cells = <1>; 4586 #size-cells = <0>; 4587 port@0 { 4588 reg = <0>; 4589 dp_in: endpoint { 4590 remote-endpoint = <&dpu_intf0_out>; 4591 }; 4592 }; 4593 4594 port@1 { 4595 reg = <1>; 4596 dp_out: endpoint { }; 4597 }; 4598 }; 4599 4600 dp_opp_table: opp-table { 4601 compatible = "operating-points-v2"; 4602 4603 opp-162000000 { 4604 opp-hz = /bits/ 64 <162000000>; 4605 required-opps = <&rpmhpd_opp_low_svs>; 4606 }; 4607 4608 opp-270000000 { 4609 opp-hz = /bits/ 64 <270000000>; 4610 required-opps = <&rpmhpd_opp_svs>; 4611 }; 4612 4613 opp-540000000 { 4614 opp-hz = /bits/ 64 <540000000>; 4615 required-opps = <&rpmhpd_opp_svs_l1>; 4616 }; 4617 4618 opp-810000000 { 4619 opp-hz = /bits/ 64 <810000000>; 4620 required-opps = <&rpmhpd_opp_nom>; 4621 }; 4622 }; 4623 }; 4624 4625 mdss_dsi0: dsi@ae94000 { 4626 compatible = "qcom,sdm845-dsi-ctrl", 4627 "qcom,mdss-dsi-ctrl"; 4628 reg = <0 0x0ae94000 0 0x400>; 4629 reg-names = "dsi_ctrl"; 4630 4631 interrupt-parent = <&mdss>; 4632 interrupts = <4>; 4633 4634 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4635 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4636 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4637 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4638 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4639 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4640 clock-names = "byte", 4641 "byte_intf", 4642 "pixel", 4643 "core", 4644 "iface", 4645 "bus"; 4646 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4647 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 4648 4649 operating-points-v2 = <&dsi_opp_table>; 4650 power-domains = <&rpmhpd SDM845_CX>; 4651 4652 phys = <&mdss_dsi0_phy>; 4653 4654 status = "disabled"; 4655 4656 #address-cells = <1>; 4657 #size-cells = <0>; 4658 4659 ports { 4660 #address-cells = <1>; 4661 #size-cells = <0>; 4662 4663 port@0 { 4664 reg = <0>; 4665 mdss_dsi0_in: endpoint { 4666 remote-endpoint = <&dpu_intf1_out>; 4667 }; 4668 }; 4669 4670 port@1 { 4671 reg = <1>; 4672 mdss_dsi0_out: endpoint { 4673 }; 4674 }; 4675 }; 4676 }; 4677 4678 mdss_dsi0_phy: phy@ae94400 { 4679 compatible = "qcom,dsi-phy-10nm"; 4680 reg = <0 0x0ae94400 0 0x200>, 4681 <0 0x0ae94600 0 0x280>, 4682 <0 0x0ae94a00 0 0x1e0>; 4683 reg-names = "dsi_phy", 4684 "dsi_phy_lane", 4685 "dsi_pll"; 4686 4687 #clock-cells = <1>; 4688 #phy-cells = <0>; 4689 4690 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4691 <&rpmhcc RPMH_CXO_CLK>; 4692 clock-names = "iface", "ref"; 4693 4694 status = "disabled"; 4695 }; 4696 4697 mdss_dsi1: dsi@ae96000 { 4698 compatible = "qcom,sdm845-dsi-ctrl", 4699 "qcom,mdss-dsi-ctrl"; 4700 reg = <0 0x0ae96000 0 0x400>; 4701 reg-names = "dsi_ctrl"; 4702 4703 interrupt-parent = <&mdss>; 4704 interrupts = <5>; 4705 4706 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4707 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4708 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4709 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4710 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4711 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4712 clock-names = "byte", 4713 "byte_intf", 4714 "pixel", 4715 "core", 4716 "iface", 4717 "bus"; 4718 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4719 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 4720 4721 operating-points-v2 = <&dsi_opp_table>; 4722 power-domains = <&rpmhpd SDM845_CX>; 4723 4724 phys = <&mdss_dsi1_phy>; 4725 4726 status = "disabled"; 4727 4728 #address-cells = <1>; 4729 #size-cells = <0>; 4730 4731 ports { 4732 #address-cells = <1>; 4733 #size-cells = <0>; 4734 4735 port@0 { 4736 reg = <0>; 4737 mdss_dsi1_in: endpoint { 4738 remote-endpoint = <&dpu_intf2_out>; 4739 }; 4740 }; 4741 4742 port@1 { 4743 reg = <1>; 4744 mdss_dsi1_out: endpoint { 4745 }; 4746 }; 4747 }; 4748 }; 4749 4750 mdss_dsi1_phy: phy@ae96400 { 4751 compatible = "qcom,dsi-phy-10nm"; 4752 reg = <0 0x0ae96400 0 0x200>, 4753 <0 0x0ae96600 0 0x280>, 4754 <0 0x0ae96a00 0 0x10e>; 4755 reg-names = "dsi_phy", 4756 "dsi_phy_lane", 4757 "dsi_pll"; 4758 4759 #clock-cells = <1>; 4760 #phy-cells = <0>; 4761 4762 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4763 <&rpmhcc RPMH_CXO_CLK>; 4764 clock-names = "iface", "ref"; 4765 4766 status = "disabled"; 4767 }; 4768 }; 4769 4770 gpu: gpu@5000000 { 4771 compatible = "qcom,adreno-630.2", "qcom,adreno"; 4772 4773 reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>; 4774 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 4775 4776 /* 4777 * Look ma, no clocks! The GPU clocks and power are 4778 * controlled entirely by the GMU 4779 */ 4780 4781 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4782 4783 iommus = <&adreno_smmu 0>; 4784 4785 operating-points-v2 = <&gpu_opp_table>; 4786 4787 qcom,gmu = <&gmu>; 4788 4789 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; 4790 interconnect-names = "gfx-mem"; 4791 4792 status = "disabled"; 4793 4794 gpu_opp_table: opp-table { 4795 compatible = "operating-points-v2"; 4796 4797 opp-710000000 { 4798 opp-hz = /bits/ 64 <710000000>; 4799 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4800 opp-peak-kBps = <7216000>; 4801 }; 4802 4803 opp-675000000 { 4804 opp-hz = /bits/ 64 <675000000>; 4805 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4806 opp-peak-kBps = <7216000>; 4807 }; 4808 4809 opp-596000000 { 4810 opp-hz = /bits/ 64 <596000000>; 4811 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4812 opp-peak-kBps = <6220000>; 4813 }; 4814 4815 opp-520000000 { 4816 opp-hz = /bits/ 64 <520000000>; 4817 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4818 opp-peak-kBps = <6220000>; 4819 }; 4820 4821 opp-414000000 { 4822 opp-hz = /bits/ 64 <414000000>; 4823 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4824 opp-peak-kBps = <4068000>; 4825 }; 4826 4827 opp-342000000 { 4828 opp-hz = /bits/ 64 <342000000>; 4829 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4830 opp-peak-kBps = <2724000>; 4831 }; 4832 4833 opp-257000000 { 4834 opp-hz = /bits/ 64 <257000000>; 4835 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4836 opp-peak-kBps = <1648000>; 4837 }; 4838 }; 4839 }; 4840 4841 adreno_smmu: iommu@5040000 { 4842 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 4843 reg = <0 0x05040000 0 0x10000>; 4844 #iommu-cells = <1>; 4845 #global-interrupts = <2>; 4846 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 4847 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 4848 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 4849 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 4850 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 4851 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 4852 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 4853 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 4854 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 4855 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 4856 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4857 <&gcc GCC_GPU_CFG_AHB_CLK>; 4858 clock-names = "bus", "iface"; 4859 4860 power-domains = <&gpucc GPU_CX_GDSC>; 4861 }; 4862 4863 gmu: gmu@506a000 { 4864 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 4865 4866 reg = <0 0x0506a000 0 0x30000>, 4867 <0 0x0b280000 0 0x10000>, 4868 <0 0x0b480000 0 0x10000>; 4869 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 4870 4871 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4872 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4873 interrupt-names = "hfi", "gmu"; 4874 4875 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 4876 <&gpucc GPU_CC_CXO_CLK>, 4877 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4878 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 4879 clock-names = "gmu", "cxo", "axi", "memnoc"; 4880 4881 power-domains = <&gpucc GPU_CX_GDSC>, 4882 <&gpucc GPU_GX_GDSC>; 4883 power-domain-names = "cx", "gx"; 4884 4885 iommus = <&adreno_smmu 5>; 4886 4887 operating-points-v2 = <&gmu_opp_table>; 4888 4889 status = "disabled"; 4890 4891 gmu_opp_table: opp-table { 4892 compatible = "operating-points-v2"; 4893 4894 opp-400000000 { 4895 opp-hz = /bits/ 64 <400000000>; 4896 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4897 }; 4898 4899 opp-200000000 { 4900 opp-hz = /bits/ 64 <200000000>; 4901 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4902 }; 4903 }; 4904 }; 4905 4906 dispcc: clock-controller@af00000 { 4907 compatible = "qcom,sdm845-dispcc"; 4908 reg = <0 0x0af00000 0 0x10000>; 4909 clocks = <&rpmhcc RPMH_CXO_CLK>, 4910 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 4911 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 4912 <&mdss_dsi0_phy 0>, 4913 <&mdss_dsi0_phy 1>, 4914 <&mdss_dsi1_phy 0>, 4915 <&mdss_dsi1_phy 1>, 4916 <&dp_phy 0>, 4917 <&dp_phy 1>; 4918 clock-names = "bi_tcxo", 4919 "gcc_disp_gpll0_clk_src", 4920 "gcc_disp_gpll0_div_clk_src", 4921 "dsi0_phy_pll_out_byteclk", 4922 "dsi0_phy_pll_out_dsiclk", 4923 "dsi1_phy_pll_out_byteclk", 4924 "dsi1_phy_pll_out_dsiclk", 4925 "dp_link_clk_divsel_ten", 4926 "dp_vco_divided_clk_src_mux"; 4927 #clock-cells = <1>; 4928 #reset-cells = <1>; 4929 #power-domain-cells = <1>; 4930 }; 4931 4932 pdc_intc: interrupt-controller@b220000 { 4933 compatible = "qcom,sdm845-pdc", "qcom,pdc"; 4934 reg = <0 0x0b220000 0 0x30000>; 4935 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; 4936 #interrupt-cells = <2>; 4937 interrupt-parent = <&intc>; 4938 interrupt-controller; 4939 }; 4940 4941 pdc_reset: reset-controller@b2e0000 { 4942 compatible = "qcom,sdm845-pdc-global"; 4943 reg = <0 0x0b2e0000 0 0x20000>; 4944 #reset-cells = <1>; 4945 }; 4946 4947 tsens0: thermal-sensor@c263000 { 4948 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4949 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4950 <0 0x0c222000 0 0x1ff>; /* SROT */ 4951 #qcom,sensors = <13>; 4952 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4953 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4954 interrupt-names = "uplow", "critical"; 4955 #thermal-sensor-cells = <1>; 4956 }; 4957 4958 tsens1: thermal-sensor@c265000 { 4959 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4960 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4961 <0 0x0c223000 0 0x1ff>; /* SROT */ 4962 #qcom,sensors = <8>; 4963 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4964 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4965 interrupt-names = "uplow", "critical"; 4966 #thermal-sensor-cells = <1>; 4967 }; 4968 4969 aoss_reset: reset-controller@c2a0000 { 4970 compatible = "qcom,sdm845-aoss-cc"; 4971 reg = <0 0x0c2a0000 0 0x31000>; 4972 #reset-cells = <1>; 4973 }; 4974 4975 aoss_qmp: power-management@c300000 { 4976 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; 4977 reg = <0 0x0c300000 0 0x400>; 4978 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 4979 mboxes = <&apss_shared 0>; 4980 4981 #clock-cells = <0>; 4982 4983 cx_cdev: cx { 4984 #cooling-cells = <2>; 4985 }; 4986 4987 ebi_cdev: ebi { 4988 #cooling-cells = <2>; 4989 }; 4990 }; 4991 4992 sram@c3f0000 { 4993 compatible = "qcom,sdm845-rpmh-stats"; 4994 reg = <0 0x0c3f0000 0 0x400>; 4995 }; 4996 4997 spmi_bus: spmi@c440000 { 4998 compatible = "qcom,spmi-pmic-arb"; 4999 reg = <0 0x0c440000 0 0x1100>, 5000 <0 0x0c600000 0 0x2000000>, 5001 <0 0x0e600000 0 0x100000>, 5002 <0 0x0e700000 0 0xa0000>, 5003 <0 0x0c40a000 0 0x26000>; 5004 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 5005 interrupt-names = "periph_irq"; 5006 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 5007 qcom,ee = <0>; 5008 qcom,channel = <0>; 5009 #address-cells = <2>; 5010 #size-cells = <0>; 5011 interrupt-controller; 5012 #interrupt-cells = <4>; 5013 }; 5014 5015 sram@146bf000 { 5016 compatible = "qcom,sdm845-imem", "syscon", "simple-mfd"; 5017 reg = <0 0x146bf000 0 0x1000>; 5018 5019 #address-cells = <1>; 5020 #size-cells = <1>; 5021 5022 ranges = <0 0 0x146bf000 0x1000>; 5023 5024 pil-reloc@94c { 5025 compatible = "qcom,pil-reloc-info"; 5026 reg = <0x94c 0xc8>; 5027 }; 5028 }; 5029 5030 apps_smmu: iommu@15000000 { 5031 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; 5032 reg = <0 0x15000000 0 0x80000>; 5033 #iommu-cells = <2>; 5034 #global-interrupts = <1>; 5035 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5036 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5037 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5038 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5039 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5040 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5041 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5042 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5043 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5044 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5045 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5046 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5047 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5048 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5049 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5050 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5051 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5052 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5053 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5054 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5055 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5056 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5057 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5058 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5059 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5060 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5061 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5062 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5063 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5064 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5065 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5066 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5067 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5068 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5069 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5070 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5071 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5072 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5073 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5074 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5075 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5076 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5077 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5078 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5079 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5080 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5081 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5082 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5083 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5084 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5085 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5086 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5087 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5088 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5089 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5090 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5091 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5092 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5093 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5094 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5095 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5096 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5097 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5098 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5099 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 5100 }; 5101 5102 lpasscc: clock-controller@17014000 { 5103 compatible = "qcom,sdm845-lpasscc"; 5104 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; 5105 reg-names = "cc", "qdsp6ss"; 5106 #clock-cells = <1>; 5107 status = "disabled"; 5108 }; 5109 5110 gladiator_noc: interconnect@17900000 { 5111 compatible = "qcom,sdm845-gladiator-noc"; 5112 reg = <0 0x17900000 0 0xd080>; 5113 #interconnect-cells = <2>; 5114 qcom,bcm-voters = <&apps_bcm_voter>; 5115 }; 5116 5117 watchdog@17980000 { 5118 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; 5119 reg = <0 0x17980000 0 0x1000>; 5120 clocks = <&sleep_clk>; 5121 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5122 }; 5123 5124 apss_shared: mailbox@17990000 { 5125 compatible = "qcom,sdm845-apss-shared"; 5126 reg = <0 0x17990000 0 0x1000>; 5127 #mbox-cells = <1>; 5128 }; 5129 5130 apps_rsc: rsc@179c0000 { 5131 label = "apps_rsc"; 5132 compatible = "qcom,rpmh-rsc"; 5133 reg = <0 0x179c0000 0 0x10000>, 5134 <0 0x179d0000 0 0x10000>, 5135 <0 0x179e0000 0 0x10000>; 5136 reg-names = "drv-0", "drv-1", "drv-2"; 5137 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5140 qcom,tcs-offset = <0xd00>; 5141 qcom,drv-id = <2>; 5142 qcom,tcs-config = <ACTIVE_TCS 2>, 5143 <SLEEP_TCS 3>, 5144 <WAKE_TCS 3>, 5145 <CONTROL_TCS 1>; 5146 power-domains = <&CLUSTER_PD>; 5147 5148 apps_bcm_voter: bcm-voter { 5149 compatible = "qcom,bcm-voter"; 5150 }; 5151 5152 rpmhcc: clock-controller { 5153 compatible = "qcom,sdm845-rpmh-clk"; 5154 #clock-cells = <1>; 5155 clock-names = "xo"; 5156 clocks = <&xo_board>; 5157 }; 5158 5159 rpmhpd: power-controller { 5160 compatible = "qcom,sdm845-rpmhpd"; 5161 #power-domain-cells = <1>; 5162 operating-points-v2 = <&rpmhpd_opp_table>; 5163 5164 rpmhpd_opp_table: opp-table { 5165 compatible = "operating-points-v2"; 5166 5167 rpmhpd_opp_ret: opp1 { 5168 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5169 }; 5170 5171 rpmhpd_opp_min_svs: opp2 { 5172 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5173 }; 5174 5175 rpmhpd_opp_low_svs: opp3 { 5176 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5177 }; 5178 5179 rpmhpd_opp_svs: opp4 { 5180 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5181 }; 5182 5183 rpmhpd_opp_svs_l1: opp5 { 5184 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5185 }; 5186 5187 rpmhpd_opp_nom: opp6 { 5188 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5189 }; 5190 5191 rpmhpd_opp_nom_l1: opp7 { 5192 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5193 }; 5194 5195 rpmhpd_opp_nom_l2: opp8 { 5196 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5197 }; 5198 5199 rpmhpd_opp_turbo: opp9 { 5200 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5201 }; 5202 5203 rpmhpd_opp_turbo_l1: opp10 { 5204 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5205 }; 5206 }; 5207 }; 5208 }; 5209 5210 intc: interrupt-controller@17a00000 { 5211 compatible = "arm,gic-v3"; 5212 #address-cells = <2>; 5213 #size-cells = <2>; 5214 ranges; 5215 #interrupt-cells = <3>; 5216 interrupt-controller; 5217 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5218 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5219 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5220 5221 msi-controller@17a40000 { 5222 compatible = "arm,gic-v3-its"; 5223 msi-controller; 5224 #msi-cells = <1>; 5225 reg = <0 0x17a40000 0 0x20000>; 5226 status = "disabled"; 5227 }; 5228 }; 5229 5230 slimbam: dma-controller@17184000 { 5231 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 5232 qcom,controlled-remotely; 5233 reg = <0 0x17184000 0 0x2a000>; 5234 num-channels = <31>; 5235 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 5236 #dma-cells = <1>; 5237 qcom,ee = <1>; 5238 qcom,num-ees = <2>; 5239 iommus = <&apps_smmu 0x1806 0x0>; 5240 }; 5241 5242 timer@17c90000 { 5243 #address-cells = <1>; 5244 #size-cells = <1>; 5245 ranges = <0 0 0 0x20000000>; 5246 compatible = "arm,armv7-timer-mem"; 5247 reg = <0 0x17c90000 0 0x1000>; 5248 5249 frame@17ca0000 { 5250 frame-number = <0>; 5251 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 5252 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5253 reg = <0x17ca0000 0x1000>, 5254 <0x17cb0000 0x1000>; 5255 }; 5256 5257 frame@17cc0000 { 5258 frame-number = <1>; 5259 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 5260 reg = <0x17cc0000 0x1000>; 5261 status = "disabled"; 5262 }; 5263 5264 frame@17cd0000 { 5265 frame-number = <2>; 5266 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5267 reg = <0x17cd0000 0x1000>; 5268 status = "disabled"; 5269 }; 5270 5271 frame@17ce0000 { 5272 frame-number = <3>; 5273 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5274 reg = <0x17ce0000 0x1000>; 5275 status = "disabled"; 5276 }; 5277 5278 frame@17cf0000 { 5279 frame-number = <4>; 5280 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5281 reg = <0x17cf0000 0x1000>; 5282 status = "disabled"; 5283 }; 5284 5285 frame@17d00000 { 5286 frame-number = <5>; 5287 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5288 reg = <0x17d00000 0x1000>; 5289 status = "disabled"; 5290 }; 5291 5292 frame@17d10000 { 5293 frame-number = <6>; 5294 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5295 reg = <0x17d10000 0x1000>; 5296 status = "disabled"; 5297 }; 5298 }; 5299 5300 osm_l3: interconnect@17d41000 { 5301 compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3"; 5302 reg = <0 0x17d41000 0 0x1400>; 5303 5304 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5305 clock-names = "xo", "alternate"; 5306 5307 #interconnect-cells = <1>; 5308 }; 5309 5310 cpufreq_hw: cpufreq@17d43000 { 5311 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw"; 5312 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 5313 reg-names = "freq-domain0", "freq-domain1"; 5314 5315 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>; 5316 5317 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5318 clock-names = "xo", "alternate"; 5319 5320 #freq-domain-cells = <1>; 5321 #clock-cells = <1>; 5322 }; 5323 5324 wifi: wifi@18800000 { 5325 compatible = "qcom,wcn3990-wifi"; 5326 status = "disabled"; 5327 reg = <0 0x18800000 0 0x800000>; 5328 reg-names = "membase"; 5329 memory-region = <&wlan_msa_mem>; 5330 clock-names = "cxo_ref_clk_pin"; 5331 clocks = <&rpmhcc RPMH_RF_CLK2>; 5332 interrupts = 5333 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 5334 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 5335 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 5336 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 5337 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5338 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5339 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 5340 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5341 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 5342 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5343 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5344 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 5345 iommus = <&apps_smmu 0x0040 0x1>; 5346 }; 5347 }; 5348 5349 sound: sound { 5350 }; 5351 5352 thermal-zones { 5353 cpu0-thermal { 5354 polling-delay-passive = <250>; 5355 polling-delay = <1000>; 5356 5357 thermal-sensors = <&tsens0 1>; 5358 5359 trips { 5360 cpu0_alert0: trip-point0 { 5361 temperature = <90000>; 5362 hysteresis = <2000>; 5363 type = "passive"; 5364 }; 5365 5366 cpu0_alert1: trip-point1 { 5367 temperature = <95000>; 5368 hysteresis = <2000>; 5369 type = "passive"; 5370 }; 5371 5372 cpu0_crit: cpu-crit { 5373 temperature = <110000>; 5374 hysteresis = <1000>; 5375 type = "critical"; 5376 }; 5377 }; 5378 }; 5379 5380 cpu1-thermal { 5381 polling-delay-passive = <250>; 5382 polling-delay = <1000>; 5383 5384 thermal-sensors = <&tsens0 2>; 5385 5386 trips { 5387 cpu1_alert0: trip-point0 { 5388 temperature = <90000>; 5389 hysteresis = <2000>; 5390 type = "passive"; 5391 }; 5392 5393 cpu1_alert1: trip-point1 { 5394 temperature = <95000>; 5395 hysteresis = <2000>; 5396 type = "passive"; 5397 }; 5398 5399 cpu1_crit: cpu-crit { 5400 temperature = <110000>; 5401 hysteresis = <1000>; 5402 type = "critical"; 5403 }; 5404 }; 5405 }; 5406 5407 cpu2-thermal { 5408 polling-delay-passive = <250>; 5409 polling-delay = <1000>; 5410 5411 thermal-sensors = <&tsens0 3>; 5412 5413 trips { 5414 cpu2_alert0: trip-point0 { 5415 temperature = <90000>; 5416 hysteresis = <2000>; 5417 type = "passive"; 5418 }; 5419 5420 cpu2_alert1: trip-point1 { 5421 temperature = <95000>; 5422 hysteresis = <2000>; 5423 type = "passive"; 5424 }; 5425 5426 cpu2_crit: cpu-crit { 5427 temperature = <110000>; 5428 hysteresis = <1000>; 5429 type = "critical"; 5430 }; 5431 }; 5432 }; 5433 5434 cpu3-thermal { 5435 polling-delay-passive = <250>; 5436 polling-delay = <1000>; 5437 5438 thermal-sensors = <&tsens0 4>; 5439 5440 trips { 5441 cpu3_alert0: trip-point0 { 5442 temperature = <90000>; 5443 hysteresis = <2000>; 5444 type = "passive"; 5445 }; 5446 5447 cpu3_alert1: trip-point1 { 5448 temperature = <95000>; 5449 hysteresis = <2000>; 5450 type = "passive"; 5451 }; 5452 5453 cpu3_crit: cpu-crit { 5454 temperature = <110000>; 5455 hysteresis = <1000>; 5456 type = "critical"; 5457 }; 5458 }; 5459 }; 5460 5461 cpu4-thermal { 5462 polling-delay-passive = <250>; 5463 polling-delay = <1000>; 5464 5465 thermal-sensors = <&tsens0 7>; 5466 5467 trips { 5468 cpu4_alert0: trip-point0 { 5469 temperature = <90000>; 5470 hysteresis = <2000>; 5471 type = "passive"; 5472 }; 5473 5474 cpu4_alert1: trip-point1 { 5475 temperature = <95000>; 5476 hysteresis = <2000>; 5477 type = "passive"; 5478 }; 5479 5480 cpu4_crit: cpu-crit { 5481 temperature = <110000>; 5482 hysteresis = <1000>; 5483 type = "critical"; 5484 }; 5485 }; 5486 }; 5487 5488 cpu5-thermal { 5489 polling-delay-passive = <250>; 5490 polling-delay = <1000>; 5491 5492 thermal-sensors = <&tsens0 8>; 5493 5494 trips { 5495 cpu5_alert0: trip-point0 { 5496 temperature = <90000>; 5497 hysteresis = <2000>; 5498 type = "passive"; 5499 }; 5500 5501 cpu5_alert1: trip-point1 { 5502 temperature = <95000>; 5503 hysteresis = <2000>; 5504 type = "passive"; 5505 }; 5506 5507 cpu5_crit: cpu-crit { 5508 temperature = <110000>; 5509 hysteresis = <1000>; 5510 type = "critical"; 5511 }; 5512 }; 5513 }; 5514 5515 cpu6-thermal { 5516 polling-delay-passive = <250>; 5517 polling-delay = <1000>; 5518 5519 thermal-sensors = <&tsens0 9>; 5520 5521 trips { 5522 cpu6_alert0: trip-point0 { 5523 temperature = <90000>; 5524 hysteresis = <2000>; 5525 type = "passive"; 5526 }; 5527 5528 cpu6_alert1: trip-point1 { 5529 temperature = <95000>; 5530 hysteresis = <2000>; 5531 type = "passive"; 5532 }; 5533 5534 cpu6_crit: cpu-crit { 5535 temperature = <110000>; 5536 hysteresis = <1000>; 5537 type = "critical"; 5538 }; 5539 }; 5540 }; 5541 5542 cpu7-thermal { 5543 polling-delay-passive = <250>; 5544 polling-delay = <1000>; 5545 5546 thermal-sensors = <&tsens0 10>; 5547 5548 trips { 5549 cpu7_alert0: trip-point0 { 5550 temperature = <90000>; 5551 hysteresis = <2000>; 5552 type = "passive"; 5553 }; 5554 5555 cpu7_alert1: trip-point1 { 5556 temperature = <95000>; 5557 hysteresis = <2000>; 5558 type = "passive"; 5559 }; 5560 5561 cpu7_crit: cpu-crit { 5562 temperature = <110000>; 5563 hysteresis = <1000>; 5564 type = "critical"; 5565 }; 5566 }; 5567 }; 5568 5569 aoss0-thermal { 5570 polling-delay-passive = <250>; 5571 polling-delay = <1000>; 5572 5573 thermal-sensors = <&tsens0 0>; 5574 5575 trips { 5576 aoss0_alert0: trip-point0 { 5577 temperature = <90000>; 5578 hysteresis = <2000>; 5579 type = "hot"; 5580 }; 5581 }; 5582 }; 5583 5584 cluster0-thermal { 5585 polling-delay-passive = <250>; 5586 polling-delay = <1000>; 5587 5588 thermal-sensors = <&tsens0 5>; 5589 5590 trips { 5591 cluster0_alert0: trip-point0 { 5592 temperature = <90000>; 5593 hysteresis = <2000>; 5594 type = "hot"; 5595 }; 5596 cluster0_crit: cluster0_crit { 5597 temperature = <110000>; 5598 hysteresis = <2000>; 5599 type = "critical"; 5600 }; 5601 }; 5602 }; 5603 5604 cluster1-thermal { 5605 polling-delay-passive = <250>; 5606 polling-delay = <1000>; 5607 5608 thermal-sensors = <&tsens0 6>; 5609 5610 trips { 5611 cluster1_alert0: trip-point0 { 5612 temperature = <90000>; 5613 hysteresis = <2000>; 5614 type = "hot"; 5615 }; 5616 cluster1_crit: cluster1_crit { 5617 temperature = <110000>; 5618 hysteresis = <2000>; 5619 type = "critical"; 5620 }; 5621 }; 5622 }; 5623 5624 gpu-top-thermal { 5625 polling-delay-passive = <250>; 5626 polling-delay = <1000>; 5627 5628 thermal-sensors = <&tsens0 11>; 5629 5630 trips { 5631 gpu1_alert0: trip-point0 { 5632 temperature = <90000>; 5633 hysteresis = <2000>; 5634 type = "hot"; 5635 }; 5636 }; 5637 }; 5638 5639 gpu-bottom-thermal { 5640 polling-delay-passive = <250>; 5641 polling-delay = <1000>; 5642 5643 thermal-sensors = <&tsens0 12>; 5644 5645 trips { 5646 gpu2_alert0: trip-point0 { 5647 temperature = <90000>; 5648 hysteresis = <2000>; 5649 type = "hot"; 5650 }; 5651 }; 5652 }; 5653 5654 aoss1-thermal { 5655 polling-delay-passive = <250>; 5656 polling-delay = <1000>; 5657 5658 thermal-sensors = <&tsens1 0>; 5659 5660 trips { 5661 aoss1_alert0: trip-point0 { 5662 temperature = <90000>; 5663 hysteresis = <2000>; 5664 type = "hot"; 5665 }; 5666 }; 5667 }; 5668 5669 q6-modem-thermal { 5670 polling-delay-passive = <250>; 5671 polling-delay = <1000>; 5672 5673 thermal-sensors = <&tsens1 1>; 5674 5675 trips { 5676 q6_modem_alert0: trip-point0 { 5677 temperature = <90000>; 5678 hysteresis = <2000>; 5679 type = "hot"; 5680 }; 5681 }; 5682 }; 5683 5684 mem-thermal { 5685 polling-delay-passive = <250>; 5686 polling-delay = <1000>; 5687 5688 thermal-sensors = <&tsens1 2>; 5689 5690 trips { 5691 mem_alert0: trip-point0 { 5692 temperature = <90000>; 5693 hysteresis = <2000>; 5694 type = "hot"; 5695 }; 5696 }; 5697 }; 5698 5699 wlan-thermal { 5700 polling-delay-passive = <250>; 5701 polling-delay = <1000>; 5702 5703 thermal-sensors = <&tsens1 3>; 5704 5705 trips { 5706 wlan_alert0: trip-point0 { 5707 temperature = <90000>; 5708 hysteresis = <2000>; 5709 type = "hot"; 5710 }; 5711 }; 5712 }; 5713 5714 q6-hvx-thermal { 5715 polling-delay-passive = <250>; 5716 polling-delay = <1000>; 5717 5718 thermal-sensors = <&tsens1 4>; 5719 5720 trips { 5721 q6_hvx_alert0: trip-point0 { 5722 temperature = <90000>; 5723 hysteresis = <2000>; 5724 type = "hot"; 5725 }; 5726 }; 5727 }; 5728 5729 camera-thermal { 5730 polling-delay-passive = <250>; 5731 polling-delay = <1000>; 5732 5733 thermal-sensors = <&tsens1 5>; 5734 5735 trips { 5736 camera_alert0: trip-point0 { 5737 temperature = <90000>; 5738 hysteresis = <2000>; 5739 type = "hot"; 5740 }; 5741 }; 5742 }; 5743 5744 video-thermal { 5745 polling-delay-passive = <250>; 5746 polling-delay = <1000>; 5747 5748 thermal-sensors = <&tsens1 6>; 5749 5750 trips { 5751 video_alert0: trip-point0 { 5752 temperature = <90000>; 5753 hysteresis = <2000>; 5754 type = "hot"; 5755 }; 5756 }; 5757 }; 5758 5759 modem-thermal { 5760 polling-delay-passive = <250>; 5761 polling-delay = <1000>; 5762 5763 thermal-sensors = <&tsens1 7>; 5764 5765 trips { 5766 modem_alert0: trip-point0 { 5767 temperature = <90000>; 5768 hysteresis = <2000>; 5769 type = "hot"; 5770 }; 5771 }; 5772 }; 5773 }; 5774 5775 timer { 5776 compatible = "arm,armv8-timer"; 5777 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 5778 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 5779 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 5780 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 5781 }; 5782}; 5783