1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,camcc-sdm845.h> 9#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 10#include <dt-bindings/clock/qcom,gcc-sdm845.h> 11#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 12#include <dt-bindings/clock/qcom,lpass-sdm845.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sdm845.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/firmware/qcom,scm.h> 17#include <dt-bindings/gpio/gpio.h> 18#include <dt-bindings/interconnect/qcom,osm-l3.h> 19#include <dt-bindings/interconnect/qcom,sdm845.h> 20#include <dt-bindings/interrupt-controller/arm-gic.h> 21#include <dt-bindings/phy/phy-qcom-qmp.h> 22#include <dt-bindings/phy/phy-qcom-qusb2.h> 23#include <dt-bindings/power/qcom-rpmpd.h> 24#include <dt-bindings/reset/qcom,sdm845-aoss.h> 25#include <dt-bindings/reset/qcom,sdm845-pdc.h> 26#include <dt-bindings/soc/qcom,apr.h> 27#include <dt-bindings/soc/qcom,rpmh-rsc.h> 28#include <dt-bindings/clock/qcom,gcc-sdm845.h> 29#include <dt-bindings/thermal/thermal.h> 30 31/ { 32 interrupt-parent = <&intc>; 33 34 #address-cells = <2>; 35 #size-cells = <2>; 36 37 aliases { 38 i2c0 = &i2c0; 39 i2c1 = &i2c1; 40 i2c2 = &i2c2; 41 i2c3 = &i2c3; 42 i2c4 = &i2c4; 43 i2c5 = &i2c5; 44 i2c6 = &i2c6; 45 i2c7 = &i2c7; 46 i2c8 = &i2c8; 47 i2c9 = &i2c9; 48 i2c10 = &i2c10; 49 i2c11 = &i2c11; 50 i2c12 = &i2c12; 51 i2c13 = &i2c13; 52 i2c14 = &i2c14; 53 i2c15 = &i2c15; 54 spi0 = &spi0; 55 spi1 = &spi1; 56 spi2 = &spi2; 57 spi3 = &spi3; 58 spi4 = &spi4; 59 spi5 = &spi5; 60 spi6 = &spi6; 61 spi7 = &spi7; 62 spi8 = &spi8; 63 spi9 = &spi9; 64 spi10 = &spi10; 65 spi11 = &spi11; 66 spi12 = &spi12; 67 spi13 = &spi13; 68 spi14 = &spi14; 69 spi15 = &spi15; 70 }; 71 72 chosen { }; 73 74 clocks { 75 xo_board: xo-board { 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <38400000>; 79 clock-output-names = "xo_board"; 80 }; 81 82 sleep_clk: sleep-clk { 83 compatible = "fixed-clock"; 84 #clock-cells = <0>; 85 clock-frequency = <32764>; 86 }; 87 }; 88 89 cpus: cpus { 90 #address-cells = <2>; 91 #size-cells = <0>; 92 93 CPU0: cpu@0 { 94 device_type = "cpu"; 95 compatible = "qcom,kryo385"; 96 reg = <0x0 0x0>; 97 clocks = <&cpufreq_hw 0>; 98 enable-method = "psci"; 99 capacity-dmips-mhz = <611>; 100 dynamic-power-coefficient = <154>; 101 qcom,freq-domain = <&cpufreq_hw 0>; 102 operating-points-v2 = <&cpu0_opp_table>; 103 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 104 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 105 power-domains = <&CPU_PD0>; 106 power-domain-names = "psci"; 107 #cooling-cells = <2>; 108 next-level-cache = <&L2_0>; 109 L2_0: l2-cache { 110 compatible = "cache"; 111 cache-level = <2>; 112 cache-unified; 113 next-level-cache = <&L3_0>; 114 L3_0: l3-cache { 115 compatible = "cache"; 116 cache-level = <3>; 117 cache-unified; 118 }; 119 }; 120 }; 121 122 CPU1: cpu@100 { 123 device_type = "cpu"; 124 compatible = "qcom,kryo385"; 125 reg = <0x0 0x100>; 126 clocks = <&cpufreq_hw 0>; 127 enable-method = "psci"; 128 capacity-dmips-mhz = <611>; 129 dynamic-power-coefficient = <154>; 130 qcom,freq-domain = <&cpufreq_hw 0>; 131 operating-points-v2 = <&cpu0_opp_table>; 132 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 133 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 134 power-domains = <&CPU_PD1>; 135 power-domain-names = "psci"; 136 #cooling-cells = <2>; 137 next-level-cache = <&L2_100>; 138 L2_100: l2-cache { 139 compatible = "cache"; 140 cache-level = <2>; 141 cache-unified; 142 next-level-cache = <&L3_0>; 143 }; 144 }; 145 146 CPU2: cpu@200 { 147 device_type = "cpu"; 148 compatible = "qcom,kryo385"; 149 reg = <0x0 0x200>; 150 clocks = <&cpufreq_hw 0>; 151 enable-method = "psci"; 152 capacity-dmips-mhz = <611>; 153 dynamic-power-coefficient = <154>; 154 qcom,freq-domain = <&cpufreq_hw 0>; 155 operating-points-v2 = <&cpu0_opp_table>; 156 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 157 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 158 power-domains = <&CPU_PD2>; 159 power-domain-names = "psci"; 160 #cooling-cells = <2>; 161 next-level-cache = <&L2_200>; 162 L2_200: l2-cache { 163 compatible = "cache"; 164 cache-level = <2>; 165 cache-unified; 166 next-level-cache = <&L3_0>; 167 }; 168 }; 169 170 CPU3: cpu@300 { 171 device_type = "cpu"; 172 compatible = "qcom,kryo385"; 173 reg = <0x0 0x300>; 174 clocks = <&cpufreq_hw 0>; 175 enable-method = "psci"; 176 capacity-dmips-mhz = <611>; 177 dynamic-power-coefficient = <154>; 178 qcom,freq-domain = <&cpufreq_hw 0>; 179 operating-points-v2 = <&cpu0_opp_table>; 180 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 181 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 182 #cooling-cells = <2>; 183 power-domains = <&CPU_PD3>; 184 power-domain-names = "psci"; 185 next-level-cache = <&L2_300>; 186 L2_300: l2-cache { 187 compatible = "cache"; 188 cache-level = <2>; 189 cache-unified; 190 next-level-cache = <&L3_0>; 191 }; 192 }; 193 194 CPU4: cpu@400 { 195 device_type = "cpu"; 196 compatible = "qcom,kryo385"; 197 reg = <0x0 0x400>; 198 clocks = <&cpufreq_hw 1>; 199 enable-method = "psci"; 200 capacity-dmips-mhz = <1024>; 201 dynamic-power-coefficient = <442>; 202 qcom,freq-domain = <&cpufreq_hw 1>; 203 operating-points-v2 = <&cpu4_opp_table>; 204 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 205 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 206 power-domains = <&CPU_PD4>; 207 power-domain-names = "psci"; 208 #cooling-cells = <2>; 209 next-level-cache = <&L2_400>; 210 L2_400: l2-cache { 211 compatible = "cache"; 212 cache-level = <2>; 213 cache-unified; 214 next-level-cache = <&L3_0>; 215 }; 216 }; 217 218 CPU5: cpu@500 { 219 device_type = "cpu"; 220 compatible = "qcom,kryo385"; 221 reg = <0x0 0x500>; 222 clocks = <&cpufreq_hw 1>; 223 enable-method = "psci"; 224 capacity-dmips-mhz = <1024>; 225 dynamic-power-coefficient = <442>; 226 qcom,freq-domain = <&cpufreq_hw 1>; 227 operating-points-v2 = <&cpu4_opp_table>; 228 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 229 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 230 power-domains = <&CPU_PD5>; 231 power-domain-names = "psci"; 232 #cooling-cells = <2>; 233 next-level-cache = <&L2_500>; 234 L2_500: l2-cache { 235 compatible = "cache"; 236 cache-level = <2>; 237 cache-unified; 238 next-level-cache = <&L3_0>; 239 }; 240 }; 241 242 CPU6: cpu@600 { 243 device_type = "cpu"; 244 compatible = "qcom,kryo385"; 245 reg = <0x0 0x600>; 246 clocks = <&cpufreq_hw 1>; 247 enable-method = "psci"; 248 capacity-dmips-mhz = <1024>; 249 dynamic-power-coefficient = <442>; 250 qcom,freq-domain = <&cpufreq_hw 1>; 251 operating-points-v2 = <&cpu4_opp_table>; 252 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 253 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 254 power-domains = <&CPU_PD6>; 255 power-domain-names = "psci"; 256 #cooling-cells = <2>; 257 next-level-cache = <&L2_600>; 258 L2_600: l2-cache { 259 compatible = "cache"; 260 cache-level = <2>; 261 cache-unified; 262 next-level-cache = <&L3_0>; 263 }; 264 }; 265 266 CPU7: cpu@700 { 267 device_type = "cpu"; 268 compatible = "qcom,kryo385"; 269 reg = <0x0 0x700>; 270 clocks = <&cpufreq_hw 1>; 271 enable-method = "psci"; 272 capacity-dmips-mhz = <1024>; 273 dynamic-power-coefficient = <442>; 274 qcom,freq-domain = <&cpufreq_hw 1>; 275 operating-points-v2 = <&cpu4_opp_table>; 276 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 277 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 278 power-domains = <&CPU_PD7>; 279 power-domain-names = "psci"; 280 #cooling-cells = <2>; 281 next-level-cache = <&L2_700>; 282 L2_700: l2-cache { 283 compatible = "cache"; 284 cache-level = <2>; 285 cache-unified; 286 next-level-cache = <&L3_0>; 287 }; 288 }; 289 290 cpu-map { 291 cluster0 { 292 core0 { 293 cpu = <&CPU0>; 294 }; 295 296 core1 { 297 cpu = <&CPU1>; 298 }; 299 300 core2 { 301 cpu = <&CPU2>; 302 }; 303 304 core3 { 305 cpu = <&CPU3>; 306 }; 307 308 core4 { 309 cpu = <&CPU4>; 310 }; 311 312 core5 { 313 cpu = <&CPU5>; 314 }; 315 316 core6 { 317 cpu = <&CPU6>; 318 }; 319 320 core7 { 321 cpu = <&CPU7>; 322 }; 323 }; 324 }; 325 326 cpu_idle_states: idle-states { 327 entry-method = "psci"; 328 329 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 330 compatible = "arm,idle-state"; 331 idle-state-name = "little-rail-power-collapse"; 332 arm,psci-suspend-param = <0x40000004>; 333 entry-latency-us = <350>; 334 exit-latency-us = <461>; 335 min-residency-us = <1890>; 336 local-timer-stop; 337 }; 338 339 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 340 compatible = "arm,idle-state"; 341 idle-state-name = "big-rail-power-collapse"; 342 arm,psci-suspend-param = <0x40000004>; 343 entry-latency-us = <264>; 344 exit-latency-us = <621>; 345 min-residency-us = <952>; 346 local-timer-stop; 347 }; 348 }; 349 350 domain-idle-states { 351 CLUSTER_SLEEP_0: cluster-sleep-0 { 352 compatible = "domain-idle-state"; 353 arm,psci-suspend-param = <0x4100c244>; 354 entry-latency-us = <3263>; 355 exit-latency-us = <6562>; 356 min-residency-us = <9987>; 357 }; 358 }; 359 }; 360 361 firmware { 362 scm { 363 compatible = "qcom,scm-sdm845", "qcom,scm"; 364 }; 365 }; 366 367 memory@80000000 { 368 device_type = "memory"; 369 /* We expect the bootloader to fill in the size */ 370 reg = <0 0x80000000 0 0>; 371 }; 372 373 cpu0_opp_table: opp-table-cpu0 { 374 compatible = "operating-points-v2"; 375 opp-shared; 376 377 cpu0_opp1: opp-300000000 { 378 opp-hz = /bits/ 64 <300000000>; 379 opp-peak-kBps = <800000 4800000>; 380 }; 381 382 cpu0_opp2: opp-403200000 { 383 opp-hz = /bits/ 64 <403200000>; 384 opp-peak-kBps = <800000 4800000>; 385 }; 386 387 cpu0_opp3: opp-480000000 { 388 opp-hz = /bits/ 64 <480000000>; 389 opp-peak-kBps = <800000 6451200>; 390 }; 391 392 cpu0_opp4: opp-576000000 { 393 opp-hz = /bits/ 64 <576000000>; 394 opp-peak-kBps = <800000 6451200>; 395 }; 396 397 cpu0_opp5: opp-652800000 { 398 opp-hz = /bits/ 64 <652800000>; 399 opp-peak-kBps = <800000 7680000>; 400 }; 401 402 cpu0_opp6: opp-748800000 { 403 opp-hz = /bits/ 64 <748800000>; 404 opp-peak-kBps = <1804000 9216000>; 405 }; 406 407 cpu0_opp7: opp-825600000 { 408 opp-hz = /bits/ 64 <825600000>; 409 opp-peak-kBps = <1804000 9216000>; 410 }; 411 412 cpu0_opp8: opp-902400000 { 413 opp-hz = /bits/ 64 <902400000>; 414 opp-peak-kBps = <1804000 10444800>; 415 }; 416 417 cpu0_opp9: opp-979200000 { 418 opp-hz = /bits/ 64 <979200000>; 419 opp-peak-kBps = <1804000 11980800>; 420 }; 421 422 cpu0_opp10: opp-1056000000 { 423 opp-hz = /bits/ 64 <1056000000>; 424 opp-peak-kBps = <1804000 11980800>; 425 }; 426 427 cpu0_opp11: opp-1132800000 { 428 opp-hz = /bits/ 64 <1132800000>; 429 opp-peak-kBps = <2188000 13516800>; 430 }; 431 432 cpu0_opp12: opp-1228800000 { 433 opp-hz = /bits/ 64 <1228800000>; 434 opp-peak-kBps = <2188000 15052800>; 435 }; 436 437 cpu0_opp13: opp-1324800000 { 438 opp-hz = /bits/ 64 <1324800000>; 439 opp-peak-kBps = <2188000 16588800>; 440 }; 441 442 cpu0_opp14: opp-1420800000 { 443 opp-hz = /bits/ 64 <1420800000>; 444 opp-peak-kBps = <3072000 18124800>; 445 }; 446 447 cpu0_opp15: opp-1516800000 { 448 opp-hz = /bits/ 64 <1516800000>; 449 opp-peak-kBps = <3072000 19353600>; 450 }; 451 452 cpu0_opp16: opp-1612800000 { 453 opp-hz = /bits/ 64 <1612800000>; 454 opp-peak-kBps = <4068000 19353600>; 455 }; 456 457 cpu0_opp17: opp-1689600000 { 458 opp-hz = /bits/ 64 <1689600000>; 459 opp-peak-kBps = <4068000 20889600>; 460 }; 461 462 cpu0_opp18: opp-1766400000 { 463 opp-hz = /bits/ 64 <1766400000>; 464 opp-peak-kBps = <4068000 22425600>; 465 }; 466 }; 467 468 cpu4_opp_table: opp-table-cpu4 { 469 compatible = "operating-points-v2"; 470 opp-shared; 471 472 cpu4_opp1: opp-300000000 { 473 opp-hz = /bits/ 64 <300000000>; 474 opp-peak-kBps = <800000 4800000>; 475 }; 476 477 cpu4_opp2: opp-403200000 { 478 opp-hz = /bits/ 64 <403200000>; 479 opp-peak-kBps = <800000 4800000>; 480 }; 481 482 cpu4_opp3: opp-480000000 { 483 opp-hz = /bits/ 64 <480000000>; 484 opp-peak-kBps = <1804000 4800000>; 485 }; 486 487 cpu4_opp4: opp-576000000 { 488 opp-hz = /bits/ 64 <576000000>; 489 opp-peak-kBps = <1804000 4800000>; 490 }; 491 492 cpu4_opp5: opp-652800000 { 493 opp-hz = /bits/ 64 <652800000>; 494 opp-peak-kBps = <1804000 4800000>; 495 }; 496 497 cpu4_opp6: opp-748800000 { 498 opp-hz = /bits/ 64 <748800000>; 499 opp-peak-kBps = <1804000 4800000>; 500 }; 501 502 cpu4_opp7: opp-825600000 { 503 opp-hz = /bits/ 64 <825600000>; 504 opp-peak-kBps = <2188000 9216000>; 505 }; 506 507 cpu4_opp8: opp-902400000 { 508 opp-hz = /bits/ 64 <902400000>; 509 opp-peak-kBps = <2188000 9216000>; 510 }; 511 512 cpu4_opp9: opp-979200000 { 513 opp-hz = /bits/ 64 <979200000>; 514 opp-peak-kBps = <2188000 9216000>; 515 }; 516 517 cpu4_opp10: opp-1056000000 { 518 opp-hz = /bits/ 64 <1056000000>; 519 opp-peak-kBps = <3072000 9216000>; 520 }; 521 522 cpu4_opp11: opp-1132800000 { 523 opp-hz = /bits/ 64 <1132800000>; 524 opp-peak-kBps = <3072000 11980800>; 525 }; 526 527 cpu4_opp12: opp-1209600000 { 528 opp-hz = /bits/ 64 <1209600000>; 529 opp-peak-kBps = <4068000 11980800>; 530 }; 531 532 cpu4_opp13: opp-1286400000 { 533 opp-hz = /bits/ 64 <1286400000>; 534 opp-peak-kBps = <4068000 11980800>; 535 }; 536 537 cpu4_opp14: opp-1363200000 { 538 opp-hz = /bits/ 64 <1363200000>; 539 opp-peak-kBps = <4068000 15052800>; 540 }; 541 542 cpu4_opp15: opp-1459200000 { 543 opp-hz = /bits/ 64 <1459200000>; 544 opp-peak-kBps = <4068000 15052800>; 545 }; 546 547 cpu4_opp16: opp-1536000000 { 548 opp-hz = /bits/ 64 <1536000000>; 549 opp-peak-kBps = <5412000 15052800>; 550 }; 551 552 cpu4_opp17: opp-1612800000 { 553 opp-hz = /bits/ 64 <1612800000>; 554 opp-peak-kBps = <5412000 15052800>; 555 }; 556 557 cpu4_opp18: opp-1689600000 { 558 opp-hz = /bits/ 64 <1689600000>; 559 opp-peak-kBps = <5412000 19353600>; 560 }; 561 562 cpu4_opp19: opp-1766400000 { 563 opp-hz = /bits/ 64 <1766400000>; 564 opp-peak-kBps = <6220000 19353600>; 565 }; 566 567 cpu4_opp20: opp-1843200000 { 568 opp-hz = /bits/ 64 <1843200000>; 569 opp-peak-kBps = <6220000 19353600>; 570 }; 571 572 cpu4_opp21: opp-1920000000 { 573 opp-hz = /bits/ 64 <1920000000>; 574 opp-peak-kBps = <7216000 19353600>; 575 }; 576 577 cpu4_opp22: opp-1996800000 { 578 opp-hz = /bits/ 64 <1996800000>; 579 opp-peak-kBps = <7216000 20889600>; 580 }; 581 582 cpu4_opp23: opp-2092800000 { 583 opp-hz = /bits/ 64 <2092800000>; 584 opp-peak-kBps = <7216000 20889600>; 585 }; 586 587 cpu4_opp24: opp-2169600000 { 588 opp-hz = /bits/ 64 <2169600000>; 589 opp-peak-kBps = <7216000 20889600>; 590 }; 591 592 cpu4_opp25: opp-2246400000 { 593 opp-hz = /bits/ 64 <2246400000>; 594 opp-peak-kBps = <7216000 20889600>; 595 }; 596 597 cpu4_opp26: opp-2323200000 { 598 opp-hz = /bits/ 64 <2323200000>; 599 opp-peak-kBps = <7216000 20889600>; 600 }; 601 602 cpu4_opp27: opp-2400000000 { 603 opp-hz = /bits/ 64 <2400000000>; 604 opp-peak-kBps = <7216000 22425600>; 605 }; 606 607 cpu4_opp28: opp-2476800000 { 608 opp-hz = /bits/ 64 <2476800000>; 609 opp-peak-kBps = <7216000 22425600>; 610 }; 611 612 cpu4_opp29: opp-2553600000 { 613 opp-hz = /bits/ 64 <2553600000>; 614 opp-peak-kBps = <7216000 22425600>; 615 }; 616 617 cpu4_opp30: opp-2649600000 { 618 opp-hz = /bits/ 64 <2649600000>; 619 opp-peak-kBps = <7216000 22425600>; 620 }; 621 622 cpu4_opp31: opp-2745600000 { 623 opp-hz = /bits/ 64 <2745600000>; 624 opp-peak-kBps = <7216000 25497600>; 625 }; 626 627 cpu4_opp32: opp-2803200000 { 628 opp-hz = /bits/ 64 <2803200000>; 629 opp-peak-kBps = <7216000 25497600>; 630 }; 631 }; 632 633 dsi_opp_table: opp-table-dsi { 634 compatible = "operating-points-v2"; 635 636 opp-19200000 { 637 opp-hz = /bits/ 64 <19200000>; 638 required-opps = <&rpmhpd_opp_min_svs>; 639 }; 640 641 opp-180000000 { 642 opp-hz = /bits/ 64 <180000000>; 643 required-opps = <&rpmhpd_opp_low_svs>; 644 }; 645 646 opp-275000000 { 647 opp-hz = /bits/ 64 <275000000>; 648 required-opps = <&rpmhpd_opp_svs>; 649 }; 650 651 opp-328580000 { 652 opp-hz = /bits/ 64 <328580000>; 653 required-opps = <&rpmhpd_opp_svs_l1>; 654 }; 655 656 opp-358000000 { 657 opp-hz = /bits/ 64 <358000000>; 658 required-opps = <&rpmhpd_opp_nom>; 659 }; 660 }; 661 662 qspi_opp_table: opp-table-qspi { 663 compatible = "operating-points-v2"; 664 665 opp-19200000 { 666 opp-hz = /bits/ 64 <19200000>; 667 required-opps = <&rpmhpd_opp_min_svs>; 668 }; 669 670 opp-100000000 { 671 opp-hz = /bits/ 64 <100000000>; 672 required-opps = <&rpmhpd_opp_low_svs>; 673 }; 674 675 opp-150000000 { 676 opp-hz = /bits/ 64 <150000000>; 677 required-opps = <&rpmhpd_opp_svs>; 678 }; 679 680 opp-300000000 { 681 opp-hz = /bits/ 64 <300000000>; 682 required-opps = <&rpmhpd_opp_nom>; 683 }; 684 }; 685 686 qup_opp_table: opp-table-qup { 687 compatible = "operating-points-v2"; 688 689 opp-50000000 { 690 opp-hz = /bits/ 64 <50000000>; 691 required-opps = <&rpmhpd_opp_min_svs>; 692 }; 693 694 opp-75000000 { 695 opp-hz = /bits/ 64 <75000000>; 696 required-opps = <&rpmhpd_opp_low_svs>; 697 }; 698 699 opp-100000000 { 700 opp-hz = /bits/ 64 <100000000>; 701 required-opps = <&rpmhpd_opp_svs>; 702 }; 703 704 opp-128000000 { 705 opp-hz = /bits/ 64 <128000000>; 706 required-opps = <&rpmhpd_opp_nom>; 707 }; 708 }; 709 710 pmu { 711 compatible = "arm,armv8-pmuv3"; 712 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 713 }; 714 715 psci: psci { 716 compatible = "arm,psci-1.0"; 717 method = "smc"; 718 719 CPU_PD0: power-domain-cpu0 { 720 #power-domain-cells = <0>; 721 power-domains = <&CLUSTER_PD>; 722 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 723 }; 724 725 CPU_PD1: power-domain-cpu1 { 726 #power-domain-cells = <0>; 727 power-domains = <&CLUSTER_PD>; 728 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 729 }; 730 731 CPU_PD2: power-domain-cpu2 { 732 #power-domain-cells = <0>; 733 power-domains = <&CLUSTER_PD>; 734 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 735 }; 736 737 CPU_PD3: power-domain-cpu3 { 738 #power-domain-cells = <0>; 739 power-domains = <&CLUSTER_PD>; 740 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 741 }; 742 743 CPU_PD4: power-domain-cpu4 { 744 #power-domain-cells = <0>; 745 power-domains = <&CLUSTER_PD>; 746 domain-idle-states = <&BIG_CPU_SLEEP_0>; 747 }; 748 749 CPU_PD5: power-domain-cpu5 { 750 #power-domain-cells = <0>; 751 power-domains = <&CLUSTER_PD>; 752 domain-idle-states = <&BIG_CPU_SLEEP_0>; 753 }; 754 755 CPU_PD6: power-domain-cpu6 { 756 #power-domain-cells = <0>; 757 power-domains = <&CLUSTER_PD>; 758 domain-idle-states = <&BIG_CPU_SLEEP_0>; 759 }; 760 761 CPU_PD7: power-domain-cpu7 { 762 #power-domain-cells = <0>; 763 power-domains = <&CLUSTER_PD>; 764 domain-idle-states = <&BIG_CPU_SLEEP_0>; 765 }; 766 767 CLUSTER_PD: power-domain-cluster { 768 #power-domain-cells = <0>; 769 domain-idle-states = <&CLUSTER_SLEEP_0>; 770 }; 771 }; 772 773 reserved-memory { 774 #address-cells = <2>; 775 #size-cells = <2>; 776 ranges; 777 778 hyp_mem: hyp-mem@85700000 { 779 reg = <0 0x85700000 0 0x600000>; 780 no-map; 781 }; 782 783 xbl_mem: xbl-mem@85e00000 { 784 reg = <0 0x85e00000 0 0x100000>; 785 no-map; 786 }; 787 788 aop_mem: aop-mem@85fc0000 { 789 reg = <0 0x85fc0000 0 0x20000>; 790 no-map; 791 }; 792 793 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { 794 compatible = "qcom,cmd-db"; 795 reg = <0x0 0x85fe0000 0 0x20000>; 796 no-map; 797 }; 798 799 smem@86000000 { 800 compatible = "qcom,smem"; 801 reg = <0x0 0x86000000 0 0x200000>; 802 no-map; 803 hwlocks = <&tcsr_mutex 3>; 804 }; 805 806 tz_mem: tz@86200000 { 807 reg = <0 0x86200000 0 0x2d00000>; 808 no-map; 809 }; 810 811 rmtfs_mem: rmtfs@88f00000 { 812 compatible = "qcom,rmtfs-mem"; 813 reg = <0 0x88f00000 0 0x200000>; 814 no-map; 815 816 qcom,client-id = <1>; 817 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 818 }; 819 820 qseecom_mem: qseecom@8ab00000 { 821 reg = <0 0x8ab00000 0 0x1400000>; 822 no-map; 823 }; 824 825 camera_mem: camera-mem@8bf00000 { 826 reg = <0 0x8bf00000 0 0x500000>; 827 no-map; 828 }; 829 830 ipa_fw_mem: ipa-fw@8c400000 { 831 reg = <0 0x8c400000 0 0x10000>; 832 no-map; 833 }; 834 835 ipa_gsi_mem: ipa-gsi@8c410000 { 836 reg = <0 0x8c410000 0 0x5000>; 837 no-map; 838 }; 839 840 gpu_mem: gpu@8c415000 { 841 reg = <0 0x8c415000 0 0x2000>; 842 no-map; 843 }; 844 845 adsp_mem: adsp@8c500000 { 846 reg = <0 0x8c500000 0 0x1a00000>; 847 no-map; 848 }; 849 850 wlan_msa_mem: wlan-msa@8df00000 { 851 reg = <0 0x8df00000 0 0x100000>; 852 no-map; 853 }; 854 855 mpss_region: mpss@8e000000 { 856 reg = <0 0x8e000000 0 0x7800000>; 857 no-map; 858 }; 859 860 venus_mem: venus@95800000 { 861 reg = <0 0x95800000 0 0x500000>; 862 no-map; 863 }; 864 865 cdsp_mem: cdsp@95d00000 { 866 reg = <0 0x95d00000 0 0x800000>; 867 no-map; 868 }; 869 870 mba_region: mba@96500000 { 871 reg = <0 0x96500000 0 0x200000>; 872 no-map; 873 }; 874 875 slpi_mem: slpi@96700000 { 876 reg = <0 0x96700000 0 0x1400000>; 877 no-map; 878 }; 879 880 spss_mem: spss@97b00000 { 881 reg = <0 0x97b00000 0 0x100000>; 882 no-map; 883 }; 884 885 mdata_mem: mpss-metadata { 886 alloc-ranges = <0 0xa0000000 0 0x20000000>; 887 size = <0 0x4000>; 888 no-map; 889 }; 890 891 fastrpc_mem: fastrpc { 892 compatible = "shared-dma-pool"; 893 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; 894 alignment = <0x0 0x400000>; 895 size = <0x0 0x1000000>; 896 reusable; 897 }; 898 }; 899 900 adsp_pas: remoteproc-adsp { 901 compatible = "qcom,sdm845-adsp-pas"; 902 903 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 904 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 905 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 906 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 907 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 908 interrupt-names = "wdog", "fatal", "ready", 909 "handover", "stop-ack"; 910 911 clocks = <&rpmhcc RPMH_CXO_CLK>; 912 clock-names = "xo"; 913 914 memory-region = <&adsp_mem>; 915 916 qcom,qmp = <&aoss_qmp>; 917 918 qcom,smem-states = <&adsp_smp2p_out 0>; 919 qcom,smem-state-names = "stop"; 920 921 status = "disabled"; 922 923 glink-edge { 924 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 925 label = "lpass"; 926 qcom,remote-pid = <2>; 927 mboxes = <&apss_shared 8>; 928 929 apr { 930 compatible = "qcom,apr-v2"; 931 qcom,glink-channels = "apr_audio_svc"; 932 qcom,domain = <APR_DOMAIN_ADSP>; 933 #address-cells = <1>; 934 #size-cells = <0>; 935 qcom,intents = <512 20>; 936 937 service@3 { 938 reg = <APR_SVC_ADSP_CORE>; 939 compatible = "qcom,q6core"; 940 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 941 }; 942 943 q6afe: service@4 { 944 compatible = "qcom,q6afe"; 945 reg = <APR_SVC_AFE>; 946 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 947 q6afedai: dais { 948 compatible = "qcom,q6afe-dais"; 949 #address-cells = <1>; 950 #size-cells = <0>; 951 #sound-dai-cells = <1>; 952 }; 953 }; 954 955 q6asm: service@7 { 956 compatible = "qcom,q6asm"; 957 reg = <APR_SVC_ASM>; 958 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 959 q6asmdai: dais { 960 compatible = "qcom,q6asm-dais"; 961 #address-cells = <1>; 962 #size-cells = <0>; 963 #sound-dai-cells = <1>; 964 iommus = <&apps_smmu 0x1821 0x0>; 965 }; 966 }; 967 968 q6adm: service@8 { 969 compatible = "qcom,q6adm"; 970 reg = <APR_SVC_ADM>; 971 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 972 q6routing: routing { 973 compatible = "qcom,q6adm-routing"; 974 #sound-dai-cells = <0>; 975 }; 976 }; 977 }; 978 979 fastrpc { 980 compatible = "qcom,fastrpc"; 981 qcom,glink-channels = "fastrpcglink-apps-dsp"; 982 label = "adsp"; 983 qcom,non-secure-domain; 984 #address-cells = <1>; 985 #size-cells = <0>; 986 987 compute-cb@3 { 988 compatible = "qcom,fastrpc-compute-cb"; 989 reg = <3>; 990 iommus = <&apps_smmu 0x1823 0x0>; 991 }; 992 993 compute-cb@4 { 994 compatible = "qcom,fastrpc-compute-cb"; 995 reg = <4>; 996 iommus = <&apps_smmu 0x1824 0x0>; 997 }; 998 }; 999 }; 1000 }; 1001 1002 cdsp_pas: remoteproc-cdsp { 1003 compatible = "qcom,sdm845-cdsp-pas"; 1004 1005 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 1006 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1007 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1008 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1009 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1010 interrupt-names = "wdog", "fatal", "ready", 1011 "handover", "stop-ack"; 1012 1013 clocks = <&rpmhcc RPMH_CXO_CLK>; 1014 clock-names = "xo"; 1015 1016 memory-region = <&cdsp_mem>; 1017 1018 qcom,qmp = <&aoss_qmp>; 1019 1020 qcom,smem-states = <&cdsp_smp2p_out 0>; 1021 qcom,smem-state-names = "stop"; 1022 1023 status = "disabled"; 1024 1025 glink-edge { 1026 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 1027 label = "turing"; 1028 qcom,remote-pid = <5>; 1029 mboxes = <&apss_shared 4>; 1030 fastrpc { 1031 compatible = "qcom,fastrpc"; 1032 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1033 label = "cdsp"; 1034 qcom,non-secure-domain; 1035 #address-cells = <1>; 1036 #size-cells = <0>; 1037 1038 compute-cb@1 { 1039 compatible = "qcom,fastrpc-compute-cb"; 1040 reg = <1>; 1041 iommus = <&apps_smmu 0x1401 0x30>; 1042 }; 1043 1044 compute-cb@2 { 1045 compatible = "qcom,fastrpc-compute-cb"; 1046 reg = <2>; 1047 iommus = <&apps_smmu 0x1402 0x30>; 1048 }; 1049 1050 compute-cb@3 { 1051 compatible = "qcom,fastrpc-compute-cb"; 1052 reg = <3>; 1053 iommus = <&apps_smmu 0x1403 0x30>; 1054 }; 1055 1056 compute-cb@4 { 1057 compatible = "qcom,fastrpc-compute-cb"; 1058 reg = <4>; 1059 iommus = <&apps_smmu 0x1404 0x30>; 1060 }; 1061 1062 compute-cb@5 { 1063 compatible = "qcom,fastrpc-compute-cb"; 1064 reg = <5>; 1065 iommus = <&apps_smmu 0x1405 0x30>; 1066 }; 1067 1068 compute-cb@6 { 1069 compatible = "qcom,fastrpc-compute-cb"; 1070 reg = <6>; 1071 iommus = <&apps_smmu 0x1406 0x30>; 1072 }; 1073 1074 compute-cb@7 { 1075 compatible = "qcom,fastrpc-compute-cb"; 1076 reg = <7>; 1077 iommus = <&apps_smmu 0x1407 0x30>; 1078 }; 1079 1080 compute-cb@8 { 1081 compatible = "qcom,fastrpc-compute-cb"; 1082 reg = <8>; 1083 iommus = <&apps_smmu 0x1408 0x30>; 1084 }; 1085 }; 1086 }; 1087 }; 1088 1089 smp2p-cdsp { 1090 compatible = "qcom,smp2p"; 1091 qcom,smem = <94>, <432>; 1092 1093 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 1094 1095 mboxes = <&apss_shared 6>; 1096 1097 qcom,local-pid = <0>; 1098 qcom,remote-pid = <5>; 1099 1100 cdsp_smp2p_out: master-kernel { 1101 qcom,entry-name = "master-kernel"; 1102 #qcom,smem-state-cells = <1>; 1103 }; 1104 1105 cdsp_smp2p_in: slave-kernel { 1106 qcom,entry-name = "slave-kernel"; 1107 1108 interrupt-controller; 1109 #interrupt-cells = <2>; 1110 }; 1111 }; 1112 1113 smp2p-lpass { 1114 compatible = "qcom,smp2p"; 1115 qcom,smem = <443>, <429>; 1116 1117 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 1118 1119 mboxes = <&apss_shared 10>; 1120 1121 qcom,local-pid = <0>; 1122 qcom,remote-pid = <2>; 1123 1124 adsp_smp2p_out: master-kernel { 1125 qcom,entry-name = "master-kernel"; 1126 #qcom,smem-state-cells = <1>; 1127 }; 1128 1129 adsp_smp2p_in: slave-kernel { 1130 qcom,entry-name = "slave-kernel"; 1131 1132 interrupt-controller; 1133 #interrupt-cells = <2>; 1134 }; 1135 }; 1136 1137 smp2p-mpss { 1138 compatible = "qcom,smp2p"; 1139 qcom,smem = <435>, <428>; 1140 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 1141 mboxes = <&apss_shared 14>; 1142 qcom,local-pid = <0>; 1143 qcom,remote-pid = <1>; 1144 1145 modem_smp2p_out: master-kernel { 1146 qcom,entry-name = "master-kernel"; 1147 #qcom,smem-state-cells = <1>; 1148 }; 1149 1150 modem_smp2p_in: slave-kernel { 1151 qcom,entry-name = "slave-kernel"; 1152 interrupt-controller; 1153 #interrupt-cells = <2>; 1154 }; 1155 1156 ipa_smp2p_out: ipa-ap-to-modem { 1157 qcom,entry-name = "ipa"; 1158 #qcom,smem-state-cells = <1>; 1159 }; 1160 1161 ipa_smp2p_in: ipa-modem-to-ap { 1162 qcom,entry-name = "ipa"; 1163 interrupt-controller; 1164 #interrupt-cells = <2>; 1165 }; 1166 }; 1167 1168 smp2p-slpi { 1169 compatible = "qcom,smp2p"; 1170 qcom,smem = <481>, <430>; 1171 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 1172 mboxes = <&apss_shared 26>; 1173 qcom,local-pid = <0>; 1174 qcom,remote-pid = <3>; 1175 1176 slpi_smp2p_out: master-kernel { 1177 qcom,entry-name = "master-kernel"; 1178 #qcom,smem-state-cells = <1>; 1179 }; 1180 1181 slpi_smp2p_in: slave-kernel { 1182 qcom,entry-name = "slave-kernel"; 1183 interrupt-controller; 1184 #interrupt-cells = <2>; 1185 }; 1186 }; 1187 1188 soc: soc@0 { 1189 #address-cells = <2>; 1190 #size-cells = <2>; 1191 ranges = <0 0 0 0 0x10 0>; 1192 dma-ranges = <0 0 0 0 0x10 0>; 1193 compatible = "simple-bus"; 1194 1195 gcc: clock-controller@100000 { 1196 compatible = "qcom,gcc-sdm845"; 1197 reg = <0 0x00100000 0 0x1f0000>; 1198 clocks = <&rpmhcc RPMH_CXO_CLK>, 1199 <&rpmhcc RPMH_CXO_CLK_A>, 1200 <&sleep_clk>, 1201 <&pcie0_phy>, 1202 <&pcie1_phy>; 1203 clock-names = "bi_tcxo", 1204 "bi_tcxo_ao", 1205 "sleep_clk", 1206 "pcie_0_pipe_clk", 1207 "pcie_1_pipe_clk"; 1208 #clock-cells = <1>; 1209 #reset-cells = <1>; 1210 #power-domain-cells = <1>; 1211 power-domains = <&rpmhpd SDM845_CX>; 1212 }; 1213 1214 qfprom@784000 { 1215 compatible = "qcom,sdm845-qfprom", "qcom,qfprom"; 1216 reg = <0 0x00784000 0 0x8ff>; 1217 #address-cells = <1>; 1218 #size-cells = <1>; 1219 1220 qusb2p_hstx_trim: hstx-trim-primary@1eb { 1221 reg = <0x1eb 0x1>; 1222 bits = <1 4>; 1223 }; 1224 1225 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 1226 reg = <0x1eb 0x2>; 1227 bits = <6 4>; 1228 }; 1229 }; 1230 1231 rng: rng@793000 { 1232 compatible = "qcom,prng-ee"; 1233 reg = <0 0x00793000 0 0x1000>; 1234 clocks = <&gcc GCC_PRNG_AHB_CLK>; 1235 clock-names = "core"; 1236 }; 1237 1238 gpi_dma0: dma-controller@800000 { 1239 #dma-cells = <3>; 1240 compatible = "qcom,sdm845-gpi-dma"; 1241 reg = <0 0x00800000 0 0x60000>; 1242 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1255 dma-channels = <13>; 1256 dma-channel-mask = <0xfa>; 1257 iommus = <&apps_smmu 0x0016 0x0>; 1258 status = "disabled"; 1259 }; 1260 1261 qupv3_id_0: geniqup@8c0000 { 1262 compatible = "qcom,geni-se-qup"; 1263 reg = <0 0x008c0000 0 0x6000>; 1264 clock-names = "m-ahb", "s-ahb"; 1265 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1266 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1267 iommus = <&apps_smmu 0x3 0x0>; 1268 #address-cells = <2>; 1269 #size-cells = <2>; 1270 ranges; 1271 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>; 1272 interconnect-names = "qup-core"; 1273 status = "disabled"; 1274 1275 i2c0: i2c@880000 { 1276 compatible = "qcom,geni-i2c"; 1277 reg = <0 0x00880000 0 0x4000>; 1278 clock-names = "se"; 1279 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1280 pinctrl-names = "default"; 1281 pinctrl-0 = <&qup_i2c0_default>; 1282 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1283 #address-cells = <1>; 1284 #size-cells = <0>; 1285 power-domains = <&rpmhpd SDM845_CX>; 1286 operating-points-v2 = <&qup_opp_table>; 1287 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1288 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1289 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1290 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1291 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1292 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1293 dma-names = "tx", "rx"; 1294 status = "disabled"; 1295 }; 1296 1297 spi0: spi@880000 { 1298 compatible = "qcom,geni-spi"; 1299 reg = <0 0x00880000 0 0x4000>; 1300 clock-names = "se"; 1301 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1302 pinctrl-names = "default"; 1303 pinctrl-0 = <&qup_spi0_default>; 1304 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1305 #address-cells = <1>; 1306 #size-cells = <0>; 1307 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1308 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1309 interconnect-names = "qup-core", "qup-config"; 1310 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1311 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1312 dma-names = "tx", "rx"; 1313 status = "disabled"; 1314 }; 1315 1316 uart0: serial@880000 { 1317 compatible = "qcom,geni-uart"; 1318 reg = <0 0x00880000 0 0x4000>; 1319 clock-names = "se"; 1320 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1321 pinctrl-names = "default"; 1322 pinctrl-0 = <&qup_uart0_default>; 1323 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1324 power-domains = <&rpmhpd SDM845_CX>; 1325 operating-points-v2 = <&qup_opp_table>; 1326 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1327 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1328 interconnect-names = "qup-core", "qup-config"; 1329 status = "disabled"; 1330 }; 1331 1332 i2c1: i2c@884000 { 1333 compatible = "qcom,geni-i2c"; 1334 reg = <0 0x00884000 0 0x4000>; 1335 clock-names = "se"; 1336 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1337 pinctrl-names = "default"; 1338 pinctrl-0 = <&qup_i2c1_default>; 1339 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1340 #address-cells = <1>; 1341 #size-cells = <0>; 1342 power-domains = <&rpmhpd SDM845_CX>; 1343 operating-points-v2 = <&qup_opp_table>; 1344 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1345 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1346 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1347 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1348 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1349 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1350 dma-names = "tx", "rx"; 1351 status = "disabled"; 1352 }; 1353 1354 spi1: spi@884000 { 1355 compatible = "qcom,geni-spi"; 1356 reg = <0 0x00884000 0 0x4000>; 1357 clock-names = "se"; 1358 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1359 pinctrl-names = "default"; 1360 pinctrl-0 = <&qup_spi1_default>; 1361 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1365 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1366 interconnect-names = "qup-core", "qup-config"; 1367 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1368 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1369 dma-names = "tx", "rx"; 1370 status = "disabled"; 1371 }; 1372 1373 uart1: serial@884000 { 1374 compatible = "qcom,geni-uart"; 1375 reg = <0 0x00884000 0 0x4000>; 1376 clock-names = "se"; 1377 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1378 pinctrl-names = "default"; 1379 pinctrl-0 = <&qup_uart1_default>; 1380 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1381 power-domains = <&rpmhpd SDM845_CX>; 1382 operating-points-v2 = <&qup_opp_table>; 1383 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1384 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1385 interconnect-names = "qup-core", "qup-config"; 1386 status = "disabled"; 1387 }; 1388 1389 i2c2: i2c@888000 { 1390 compatible = "qcom,geni-i2c"; 1391 reg = <0 0x00888000 0 0x4000>; 1392 clock-names = "se"; 1393 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1394 pinctrl-names = "default"; 1395 pinctrl-0 = <&qup_i2c2_default>; 1396 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1397 #address-cells = <1>; 1398 #size-cells = <0>; 1399 power-domains = <&rpmhpd SDM845_CX>; 1400 operating-points-v2 = <&qup_opp_table>; 1401 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1402 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1403 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1404 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1405 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1406 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1407 dma-names = "tx", "rx"; 1408 status = "disabled"; 1409 }; 1410 1411 spi2: spi@888000 { 1412 compatible = "qcom,geni-spi"; 1413 reg = <0 0x00888000 0 0x4000>; 1414 clock-names = "se"; 1415 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1416 pinctrl-names = "default"; 1417 pinctrl-0 = <&qup_spi2_default>; 1418 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1419 #address-cells = <1>; 1420 #size-cells = <0>; 1421 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1422 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1423 interconnect-names = "qup-core", "qup-config"; 1424 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1425 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1426 dma-names = "tx", "rx"; 1427 status = "disabled"; 1428 }; 1429 1430 uart2: serial@888000 { 1431 compatible = "qcom,geni-uart"; 1432 reg = <0 0x00888000 0 0x4000>; 1433 clock-names = "se"; 1434 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1435 pinctrl-names = "default"; 1436 pinctrl-0 = <&qup_uart2_default>; 1437 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1438 power-domains = <&rpmhpd SDM845_CX>; 1439 operating-points-v2 = <&qup_opp_table>; 1440 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1441 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1442 interconnect-names = "qup-core", "qup-config"; 1443 status = "disabled"; 1444 }; 1445 1446 i2c3: i2c@88c000 { 1447 compatible = "qcom,geni-i2c"; 1448 reg = <0 0x0088c000 0 0x4000>; 1449 clock-names = "se"; 1450 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1451 pinctrl-names = "default"; 1452 pinctrl-0 = <&qup_i2c3_default>; 1453 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1454 #address-cells = <1>; 1455 #size-cells = <0>; 1456 power-domains = <&rpmhpd SDM845_CX>; 1457 operating-points-v2 = <&qup_opp_table>; 1458 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1459 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1460 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1461 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1462 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1463 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1464 dma-names = "tx", "rx"; 1465 status = "disabled"; 1466 }; 1467 1468 spi3: spi@88c000 { 1469 compatible = "qcom,geni-spi"; 1470 reg = <0 0x0088c000 0 0x4000>; 1471 clock-names = "se"; 1472 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1473 pinctrl-names = "default"; 1474 pinctrl-0 = <&qup_spi3_default>; 1475 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1476 #address-cells = <1>; 1477 #size-cells = <0>; 1478 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1479 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1480 interconnect-names = "qup-core", "qup-config"; 1481 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1482 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1483 dma-names = "tx", "rx"; 1484 status = "disabled"; 1485 }; 1486 1487 uart3: serial@88c000 { 1488 compatible = "qcom,geni-uart"; 1489 reg = <0 0x0088c000 0 0x4000>; 1490 clock-names = "se"; 1491 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1492 pinctrl-names = "default"; 1493 pinctrl-0 = <&qup_uart3_default>; 1494 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1495 power-domains = <&rpmhpd SDM845_CX>; 1496 operating-points-v2 = <&qup_opp_table>; 1497 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1498 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1499 interconnect-names = "qup-core", "qup-config"; 1500 status = "disabled"; 1501 }; 1502 1503 i2c4: i2c@890000 { 1504 compatible = "qcom,geni-i2c"; 1505 reg = <0 0x00890000 0 0x4000>; 1506 clock-names = "se"; 1507 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1508 pinctrl-names = "default"; 1509 pinctrl-0 = <&qup_i2c4_default>; 1510 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1511 #address-cells = <1>; 1512 #size-cells = <0>; 1513 power-domains = <&rpmhpd SDM845_CX>; 1514 operating-points-v2 = <&qup_opp_table>; 1515 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1516 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1517 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1518 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1519 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1520 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1521 dma-names = "tx", "rx"; 1522 status = "disabled"; 1523 }; 1524 1525 spi4: spi@890000 { 1526 compatible = "qcom,geni-spi"; 1527 reg = <0 0x00890000 0 0x4000>; 1528 clock-names = "se"; 1529 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1530 pinctrl-names = "default"; 1531 pinctrl-0 = <&qup_spi4_default>; 1532 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1533 #address-cells = <1>; 1534 #size-cells = <0>; 1535 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1536 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1537 interconnect-names = "qup-core", "qup-config"; 1538 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1539 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1540 dma-names = "tx", "rx"; 1541 status = "disabled"; 1542 }; 1543 1544 uart4: serial@890000 { 1545 compatible = "qcom,geni-uart"; 1546 reg = <0 0x00890000 0 0x4000>; 1547 clock-names = "se"; 1548 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1549 pinctrl-names = "default"; 1550 pinctrl-0 = <&qup_uart4_default>; 1551 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1552 power-domains = <&rpmhpd SDM845_CX>; 1553 operating-points-v2 = <&qup_opp_table>; 1554 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1555 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1556 interconnect-names = "qup-core", "qup-config"; 1557 status = "disabled"; 1558 }; 1559 1560 i2c5: i2c@894000 { 1561 compatible = "qcom,geni-i2c"; 1562 reg = <0 0x00894000 0 0x4000>; 1563 clock-names = "se"; 1564 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1565 pinctrl-names = "default"; 1566 pinctrl-0 = <&qup_i2c5_default>; 1567 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1568 #address-cells = <1>; 1569 #size-cells = <0>; 1570 power-domains = <&rpmhpd SDM845_CX>; 1571 operating-points-v2 = <&qup_opp_table>; 1572 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1573 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1574 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1575 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1576 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1577 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1578 dma-names = "tx", "rx"; 1579 status = "disabled"; 1580 }; 1581 1582 spi5: spi@894000 { 1583 compatible = "qcom,geni-spi"; 1584 reg = <0 0x00894000 0 0x4000>; 1585 clock-names = "se"; 1586 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1587 pinctrl-names = "default"; 1588 pinctrl-0 = <&qup_spi5_default>; 1589 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1590 #address-cells = <1>; 1591 #size-cells = <0>; 1592 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1593 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1594 interconnect-names = "qup-core", "qup-config"; 1595 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1596 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1597 dma-names = "tx", "rx"; 1598 status = "disabled"; 1599 }; 1600 1601 uart5: serial@894000 { 1602 compatible = "qcom,geni-uart"; 1603 reg = <0 0x00894000 0 0x4000>; 1604 clock-names = "se"; 1605 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1606 pinctrl-names = "default"; 1607 pinctrl-0 = <&qup_uart5_default>; 1608 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1609 power-domains = <&rpmhpd SDM845_CX>; 1610 operating-points-v2 = <&qup_opp_table>; 1611 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1612 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1613 interconnect-names = "qup-core", "qup-config"; 1614 status = "disabled"; 1615 }; 1616 1617 i2c6: i2c@898000 { 1618 compatible = "qcom,geni-i2c"; 1619 reg = <0 0x00898000 0 0x4000>; 1620 clock-names = "se"; 1621 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1622 pinctrl-names = "default"; 1623 pinctrl-0 = <&qup_i2c6_default>; 1624 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1625 #address-cells = <1>; 1626 #size-cells = <0>; 1627 power-domains = <&rpmhpd SDM845_CX>; 1628 operating-points-v2 = <&qup_opp_table>; 1629 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1630 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1631 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1632 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1633 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1634 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1635 dma-names = "tx", "rx"; 1636 status = "disabled"; 1637 }; 1638 1639 spi6: spi@898000 { 1640 compatible = "qcom,geni-spi"; 1641 reg = <0 0x00898000 0 0x4000>; 1642 clock-names = "se"; 1643 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1644 pinctrl-names = "default"; 1645 pinctrl-0 = <&qup_spi6_default>; 1646 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1647 #address-cells = <1>; 1648 #size-cells = <0>; 1649 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1650 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1651 interconnect-names = "qup-core", "qup-config"; 1652 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1653 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1654 dma-names = "tx", "rx"; 1655 status = "disabled"; 1656 }; 1657 1658 uart6: serial@898000 { 1659 compatible = "qcom,geni-uart"; 1660 reg = <0 0x00898000 0 0x4000>; 1661 clock-names = "se"; 1662 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1663 pinctrl-names = "default"; 1664 pinctrl-0 = <&qup_uart6_default>; 1665 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1666 power-domains = <&rpmhpd SDM845_CX>; 1667 operating-points-v2 = <&qup_opp_table>; 1668 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1669 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1670 interconnect-names = "qup-core", "qup-config"; 1671 status = "disabled"; 1672 }; 1673 1674 i2c7: i2c@89c000 { 1675 compatible = "qcom,geni-i2c"; 1676 reg = <0 0x0089c000 0 0x4000>; 1677 clock-names = "se"; 1678 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1679 pinctrl-names = "default"; 1680 pinctrl-0 = <&qup_i2c7_default>; 1681 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1682 #address-cells = <1>; 1683 #size-cells = <0>; 1684 power-domains = <&rpmhpd SDM845_CX>; 1685 operating-points-v2 = <&qup_opp_table>; 1686 status = "disabled"; 1687 }; 1688 1689 spi7: spi@89c000 { 1690 compatible = "qcom,geni-spi"; 1691 reg = <0 0x0089c000 0 0x4000>; 1692 clock-names = "se"; 1693 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1694 pinctrl-names = "default"; 1695 pinctrl-0 = <&qup_spi7_default>; 1696 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1697 #address-cells = <1>; 1698 #size-cells = <0>; 1699 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1700 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1701 interconnect-names = "qup-core", "qup-config"; 1702 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1703 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1704 dma-names = "tx", "rx"; 1705 status = "disabled"; 1706 }; 1707 1708 uart7: serial@89c000 { 1709 compatible = "qcom,geni-uart"; 1710 reg = <0 0x0089c000 0 0x4000>; 1711 clock-names = "se"; 1712 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1713 pinctrl-names = "default"; 1714 pinctrl-0 = <&qup_uart7_default>; 1715 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1716 power-domains = <&rpmhpd SDM845_CX>; 1717 operating-points-v2 = <&qup_opp_table>; 1718 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1719 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1720 interconnect-names = "qup-core", "qup-config"; 1721 status = "disabled"; 1722 }; 1723 }; 1724 1725 gpi_dma1: dma-controller@a00000 { 1726 #dma-cells = <3>; 1727 compatible = "qcom,sdm845-gpi-dma"; 1728 reg = <0 0x00a00000 0 0x60000>; 1729 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1742 dma-channels = <13>; 1743 dma-channel-mask = <0xfa>; 1744 iommus = <&apps_smmu 0x06d6 0x0>; 1745 status = "disabled"; 1746 }; 1747 1748 qupv3_id_1: geniqup@ac0000 { 1749 compatible = "qcom,geni-se-qup"; 1750 reg = <0 0x00ac0000 0 0x6000>; 1751 clock-names = "m-ahb", "s-ahb"; 1752 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1753 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1754 iommus = <&apps_smmu 0x6c3 0x0>; 1755 #address-cells = <2>; 1756 #size-cells = <2>; 1757 ranges; 1758 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>; 1759 interconnect-names = "qup-core"; 1760 status = "disabled"; 1761 1762 i2c8: i2c@a80000 { 1763 compatible = "qcom,geni-i2c"; 1764 reg = <0 0x00a80000 0 0x4000>; 1765 clock-names = "se"; 1766 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1767 pinctrl-names = "default"; 1768 pinctrl-0 = <&qup_i2c8_default>; 1769 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1770 #address-cells = <1>; 1771 #size-cells = <0>; 1772 power-domains = <&rpmhpd SDM845_CX>; 1773 operating-points-v2 = <&qup_opp_table>; 1774 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1775 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1776 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1777 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1778 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1779 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1780 dma-names = "tx", "rx"; 1781 status = "disabled"; 1782 }; 1783 1784 spi8: spi@a80000 { 1785 compatible = "qcom,geni-spi"; 1786 reg = <0 0x00a80000 0 0x4000>; 1787 clock-names = "se"; 1788 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1789 pinctrl-names = "default"; 1790 pinctrl-0 = <&qup_spi8_default>; 1791 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1792 #address-cells = <1>; 1793 #size-cells = <0>; 1794 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1795 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1796 interconnect-names = "qup-core", "qup-config"; 1797 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1798 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1799 dma-names = "tx", "rx"; 1800 status = "disabled"; 1801 }; 1802 1803 uart8: serial@a80000 { 1804 compatible = "qcom,geni-uart"; 1805 reg = <0 0x00a80000 0 0x4000>; 1806 clock-names = "se"; 1807 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1808 pinctrl-names = "default"; 1809 pinctrl-0 = <&qup_uart8_default>; 1810 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1811 power-domains = <&rpmhpd SDM845_CX>; 1812 operating-points-v2 = <&qup_opp_table>; 1813 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1814 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1815 interconnect-names = "qup-core", "qup-config"; 1816 status = "disabled"; 1817 }; 1818 1819 i2c9: i2c@a84000 { 1820 compatible = "qcom,geni-i2c"; 1821 reg = <0 0x00a84000 0 0x4000>; 1822 clock-names = "se"; 1823 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1824 pinctrl-names = "default"; 1825 pinctrl-0 = <&qup_i2c9_default>; 1826 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1827 #address-cells = <1>; 1828 #size-cells = <0>; 1829 power-domains = <&rpmhpd SDM845_CX>; 1830 operating-points-v2 = <&qup_opp_table>; 1831 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1832 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1833 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1834 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1835 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1836 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1837 dma-names = "tx", "rx"; 1838 status = "disabled"; 1839 }; 1840 1841 spi9: spi@a84000 { 1842 compatible = "qcom,geni-spi"; 1843 reg = <0 0x00a84000 0 0x4000>; 1844 clock-names = "se"; 1845 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1846 pinctrl-names = "default"; 1847 pinctrl-0 = <&qup_spi9_default>; 1848 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1849 #address-cells = <1>; 1850 #size-cells = <0>; 1851 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1852 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1853 interconnect-names = "qup-core", "qup-config"; 1854 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1855 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1856 dma-names = "tx", "rx"; 1857 status = "disabled"; 1858 }; 1859 1860 uart9: serial@a84000 { 1861 compatible = "qcom,geni-debug-uart"; 1862 reg = <0 0x00a84000 0 0x4000>; 1863 clock-names = "se"; 1864 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1865 pinctrl-names = "default"; 1866 pinctrl-0 = <&qup_uart9_default>; 1867 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1868 power-domains = <&rpmhpd SDM845_CX>; 1869 operating-points-v2 = <&qup_opp_table>; 1870 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1871 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1872 interconnect-names = "qup-core", "qup-config"; 1873 status = "disabled"; 1874 }; 1875 1876 i2c10: i2c@a88000 { 1877 compatible = "qcom,geni-i2c"; 1878 reg = <0 0x00a88000 0 0x4000>; 1879 clock-names = "se"; 1880 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1881 pinctrl-names = "default"; 1882 pinctrl-0 = <&qup_i2c10_default>; 1883 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1884 #address-cells = <1>; 1885 #size-cells = <0>; 1886 power-domains = <&rpmhpd SDM845_CX>; 1887 operating-points-v2 = <&qup_opp_table>; 1888 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1889 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1890 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1891 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1892 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1893 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1894 dma-names = "tx", "rx"; 1895 status = "disabled"; 1896 }; 1897 1898 spi10: spi@a88000 { 1899 compatible = "qcom,geni-spi"; 1900 reg = <0 0x00a88000 0 0x4000>; 1901 clock-names = "se"; 1902 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1903 pinctrl-names = "default"; 1904 pinctrl-0 = <&qup_spi10_default>; 1905 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1906 #address-cells = <1>; 1907 #size-cells = <0>; 1908 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1909 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1910 interconnect-names = "qup-core", "qup-config"; 1911 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1912 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1913 dma-names = "tx", "rx"; 1914 status = "disabled"; 1915 }; 1916 1917 uart10: serial@a88000 { 1918 compatible = "qcom,geni-uart"; 1919 reg = <0 0x00a88000 0 0x4000>; 1920 clock-names = "se"; 1921 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1922 pinctrl-names = "default"; 1923 pinctrl-0 = <&qup_uart10_default>; 1924 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1925 power-domains = <&rpmhpd SDM845_CX>; 1926 operating-points-v2 = <&qup_opp_table>; 1927 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1928 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1929 interconnect-names = "qup-core", "qup-config"; 1930 status = "disabled"; 1931 }; 1932 1933 i2c11: i2c@a8c000 { 1934 compatible = "qcom,geni-i2c"; 1935 reg = <0 0x00a8c000 0 0x4000>; 1936 clock-names = "se"; 1937 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1938 pinctrl-names = "default"; 1939 pinctrl-0 = <&qup_i2c11_default>; 1940 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1941 #address-cells = <1>; 1942 #size-cells = <0>; 1943 power-domains = <&rpmhpd SDM845_CX>; 1944 operating-points-v2 = <&qup_opp_table>; 1945 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1946 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1947 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1948 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1949 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1950 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1951 dma-names = "tx", "rx"; 1952 status = "disabled"; 1953 }; 1954 1955 spi11: spi@a8c000 { 1956 compatible = "qcom,geni-spi"; 1957 reg = <0 0x00a8c000 0 0x4000>; 1958 clock-names = "se"; 1959 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1960 pinctrl-names = "default"; 1961 pinctrl-0 = <&qup_spi11_default>; 1962 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1963 #address-cells = <1>; 1964 #size-cells = <0>; 1965 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1966 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1967 interconnect-names = "qup-core", "qup-config"; 1968 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1969 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1970 dma-names = "tx", "rx"; 1971 status = "disabled"; 1972 }; 1973 1974 uart11: serial@a8c000 { 1975 compatible = "qcom,geni-uart"; 1976 reg = <0 0x00a8c000 0 0x4000>; 1977 clock-names = "se"; 1978 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1979 pinctrl-names = "default"; 1980 pinctrl-0 = <&qup_uart11_default>; 1981 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1982 power-domains = <&rpmhpd SDM845_CX>; 1983 operating-points-v2 = <&qup_opp_table>; 1984 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1985 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1986 interconnect-names = "qup-core", "qup-config"; 1987 status = "disabled"; 1988 }; 1989 1990 i2c12: i2c@a90000 { 1991 compatible = "qcom,geni-i2c"; 1992 reg = <0 0x00a90000 0 0x4000>; 1993 clock-names = "se"; 1994 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1995 pinctrl-names = "default"; 1996 pinctrl-0 = <&qup_i2c12_default>; 1997 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1998 #address-cells = <1>; 1999 #size-cells = <0>; 2000 power-domains = <&rpmhpd SDM845_CX>; 2001 operating-points-v2 = <&qup_opp_table>; 2002 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2003 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2004 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2005 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2006 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 2007 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 2008 dma-names = "tx", "rx"; 2009 status = "disabled"; 2010 }; 2011 2012 spi12: spi@a90000 { 2013 compatible = "qcom,geni-spi"; 2014 reg = <0 0x00a90000 0 0x4000>; 2015 clock-names = "se"; 2016 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2017 pinctrl-names = "default"; 2018 pinctrl-0 = <&qup_spi12_default>; 2019 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2020 #address-cells = <1>; 2021 #size-cells = <0>; 2022 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2023 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2024 interconnect-names = "qup-core", "qup-config"; 2025 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 2026 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2027 dma-names = "tx", "rx"; 2028 status = "disabled"; 2029 }; 2030 2031 uart12: serial@a90000 { 2032 compatible = "qcom,geni-uart"; 2033 reg = <0 0x00a90000 0 0x4000>; 2034 clock-names = "se"; 2035 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2036 pinctrl-names = "default"; 2037 pinctrl-0 = <&qup_uart12_default>; 2038 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2039 power-domains = <&rpmhpd SDM845_CX>; 2040 operating-points-v2 = <&qup_opp_table>; 2041 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2042 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2043 interconnect-names = "qup-core", "qup-config"; 2044 status = "disabled"; 2045 }; 2046 2047 i2c13: i2c@a94000 { 2048 compatible = "qcom,geni-i2c"; 2049 reg = <0 0x00a94000 0 0x4000>; 2050 clock-names = "se"; 2051 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2052 pinctrl-names = "default"; 2053 pinctrl-0 = <&qup_i2c13_default>; 2054 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2055 #address-cells = <1>; 2056 #size-cells = <0>; 2057 power-domains = <&rpmhpd SDM845_CX>; 2058 operating-points-v2 = <&qup_opp_table>; 2059 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2060 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2061 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2062 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2063 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2064 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2065 dma-names = "tx", "rx"; 2066 status = "disabled"; 2067 }; 2068 2069 spi13: spi@a94000 { 2070 compatible = "qcom,geni-spi"; 2071 reg = <0 0x00a94000 0 0x4000>; 2072 clock-names = "se"; 2073 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2074 pinctrl-names = "default"; 2075 pinctrl-0 = <&qup_spi13_default>; 2076 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2077 #address-cells = <1>; 2078 #size-cells = <0>; 2079 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2080 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2081 interconnect-names = "qup-core", "qup-config"; 2082 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2083 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2084 dma-names = "tx", "rx"; 2085 status = "disabled"; 2086 }; 2087 2088 uart13: serial@a94000 { 2089 compatible = "qcom,geni-uart"; 2090 reg = <0 0x00a94000 0 0x4000>; 2091 clock-names = "se"; 2092 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2093 pinctrl-names = "default"; 2094 pinctrl-0 = <&qup_uart13_default>; 2095 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2096 power-domains = <&rpmhpd SDM845_CX>; 2097 operating-points-v2 = <&qup_opp_table>; 2098 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2099 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2100 interconnect-names = "qup-core", "qup-config"; 2101 status = "disabled"; 2102 }; 2103 2104 i2c14: i2c@a98000 { 2105 compatible = "qcom,geni-i2c"; 2106 reg = <0 0x00a98000 0 0x4000>; 2107 clock-names = "se"; 2108 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2109 pinctrl-names = "default"; 2110 pinctrl-0 = <&qup_i2c14_default>; 2111 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2112 #address-cells = <1>; 2113 #size-cells = <0>; 2114 power-domains = <&rpmhpd SDM845_CX>; 2115 operating-points-v2 = <&qup_opp_table>; 2116 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2117 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2118 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2119 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2120 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2121 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2122 dma-names = "tx", "rx"; 2123 status = "disabled"; 2124 }; 2125 2126 spi14: spi@a98000 { 2127 compatible = "qcom,geni-spi"; 2128 reg = <0 0x00a98000 0 0x4000>; 2129 clock-names = "se"; 2130 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2131 pinctrl-names = "default"; 2132 pinctrl-0 = <&qup_spi14_default>; 2133 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2134 #address-cells = <1>; 2135 #size-cells = <0>; 2136 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2137 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2138 interconnect-names = "qup-core", "qup-config"; 2139 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2140 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2141 dma-names = "tx", "rx"; 2142 status = "disabled"; 2143 }; 2144 2145 uart14: serial@a98000 { 2146 compatible = "qcom,geni-uart"; 2147 reg = <0 0x00a98000 0 0x4000>; 2148 clock-names = "se"; 2149 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2150 pinctrl-names = "default"; 2151 pinctrl-0 = <&qup_uart14_default>; 2152 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2153 power-domains = <&rpmhpd SDM845_CX>; 2154 operating-points-v2 = <&qup_opp_table>; 2155 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2156 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2157 interconnect-names = "qup-core", "qup-config"; 2158 status = "disabled"; 2159 }; 2160 2161 i2c15: i2c@a9c000 { 2162 compatible = "qcom,geni-i2c"; 2163 reg = <0 0x00a9c000 0 0x4000>; 2164 clock-names = "se"; 2165 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2166 pinctrl-names = "default"; 2167 pinctrl-0 = <&qup_i2c15_default>; 2168 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2169 #address-cells = <1>; 2170 #size-cells = <0>; 2171 power-domains = <&rpmhpd SDM845_CX>; 2172 operating-points-v2 = <&qup_opp_table>; 2173 status = "disabled"; 2174 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2175 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2176 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2177 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2178 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2179 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2180 dma-names = "tx", "rx"; 2181 }; 2182 2183 spi15: spi@a9c000 { 2184 compatible = "qcom,geni-spi"; 2185 reg = <0 0x00a9c000 0 0x4000>; 2186 clock-names = "se"; 2187 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2188 pinctrl-names = "default"; 2189 pinctrl-0 = <&qup_spi15_default>; 2190 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2191 #address-cells = <1>; 2192 #size-cells = <0>; 2193 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2194 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2195 interconnect-names = "qup-core", "qup-config"; 2196 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2197 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2198 dma-names = "tx", "rx"; 2199 status = "disabled"; 2200 }; 2201 2202 uart15: serial@a9c000 { 2203 compatible = "qcom,geni-uart"; 2204 reg = <0 0x00a9c000 0 0x4000>; 2205 clock-names = "se"; 2206 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2207 pinctrl-names = "default"; 2208 pinctrl-0 = <&qup_uart15_default>; 2209 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2210 power-domains = <&rpmhpd SDM845_CX>; 2211 operating-points-v2 = <&qup_opp_table>; 2212 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2213 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2214 interconnect-names = "qup-core", "qup-config"; 2215 status = "disabled"; 2216 }; 2217 }; 2218 2219 llcc: system-cache-controller@1100000 { 2220 compatible = "qcom,sdm845-llcc"; 2221 reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>, 2222 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, 2223 <0 0x01300000 0 0x50000>; 2224 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2225 "llcc3_base", "llcc_broadcast_base"; 2226 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2227 }; 2228 2229 dma@10a2000 { 2230 compatible = "qcom,sdm845-dcc", "qcom,dcc"; 2231 reg = <0x0 0x010a2000 0x0 0x1000>, 2232 <0x0 0x010ae000 0x0 0x2000>; 2233 }; 2234 2235 pmu@114a000 { 2236 compatible = "qcom,sdm845-llcc-bwmon"; 2237 reg = <0 0x0114a000 0 0x1000>; 2238 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 2239 interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>; 2240 2241 operating-points-v2 = <&llcc_bwmon_opp_table>; 2242 2243 llcc_bwmon_opp_table: opp-table { 2244 compatible = "operating-points-v2"; 2245 2246 /* 2247 * The interconnect path bandwidth taken from 2248 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc 2249 * interconnect. This also matches the 2250 * bandwidth table of qcom,llccbw (qcom,bw-tbl, 2251 * bus width: 4 bytes) from msm-4.9 downstream 2252 * kernel. 2253 */ 2254 opp-0 { 2255 opp-peak-kBps = <800000>; 2256 }; 2257 opp-1 { 2258 opp-peak-kBps = <1804000>; 2259 }; 2260 opp-2 { 2261 opp-peak-kBps = <3072000>; 2262 }; 2263 opp-3 { 2264 opp-peak-kBps = <5412000>; 2265 }; 2266 opp-4 { 2267 opp-peak-kBps = <7216000>; 2268 }; 2269 }; 2270 }; 2271 2272 pmu@1436400 { 2273 compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon"; 2274 reg = <0 0x01436400 0 0x600>; 2275 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 2276 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>; 2277 2278 operating-points-v2 = <&cpu_bwmon_opp_table>; 2279 2280 cpu_bwmon_opp_table: opp-table { 2281 compatible = "operating-points-v2"; 2282 2283 /* 2284 * The interconnect path bandwidth taken from 2285 * cpu4_opp_table bandwidth for OSM L3 2286 * interconnect. This also matches the OSM L3 2287 * from bandwidth table of qcom,cpu4-l3lat-mon 2288 * (qcom,core-dev-table, bus width: 16 bytes) 2289 * from msm-4.9 downstream kernel. 2290 */ 2291 opp-0 { 2292 opp-peak-kBps = <4800000>; 2293 }; 2294 opp-1 { 2295 opp-peak-kBps = <9216000>; 2296 }; 2297 opp-2 { 2298 opp-peak-kBps = <15052800>; 2299 }; 2300 opp-3 { 2301 opp-peak-kBps = <20889600>; 2302 }; 2303 opp-4 { 2304 opp-peak-kBps = <25497600>; 2305 }; 2306 }; 2307 }; 2308 2309 pcie0: pcie@1c00000 { 2310 compatible = "qcom,pcie-sdm845"; 2311 reg = <0 0x01c00000 0 0x2000>, 2312 <0 0x60000000 0 0xf1d>, 2313 <0 0x60000f20 0 0xa8>, 2314 <0 0x60100000 0 0x100000>, 2315 <0 0x01c07000 0 0x1000>; 2316 reg-names = "parf", "dbi", "elbi", "config", "mhi"; 2317 device_type = "pci"; 2318 linux,pci-domain = <0>; 2319 bus-range = <0x00 0xff>; 2320 num-lanes = <1>; 2321 2322 #address-cells = <3>; 2323 #size-cells = <2>; 2324 2325 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 2326 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>; 2327 2328 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 2329 interrupt-names = "msi"; 2330 #interrupt-cells = <1>; 2331 interrupt-map-mask = <0 0 0 0x7>; 2332 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2333 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2334 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2335 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2336 2337 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2338 <&gcc GCC_PCIE_0_AUX_CLK>, 2339 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2340 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2341 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2342 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2343 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2344 clock-names = "pipe", 2345 "aux", 2346 "cfg", 2347 "bus_master", 2348 "bus_slave", 2349 "slave_q2a", 2350 "tbu"; 2351 2352 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, 2353 <0x100 &apps_smmu 0x1c11 0x1>, 2354 <0x200 &apps_smmu 0x1c12 0x1>, 2355 <0x300 &apps_smmu 0x1c13 0x1>, 2356 <0x400 &apps_smmu 0x1c14 0x1>, 2357 <0x500 &apps_smmu 0x1c15 0x1>, 2358 <0x600 &apps_smmu 0x1c16 0x1>, 2359 <0x700 &apps_smmu 0x1c17 0x1>, 2360 <0x800 &apps_smmu 0x1c18 0x1>, 2361 <0x900 &apps_smmu 0x1c19 0x1>, 2362 <0xa00 &apps_smmu 0x1c1a 0x1>, 2363 <0xb00 &apps_smmu 0x1c1b 0x1>, 2364 <0xc00 &apps_smmu 0x1c1c 0x1>, 2365 <0xd00 &apps_smmu 0x1c1d 0x1>, 2366 <0xe00 &apps_smmu 0x1c1e 0x1>, 2367 <0xf00 &apps_smmu 0x1c1f 0x1>; 2368 2369 resets = <&gcc GCC_PCIE_0_BCR>; 2370 reset-names = "pci"; 2371 2372 power-domains = <&gcc PCIE_0_GDSC>; 2373 2374 phys = <&pcie0_phy>; 2375 phy-names = "pciephy"; 2376 2377 status = "disabled"; 2378 }; 2379 2380 pcie0_phy: phy@1c06000 { 2381 compatible = "qcom,sdm845-qmp-pcie-phy"; 2382 reg = <0 0x01c06000 0 0x1000>; 2383 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2384 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2385 <&gcc GCC_PCIE_0_CLKREF_CLK>, 2386 <&gcc GCC_PCIE_PHY_REFGEN_CLK>, 2387 <&gcc GCC_PCIE_0_PIPE_CLK>; 2388 clock-names = "aux", 2389 "cfg_ahb", 2390 "ref", 2391 "refgen", 2392 "pipe"; 2393 2394 clock-output-names = "pcie_0_pipe_clk"; 2395 #clock-cells = <0>; 2396 2397 #phy-cells = <0>; 2398 2399 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2400 reset-names = "phy"; 2401 2402 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2403 assigned-clock-rates = <100000000>; 2404 2405 status = "disabled"; 2406 }; 2407 2408 pcie1: pcie@1c08000 { 2409 compatible = "qcom,pcie-sdm845"; 2410 reg = <0 0x01c08000 0 0x2000>, 2411 <0 0x40000000 0 0xf1d>, 2412 <0 0x40000f20 0 0xa8>, 2413 <0 0x40100000 0 0x100000>, 2414 <0 0x01c0c000 0 0x1000>; 2415 reg-names = "parf", "dbi", "elbi", "config", "mhi"; 2416 device_type = "pci"; 2417 linux,pci-domain = <1>; 2418 bus-range = <0x00 0xff>; 2419 num-lanes = <1>; 2420 2421 #address-cells = <3>; 2422 #size-cells = <2>; 2423 2424 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2425 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2426 2427 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 2428 interrupt-names = "msi"; 2429 #interrupt-cells = <1>; 2430 interrupt-map-mask = <0 0 0 0x7>; 2431 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2432 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2433 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2434 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2435 2436 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2437 <&gcc GCC_PCIE_1_AUX_CLK>, 2438 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2439 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2440 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2441 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2442 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2443 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2444 clock-names = "pipe", 2445 "aux", 2446 "cfg", 2447 "bus_master", 2448 "bus_slave", 2449 "slave_q2a", 2450 "ref", 2451 "tbu"; 2452 2453 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2454 assigned-clock-rates = <19200000>; 2455 2456 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2457 <0x100 &apps_smmu 0x1c01 0x1>, 2458 <0x200 &apps_smmu 0x1c02 0x1>, 2459 <0x300 &apps_smmu 0x1c03 0x1>, 2460 <0x400 &apps_smmu 0x1c04 0x1>, 2461 <0x500 &apps_smmu 0x1c05 0x1>, 2462 <0x600 &apps_smmu 0x1c06 0x1>, 2463 <0x700 &apps_smmu 0x1c07 0x1>, 2464 <0x800 &apps_smmu 0x1c08 0x1>, 2465 <0x900 &apps_smmu 0x1c09 0x1>, 2466 <0xa00 &apps_smmu 0x1c0a 0x1>, 2467 <0xb00 &apps_smmu 0x1c0b 0x1>, 2468 <0xc00 &apps_smmu 0x1c0c 0x1>, 2469 <0xd00 &apps_smmu 0x1c0d 0x1>, 2470 <0xe00 &apps_smmu 0x1c0e 0x1>, 2471 <0xf00 &apps_smmu 0x1c0f 0x1>; 2472 2473 resets = <&gcc GCC_PCIE_1_BCR>; 2474 reset-names = "pci"; 2475 2476 power-domains = <&gcc PCIE_1_GDSC>; 2477 2478 phys = <&pcie1_phy>; 2479 phy-names = "pciephy"; 2480 2481 status = "disabled"; 2482 }; 2483 2484 pcie1_phy: phy@1c0a000 { 2485 compatible = "qcom,sdm845-qhp-pcie-phy"; 2486 reg = <0 0x01c0a000 0 0x2000>; 2487 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2488 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2489 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2490 <&gcc GCC_PCIE_PHY_REFGEN_CLK>, 2491 <&gcc GCC_PCIE_1_PIPE_CLK>; 2492 clock-names = "aux", 2493 "cfg_ahb", 2494 "ref", 2495 "refgen", 2496 "pipe"; 2497 2498 clock-output-names = "pcie_1_pipe_clk"; 2499 #clock-cells = <0>; 2500 2501 #phy-cells = <0>; 2502 2503 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2504 reset-names = "phy"; 2505 2506 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2507 assigned-clock-rates = <100000000>; 2508 2509 status = "disabled"; 2510 }; 2511 2512 mem_noc: interconnect@1380000 { 2513 compatible = "qcom,sdm845-mem-noc"; 2514 reg = <0 0x01380000 0 0x27200>; 2515 #interconnect-cells = <2>; 2516 qcom,bcm-voters = <&apps_bcm_voter>; 2517 }; 2518 2519 dc_noc: interconnect@14e0000 { 2520 compatible = "qcom,sdm845-dc-noc"; 2521 reg = <0 0x014e0000 0 0x400>; 2522 #interconnect-cells = <2>; 2523 qcom,bcm-voters = <&apps_bcm_voter>; 2524 }; 2525 2526 config_noc: interconnect@1500000 { 2527 compatible = "qcom,sdm845-config-noc"; 2528 reg = <0 0x01500000 0 0x5080>; 2529 #interconnect-cells = <2>; 2530 qcom,bcm-voters = <&apps_bcm_voter>; 2531 }; 2532 2533 system_noc: interconnect@1620000 { 2534 compatible = "qcom,sdm845-system-noc"; 2535 reg = <0 0x01620000 0 0x18080>; 2536 #interconnect-cells = <2>; 2537 qcom,bcm-voters = <&apps_bcm_voter>; 2538 }; 2539 2540 aggre1_noc: interconnect@16e0000 { 2541 compatible = "qcom,sdm845-aggre1-noc"; 2542 reg = <0 0x016e0000 0 0x15080>; 2543 #interconnect-cells = <2>; 2544 qcom,bcm-voters = <&apps_bcm_voter>; 2545 }; 2546 2547 aggre2_noc: interconnect@1700000 { 2548 compatible = "qcom,sdm845-aggre2-noc"; 2549 reg = <0 0x01700000 0 0x1f300>; 2550 #interconnect-cells = <2>; 2551 qcom,bcm-voters = <&apps_bcm_voter>; 2552 }; 2553 2554 mmss_noc: interconnect@1740000 { 2555 compatible = "qcom,sdm845-mmss-noc"; 2556 reg = <0 0x01740000 0 0x1c100>; 2557 #interconnect-cells = <2>; 2558 qcom,bcm-voters = <&apps_bcm_voter>; 2559 }; 2560 2561 ufs_mem_hc: ufshc@1d84000 { 2562 compatible = "qcom,sdm845-ufshc", "qcom,ufshc", 2563 "jedec,ufs-2.0"; 2564 reg = <0 0x01d84000 0 0x2500>, 2565 <0 0x01d90000 0 0x8000>; 2566 reg-names = "std", "ice"; 2567 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2568 phys = <&ufs_mem_phy>; 2569 phy-names = "ufsphy"; 2570 lanes-per-direction = <2>; 2571 power-domains = <&gcc UFS_PHY_GDSC>; 2572 #reset-cells = <1>; 2573 resets = <&gcc GCC_UFS_PHY_BCR>; 2574 reset-names = "rst"; 2575 2576 iommus = <&apps_smmu 0x100 0xf>; 2577 2578 clock-names = 2579 "core_clk", 2580 "bus_aggr_clk", 2581 "iface_clk", 2582 "core_clk_unipro", 2583 "ref_clk", 2584 "tx_lane0_sync_clk", 2585 "rx_lane0_sync_clk", 2586 "rx_lane1_sync_clk", 2587 "ice_core_clk"; 2588 clocks = 2589 <&gcc GCC_UFS_PHY_AXI_CLK>, 2590 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2591 <&gcc GCC_UFS_PHY_AHB_CLK>, 2592 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2593 <&rpmhcc RPMH_CXO_CLK>, 2594 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2595 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2596 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2597 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2598 2599 operating-points-v2 = <&ufs_opp_table>; 2600 2601 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>, 2602 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 2603 interconnect-names = "ufs-ddr", "cpu-ufs"; 2604 2605 status = "disabled"; 2606 2607 ufs_opp_table: opp-table { 2608 compatible = "operating-points-v2"; 2609 2610 opp-50000000 { 2611 opp-hz = /bits/ 64 <50000000>, 2612 /bits/ 64 <0>, 2613 /bits/ 64 <0>, 2614 /bits/ 64 <37500000>, 2615 /bits/ 64 <0>, 2616 /bits/ 64 <0>, 2617 /bits/ 64 <0>, 2618 /bits/ 64 <0>, 2619 /bits/ 64 <75000000>; 2620 required-opps = <&rpmhpd_opp_low_svs>; 2621 }; 2622 2623 opp-200000000 { 2624 opp-hz = /bits/ 64 <200000000>, 2625 /bits/ 64 <0>, 2626 /bits/ 64 <0>, 2627 /bits/ 64 <150000000>, 2628 /bits/ 64 <0>, 2629 /bits/ 64 <0>, 2630 /bits/ 64 <0>, 2631 /bits/ 64 <0>, 2632 /bits/ 64 <300000000>; 2633 required-opps = <&rpmhpd_opp_nom>; 2634 }; 2635 }; 2636 }; 2637 2638 ufs_mem_phy: phy@1d87000 { 2639 compatible = "qcom,sdm845-qmp-ufs-phy"; 2640 reg = <0 0x01d87000 0 0x1000>; 2641 2642 clocks = <&rpmhcc RPMH_CXO_CLK>, 2643 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2644 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 2645 clock-names = "ref", 2646 "ref_aux", 2647 "qref"; 2648 2649 resets = <&ufs_mem_hc 0>; 2650 reset-names = "ufsphy"; 2651 2652 #phy-cells = <0>; 2653 status = "disabled"; 2654 }; 2655 2656 cryptobam: dma-controller@1dc4000 { 2657 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2658 reg = <0 0x01dc4000 0 0x24000>; 2659 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2660 clocks = <&rpmhcc RPMH_CE_CLK>; 2661 clock-names = "bam_clk"; 2662 #dma-cells = <1>; 2663 qcom,ee = <0>; 2664 qcom,controlled-remotely; 2665 iommus = <&apps_smmu 0x704 0x1>, 2666 <&apps_smmu 0x706 0x1>, 2667 <&apps_smmu 0x714 0x1>, 2668 <&apps_smmu 0x716 0x1>; 2669 }; 2670 2671 crypto: crypto@1dfa000 { 2672 compatible = "qcom,crypto-v5.4"; 2673 reg = <0 0x01dfa000 0 0x6000>; 2674 clocks = <&gcc GCC_CE1_AHB_CLK>, 2675 <&gcc GCC_CE1_AXI_CLK>, 2676 <&rpmhcc RPMH_CE_CLK>; 2677 clock-names = "iface", "bus", "core"; 2678 dmas = <&cryptobam 6>, <&cryptobam 7>; 2679 dma-names = "rx", "tx"; 2680 iommus = <&apps_smmu 0x704 0x1>, 2681 <&apps_smmu 0x706 0x1>, 2682 <&apps_smmu 0x714 0x1>, 2683 <&apps_smmu 0x716 0x1>; 2684 }; 2685 2686 ipa: ipa@1e40000 { 2687 compatible = "qcom,sdm845-ipa"; 2688 2689 iommus = <&apps_smmu 0x720 0x0>, 2690 <&apps_smmu 0x722 0x0>; 2691 reg = <0 0x01e40000 0 0x7000>, 2692 <0 0x01e47000 0 0x2000>, 2693 <0 0x01e04000 0 0x2c000>; 2694 reg-names = "ipa-reg", 2695 "ipa-shared", 2696 "gsi"; 2697 2698 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 2699 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2700 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2701 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2702 interrupt-names = "ipa", 2703 "gsi", 2704 "ipa-clock-query", 2705 "ipa-setup-ready"; 2706 2707 clocks = <&rpmhcc RPMH_IPA_CLK>; 2708 clock-names = "core"; 2709 2710 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>, 2711 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 2712 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2713 interconnect-names = "memory", 2714 "imem", 2715 "config"; 2716 2717 qcom,smem-states = <&ipa_smp2p_out 0>, 2718 <&ipa_smp2p_out 1>; 2719 qcom,smem-state-names = "ipa-clock-enabled-valid", 2720 "ipa-clock-enabled"; 2721 2722 status = "disabled"; 2723 }; 2724 2725 tcsr_mutex: hwlock@1f40000 { 2726 compatible = "qcom,tcsr-mutex"; 2727 reg = <0 0x01f40000 0 0x20000>; 2728 #hwlock-cells = <1>; 2729 }; 2730 2731 tcsr_regs_1: syscon@1f60000 { 2732 compatible = "qcom,sdm845-tcsr", "syscon"; 2733 reg = <0 0x01f60000 0 0x20000>; 2734 }; 2735 2736 tlmm: pinctrl@3400000 { 2737 compatible = "qcom,sdm845-pinctrl"; 2738 reg = <0 0x03400000 0 0xc00000>; 2739 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2740 gpio-controller; 2741 #gpio-cells = <2>; 2742 interrupt-controller; 2743 #interrupt-cells = <2>; 2744 gpio-ranges = <&tlmm 0 0 151>; 2745 wakeup-parent = <&pdc_intc>; 2746 2747 cci0_default: cci0-default-state { 2748 /* SDA, SCL */ 2749 pins = "gpio17", "gpio18"; 2750 function = "cci_i2c"; 2751 2752 bias-pull-up; 2753 drive-strength = <2>; /* 2 mA */ 2754 }; 2755 2756 cci0_sleep: cci0-sleep-state { 2757 /* SDA, SCL */ 2758 pins = "gpio17", "gpio18"; 2759 function = "cci_i2c"; 2760 2761 drive-strength = <2>; /* 2 mA */ 2762 bias-pull-down; 2763 }; 2764 2765 cci1_default: cci1-default-state { 2766 /* SDA, SCL */ 2767 pins = "gpio19", "gpio20"; 2768 function = "cci_i2c"; 2769 2770 bias-pull-up; 2771 drive-strength = <2>; /* 2 mA */ 2772 }; 2773 2774 cci1_sleep: cci1-sleep-state { 2775 /* SDA, SCL */ 2776 pins = "gpio19", "gpio20"; 2777 function = "cci_i2c"; 2778 2779 drive-strength = <2>; /* 2 mA */ 2780 bias-pull-down; 2781 }; 2782 2783 qspi_clk: qspi-clk-state { 2784 pins = "gpio95"; 2785 function = "qspi_clk"; 2786 }; 2787 2788 qspi_cs0: qspi-cs0-state { 2789 pins = "gpio90"; 2790 function = "qspi_cs"; 2791 }; 2792 2793 qspi_cs1: qspi-cs1-state { 2794 pins = "gpio89"; 2795 function = "qspi_cs"; 2796 }; 2797 2798 qspi_data0: qspi-data0-state { 2799 pins = "gpio91"; 2800 function = "qspi_data"; 2801 }; 2802 2803 qspi_data1: qspi-data1-state { 2804 pins = "gpio92"; 2805 function = "qspi_data"; 2806 }; 2807 2808 qspi_data23: qspi-data23-state { 2809 pins = "gpio93", "gpio94"; 2810 function = "qspi_data"; 2811 }; 2812 2813 qup_i2c0_default: qup-i2c0-default-state { 2814 pins = "gpio0", "gpio1"; 2815 function = "qup0"; 2816 }; 2817 2818 qup_i2c1_default: qup-i2c1-default-state { 2819 pins = "gpio17", "gpio18"; 2820 function = "qup1"; 2821 }; 2822 2823 qup_i2c2_default: qup-i2c2-default-state { 2824 pins = "gpio27", "gpio28"; 2825 function = "qup2"; 2826 }; 2827 2828 qup_i2c3_default: qup-i2c3-default-state { 2829 pins = "gpio41", "gpio42"; 2830 function = "qup3"; 2831 }; 2832 2833 qup_i2c4_default: qup-i2c4-default-state { 2834 pins = "gpio89", "gpio90"; 2835 function = "qup4"; 2836 }; 2837 2838 qup_i2c5_default: qup-i2c5-default-state { 2839 pins = "gpio85", "gpio86"; 2840 function = "qup5"; 2841 }; 2842 2843 qup_i2c6_default: qup-i2c6-default-state { 2844 pins = "gpio45", "gpio46"; 2845 function = "qup6"; 2846 }; 2847 2848 qup_i2c7_default: qup-i2c7-default-state { 2849 pins = "gpio93", "gpio94"; 2850 function = "qup7"; 2851 }; 2852 2853 qup_i2c8_default: qup-i2c8-default-state { 2854 pins = "gpio65", "gpio66"; 2855 function = "qup8"; 2856 }; 2857 2858 qup_i2c9_default: qup-i2c9-default-state { 2859 pins = "gpio6", "gpio7"; 2860 function = "qup9"; 2861 }; 2862 2863 qup_i2c10_default: qup-i2c10-default-state { 2864 pins = "gpio55", "gpio56"; 2865 function = "qup10"; 2866 }; 2867 2868 qup_i2c11_default: qup-i2c11-default-state { 2869 pins = "gpio31", "gpio32"; 2870 function = "qup11"; 2871 }; 2872 2873 qup_i2c12_default: qup-i2c12-default-state { 2874 pins = "gpio49", "gpio50"; 2875 function = "qup12"; 2876 }; 2877 2878 qup_i2c13_default: qup-i2c13-default-state { 2879 pins = "gpio105", "gpio106"; 2880 function = "qup13"; 2881 }; 2882 2883 qup_i2c14_default: qup-i2c14-default-state { 2884 pins = "gpio33", "gpio34"; 2885 function = "qup14"; 2886 }; 2887 2888 qup_i2c15_default: qup-i2c15-default-state { 2889 pins = "gpio81", "gpio82"; 2890 function = "qup15"; 2891 }; 2892 2893 qup_spi0_default: qup-spi0-default-state { 2894 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2895 function = "qup0"; 2896 }; 2897 2898 qup_spi1_default: qup-spi1-default-state { 2899 pins = "gpio17", "gpio18", "gpio19", "gpio20"; 2900 function = "qup1"; 2901 }; 2902 2903 qup_spi2_default: qup-spi2-default-state { 2904 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2905 function = "qup2"; 2906 }; 2907 2908 qup_spi3_default: qup-spi3-default-state { 2909 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 2910 function = "qup3"; 2911 }; 2912 2913 qup_spi4_default: qup-spi4-default-state { 2914 pins = "gpio89", "gpio90", "gpio91", "gpio92"; 2915 function = "qup4"; 2916 }; 2917 2918 qup_spi5_default: qup-spi5-default-state { 2919 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 2920 function = "qup5"; 2921 }; 2922 2923 qup_spi6_default: qup-spi6-default-state { 2924 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 2925 function = "qup6"; 2926 }; 2927 2928 qup_spi7_default: qup-spi7-default-state { 2929 pins = "gpio93", "gpio94", "gpio95", "gpio96"; 2930 function = "qup7"; 2931 }; 2932 2933 qup_spi8_default: qup-spi8-default-state { 2934 pins = "gpio65", "gpio66", "gpio67", "gpio68"; 2935 function = "qup8"; 2936 }; 2937 2938 qup_spi9_default: qup-spi9-default-state { 2939 pins = "gpio6", "gpio7", "gpio4", "gpio5"; 2940 function = "qup9"; 2941 }; 2942 2943 qup_spi10_default: qup-spi10-default-state { 2944 pins = "gpio55", "gpio56", "gpio53", "gpio54"; 2945 function = "qup10"; 2946 }; 2947 2948 qup_spi11_default: qup-spi11-default-state { 2949 pins = "gpio31", "gpio32", "gpio33", "gpio34"; 2950 function = "qup11"; 2951 }; 2952 2953 qup_spi12_default: qup-spi12-default-state { 2954 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 2955 function = "qup12"; 2956 }; 2957 2958 qup_spi13_default: qup-spi13-default-state { 2959 pins = "gpio105", "gpio106", "gpio107", "gpio108"; 2960 function = "qup13"; 2961 }; 2962 2963 qup_spi14_default: qup-spi14-default-state { 2964 pins = "gpio33", "gpio34", "gpio31", "gpio32"; 2965 function = "qup14"; 2966 }; 2967 2968 qup_spi15_default: qup-spi15-default-state { 2969 pins = "gpio81", "gpio82", "gpio83", "gpio84"; 2970 function = "qup15"; 2971 }; 2972 2973 qup_uart0_default: qup-uart0-default-state { 2974 qup_uart0_tx: tx-pins { 2975 pins = "gpio2"; 2976 function = "qup0"; 2977 }; 2978 2979 qup_uart0_rx: rx-pins { 2980 pins = "gpio3"; 2981 function = "qup0"; 2982 }; 2983 }; 2984 2985 qup_uart1_default: qup-uart1-default-state { 2986 qup_uart1_tx: tx-pins { 2987 pins = "gpio19"; 2988 function = "qup1"; 2989 }; 2990 2991 qup_uart1_rx: rx-pins { 2992 pins = "gpio20"; 2993 function = "qup1"; 2994 }; 2995 }; 2996 2997 qup_uart2_default: qup-uart2-default-state { 2998 qup_uart2_tx: tx-pins { 2999 pins = "gpio29"; 3000 function = "qup2"; 3001 }; 3002 3003 qup_uart2_rx: rx-pins { 3004 pins = "gpio30"; 3005 function = "qup2"; 3006 }; 3007 }; 3008 3009 qup_uart3_default: qup-uart3-default-state { 3010 qup_uart3_tx: tx-pins { 3011 pins = "gpio43"; 3012 function = "qup3"; 3013 }; 3014 3015 qup_uart3_rx: rx-pins { 3016 pins = "gpio44"; 3017 function = "qup3"; 3018 }; 3019 }; 3020 3021 qup_uart3_4pin: qup-uart3-4pin-state { 3022 qup_uart3_4pin_cts: cts-pins { 3023 pins = "gpio41"; 3024 function = "qup3"; 3025 }; 3026 3027 qup_uart3_4pin_rts_tx: rts-tx-pins { 3028 pins = "gpio42", "gpio43"; 3029 function = "qup3"; 3030 }; 3031 3032 qup_uart3_4pin_rx: rx-pins { 3033 pins = "gpio44"; 3034 function = "qup3"; 3035 }; 3036 }; 3037 3038 qup_uart4_default: qup-uart4-default-state { 3039 qup_uart4_tx: tx-pins { 3040 pins = "gpio91"; 3041 function = "qup4"; 3042 }; 3043 3044 qup_uart4_rx: rx-pins { 3045 pins = "gpio92"; 3046 function = "qup4"; 3047 }; 3048 }; 3049 3050 qup_uart5_default: qup-uart5-default-state { 3051 qup_uart5_tx: tx-pins { 3052 pins = "gpio87"; 3053 function = "qup5"; 3054 }; 3055 3056 qup_uart5_rx: rx-pins { 3057 pins = "gpio88"; 3058 function = "qup5"; 3059 }; 3060 }; 3061 3062 qup_uart6_default: qup-uart6-default-state { 3063 qup_uart6_tx: tx-pins { 3064 pins = "gpio47"; 3065 function = "qup6"; 3066 }; 3067 3068 qup_uart6_rx: rx-pins { 3069 pins = "gpio48"; 3070 function = "qup6"; 3071 }; 3072 }; 3073 3074 qup_uart6_4pin: qup-uart6-4pin-state { 3075 qup_uart6_4pin_cts: cts-pins { 3076 pins = "gpio45"; 3077 function = "qup6"; 3078 bias-pull-down; 3079 }; 3080 3081 qup_uart6_4pin_rts_tx: rts-tx-pins { 3082 pins = "gpio46", "gpio47"; 3083 function = "qup6"; 3084 drive-strength = <2>; 3085 bias-disable; 3086 }; 3087 3088 qup_uart6_4pin_rx: rx-pins { 3089 pins = "gpio48"; 3090 function = "qup6"; 3091 bias-pull-up; 3092 }; 3093 }; 3094 3095 qup_uart7_default: qup-uart7-default-state { 3096 qup_uart7_tx: tx-pins { 3097 pins = "gpio95"; 3098 function = "qup7"; 3099 }; 3100 3101 qup_uart7_rx: rx-pins { 3102 pins = "gpio96"; 3103 function = "qup7"; 3104 }; 3105 }; 3106 3107 qup_uart8_default: qup-uart8-default-state { 3108 qup_uart8_tx: tx-pins { 3109 pins = "gpio67"; 3110 function = "qup8"; 3111 }; 3112 3113 qup_uart8_rx: rx-pins { 3114 pins = "gpio68"; 3115 function = "qup8"; 3116 }; 3117 }; 3118 3119 qup_uart9_default: qup-uart9-default-state { 3120 qup_uart9_tx: tx-pins { 3121 pins = "gpio4"; 3122 function = "qup9"; 3123 }; 3124 3125 qup_uart9_rx: rx-pins { 3126 pins = "gpio5"; 3127 function = "qup9"; 3128 }; 3129 }; 3130 3131 qup_uart10_default: qup-uart10-default-state { 3132 qup_uart10_tx: tx-pins { 3133 pins = "gpio53"; 3134 function = "qup10"; 3135 }; 3136 3137 qup_uart10_rx: rx-pins { 3138 pins = "gpio54"; 3139 function = "qup10"; 3140 }; 3141 }; 3142 3143 qup_uart11_default: qup-uart11-default-state { 3144 qup_uart11_tx: tx-pins { 3145 pins = "gpio33"; 3146 function = "qup11"; 3147 }; 3148 3149 qup_uart11_rx: rx-pins { 3150 pins = "gpio34"; 3151 function = "qup11"; 3152 }; 3153 }; 3154 3155 qup_uart12_default: qup-uart12-default-state { 3156 qup_uart12_tx: tx-pins { 3157 pins = "gpio51"; 3158 function = "qup0"; 3159 }; 3160 3161 qup_uart12_rx: rx-pins { 3162 pins = "gpio52"; 3163 function = "qup0"; 3164 }; 3165 }; 3166 3167 qup_uart13_default: qup-uart13-default-state { 3168 qup_uart13_tx: tx-pins { 3169 pins = "gpio107"; 3170 function = "qup13"; 3171 }; 3172 3173 qup_uart13_rx: rx-pins { 3174 pins = "gpio108"; 3175 function = "qup13"; 3176 }; 3177 }; 3178 3179 qup_uart14_default: qup-uart14-default-state { 3180 qup_uart14_tx: tx-pins { 3181 pins = "gpio31"; 3182 function = "qup14"; 3183 }; 3184 3185 qup_uart14_rx: rx-pins { 3186 pins = "gpio32"; 3187 function = "qup14"; 3188 }; 3189 }; 3190 3191 qup_uart15_default: qup-uart15-default-state { 3192 qup_uart15_tx: tx-pins { 3193 pins = "gpio83"; 3194 function = "qup15"; 3195 }; 3196 3197 qup_uart15_rx: rx-pins { 3198 pins = "gpio84"; 3199 function = "qup15"; 3200 }; 3201 }; 3202 3203 quat_mi2s_sleep: quat-mi2s-sleep-state { 3204 pins = "gpio58", "gpio59"; 3205 function = "gpio"; 3206 drive-strength = <2>; 3207 bias-pull-down; 3208 }; 3209 3210 quat_mi2s_active: quat-mi2s-active-state { 3211 pins = "gpio58", "gpio59"; 3212 function = "qua_mi2s"; 3213 drive-strength = <8>; 3214 bias-disable; 3215 output-high; 3216 }; 3217 3218 quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state { 3219 pins = "gpio60"; 3220 function = "gpio"; 3221 drive-strength = <2>; 3222 bias-pull-down; 3223 }; 3224 3225 quat_mi2s_sd0_active: quat-mi2s-sd0-active-state { 3226 pins = "gpio60"; 3227 function = "qua_mi2s"; 3228 drive-strength = <8>; 3229 bias-disable; 3230 }; 3231 3232 quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state { 3233 pins = "gpio61"; 3234 function = "gpio"; 3235 drive-strength = <2>; 3236 bias-pull-down; 3237 }; 3238 3239 quat_mi2s_sd1_active: quat-mi2s-sd1-active-state { 3240 pins = "gpio61"; 3241 function = "qua_mi2s"; 3242 drive-strength = <8>; 3243 bias-disable; 3244 }; 3245 3246 quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state { 3247 pins = "gpio62"; 3248 function = "gpio"; 3249 drive-strength = <2>; 3250 bias-pull-down; 3251 }; 3252 3253 quat_mi2s_sd2_active: quat-mi2s-sd2-active-state { 3254 pins = "gpio62"; 3255 function = "qua_mi2s"; 3256 drive-strength = <8>; 3257 bias-disable; 3258 }; 3259 3260 quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state { 3261 pins = "gpio63"; 3262 function = "gpio"; 3263 drive-strength = <2>; 3264 bias-pull-down; 3265 }; 3266 3267 quat_mi2s_sd3_active: quat-mi2s-sd3-active-state { 3268 pins = "gpio63"; 3269 function = "qua_mi2s"; 3270 drive-strength = <8>; 3271 bias-disable; 3272 }; 3273 }; 3274 3275 mss_pil: remoteproc@4080000 { 3276 compatible = "qcom,sdm845-mss-pil"; 3277 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; 3278 reg-names = "qdsp6", "rmb"; 3279 3280 interrupts-extended = 3281 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 3282 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3283 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3284 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3285 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3286 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3287 interrupt-names = "wdog", "fatal", "ready", 3288 "handover", "stop-ack", 3289 "shutdown-ack"; 3290 3291 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 3292 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 3293 <&gcc GCC_BOOT_ROM_AHB_CLK>, 3294 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 3295 <&gcc GCC_MSS_SNOC_AXI_CLK>, 3296 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 3297 <&gcc GCC_PRNG_AHB_CLK>, 3298 <&rpmhcc RPMH_CXO_CLK>; 3299 clock-names = "iface", "bus", "mem", "gpll0_mss", 3300 "snoc_axi", "mnoc_axi", "prng", "xo"; 3301 3302 qcom,qmp = <&aoss_qmp>; 3303 3304 qcom,smem-states = <&modem_smp2p_out 0>; 3305 qcom,smem-state-names = "stop"; 3306 3307 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 3308 <&pdc_reset PDC_MODEM_SYNC_RESET>; 3309 reset-names = "mss_restart", "pdc_reset"; 3310 3311 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 3312 3313 power-domains = <&rpmhpd SDM845_CX>, 3314 <&rpmhpd SDM845_MX>, 3315 <&rpmhpd SDM845_MSS>; 3316 power-domain-names = "cx", "mx", "mss"; 3317 3318 status = "disabled"; 3319 3320 mba { 3321 memory-region = <&mba_region>; 3322 }; 3323 3324 mpss { 3325 memory-region = <&mpss_region>; 3326 }; 3327 3328 metadata { 3329 memory-region = <&mdata_mem>; 3330 }; 3331 3332 glink-edge { 3333 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 3334 label = "modem"; 3335 qcom,remote-pid = <1>; 3336 mboxes = <&apss_shared 12>; 3337 }; 3338 }; 3339 3340 gpucc: clock-controller@5090000 { 3341 compatible = "qcom,sdm845-gpucc"; 3342 reg = <0 0x05090000 0 0x9000>; 3343 #clock-cells = <1>; 3344 #reset-cells = <1>; 3345 #power-domain-cells = <1>; 3346 clocks = <&rpmhcc RPMH_CXO_CLK>, 3347 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3348 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3349 clock-names = "bi_tcxo", 3350 "gcc_gpu_gpll0_clk_src", 3351 "gcc_gpu_gpll0_div_clk_src"; 3352 }; 3353 3354 slpi_pas: remoteproc@5c00000 { 3355 compatible = "qcom,sdm845-slpi-pas"; 3356 reg = <0 0x5c00000 0 0x4000>; 3357 3358 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 3359 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3360 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3361 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3362 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3363 interrupt-names = "wdog", "fatal", "ready", 3364 "handover", "stop-ack"; 3365 3366 clocks = <&rpmhcc RPMH_CXO_CLK>; 3367 clock-names = "xo"; 3368 3369 qcom,qmp = <&aoss_qmp>; 3370 3371 power-domains = <&rpmhpd SDM845_LCX>, 3372 <&rpmhpd SDM845_LMX>; 3373 power-domain-names = "lcx", "lmx"; 3374 3375 memory-region = <&slpi_mem>; 3376 3377 qcom,smem-states = <&slpi_smp2p_out 0>; 3378 qcom,smem-state-names = "stop"; 3379 3380 status = "disabled"; 3381 3382 glink-edge { 3383 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 3384 label = "dsps"; 3385 qcom,remote-pid = <3>; 3386 mboxes = <&apss_shared 24>; 3387 3388 fastrpc { 3389 compatible = "qcom,fastrpc"; 3390 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3391 label = "sdsp"; 3392 qcom,non-secure-domain; 3393 qcom,vmids = <QCOM_SCM_VMID_HLOS QCOM_SCM_VMID_MSS_MSA 3394 QCOM_SCM_VMID_SSC_Q6 QCOM_SCM_VMID_ADSP_Q6>; 3395 memory-region = <&fastrpc_mem>; 3396 #address-cells = <1>; 3397 #size-cells = <0>; 3398 3399 compute-cb@0 { 3400 compatible = "qcom,fastrpc-compute-cb"; 3401 reg = <0>; 3402 }; 3403 }; 3404 }; 3405 }; 3406 3407 stm@6002000 { 3408 compatible = "arm,coresight-stm", "arm,primecell"; 3409 reg = <0 0x06002000 0 0x1000>, 3410 <0 0x16280000 0 0x180000>; 3411 reg-names = "stm-base", "stm-stimulus-base"; 3412 3413 clocks = <&aoss_qmp>; 3414 clock-names = "apb_pclk"; 3415 3416 out-ports { 3417 port { 3418 stm_out: endpoint { 3419 remote-endpoint = 3420 <&funnel0_in7>; 3421 }; 3422 }; 3423 }; 3424 }; 3425 3426 funnel@6041000 { 3427 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3428 reg = <0 0x06041000 0 0x1000>; 3429 3430 clocks = <&aoss_qmp>; 3431 clock-names = "apb_pclk"; 3432 3433 out-ports { 3434 port { 3435 funnel0_out: endpoint { 3436 remote-endpoint = 3437 <&merge_funnel_in0>; 3438 }; 3439 }; 3440 }; 3441 3442 in-ports { 3443 #address-cells = <1>; 3444 #size-cells = <0>; 3445 3446 port@7 { 3447 reg = <7>; 3448 funnel0_in7: endpoint { 3449 remote-endpoint = <&stm_out>; 3450 }; 3451 }; 3452 }; 3453 }; 3454 3455 funnel@6043000 { 3456 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3457 reg = <0 0x06043000 0 0x1000>; 3458 3459 clocks = <&aoss_qmp>; 3460 clock-names = "apb_pclk"; 3461 3462 out-ports { 3463 port { 3464 funnel2_out: endpoint { 3465 remote-endpoint = 3466 <&merge_funnel_in2>; 3467 }; 3468 }; 3469 }; 3470 3471 in-ports { 3472 #address-cells = <1>; 3473 #size-cells = <0>; 3474 3475 port@5 { 3476 reg = <5>; 3477 funnel2_in5: endpoint { 3478 remote-endpoint = 3479 <&apss_merge_funnel_out>; 3480 }; 3481 }; 3482 }; 3483 }; 3484 3485 funnel@6045000 { 3486 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3487 reg = <0 0x06045000 0 0x1000>; 3488 3489 clocks = <&aoss_qmp>; 3490 clock-names = "apb_pclk"; 3491 3492 out-ports { 3493 port { 3494 merge_funnel_out: endpoint { 3495 remote-endpoint = <&etf_in>; 3496 }; 3497 }; 3498 }; 3499 3500 in-ports { 3501 #address-cells = <1>; 3502 #size-cells = <0>; 3503 3504 port@0 { 3505 reg = <0>; 3506 merge_funnel_in0: endpoint { 3507 remote-endpoint = 3508 <&funnel0_out>; 3509 }; 3510 }; 3511 3512 port@2 { 3513 reg = <2>; 3514 merge_funnel_in2: endpoint { 3515 remote-endpoint = 3516 <&funnel2_out>; 3517 }; 3518 }; 3519 }; 3520 }; 3521 3522 replicator@6046000 { 3523 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3524 reg = <0 0x06046000 0 0x1000>; 3525 3526 clocks = <&aoss_qmp>; 3527 clock-names = "apb_pclk"; 3528 3529 out-ports { 3530 port { 3531 replicator_out: endpoint { 3532 remote-endpoint = <&etr_in>; 3533 }; 3534 }; 3535 }; 3536 3537 in-ports { 3538 port { 3539 replicator_in: endpoint { 3540 remote-endpoint = <&etf_out>; 3541 }; 3542 }; 3543 }; 3544 }; 3545 3546 etf@6047000 { 3547 compatible = "arm,coresight-tmc", "arm,primecell"; 3548 reg = <0 0x06047000 0 0x1000>; 3549 3550 clocks = <&aoss_qmp>; 3551 clock-names = "apb_pclk"; 3552 3553 out-ports { 3554 port { 3555 etf_out: endpoint { 3556 remote-endpoint = 3557 <&replicator_in>; 3558 }; 3559 }; 3560 }; 3561 3562 in-ports { 3563 3564 port { 3565 etf_in: endpoint { 3566 remote-endpoint = 3567 <&merge_funnel_out>; 3568 }; 3569 }; 3570 }; 3571 }; 3572 3573 etr@6048000 { 3574 compatible = "arm,coresight-tmc", "arm,primecell"; 3575 reg = <0 0x06048000 0 0x1000>; 3576 3577 clocks = <&aoss_qmp>; 3578 clock-names = "apb_pclk"; 3579 arm,scatter-gather; 3580 3581 in-ports { 3582 port { 3583 etr_in: endpoint { 3584 remote-endpoint = 3585 <&replicator_out>; 3586 }; 3587 }; 3588 }; 3589 }; 3590 3591 etm@7040000 { 3592 compatible = "arm,coresight-etm4x", "arm,primecell"; 3593 reg = <0 0x07040000 0 0x1000>; 3594 3595 cpu = <&CPU0>; 3596 3597 clocks = <&aoss_qmp>; 3598 clock-names = "apb_pclk"; 3599 arm,coresight-loses-context-with-cpu; 3600 3601 out-ports { 3602 port { 3603 etm0_out: endpoint { 3604 remote-endpoint = 3605 <&apss_funnel_in0>; 3606 }; 3607 }; 3608 }; 3609 }; 3610 3611 etm@7140000 { 3612 compatible = "arm,coresight-etm4x", "arm,primecell"; 3613 reg = <0 0x07140000 0 0x1000>; 3614 3615 cpu = <&CPU1>; 3616 3617 clocks = <&aoss_qmp>; 3618 clock-names = "apb_pclk"; 3619 arm,coresight-loses-context-with-cpu; 3620 3621 out-ports { 3622 port { 3623 etm1_out: endpoint { 3624 remote-endpoint = 3625 <&apss_funnel_in1>; 3626 }; 3627 }; 3628 }; 3629 }; 3630 3631 etm@7240000 { 3632 compatible = "arm,coresight-etm4x", "arm,primecell"; 3633 reg = <0 0x07240000 0 0x1000>; 3634 3635 cpu = <&CPU2>; 3636 3637 clocks = <&aoss_qmp>; 3638 clock-names = "apb_pclk"; 3639 arm,coresight-loses-context-with-cpu; 3640 3641 out-ports { 3642 port { 3643 etm2_out: endpoint { 3644 remote-endpoint = 3645 <&apss_funnel_in2>; 3646 }; 3647 }; 3648 }; 3649 }; 3650 3651 etm@7340000 { 3652 compatible = "arm,coresight-etm4x", "arm,primecell"; 3653 reg = <0 0x07340000 0 0x1000>; 3654 3655 cpu = <&CPU3>; 3656 3657 clocks = <&aoss_qmp>; 3658 clock-names = "apb_pclk"; 3659 arm,coresight-loses-context-with-cpu; 3660 3661 out-ports { 3662 port { 3663 etm3_out: endpoint { 3664 remote-endpoint = 3665 <&apss_funnel_in3>; 3666 }; 3667 }; 3668 }; 3669 }; 3670 3671 etm@7440000 { 3672 compatible = "arm,coresight-etm4x", "arm,primecell"; 3673 reg = <0 0x07440000 0 0x1000>; 3674 3675 cpu = <&CPU4>; 3676 3677 clocks = <&aoss_qmp>; 3678 clock-names = "apb_pclk"; 3679 arm,coresight-loses-context-with-cpu; 3680 3681 out-ports { 3682 port { 3683 etm4_out: endpoint { 3684 remote-endpoint = 3685 <&apss_funnel_in4>; 3686 }; 3687 }; 3688 }; 3689 }; 3690 3691 etm@7540000 { 3692 compatible = "arm,coresight-etm4x", "arm,primecell"; 3693 reg = <0 0x07540000 0 0x1000>; 3694 3695 cpu = <&CPU5>; 3696 3697 clocks = <&aoss_qmp>; 3698 clock-names = "apb_pclk"; 3699 arm,coresight-loses-context-with-cpu; 3700 3701 out-ports { 3702 port { 3703 etm5_out: endpoint { 3704 remote-endpoint = 3705 <&apss_funnel_in5>; 3706 }; 3707 }; 3708 }; 3709 }; 3710 3711 etm@7640000 { 3712 compatible = "arm,coresight-etm4x", "arm,primecell"; 3713 reg = <0 0x07640000 0 0x1000>; 3714 3715 cpu = <&CPU6>; 3716 3717 clocks = <&aoss_qmp>; 3718 clock-names = "apb_pclk"; 3719 arm,coresight-loses-context-with-cpu; 3720 3721 out-ports { 3722 port { 3723 etm6_out: endpoint { 3724 remote-endpoint = 3725 <&apss_funnel_in6>; 3726 }; 3727 }; 3728 }; 3729 }; 3730 3731 etm@7740000 { 3732 compatible = "arm,coresight-etm4x", "arm,primecell"; 3733 reg = <0 0x07740000 0 0x1000>; 3734 3735 cpu = <&CPU7>; 3736 3737 clocks = <&aoss_qmp>; 3738 clock-names = "apb_pclk"; 3739 arm,coresight-loses-context-with-cpu; 3740 3741 out-ports { 3742 port { 3743 etm7_out: endpoint { 3744 remote-endpoint = 3745 <&apss_funnel_in7>; 3746 }; 3747 }; 3748 }; 3749 }; 3750 3751 funnel@7800000 { /* APSS Funnel */ 3752 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3753 reg = <0 0x07800000 0 0x1000>; 3754 3755 clocks = <&aoss_qmp>; 3756 clock-names = "apb_pclk"; 3757 3758 out-ports { 3759 port { 3760 apss_funnel_out: endpoint { 3761 remote-endpoint = 3762 <&apss_merge_funnel_in>; 3763 }; 3764 }; 3765 }; 3766 3767 in-ports { 3768 #address-cells = <1>; 3769 #size-cells = <0>; 3770 3771 port@0 { 3772 reg = <0>; 3773 apss_funnel_in0: endpoint { 3774 remote-endpoint = 3775 <&etm0_out>; 3776 }; 3777 }; 3778 3779 port@1 { 3780 reg = <1>; 3781 apss_funnel_in1: endpoint { 3782 remote-endpoint = 3783 <&etm1_out>; 3784 }; 3785 }; 3786 3787 port@2 { 3788 reg = <2>; 3789 apss_funnel_in2: endpoint { 3790 remote-endpoint = 3791 <&etm2_out>; 3792 }; 3793 }; 3794 3795 port@3 { 3796 reg = <3>; 3797 apss_funnel_in3: endpoint { 3798 remote-endpoint = 3799 <&etm3_out>; 3800 }; 3801 }; 3802 3803 port@4 { 3804 reg = <4>; 3805 apss_funnel_in4: endpoint { 3806 remote-endpoint = 3807 <&etm4_out>; 3808 }; 3809 }; 3810 3811 port@5 { 3812 reg = <5>; 3813 apss_funnel_in5: endpoint { 3814 remote-endpoint = 3815 <&etm5_out>; 3816 }; 3817 }; 3818 3819 port@6 { 3820 reg = <6>; 3821 apss_funnel_in6: endpoint { 3822 remote-endpoint = 3823 <&etm6_out>; 3824 }; 3825 }; 3826 3827 port@7 { 3828 reg = <7>; 3829 apss_funnel_in7: endpoint { 3830 remote-endpoint = 3831 <&etm7_out>; 3832 }; 3833 }; 3834 }; 3835 }; 3836 3837 funnel@7810000 { 3838 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3839 reg = <0 0x07810000 0 0x1000>; 3840 3841 clocks = <&aoss_qmp>; 3842 clock-names = "apb_pclk"; 3843 3844 out-ports { 3845 port { 3846 apss_merge_funnel_out: endpoint { 3847 remote-endpoint = 3848 <&funnel2_in5>; 3849 }; 3850 }; 3851 }; 3852 3853 in-ports { 3854 port { 3855 apss_merge_funnel_in: endpoint { 3856 remote-endpoint = 3857 <&apss_funnel_out>; 3858 }; 3859 }; 3860 }; 3861 }; 3862 3863 sdhc_2: mmc@8804000 { 3864 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 3865 reg = <0 0x08804000 0 0x1000>; 3866 3867 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3868 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3869 interrupt-names = "hc_irq", "pwr_irq"; 3870 3871 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3872 <&gcc GCC_SDCC2_APPS_CLK>, 3873 <&rpmhcc RPMH_CXO_CLK>; 3874 clock-names = "iface", "core", "xo"; 3875 iommus = <&apps_smmu 0xa0 0xf>; 3876 power-domains = <&rpmhpd SDM845_CX>; 3877 operating-points-v2 = <&sdhc2_opp_table>; 3878 3879 status = "disabled"; 3880 3881 sdhc2_opp_table: opp-table { 3882 compatible = "operating-points-v2"; 3883 3884 opp-9600000 { 3885 opp-hz = /bits/ 64 <9600000>; 3886 required-opps = <&rpmhpd_opp_min_svs>; 3887 }; 3888 3889 opp-19200000 { 3890 opp-hz = /bits/ 64 <19200000>; 3891 required-opps = <&rpmhpd_opp_low_svs>; 3892 }; 3893 3894 opp-100000000 { 3895 opp-hz = /bits/ 64 <100000000>; 3896 required-opps = <&rpmhpd_opp_svs>; 3897 }; 3898 3899 opp-201500000 { 3900 opp-hz = /bits/ 64 <201500000>; 3901 required-opps = <&rpmhpd_opp_svs_l1>; 3902 }; 3903 }; 3904 }; 3905 3906 qspi: spi@88df000 { 3907 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 3908 reg = <0 0x088df000 0 0x600>; 3909 iommus = <&apps_smmu 0x160 0x0>; 3910 #address-cells = <1>; 3911 #size-cells = <0>; 3912 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3913 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3914 <&gcc GCC_QSPI_CORE_CLK>; 3915 clock-names = "iface", "core"; 3916 power-domains = <&rpmhpd SDM845_CX>; 3917 operating-points-v2 = <&qspi_opp_table>; 3918 status = "disabled"; 3919 }; 3920 3921 slim: slim-ngd@171c0000 { 3922 compatible = "qcom,slim-ngd-v2.1.0"; 3923 reg = <0 0x171c0000 0 0x2c000>; 3924 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 3925 3926 dmas = <&slimbam 3>, <&slimbam 4>; 3927 dma-names = "rx", "tx"; 3928 3929 iommus = <&apps_smmu 0x1806 0x0>; 3930 #address-cells = <1>; 3931 #size-cells = <0>; 3932 status = "disabled"; 3933 }; 3934 3935 lmh_cluster1: lmh@17d70800 { 3936 compatible = "qcom,sdm845-lmh"; 3937 reg = <0 0x17d70800 0 0x400>; 3938 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3939 cpus = <&CPU4>; 3940 qcom,lmh-temp-arm-millicelsius = <65000>; 3941 qcom,lmh-temp-low-millicelsius = <94500>; 3942 qcom,lmh-temp-high-millicelsius = <95000>; 3943 interrupt-controller; 3944 #interrupt-cells = <1>; 3945 }; 3946 3947 lmh_cluster0: lmh@17d78800 { 3948 compatible = "qcom,sdm845-lmh"; 3949 reg = <0 0x17d78800 0 0x400>; 3950 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3951 cpus = <&CPU0>; 3952 qcom,lmh-temp-arm-millicelsius = <65000>; 3953 qcom,lmh-temp-low-millicelsius = <94500>; 3954 qcom,lmh-temp-high-millicelsius = <95000>; 3955 interrupt-controller; 3956 #interrupt-cells = <1>; 3957 }; 3958 3959 usb_1_hsphy: phy@88e2000 { 3960 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3961 reg = <0 0x088e2000 0 0x400>; 3962 status = "disabled"; 3963 #phy-cells = <0>; 3964 3965 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3966 <&rpmhcc RPMH_CXO_CLK>; 3967 clock-names = "cfg_ahb", "ref"; 3968 3969 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3970 3971 nvmem-cells = <&qusb2p_hstx_trim>; 3972 }; 3973 3974 usb_2_hsphy: phy@88e3000 { 3975 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3976 reg = <0 0x088e3000 0 0x400>; 3977 status = "disabled"; 3978 #phy-cells = <0>; 3979 3980 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3981 <&rpmhcc RPMH_CXO_CLK>; 3982 clock-names = "cfg_ahb", "ref"; 3983 3984 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3985 3986 nvmem-cells = <&qusb2s_hstx_trim>; 3987 }; 3988 3989 usb_1_qmpphy: phy@88e8000 { 3990 compatible = "qcom,sdm845-qmp-usb3-dp-phy"; 3991 reg = <0 0x088e8000 0 0x3000>; 3992 status = "disabled"; 3993 3994 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3995 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3996 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3997 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, 3998 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 3999 clock-names = "aux", 4000 "ref", 4001 "com_aux", 4002 "usb3_pipe", 4003 "cfg_ahb"; 4004 4005 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 4006 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 4007 reset-names = "phy", "common"; 4008 4009 #clock-cells = <1>; 4010 #phy-cells = <1>; 4011 }; 4012 4013 usb_2_qmpphy: phy@88eb000 { 4014 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 4015 reg = <0 0x088eb000 0 0x1000>; 4016 4017 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 4018 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 4019 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 4020 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 4021 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 4022 clock-names = "aux", 4023 "cfg_ahb", 4024 "ref", 4025 "com_aux", 4026 "pipe"; 4027 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 4028 #clock-cells = <0>; 4029 #phy-cells = <0>; 4030 4031 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 4032 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 4033 reset-names = "phy", 4034 "phy_phy"; 4035 4036 status = "disabled"; 4037 }; 4038 4039 usb_1: usb@a6f8800 { 4040 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 4041 reg = <0 0x0a6f8800 0 0x400>; 4042 status = "disabled"; 4043 #address-cells = <2>; 4044 #size-cells = <2>; 4045 ranges; 4046 dma-ranges; 4047 4048 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4049 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4050 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4051 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4052 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4053 clock-names = "cfg_noc", 4054 "core", 4055 "iface", 4056 "sleep", 4057 "mock_utmi"; 4058 4059 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4060 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4061 assigned-clock-rates = <19200000>, <150000000>; 4062 4063 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4064 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4065 <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>, 4066 <&pdc_intc 8 IRQ_TYPE_EDGE_BOTH>, 4067 <&pdc_intc 6 IRQ_TYPE_LEVEL_HIGH>; 4068 interrupt-names = "pwr_event", 4069 "hs_phy_irq", 4070 "dp_hs_phy_irq", 4071 "dm_hs_phy_irq", 4072 "ss_phy_irq"; 4073 4074 power-domains = <&gcc USB30_PRIM_GDSC>; 4075 4076 resets = <&gcc GCC_USB30_PRIM_BCR>; 4077 4078 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>, 4079 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4080 interconnect-names = "usb-ddr", "apps-usb"; 4081 4082 usb_1_dwc3: usb@a600000 { 4083 compatible = "snps,dwc3"; 4084 reg = <0 0x0a600000 0 0xcd00>; 4085 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4086 iommus = <&apps_smmu 0x740 0>; 4087 snps,dis_u2_susphy_quirk; 4088 snps,dis_enblslpm_quirk; 4089 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4090 phy-names = "usb2-phy", "usb3-phy"; 4091 }; 4092 }; 4093 4094 usb_2: usb@a8f8800 { 4095 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 4096 reg = <0 0x0a8f8800 0 0x400>; 4097 status = "disabled"; 4098 #address-cells = <2>; 4099 #size-cells = <2>; 4100 ranges; 4101 dma-ranges; 4102 4103 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4104 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4105 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4106 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4107 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 4108 clock-names = "cfg_noc", 4109 "core", 4110 "iface", 4111 "sleep", 4112 "mock_utmi"; 4113 4114 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4115 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4116 assigned-clock-rates = <19200000>, <150000000>; 4117 4118 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 4119 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 4120 <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>, 4121 <&pdc_intc 10 IRQ_TYPE_EDGE_BOTH>, 4122 <&pdc_intc 7 IRQ_TYPE_LEVEL_HIGH>; 4123 interrupt-names = "pwr_event", 4124 "hs_phy_irq", 4125 "dp_hs_phy_irq", 4126 "dm_hs_phy_irq", 4127 "ss_phy_irq"; 4128 4129 power-domains = <&gcc USB30_SEC_GDSC>; 4130 4131 resets = <&gcc GCC_USB30_SEC_BCR>; 4132 4133 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>, 4134 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 4135 interconnect-names = "usb-ddr", "apps-usb"; 4136 4137 usb_2_dwc3: usb@a800000 { 4138 compatible = "snps,dwc3"; 4139 reg = <0 0x0a800000 0 0xcd00>; 4140 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 4141 iommus = <&apps_smmu 0x760 0>; 4142 snps,dis_u2_susphy_quirk; 4143 snps,dis_enblslpm_quirk; 4144 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 4145 phy-names = "usb2-phy", "usb3-phy"; 4146 }; 4147 }; 4148 4149 venus: video-codec@aa00000 { 4150 compatible = "qcom,sdm845-venus-v2"; 4151 reg = <0 0x0aa00000 0 0xff000>; 4152 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4153 power-domains = <&videocc VENUS_GDSC>, 4154 <&videocc VCODEC0_GDSC>, 4155 <&videocc VCODEC1_GDSC>, 4156 <&rpmhpd SDM845_CX>; 4157 power-domain-names = "venus", "vcodec0", "vcodec1", "cx"; 4158 operating-points-v2 = <&venus_opp_table>; 4159 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 4160 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 4161 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 4162 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 4163 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>, 4164 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, 4165 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; 4166 clock-names = "core", "iface", "bus", 4167 "vcodec0_core", "vcodec0_bus", 4168 "vcodec1_core", "vcodec1_bus"; 4169 iommus = <&apps_smmu 0x10a0 0x8>, 4170 <&apps_smmu 0x10b0 0x0>; 4171 memory-region = <&venus_mem>; 4172 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>, 4173 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 4174 interconnect-names = "video-mem", "cpu-cfg"; 4175 4176 status = "disabled"; 4177 4178 video-core0 { 4179 compatible = "venus-decoder"; 4180 }; 4181 4182 video-core1 { 4183 compatible = "venus-encoder"; 4184 }; 4185 4186 venus_opp_table: opp-table { 4187 compatible = "operating-points-v2"; 4188 4189 opp-100000000 { 4190 opp-hz = /bits/ 64 <100000000>; 4191 required-opps = <&rpmhpd_opp_min_svs>; 4192 }; 4193 4194 opp-200000000 { 4195 opp-hz = /bits/ 64 <200000000>; 4196 required-opps = <&rpmhpd_opp_low_svs>; 4197 }; 4198 4199 opp-320000000 { 4200 opp-hz = /bits/ 64 <320000000>; 4201 required-opps = <&rpmhpd_opp_svs>; 4202 }; 4203 4204 opp-380000000 { 4205 opp-hz = /bits/ 64 <380000000>; 4206 required-opps = <&rpmhpd_opp_svs_l1>; 4207 }; 4208 4209 opp-444000000 { 4210 opp-hz = /bits/ 64 <444000000>; 4211 required-opps = <&rpmhpd_opp_nom>; 4212 }; 4213 4214 opp-533000097 { 4215 opp-hz = /bits/ 64 <533000097>; 4216 required-opps = <&rpmhpd_opp_turbo>; 4217 }; 4218 }; 4219 }; 4220 4221 videocc: clock-controller@ab00000 { 4222 compatible = "qcom,sdm845-videocc"; 4223 reg = <0 0x0ab00000 0 0x10000>; 4224 clocks = <&rpmhcc RPMH_CXO_CLK>; 4225 clock-names = "bi_tcxo"; 4226 #clock-cells = <1>; 4227 #power-domain-cells = <1>; 4228 #reset-cells = <1>; 4229 }; 4230 4231 camss: camss@acb3000 { 4232 compatible = "qcom,sdm845-camss"; 4233 4234 reg = <0 0x0acb3000 0 0x1000>, 4235 <0 0x0acba000 0 0x1000>, 4236 <0 0x0acc8000 0 0x1000>, 4237 <0 0x0ac65000 0 0x1000>, 4238 <0 0x0ac66000 0 0x1000>, 4239 <0 0x0ac67000 0 0x1000>, 4240 <0 0x0ac68000 0 0x1000>, 4241 <0 0x0acaf000 0 0x4000>, 4242 <0 0x0acb6000 0 0x4000>, 4243 <0 0x0acc4000 0 0x4000>; 4244 reg-names = "csid0", 4245 "csid1", 4246 "csid2", 4247 "csiphy0", 4248 "csiphy1", 4249 "csiphy2", 4250 "csiphy3", 4251 "vfe0", 4252 "vfe1", 4253 "vfe_lite"; 4254 4255 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 4256 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 4257 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 4258 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 4259 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 4260 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 4261 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 4262 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 4263 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 4264 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 4265 interrupt-names = "csid0", 4266 "csid1", 4267 "csid2", 4268 "csiphy0", 4269 "csiphy1", 4270 "csiphy2", 4271 "csiphy3", 4272 "vfe0", 4273 "vfe1", 4274 "vfe_lite"; 4275 4276 power-domains = <&clock_camcc IFE_0_GDSC>, 4277 <&clock_camcc IFE_1_GDSC>, 4278 <&clock_camcc TITAN_TOP_GDSC>; 4279 4280 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4281 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 4282 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, 4283 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, 4284 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, 4285 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, 4286 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, 4287 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, 4288 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, 4289 <&clock_camcc CAM_CC_CSIPHY0_CLK>, 4290 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, 4291 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, 4292 <&clock_camcc CAM_CC_CSIPHY1_CLK>, 4293 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, 4294 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, 4295 <&clock_camcc CAM_CC_CSIPHY2_CLK>, 4296 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, 4297 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, 4298 <&clock_camcc CAM_CC_CSIPHY3_CLK>, 4299 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, 4300 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, 4301 <&gcc GCC_CAMERA_AHB_CLK>, 4302 <&gcc GCC_CAMERA_AXI_CLK>, 4303 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4304 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4305 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, 4306 <&clock_camcc CAM_CC_IFE_0_CLK>, 4307 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4308 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, 4309 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, 4310 <&clock_camcc CAM_CC_IFE_1_CLK>, 4311 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4312 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, 4313 <&clock_camcc CAM_CC_IFE_LITE_CLK>, 4314 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4315 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>; 4316 clock-names = "camnoc_axi", 4317 "cpas_ahb", 4318 "cphy_rx_src", 4319 "csi0", 4320 "csi0_src", 4321 "csi1", 4322 "csi1_src", 4323 "csi2", 4324 "csi2_src", 4325 "csiphy0", 4326 "csiphy0_timer", 4327 "csiphy0_timer_src", 4328 "csiphy1", 4329 "csiphy1_timer", 4330 "csiphy1_timer_src", 4331 "csiphy2", 4332 "csiphy2_timer", 4333 "csiphy2_timer_src", 4334 "csiphy3", 4335 "csiphy3_timer", 4336 "csiphy3_timer_src", 4337 "gcc_camera_ahb", 4338 "gcc_camera_axi", 4339 "slow_ahb_src", 4340 "soc_ahb", 4341 "vfe0_axi", 4342 "vfe0", 4343 "vfe0_cphy_rx", 4344 "vfe0_src", 4345 "vfe1_axi", 4346 "vfe1", 4347 "vfe1_cphy_rx", 4348 "vfe1_src", 4349 "vfe_lite", 4350 "vfe_lite_cphy_rx", 4351 "vfe_lite_src"; 4352 4353 iommus = <&apps_smmu 0x0808 0x0>, 4354 <&apps_smmu 0x0810 0x8>, 4355 <&apps_smmu 0x0c08 0x0>, 4356 <&apps_smmu 0x0c10 0x8>; 4357 4358 status = "disabled"; 4359 4360 ports { 4361 #address-cells = <1>; 4362 #size-cells = <0>; 4363 4364 port@0 { 4365 reg = <0>; 4366 }; 4367 4368 port@1 { 4369 reg = <1>; 4370 }; 4371 4372 port@2 { 4373 reg = <2>; 4374 }; 4375 4376 port@3 { 4377 reg = <3>; 4378 }; 4379 }; 4380 }; 4381 4382 cci: cci@ac4a000 { 4383 compatible = "qcom,sdm845-cci", "qcom,msm8996-cci"; 4384 #address-cells = <1>; 4385 #size-cells = <0>; 4386 4387 reg = <0 0x0ac4a000 0 0x4000>; 4388 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4389 power-domains = <&clock_camcc TITAN_TOP_GDSC>; 4390 4391 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4392 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4393 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4394 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 4395 <&clock_camcc CAM_CC_CCI_CLK>, 4396 <&clock_camcc CAM_CC_CCI_CLK_SRC>; 4397 clock-names = "camnoc_axi", 4398 "soc_ahb", 4399 "slow_ahb_src", 4400 "cpas_ahb", 4401 "cci", 4402 "cci_src"; 4403 4404 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4405 <&clock_camcc CAM_CC_CCI_CLK>; 4406 assigned-clock-rates = <80000000>, <37500000>; 4407 4408 pinctrl-names = "default", "sleep"; 4409 pinctrl-0 = <&cci0_default &cci1_default>; 4410 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 4411 4412 status = "disabled"; 4413 4414 cci_i2c0: i2c-bus@0 { 4415 reg = <0>; 4416 clock-frequency = <1000000>; 4417 #address-cells = <1>; 4418 #size-cells = <0>; 4419 }; 4420 4421 cci_i2c1: i2c-bus@1 { 4422 reg = <1>; 4423 clock-frequency = <1000000>; 4424 #address-cells = <1>; 4425 #size-cells = <0>; 4426 }; 4427 }; 4428 4429 clock_camcc: clock-controller@ad00000 { 4430 compatible = "qcom,sdm845-camcc"; 4431 reg = <0 0x0ad00000 0 0x10000>; 4432 #clock-cells = <1>; 4433 #reset-cells = <1>; 4434 #power-domain-cells = <1>; 4435 clocks = <&rpmhcc RPMH_CXO_CLK>; 4436 clock-names = "bi_tcxo"; 4437 }; 4438 4439 mdss: display-subsystem@ae00000 { 4440 compatible = "qcom,sdm845-mdss"; 4441 reg = <0 0x0ae00000 0 0x1000>; 4442 reg-names = "mdss"; 4443 4444 power-domains = <&dispcc MDSS_GDSC>; 4445 4446 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4447 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4448 clock-names = "iface", "core"; 4449 4450 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4451 interrupt-controller; 4452 #interrupt-cells = <1>; 4453 4454 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>, 4455 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>; 4456 interconnect-names = "mdp0-mem", "mdp1-mem"; 4457 4458 iommus = <&apps_smmu 0x880 0x8>, 4459 <&apps_smmu 0xc80 0x8>; 4460 4461 status = "disabled"; 4462 4463 #address-cells = <2>; 4464 #size-cells = <2>; 4465 ranges; 4466 4467 mdss_mdp: display-controller@ae01000 { 4468 compatible = "qcom,sdm845-dpu"; 4469 reg = <0 0x0ae01000 0 0x8f000>, 4470 <0 0x0aeb0000 0 0x2008>; 4471 reg-names = "mdp", "vbif"; 4472 4473 clocks = <&gcc GCC_DISP_AXI_CLK>, 4474 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4475 <&dispcc DISP_CC_MDSS_AXI_CLK>, 4476 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4477 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4478 clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; 4479 4480 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4481 assigned-clock-rates = <19200000>; 4482 operating-points-v2 = <&mdp_opp_table>; 4483 power-domains = <&rpmhpd SDM845_CX>; 4484 4485 interrupt-parent = <&mdss>; 4486 interrupts = <0>; 4487 4488 ports { 4489 #address-cells = <1>; 4490 #size-cells = <0>; 4491 4492 port@0 { 4493 reg = <0>; 4494 dpu_intf0_out: endpoint { 4495 remote-endpoint = <&dp_in>; 4496 }; 4497 }; 4498 4499 port@1 { 4500 reg = <1>; 4501 dpu_intf1_out: endpoint { 4502 remote-endpoint = <&mdss_dsi0_in>; 4503 }; 4504 }; 4505 4506 port@2 { 4507 reg = <2>; 4508 dpu_intf2_out: endpoint { 4509 remote-endpoint = <&mdss_dsi1_in>; 4510 }; 4511 }; 4512 }; 4513 4514 mdp_opp_table: opp-table { 4515 compatible = "operating-points-v2"; 4516 4517 opp-19200000 { 4518 opp-hz = /bits/ 64 <19200000>; 4519 required-opps = <&rpmhpd_opp_min_svs>; 4520 }; 4521 4522 opp-171428571 { 4523 opp-hz = /bits/ 64 <171428571>; 4524 required-opps = <&rpmhpd_opp_low_svs>; 4525 }; 4526 4527 opp-344000000 { 4528 opp-hz = /bits/ 64 <344000000>; 4529 required-opps = <&rpmhpd_opp_svs_l1>; 4530 }; 4531 4532 opp-430000000 { 4533 opp-hz = /bits/ 64 <430000000>; 4534 required-opps = <&rpmhpd_opp_nom>; 4535 }; 4536 }; 4537 }; 4538 4539 mdss_dp: displayport-controller@ae90000 { 4540 status = "disabled"; 4541 compatible = "qcom,sdm845-dp"; 4542 4543 reg = <0 0x0ae90000 0 0x200>, 4544 <0 0x0ae90200 0 0x200>, 4545 <0 0x0ae90400 0 0x600>, 4546 <0 0x0ae90a00 0 0x600>, 4547 <0 0x0ae91000 0 0x600>; 4548 4549 interrupt-parent = <&mdss>; 4550 interrupts = <12>; 4551 4552 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4553 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4554 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4555 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4556 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4557 clock-names = "core_iface", "core_aux", "ctrl_link", 4558 "ctrl_link_iface", "stream_pixel"; 4559 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4560 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4561 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4562 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4563 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4564 phy-names = "dp"; 4565 4566 operating-points-v2 = <&dp_opp_table>; 4567 power-domains = <&rpmhpd SDM845_CX>; 4568 4569 ports { 4570 #address-cells = <1>; 4571 #size-cells = <0>; 4572 port@0 { 4573 reg = <0>; 4574 dp_in: endpoint { 4575 remote-endpoint = <&dpu_intf0_out>; 4576 }; 4577 }; 4578 4579 port@1 { 4580 reg = <1>; 4581 dp_out: endpoint { }; 4582 }; 4583 }; 4584 4585 dp_opp_table: opp-table { 4586 compatible = "operating-points-v2"; 4587 4588 opp-162000000 { 4589 opp-hz = /bits/ 64 <162000000>; 4590 required-opps = <&rpmhpd_opp_low_svs>; 4591 }; 4592 4593 opp-270000000 { 4594 opp-hz = /bits/ 64 <270000000>; 4595 required-opps = <&rpmhpd_opp_svs>; 4596 }; 4597 4598 opp-540000000 { 4599 opp-hz = /bits/ 64 <540000000>; 4600 required-opps = <&rpmhpd_opp_svs_l1>; 4601 }; 4602 4603 opp-810000000 { 4604 opp-hz = /bits/ 64 <810000000>; 4605 required-opps = <&rpmhpd_opp_nom>; 4606 }; 4607 }; 4608 }; 4609 4610 mdss_dsi0: dsi@ae94000 { 4611 compatible = "qcom,sdm845-dsi-ctrl", 4612 "qcom,mdss-dsi-ctrl"; 4613 reg = <0 0x0ae94000 0 0x400>; 4614 reg-names = "dsi_ctrl"; 4615 4616 interrupt-parent = <&mdss>; 4617 interrupts = <4>; 4618 4619 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4620 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4621 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4622 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4623 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4624 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4625 clock-names = "byte", 4626 "byte_intf", 4627 "pixel", 4628 "core", 4629 "iface", 4630 "bus"; 4631 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4632 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 4633 4634 operating-points-v2 = <&dsi_opp_table>; 4635 power-domains = <&rpmhpd SDM845_CX>; 4636 4637 phys = <&mdss_dsi0_phy>; 4638 4639 status = "disabled"; 4640 4641 #address-cells = <1>; 4642 #size-cells = <0>; 4643 4644 ports { 4645 #address-cells = <1>; 4646 #size-cells = <0>; 4647 4648 port@0 { 4649 reg = <0>; 4650 mdss_dsi0_in: endpoint { 4651 remote-endpoint = <&dpu_intf1_out>; 4652 }; 4653 }; 4654 4655 port@1 { 4656 reg = <1>; 4657 mdss_dsi0_out: endpoint { 4658 }; 4659 }; 4660 }; 4661 }; 4662 4663 mdss_dsi0_phy: phy@ae94400 { 4664 compatible = "qcom,dsi-phy-10nm"; 4665 reg = <0 0x0ae94400 0 0x200>, 4666 <0 0x0ae94600 0 0x280>, 4667 <0 0x0ae94a00 0 0x1e0>; 4668 reg-names = "dsi_phy", 4669 "dsi_phy_lane", 4670 "dsi_pll"; 4671 4672 #clock-cells = <1>; 4673 #phy-cells = <0>; 4674 4675 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4676 <&rpmhcc RPMH_CXO_CLK>; 4677 clock-names = "iface", "ref"; 4678 4679 status = "disabled"; 4680 }; 4681 4682 mdss_dsi1: dsi@ae96000 { 4683 compatible = "qcom,sdm845-dsi-ctrl", 4684 "qcom,mdss-dsi-ctrl"; 4685 reg = <0 0x0ae96000 0 0x400>; 4686 reg-names = "dsi_ctrl"; 4687 4688 interrupt-parent = <&mdss>; 4689 interrupts = <5>; 4690 4691 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4692 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4693 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4694 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4695 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4696 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4697 clock-names = "byte", 4698 "byte_intf", 4699 "pixel", 4700 "core", 4701 "iface", 4702 "bus"; 4703 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4704 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 4705 4706 operating-points-v2 = <&dsi_opp_table>; 4707 power-domains = <&rpmhpd SDM845_CX>; 4708 4709 phys = <&mdss_dsi1_phy>; 4710 4711 status = "disabled"; 4712 4713 #address-cells = <1>; 4714 #size-cells = <0>; 4715 4716 ports { 4717 #address-cells = <1>; 4718 #size-cells = <0>; 4719 4720 port@0 { 4721 reg = <0>; 4722 mdss_dsi1_in: endpoint { 4723 remote-endpoint = <&dpu_intf2_out>; 4724 }; 4725 }; 4726 4727 port@1 { 4728 reg = <1>; 4729 mdss_dsi1_out: endpoint { 4730 }; 4731 }; 4732 }; 4733 }; 4734 4735 mdss_dsi1_phy: phy@ae96400 { 4736 compatible = "qcom,dsi-phy-10nm"; 4737 reg = <0 0x0ae96400 0 0x200>, 4738 <0 0x0ae96600 0 0x280>, 4739 <0 0x0ae96a00 0 0x10e>; 4740 reg-names = "dsi_phy", 4741 "dsi_phy_lane", 4742 "dsi_pll"; 4743 4744 #clock-cells = <1>; 4745 #phy-cells = <0>; 4746 4747 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4748 <&rpmhcc RPMH_CXO_CLK>; 4749 clock-names = "iface", "ref"; 4750 4751 status = "disabled"; 4752 }; 4753 }; 4754 4755 gpu: gpu@5000000 { 4756 compatible = "qcom,adreno-630.2", "qcom,adreno"; 4757 4758 reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>; 4759 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 4760 4761 /* 4762 * Look ma, no clocks! The GPU clocks and power are 4763 * controlled entirely by the GMU 4764 */ 4765 4766 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4767 4768 iommus = <&adreno_smmu 0>; 4769 4770 operating-points-v2 = <&gpu_opp_table>; 4771 4772 qcom,gmu = <&gmu>; 4773 #cooling-cells = <2>; 4774 4775 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; 4776 interconnect-names = "gfx-mem"; 4777 4778 status = "disabled"; 4779 4780 gpu_opp_table: opp-table { 4781 compatible = "operating-points-v2"; 4782 4783 opp-710000000 { 4784 opp-hz = /bits/ 64 <710000000>; 4785 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4786 opp-peak-kBps = <7216000>; 4787 }; 4788 4789 opp-675000000 { 4790 opp-hz = /bits/ 64 <675000000>; 4791 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4792 opp-peak-kBps = <7216000>; 4793 }; 4794 4795 opp-596000000 { 4796 opp-hz = /bits/ 64 <596000000>; 4797 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4798 opp-peak-kBps = <6220000>; 4799 }; 4800 4801 opp-520000000 { 4802 opp-hz = /bits/ 64 <520000000>; 4803 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4804 opp-peak-kBps = <6220000>; 4805 }; 4806 4807 opp-414000000 { 4808 opp-hz = /bits/ 64 <414000000>; 4809 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4810 opp-peak-kBps = <4068000>; 4811 }; 4812 4813 opp-342000000 { 4814 opp-hz = /bits/ 64 <342000000>; 4815 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4816 opp-peak-kBps = <2724000>; 4817 }; 4818 4819 opp-257000000 { 4820 opp-hz = /bits/ 64 <257000000>; 4821 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4822 opp-peak-kBps = <1648000>; 4823 }; 4824 }; 4825 }; 4826 4827 adreno_smmu: iommu@5040000 { 4828 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 4829 reg = <0 0x05040000 0 0x10000>; 4830 #iommu-cells = <1>; 4831 #global-interrupts = <2>; 4832 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 4833 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 4834 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 4835 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 4836 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 4837 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 4838 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 4839 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 4840 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 4841 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 4842 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4843 <&gcc GCC_GPU_CFG_AHB_CLK>; 4844 clock-names = "bus", "iface"; 4845 4846 power-domains = <&gpucc GPU_CX_GDSC>; 4847 }; 4848 4849 gmu: gmu@506a000 { 4850 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 4851 4852 reg = <0 0x0506a000 0 0x30000>, 4853 <0 0x0b280000 0 0x10000>, 4854 <0 0x0b480000 0 0x10000>; 4855 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 4856 4857 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4858 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4859 interrupt-names = "hfi", "gmu"; 4860 4861 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 4862 <&gpucc GPU_CC_CXO_CLK>, 4863 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4864 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 4865 clock-names = "gmu", "cxo", "axi", "memnoc"; 4866 4867 power-domains = <&gpucc GPU_CX_GDSC>, 4868 <&gpucc GPU_GX_GDSC>; 4869 power-domain-names = "cx", "gx"; 4870 4871 iommus = <&adreno_smmu 5>; 4872 4873 operating-points-v2 = <&gmu_opp_table>; 4874 4875 status = "disabled"; 4876 4877 gmu_opp_table: opp-table { 4878 compatible = "operating-points-v2"; 4879 4880 opp-400000000 { 4881 opp-hz = /bits/ 64 <400000000>; 4882 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4883 }; 4884 4885 opp-200000000 { 4886 opp-hz = /bits/ 64 <200000000>; 4887 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4888 }; 4889 }; 4890 }; 4891 4892 dispcc: clock-controller@af00000 { 4893 compatible = "qcom,sdm845-dispcc"; 4894 reg = <0 0x0af00000 0 0x10000>; 4895 clocks = <&rpmhcc RPMH_CXO_CLK>, 4896 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 4897 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 4898 <&mdss_dsi0_phy 0>, 4899 <&mdss_dsi0_phy 1>, 4900 <&mdss_dsi1_phy 0>, 4901 <&mdss_dsi1_phy 1>, 4902 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4903 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4904 clock-names = "bi_tcxo", 4905 "gcc_disp_gpll0_clk_src", 4906 "gcc_disp_gpll0_div_clk_src", 4907 "dsi0_phy_pll_out_byteclk", 4908 "dsi0_phy_pll_out_dsiclk", 4909 "dsi1_phy_pll_out_byteclk", 4910 "dsi1_phy_pll_out_dsiclk", 4911 "dp_link_clk_divsel_ten", 4912 "dp_vco_divided_clk_src_mux"; 4913 #clock-cells = <1>; 4914 #reset-cells = <1>; 4915 #power-domain-cells = <1>; 4916 }; 4917 4918 pdc_intc: interrupt-controller@b220000 { 4919 compatible = "qcom,sdm845-pdc", "qcom,pdc"; 4920 reg = <0 0x0b220000 0 0x30000>; 4921 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; 4922 #interrupt-cells = <2>; 4923 interrupt-parent = <&intc>; 4924 interrupt-controller; 4925 }; 4926 4927 pdc_reset: reset-controller@b2e0000 { 4928 compatible = "qcom,sdm845-pdc-global"; 4929 reg = <0 0x0b2e0000 0 0x20000>; 4930 #reset-cells = <1>; 4931 }; 4932 4933 tsens0: thermal-sensor@c263000 { 4934 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4935 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4936 <0 0x0c222000 0 0x1ff>; /* SROT */ 4937 #qcom,sensors = <13>; 4938 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4939 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4940 interrupt-names = "uplow", "critical"; 4941 #thermal-sensor-cells = <1>; 4942 }; 4943 4944 tsens1: thermal-sensor@c265000 { 4945 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4946 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4947 <0 0x0c223000 0 0x1ff>; /* SROT */ 4948 #qcom,sensors = <8>; 4949 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4950 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4951 interrupt-names = "uplow", "critical"; 4952 #thermal-sensor-cells = <1>; 4953 }; 4954 4955 aoss_reset: reset-controller@c2a0000 { 4956 compatible = "qcom,sdm845-aoss-cc"; 4957 reg = <0 0x0c2a0000 0 0x31000>; 4958 #reset-cells = <1>; 4959 }; 4960 4961 aoss_qmp: power-management@c300000 { 4962 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; 4963 reg = <0 0x0c300000 0 0x400>; 4964 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 4965 mboxes = <&apss_shared 0>; 4966 4967 #clock-cells = <0>; 4968 4969 cx_cdev: cx { 4970 #cooling-cells = <2>; 4971 }; 4972 4973 ebi_cdev: ebi { 4974 #cooling-cells = <2>; 4975 }; 4976 }; 4977 4978 sram@c3f0000 { 4979 compatible = "qcom,sdm845-rpmh-stats"; 4980 reg = <0 0x0c3f0000 0 0x400>; 4981 }; 4982 4983 spmi_bus: spmi@c440000 { 4984 compatible = "qcom,spmi-pmic-arb"; 4985 reg = <0 0x0c440000 0 0x1100>, 4986 <0 0x0c600000 0 0x2000000>, 4987 <0 0x0e600000 0 0x100000>, 4988 <0 0x0e700000 0 0xa0000>, 4989 <0 0x0c40a000 0 0x26000>; 4990 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4991 interrupt-names = "periph_irq"; 4992 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 4993 qcom,ee = <0>; 4994 qcom,channel = <0>; 4995 #address-cells = <2>; 4996 #size-cells = <0>; 4997 interrupt-controller; 4998 #interrupt-cells = <4>; 4999 }; 5000 5001 sram@146bf000 { 5002 compatible = "qcom,sdm845-imem", "syscon", "simple-mfd"; 5003 reg = <0 0x146bf000 0 0x1000>; 5004 5005 #address-cells = <1>; 5006 #size-cells = <1>; 5007 5008 ranges = <0 0 0x146bf000 0x1000>; 5009 5010 pil-reloc@94c { 5011 compatible = "qcom,pil-reloc-info"; 5012 reg = <0x94c 0xc8>; 5013 }; 5014 }; 5015 5016 apps_smmu: iommu@15000000 { 5017 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; 5018 reg = <0 0x15000000 0 0x80000>; 5019 #iommu-cells = <2>; 5020 #global-interrupts = <1>; 5021 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5022 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5023 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5024 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5025 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5026 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5027 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5028 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5029 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5030 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5031 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5032 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5033 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5034 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5035 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5036 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5037 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5038 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5039 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5040 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5041 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5042 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5043 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5044 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5045 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5046 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5047 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5048 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5049 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5050 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5051 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5052 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5053 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5054 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5055 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5056 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5057 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5058 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5059 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5060 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5061 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5062 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5063 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5064 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5065 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5066 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5067 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5068 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5069 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5070 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5071 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5072 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5073 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5074 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5075 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5076 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5077 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5078 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5079 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5080 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5081 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5082 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5083 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5084 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5085 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 5086 }; 5087 5088 lpasscc: clock-controller@17014000 { 5089 compatible = "qcom,sdm845-lpasscc"; 5090 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; 5091 reg-names = "cc", "qdsp6ss"; 5092 #clock-cells = <1>; 5093 status = "disabled"; 5094 }; 5095 5096 gladiator_noc: interconnect@17900000 { 5097 compatible = "qcom,sdm845-gladiator-noc"; 5098 reg = <0 0x17900000 0 0xd080>; 5099 #interconnect-cells = <2>; 5100 qcom,bcm-voters = <&apps_bcm_voter>; 5101 }; 5102 5103 watchdog@17980000 { 5104 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; 5105 reg = <0 0x17980000 0 0x1000>; 5106 clocks = <&sleep_clk>; 5107 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5108 }; 5109 5110 apss_shared: mailbox@17990000 { 5111 compatible = "qcom,sdm845-apss-shared"; 5112 reg = <0 0x17990000 0 0x1000>; 5113 #mbox-cells = <1>; 5114 }; 5115 5116 apps_rsc: rsc@179c0000 { 5117 label = "apps_rsc"; 5118 compatible = "qcom,rpmh-rsc"; 5119 reg = <0 0x179c0000 0 0x10000>, 5120 <0 0x179d0000 0 0x10000>, 5121 <0 0x179e0000 0 0x10000>; 5122 reg-names = "drv-0", "drv-1", "drv-2"; 5123 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5126 qcom,tcs-offset = <0xd00>; 5127 qcom,drv-id = <2>; 5128 qcom,tcs-config = <ACTIVE_TCS 2>, 5129 <SLEEP_TCS 3>, 5130 <WAKE_TCS 3>, 5131 <CONTROL_TCS 1>; 5132 power-domains = <&CLUSTER_PD>; 5133 5134 apps_bcm_voter: bcm-voter { 5135 compatible = "qcom,bcm-voter"; 5136 }; 5137 5138 rpmhcc: clock-controller { 5139 compatible = "qcom,sdm845-rpmh-clk"; 5140 #clock-cells = <1>; 5141 clock-names = "xo"; 5142 clocks = <&xo_board>; 5143 }; 5144 5145 rpmhpd: power-controller { 5146 compatible = "qcom,sdm845-rpmhpd"; 5147 #power-domain-cells = <1>; 5148 operating-points-v2 = <&rpmhpd_opp_table>; 5149 5150 rpmhpd_opp_table: opp-table { 5151 compatible = "operating-points-v2"; 5152 5153 rpmhpd_opp_ret: opp1 { 5154 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5155 }; 5156 5157 rpmhpd_opp_min_svs: opp2 { 5158 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5159 }; 5160 5161 rpmhpd_opp_low_svs: opp3 { 5162 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5163 }; 5164 5165 rpmhpd_opp_svs: opp4 { 5166 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5167 }; 5168 5169 rpmhpd_opp_svs_l1: opp5 { 5170 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5171 }; 5172 5173 rpmhpd_opp_nom: opp6 { 5174 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5175 }; 5176 5177 rpmhpd_opp_nom_l1: opp7 { 5178 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5179 }; 5180 5181 rpmhpd_opp_nom_l2: opp8 { 5182 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5183 }; 5184 5185 rpmhpd_opp_turbo: opp9 { 5186 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5187 }; 5188 5189 rpmhpd_opp_turbo_l1: opp10 { 5190 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5191 }; 5192 }; 5193 }; 5194 }; 5195 5196 intc: interrupt-controller@17a00000 { 5197 compatible = "arm,gic-v3"; 5198 #address-cells = <2>; 5199 #size-cells = <2>; 5200 ranges; 5201 #interrupt-cells = <3>; 5202 interrupt-controller; 5203 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5204 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5205 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5206 5207 msi-controller@17a40000 { 5208 compatible = "arm,gic-v3-its"; 5209 msi-controller; 5210 #msi-cells = <1>; 5211 reg = <0 0x17a40000 0 0x20000>; 5212 status = "disabled"; 5213 }; 5214 }; 5215 5216 slimbam: dma-controller@17184000 { 5217 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 5218 qcom,controlled-remotely; 5219 reg = <0 0x17184000 0 0x2a000>; 5220 num-channels = <31>; 5221 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 5222 #dma-cells = <1>; 5223 qcom,ee = <1>; 5224 qcom,num-ees = <2>; 5225 iommus = <&apps_smmu 0x1806 0x0>; 5226 }; 5227 5228 timer@17c90000 { 5229 #address-cells = <1>; 5230 #size-cells = <1>; 5231 ranges = <0 0 0 0x20000000>; 5232 compatible = "arm,armv7-timer-mem"; 5233 reg = <0 0x17c90000 0 0x1000>; 5234 5235 frame@17ca0000 { 5236 frame-number = <0>; 5237 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 5238 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5239 reg = <0x17ca0000 0x1000>, 5240 <0x17cb0000 0x1000>; 5241 }; 5242 5243 frame@17cc0000 { 5244 frame-number = <1>; 5245 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 5246 reg = <0x17cc0000 0x1000>; 5247 status = "disabled"; 5248 }; 5249 5250 frame@17cd0000 { 5251 frame-number = <2>; 5252 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5253 reg = <0x17cd0000 0x1000>; 5254 status = "disabled"; 5255 }; 5256 5257 frame@17ce0000 { 5258 frame-number = <3>; 5259 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5260 reg = <0x17ce0000 0x1000>; 5261 status = "disabled"; 5262 }; 5263 5264 frame@17cf0000 { 5265 frame-number = <4>; 5266 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5267 reg = <0x17cf0000 0x1000>; 5268 status = "disabled"; 5269 }; 5270 5271 frame@17d00000 { 5272 frame-number = <5>; 5273 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5274 reg = <0x17d00000 0x1000>; 5275 status = "disabled"; 5276 }; 5277 5278 frame@17d10000 { 5279 frame-number = <6>; 5280 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5281 reg = <0x17d10000 0x1000>; 5282 status = "disabled"; 5283 }; 5284 }; 5285 5286 osm_l3: interconnect@17d41000 { 5287 compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3"; 5288 reg = <0 0x17d41000 0 0x1400>; 5289 5290 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5291 clock-names = "xo", "alternate"; 5292 5293 #interconnect-cells = <1>; 5294 }; 5295 5296 cpufreq_hw: cpufreq@17d43000 { 5297 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw"; 5298 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 5299 reg-names = "freq-domain0", "freq-domain1"; 5300 5301 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>; 5302 5303 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5304 clock-names = "xo", "alternate"; 5305 5306 #freq-domain-cells = <1>; 5307 #clock-cells = <1>; 5308 }; 5309 5310 wifi: wifi@18800000 { 5311 compatible = "qcom,wcn3990-wifi"; 5312 status = "disabled"; 5313 reg = <0 0x18800000 0 0x800000>; 5314 reg-names = "membase"; 5315 memory-region = <&wlan_msa_mem>; 5316 clock-names = "cxo_ref_clk_pin"; 5317 clocks = <&rpmhcc RPMH_RF_CLK2>; 5318 interrupts = 5319 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 5320 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 5321 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 5322 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 5323 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5324 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5325 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 5326 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5327 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 5328 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5329 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5330 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 5331 iommus = <&apps_smmu 0x0040 0x1>; 5332 }; 5333 }; 5334 5335 sound: sound { 5336 }; 5337 5338 thermal-zones { 5339 cpu0-thermal { 5340 polling-delay-passive = <250>; 5341 polling-delay = <1000>; 5342 5343 thermal-sensors = <&tsens0 1>; 5344 5345 trips { 5346 cpu0_alert0: trip-point0 { 5347 temperature = <90000>; 5348 hysteresis = <2000>; 5349 type = "passive"; 5350 }; 5351 5352 cpu0_alert1: trip-point1 { 5353 temperature = <95000>; 5354 hysteresis = <2000>; 5355 type = "passive"; 5356 }; 5357 5358 cpu0_crit: cpu-crit { 5359 temperature = <110000>; 5360 hysteresis = <1000>; 5361 type = "critical"; 5362 }; 5363 }; 5364 }; 5365 5366 cpu1-thermal { 5367 polling-delay-passive = <250>; 5368 polling-delay = <1000>; 5369 5370 thermal-sensors = <&tsens0 2>; 5371 5372 trips { 5373 cpu1_alert0: trip-point0 { 5374 temperature = <90000>; 5375 hysteresis = <2000>; 5376 type = "passive"; 5377 }; 5378 5379 cpu1_alert1: trip-point1 { 5380 temperature = <95000>; 5381 hysteresis = <2000>; 5382 type = "passive"; 5383 }; 5384 5385 cpu1_crit: cpu-crit { 5386 temperature = <110000>; 5387 hysteresis = <1000>; 5388 type = "critical"; 5389 }; 5390 }; 5391 }; 5392 5393 cpu2-thermal { 5394 polling-delay-passive = <250>; 5395 polling-delay = <1000>; 5396 5397 thermal-sensors = <&tsens0 3>; 5398 5399 trips { 5400 cpu2_alert0: trip-point0 { 5401 temperature = <90000>; 5402 hysteresis = <2000>; 5403 type = "passive"; 5404 }; 5405 5406 cpu2_alert1: trip-point1 { 5407 temperature = <95000>; 5408 hysteresis = <2000>; 5409 type = "passive"; 5410 }; 5411 5412 cpu2_crit: cpu-crit { 5413 temperature = <110000>; 5414 hysteresis = <1000>; 5415 type = "critical"; 5416 }; 5417 }; 5418 }; 5419 5420 cpu3-thermal { 5421 polling-delay-passive = <250>; 5422 polling-delay = <1000>; 5423 5424 thermal-sensors = <&tsens0 4>; 5425 5426 trips { 5427 cpu3_alert0: trip-point0 { 5428 temperature = <90000>; 5429 hysteresis = <2000>; 5430 type = "passive"; 5431 }; 5432 5433 cpu3_alert1: trip-point1 { 5434 temperature = <95000>; 5435 hysteresis = <2000>; 5436 type = "passive"; 5437 }; 5438 5439 cpu3_crit: cpu-crit { 5440 temperature = <110000>; 5441 hysteresis = <1000>; 5442 type = "critical"; 5443 }; 5444 }; 5445 }; 5446 5447 cpu4-thermal { 5448 polling-delay-passive = <250>; 5449 polling-delay = <1000>; 5450 5451 thermal-sensors = <&tsens0 7>; 5452 5453 trips { 5454 cpu4_alert0: trip-point0 { 5455 temperature = <90000>; 5456 hysteresis = <2000>; 5457 type = "passive"; 5458 }; 5459 5460 cpu4_alert1: trip-point1 { 5461 temperature = <95000>; 5462 hysteresis = <2000>; 5463 type = "passive"; 5464 }; 5465 5466 cpu4_crit: cpu-crit { 5467 temperature = <110000>; 5468 hysteresis = <1000>; 5469 type = "critical"; 5470 }; 5471 }; 5472 }; 5473 5474 cpu5-thermal { 5475 polling-delay-passive = <250>; 5476 polling-delay = <1000>; 5477 5478 thermal-sensors = <&tsens0 8>; 5479 5480 trips { 5481 cpu5_alert0: trip-point0 { 5482 temperature = <90000>; 5483 hysteresis = <2000>; 5484 type = "passive"; 5485 }; 5486 5487 cpu5_alert1: trip-point1 { 5488 temperature = <95000>; 5489 hysteresis = <2000>; 5490 type = "passive"; 5491 }; 5492 5493 cpu5_crit: cpu-crit { 5494 temperature = <110000>; 5495 hysteresis = <1000>; 5496 type = "critical"; 5497 }; 5498 }; 5499 }; 5500 5501 cpu6-thermal { 5502 polling-delay-passive = <250>; 5503 polling-delay = <1000>; 5504 5505 thermal-sensors = <&tsens0 9>; 5506 5507 trips { 5508 cpu6_alert0: trip-point0 { 5509 temperature = <90000>; 5510 hysteresis = <2000>; 5511 type = "passive"; 5512 }; 5513 5514 cpu6_alert1: trip-point1 { 5515 temperature = <95000>; 5516 hysteresis = <2000>; 5517 type = "passive"; 5518 }; 5519 5520 cpu6_crit: cpu-crit { 5521 temperature = <110000>; 5522 hysteresis = <1000>; 5523 type = "critical"; 5524 }; 5525 }; 5526 }; 5527 5528 cpu7-thermal { 5529 polling-delay-passive = <250>; 5530 polling-delay = <1000>; 5531 5532 thermal-sensors = <&tsens0 10>; 5533 5534 trips { 5535 cpu7_alert0: trip-point0 { 5536 temperature = <90000>; 5537 hysteresis = <2000>; 5538 type = "passive"; 5539 }; 5540 5541 cpu7_alert1: trip-point1 { 5542 temperature = <95000>; 5543 hysteresis = <2000>; 5544 type = "passive"; 5545 }; 5546 5547 cpu7_crit: cpu-crit { 5548 temperature = <110000>; 5549 hysteresis = <1000>; 5550 type = "critical"; 5551 }; 5552 }; 5553 }; 5554 5555 aoss0-thermal { 5556 polling-delay-passive = <250>; 5557 polling-delay = <1000>; 5558 5559 thermal-sensors = <&tsens0 0>; 5560 5561 trips { 5562 aoss0_alert0: trip-point0 { 5563 temperature = <90000>; 5564 hysteresis = <2000>; 5565 type = "hot"; 5566 }; 5567 }; 5568 }; 5569 5570 cluster0-thermal { 5571 polling-delay-passive = <250>; 5572 polling-delay = <1000>; 5573 5574 thermal-sensors = <&tsens0 5>; 5575 5576 trips { 5577 cluster0_alert0: trip-point0 { 5578 temperature = <90000>; 5579 hysteresis = <2000>; 5580 type = "hot"; 5581 }; 5582 cluster0_crit: cluster0-crit { 5583 temperature = <110000>; 5584 hysteresis = <2000>; 5585 type = "critical"; 5586 }; 5587 }; 5588 }; 5589 5590 cluster1-thermal { 5591 polling-delay-passive = <250>; 5592 polling-delay = <1000>; 5593 5594 thermal-sensors = <&tsens0 6>; 5595 5596 trips { 5597 cluster1_alert0: trip-point0 { 5598 temperature = <90000>; 5599 hysteresis = <2000>; 5600 type = "hot"; 5601 }; 5602 cluster1_crit: cluster1-crit { 5603 temperature = <110000>; 5604 hysteresis = <2000>; 5605 type = "critical"; 5606 }; 5607 }; 5608 }; 5609 5610 gpu-top-thermal { 5611 polling-delay-passive = <250>; 5612 polling-delay = <1000>; 5613 5614 thermal-sensors = <&tsens0 11>; 5615 5616 cooling-maps { 5617 map0 { 5618 trip = <&gpu_top_alert0>; 5619 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5620 }; 5621 }; 5622 5623 trips { 5624 gpu_top_alert0: trip-point0 { 5625 temperature = <90000>; 5626 hysteresis = <2000>; 5627 type = "hot"; 5628 }; 5629 }; 5630 }; 5631 5632 gpu-bottom-thermal { 5633 polling-delay-passive = <250>; 5634 polling-delay = <1000>; 5635 5636 thermal-sensors = <&tsens0 12>; 5637 5638 cooling-maps { 5639 map0 { 5640 trip = <&gpu_bottom_alert0>; 5641 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5642 }; 5643 }; 5644 5645 trips { 5646 gpu_bottom_alert0: trip-point0 { 5647 temperature = <90000>; 5648 hysteresis = <2000>; 5649 type = "hot"; 5650 }; 5651 }; 5652 }; 5653 5654 aoss1-thermal { 5655 polling-delay-passive = <250>; 5656 polling-delay = <1000>; 5657 5658 thermal-sensors = <&tsens1 0>; 5659 5660 trips { 5661 aoss1_alert0: trip-point0 { 5662 temperature = <90000>; 5663 hysteresis = <2000>; 5664 type = "hot"; 5665 }; 5666 }; 5667 }; 5668 5669 q6-modem-thermal { 5670 polling-delay-passive = <250>; 5671 polling-delay = <1000>; 5672 5673 thermal-sensors = <&tsens1 1>; 5674 5675 trips { 5676 q6_modem_alert0: trip-point0 { 5677 temperature = <90000>; 5678 hysteresis = <2000>; 5679 type = "hot"; 5680 }; 5681 }; 5682 }; 5683 5684 mem-thermal { 5685 polling-delay-passive = <250>; 5686 polling-delay = <1000>; 5687 5688 thermal-sensors = <&tsens1 2>; 5689 5690 trips { 5691 mem_alert0: trip-point0 { 5692 temperature = <90000>; 5693 hysteresis = <2000>; 5694 type = "hot"; 5695 }; 5696 }; 5697 }; 5698 5699 wlan-thermal { 5700 polling-delay-passive = <250>; 5701 polling-delay = <1000>; 5702 5703 thermal-sensors = <&tsens1 3>; 5704 5705 trips { 5706 wlan_alert0: trip-point0 { 5707 temperature = <90000>; 5708 hysteresis = <2000>; 5709 type = "hot"; 5710 }; 5711 }; 5712 }; 5713 5714 q6-hvx-thermal { 5715 polling-delay-passive = <250>; 5716 polling-delay = <1000>; 5717 5718 thermal-sensors = <&tsens1 4>; 5719 5720 trips { 5721 q6_hvx_alert0: trip-point0 { 5722 temperature = <90000>; 5723 hysteresis = <2000>; 5724 type = "hot"; 5725 }; 5726 }; 5727 }; 5728 5729 camera-thermal { 5730 polling-delay-passive = <250>; 5731 polling-delay = <1000>; 5732 5733 thermal-sensors = <&tsens1 5>; 5734 5735 trips { 5736 camera_alert0: trip-point0 { 5737 temperature = <90000>; 5738 hysteresis = <2000>; 5739 type = "hot"; 5740 }; 5741 }; 5742 }; 5743 5744 video-thermal { 5745 polling-delay-passive = <250>; 5746 polling-delay = <1000>; 5747 5748 thermal-sensors = <&tsens1 6>; 5749 5750 trips { 5751 video_alert0: trip-point0 { 5752 temperature = <90000>; 5753 hysteresis = <2000>; 5754 type = "hot"; 5755 }; 5756 }; 5757 }; 5758 5759 modem-thermal { 5760 polling-delay-passive = <250>; 5761 polling-delay = <1000>; 5762 5763 thermal-sensors = <&tsens1 7>; 5764 5765 trips { 5766 modem_alert0: trip-point0 { 5767 temperature = <90000>; 5768 hysteresis = <2000>; 5769 type = "hot"; 5770 }; 5771 }; 5772 }; 5773 }; 5774 5775 timer { 5776 compatible = "arm,armv8-timer"; 5777 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 5778 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 5779 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 5780 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 5781 }; 5782}; 5783