1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 9#include <dt-bindings/clock/qcom,gcc-sdm845.h> 10#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 11#include <dt-bindings/clock/qcom,lpass-sdm845.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/clock/qcom,videocc-sdm845.h> 14#include <dt-bindings/interconnect/qcom,sdm845.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/phy/phy-qcom-qusb2.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/reset/qcom,sdm845-aoss.h> 19#include <dt-bindings/reset/qcom,sdm845-pdc.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/clock/qcom,gcc-sdm845.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 aliases { 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 i2c4 = &i2c4; 36 i2c5 = &i2c5; 37 i2c6 = &i2c6; 38 i2c7 = &i2c7; 39 i2c8 = &i2c8; 40 i2c9 = &i2c9; 41 i2c10 = &i2c10; 42 i2c11 = &i2c11; 43 i2c12 = &i2c12; 44 i2c13 = &i2c13; 45 i2c14 = &i2c14; 46 i2c15 = &i2c15; 47 spi0 = &spi0; 48 spi1 = &spi1; 49 spi2 = &spi2; 50 spi3 = &spi3; 51 spi4 = &spi4; 52 spi5 = &spi5; 53 spi6 = &spi6; 54 spi7 = &spi7; 55 spi8 = &spi8; 56 spi9 = &spi9; 57 spi10 = &spi10; 58 spi11 = &spi11; 59 spi12 = &spi12; 60 spi13 = &spi13; 61 spi14 = &spi14; 62 spi15 = &spi15; 63 }; 64 65 chosen { }; 66 67 memory@80000000 { 68 device_type = "memory"; 69 /* We expect the bootloader to fill in the size */ 70 reg = <0 0x80000000 0 0>; 71 }; 72 73 reserved-memory { 74 #address-cells = <2>; 75 #size-cells = <2>; 76 ranges; 77 78 hyp_mem: memory@85700000 { 79 reg = <0 0x85700000 0 0x600000>; 80 no-map; 81 }; 82 83 xbl_mem: memory@85e00000 { 84 reg = <0 0x85e00000 0 0x100000>; 85 no-map; 86 }; 87 88 aop_mem: memory@85fc0000 { 89 reg = <0 0x85fc0000 0 0x20000>; 90 no-map; 91 }; 92 93 aop_cmd_db_mem: memory@85fe0000 { 94 compatible = "qcom,cmd-db"; 95 reg = <0x0 0x85fe0000 0 0x20000>; 96 no-map; 97 }; 98 99 smem_mem: memory@86000000 { 100 reg = <0x0 0x86000000 0 0x200000>; 101 no-map; 102 }; 103 104 tz_mem: memory@86200000 { 105 reg = <0 0x86200000 0 0x2d00000>; 106 no-map; 107 }; 108 109 rmtfs_mem: memory@88f00000 { 110 compatible = "qcom,rmtfs-mem"; 111 reg = <0 0x88f00000 0 0x200000>; 112 no-map; 113 114 qcom,client-id = <1>; 115 qcom,vmid = <15>; 116 }; 117 118 qseecom_mem: memory@8ab00000 { 119 reg = <0 0x8ab00000 0 0x1400000>; 120 no-map; 121 }; 122 123 camera_mem: memory@8bf00000 { 124 reg = <0 0x8bf00000 0 0x500000>; 125 no-map; 126 }; 127 128 ipa_fw_mem: memory@8c400000 { 129 reg = <0 0x8c400000 0 0x10000>; 130 no-map; 131 }; 132 133 ipa_gsi_mem: memory@8c410000 { 134 reg = <0 0x8c410000 0 0x5000>; 135 no-map; 136 }; 137 138 gpu_mem: memory@8c415000 { 139 reg = <0 0x8c415000 0 0x2000>; 140 no-map; 141 }; 142 143 adsp_mem: memory@8c500000 { 144 reg = <0 0x8c500000 0 0x1a00000>; 145 no-map; 146 }; 147 148 wlan_msa_mem: memory@8df00000 { 149 reg = <0 0x8df00000 0 0x100000>; 150 no-map; 151 }; 152 153 mpss_region: memory@8e000000 { 154 reg = <0 0x8e000000 0 0x7800000>; 155 no-map; 156 }; 157 158 venus_mem: memory@95800000 { 159 reg = <0 0x95800000 0 0x500000>; 160 no-map; 161 }; 162 163 cdsp_mem: memory@95d00000 { 164 reg = <0 0x95d00000 0 0x800000>; 165 no-map; 166 }; 167 168 mba_region: memory@96500000 { 169 reg = <0 0x96500000 0 0x200000>; 170 no-map; 171 }; 172 173 slpi_mem: memory@96700000 { 174 reg = <0 0x96700000 0 0x1400000>; 175 no-map; 176 }; 177 178 spss_mem: memory@97b00000 { 179 reg = <0 0x97b00000 0 0x100000>; 180 no-map; 181 }; 182 }; 183 184 cpus { 185 #address-cells = <2>; 186 #size-cells = <0>; 187 188 CPU0: cpu@0 { 189 device_type = "cpu"; 190 compatible = "qcom,kryo385"; 191 reg = <0x0 0x0>; 192 enable-method = "psci"; 193 capacity-dmips-mhz = <607>; 194 qcom,freq-domain = <&cpufreq_hw 0>; 195 #cooling-cells = <2>; 196 next-level-cache = <&L2_0>; 197 L2_0: l2-cache { 198 compatible = "cache"; 199 next-level-cache = <&L3_0>; 200 L3_0: l3-cache { 201 compatible = "cache"; 202 }; 203 }; 204 }; 205 206 CPU1: cpu@100 { 207 device_type = "cpu"; 208 compatible = "qcom,kryo385"; 209 reg = <0x0 0x100>; 210 enable-method = "psci"; 211 capacity-dmips-mhz = <607>; 212 qcom,freq-domain = <&cpufreq_hw 0>; 213 #cooling-cells = <2>; 214 next-level-cache = <&L2_100>; 215 L2_100: l2-cache { 216 compatible = "cache"; 217 next-level-cache = <&L3_0>; 218 }; 219 }; 220 221 CPU2: cpu@200 { 222 device_type = "cpu"; 223 compatible = "qcom,kryo385"; 224 reg = <0x0 0x200>; 225 enable-method = "psci"; 226 capacity-dmips-mhz = <607>; 227 qcom,freq-domain = <&cpufreq_hw 0>; 228 #cooling-cells = <2>; 229 next-level-cache = <&L2_200>; 230 L2_200: l2-cache { 231 compatible = "cache"; 232 next-level-cache = <&L3_0>; 233 }; 234 }; 235 236 CPU3: cpu@300 { 237 device_type = "cpu"; 238 compatible = "qcom,kryo385"; 239 reg = <0x0 0x300>; 240 enable-method = "psci"; 241 capacity-dmips-mhz = <607>; 242 qcom,freq-domain = <&cpufreq_hw 0>; 243 #cooling-cells = <2>; 244 next-level-cache = <&L2_300>; 245 L2_300: l2-cache { 246 compatible = "cache"; 247 next-level-cache = <&L3_0>; 248 }; 249 }; 250 251 CPU4: cpu@400 { 252 device_type = "cpu"; 253 compatible = "qcom,kryo385"; 254 reg = <0x0 0x400>; 255 enable-method = "psci"; 256 capacity-dmips-mhz = <1024>; 257 qcom,freq-domain = <&cpufreq_hw 1>; 258 #cooling-cells = <2>; 259 next-level-cache = <&L2_400>; 260 L2_400: l2-cache { 261 compatible = "cache"; 262 next-level-cache = <&L3_0>; 263 }; 264 }; 265 266 CPU5: cpu@500 { 267 device_type = "cpu"; 268 compatible = "qcom,kryo385"; 269 reg = <0x0 0x500>; 270 enable-method = "psci"; 271 capacity-dmips-mhz = <1024>; 272 qcom,freq-domain = <&cpufreq_hw 1>; 273 #cooling-cells = <2>; 274 next-level-cache = <&L2_500>; 275 L2_500: l2-cache { 276 compatible = "cache"; 277 next-level-cache = <&L3_0>; 278 }; 279 }; 280 281 CPU6: cpu@600 { 282 device_type = "cpu"; 283 compatible = "qcom,kryo385"; 284 reg = <0x0 0x600>; 285 enable-method = "psci"; 286 capacity-dmips-mhz = <1024>; 287 qcom,freq-domain = <&cpufreq_hw 1>; 288 #cooling-cells = <2>; 289 next-level-cache = <&L2_600>; 290 L2_600: l2-cache { 291 compatible = "cache"; 292 next-level-cache = <&L3_0>; 293 }; 294 }; 295 296 CPU7: cpu@700 { 297 device_type = "cpu"; 298 compatible = "qcom,kryo385"; 299 reg = <0x0 0x700>; 300 enable-method = "psci"; 301 capacity-dmips-mhz = <1024>; 302 qcom,freq-domain = <&cpufreq_hw 1>; 303 #cooling-cells = <2>; 304 next-level-cache = <&L2_700>; 305 L2_700: l2-cache { 306 compatible = "cache"; 307 next-level-cache = <&L3_0>; 308 }; 309 }; 310 311 cpu-map { 312 cluster0 { 313 core0 { 314 cpu = <&CPU0>; 315 }; 316 317 core1 { 318 cpu = <&CPU1>; 319 }; 320 321 core2 { 322 cpu = <&CPU2>; 323 }; 324 325 core3 { 326 cpu = <&CPU3>; 327 }; 328 }; 329 330 cluster1 { 331 core0 { 332 cpu = <&CPU4>; 333 }; 334 335 core1 { 336 cpu = <&CPU5>; 337 }; 338 339 core2 { 340 cpu = <&CPU6>; 341 }; 342 343 core3 { 344 cpu = <&CPU7>; 345 }; 346 }; 347 }; 348 }; 349 350 pmu { 351 compatible = "arm,armv8-pmuv3"; 352 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 353 }; 354 355 timer { 356 compatible = "arm,armv8-timer"; 357 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 358 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 359 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 360 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 361 }; 362 363 clocks { 364 xo_board: xo-board { 365 compatible = "fixed-clock"; 366 #clock-cells = <0>; 367 clock-frequency = <38400000>; 368 clock-output-names = "xo_board"; 369 }; 370 371 sleep_clk: sleep-clk { 372 compatible = "fixed-clock"; 373 #clock-cells = <0>; 374 clock-frequency = <32764>; 375 }; 376 }; 377 378 firmware { 379 scm { 380 compatible = "qcom,scm-sdm845", "qcom,scm"; 381 }; 382 }; 383 384 adsp_pas: remoteproc-adsp { 385 compatible = "qcom,sdm845-adsp-pas"; 386 387 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 388 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 389 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 390 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 391 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 392 interrupt-names = "wdog", "fatal", "ready", 393 "handover", "stop-ack"; 394 395 clocks = <&rpmhcc RPMH_CXO_CLK>; 396 clock-names = "xo"; 397 398 memory-region = <&adsp_mem>; 399 400 qcom,smem-states = <&adsp_smp2p_out 0>; 401 qcom,smem-state-names = "stop"; 402 403 status = "disabled"; 404 405 glink-edge { 406 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 407 label = "lpass"; 408 qcom,remote-pid = <2>; 409 mboxes = <&apss_shared 8>; 410 }; 411 }; 412 413 cdsp_pas: remoteproc-cdsp { 414 compatible = "qcom,sdm845-cdsp-pas"; 415 416 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 417 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 418 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 419 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 420 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 421 interrupt-names = "wdog", "fatal", "ready", 422 "handover", "stop-ack"; 423 424 clocks = <&rpmhcc RPMH_CXO_CLK>; 425 clock-names = "xo"; 426 427 memory-region = <&cdsp_mem>; 428 429 qcom,smem-states = <&cdsp_smp2p_out 0>; 430 qcom,smem-state-names = "stop"; 431 432 status = "disabled"; 433 434 glink-edge { 435 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 436 label = "turing"; 437 qcom,remote-pid = <5>; 438 mboxes = <&apss_shared 4>; 439 }; 440 }; 441 442 tcsr_mutex: hwlock { 443 compatible = "qcom,tcsr-mutex"; 444 syscon = <&tcsr_mutex_regs 0 0x1000>; 445 #hwlock-cells = <1>; 446 }; 447 448 smem { 449 compatible = "qcom,smem"; 450 memory-region = <&smem_mem>; 451 hwlocks = <&tcsr_mutex 3>; 452 }; 453 454 smp2p-cdsp { 455 compatible = "qcom,smp2p"; 456 qcom,smem = <94>, <432>; 457 458 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 459 460 mboxes = <&apss_shared 6>; 461 462 qcom,local-pid = <0>; 463 qcom,remote-pid = <5>; 464 465 cdsp_smp2p_out: master-kernel { 466 qcom,entry-name = "master-kernel"; 467 #qcom,smem-state-cells = <1>; 468 }; 469 470 cdsp_smp2p_in: slave-kernel { 471 qcom,entry-name = "slave-kernel"; 472 473 interrupt-controller; 474 #interrupt-cells = <2>; 475 }; 476 }; 477 478 smp2p-lpass { 479 compatible = "qcom,smp2p"; 480 qcom,smem = <443>, <429>; 481 482 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 483 484 mboxes = <&apss_shared 10>; 485 486 qcom,local-pid = <0>; 487 qcom,remote-pid = <2>; 488 489 adsp_smp2p_out: master-kernel { 490 qcom,entry-name = "master-kernel"; 491 #qcom,smem-state-cells = <1>; 492 }; 493 494 adsp_smp2p_in: slave-kernel { 495 qcom,entry-name = "slave-kernel"; 496 497 interrupt-controller; 498 #interrupt-cells = <2>; 499 }; 500 }; 501 502 smp2p-mpss { 503 compatible = "qcom,smp2p"; 504 qcom,smem = <435>, <428>; 505 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 506 mboxes = <&apss_shared 14>; 507 qcom,local-pid = <0>; 508 qcom,remote-pid = <1>; 509 510 modem_smp2p_out: master-kernel { 511 qcom,entry-name = "master-kernel"; 512 #qcom,smem-state-cells = <1>; 513 }; 514 515 modem_smp2p_in: slave-kernel { 516 qcom,entry-name = "slave-kernel"; 517 interrupt-controller; 518 #interrupt-cells = <2>; 519 }; 520 }; 521 522 smp2p-slpi { 523 compatible = "qcom,smp2p"; 524 qcom,smem = <481>, <430>; 525 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 526 mboxes = <&apss_shared 26>; 527 qcom,local-pid = <0>; 528 qcom,remote-pid = <3>; 529 530 slpi_smp2p_out: master-kernel { 531 qcom,entry-name = "master-kernel"; 532 #qcom,smem-state-cells = <1>; 533 }; 534 535 slpi_smp2p_in: slave-kernel { 536 qcom,entry-name = "slave-kernel"; 537 interrupt-controller; 538 #interrupt-cells = <2>; 539 }; 540 }; 541 542 psci { 543 compatible = "arm,psci-1.0"; 544 method = "smc"; 545 }; 546 547 soc: soc { 548 #address-cells = <2>; 549 #size-cells = <2>; 550 ranges = <0 0 0 0 0x10 0>; 551 dma-ranges = <0 0 0 0 0x10 0>; 552 compatible = "simple-bus"; 553 554 gcc: clock-controller@100000 { 555 compatible = "qcom,gcc-sdm845"; 556 reg = <0 0x00100000 0 0x1f0000>; 557 #clock-cells = <1>; 558 #reset-cells = <1>; 559 #power-domain-cells = <1>; 560 }; 561 562 qfprom@784000 { 563 compatible = "qcom,qfprom"; 564 reg = <0 0x00784000 0 0x8ff>; 565 #address-cells = <1>; 566 #size-cells = <1>; 567 568 qusb2p_hstx_trim: hstx-trim-primary@1eb { 569 reg = <0x1eb 0x1>; 570 bits = <1 4>; 571 }; 572 573 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 574 reg = <0x1eb 0x2>; 575 bits = <6 4>; 576 }; 577 }; 578 579 rng: rng@793000 { 580 compatible = "qcom,prng-ee"; 581 reg = <0 0x00793000 0 0x1000>; 582 clocks = <&gcc GCC_PRNG_AHB_CLK>; 583 clock-names = "core"; 584 }; 585 586 qupv3_id_0: geniqup@8c0000 { 587 compatible = "qcom,geni-se-qup"; 588 reg = <0 0x008c0000 0 0x6000>; 589 clock-names = "m-ahb", "s-ahb"; 590 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 591 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 592 #address-cells = <2>; 593 #size-cells = <2>; 594 ranges; 595 status = "disabled"; 596 597 i2c0: i2c@880000 { 598 compatible = "qcom,geni-i2c"; 599 reg = <0 0x00880000 0 0x4000>; 600 clock-names = "se"; 601 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 602 pinctrl-names = "default"; 603 pinctrl-0 = <&qup_i2c0_default>; 604 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 status = "disabled"; 608 }; 609 610 spi0: spi@880000 { 611 compatible = "qcom,geni-spi"; 612 reg = <0 0x00880000 0 0x4000>; 613 clock-names = "se"; 614 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 615 pinctrl-names = "default"; 616 pinctrl-0 = <&qup_spi0_default>; 617 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 status = "disabled"; 621 }; 622 623 uart0: serial@880000 { 624 compatible = "qcom,geni-uart"; 625 reg = <0 0x00880000 0 0x4000>; 626 clock-names = "se"; 627 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 628 pinctrl-names = "default"; 629 pinctrl-0 = <&qup_uart0_default>; 630 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 631 status = "disabled"; 632 }; 633 634 i2c1: i2c@884000 { 635 compatible = "qcom,geni-i2c"; 636 reg = <0 0x00884000 0 0x4000>; 637 clock-names = "se"; 638 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 639 pinctrl-names = "default"; 640 pinctrl-0 = <&qup_i2c1_default>; 641 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 642 #address-cells = <1>; 643 #size-cells = <0>; 644 status = "disabled"; 645 }; 646 647 spi1: spi@884000 { 648 compatible = "qcom,geni-spi"; 649 reg = <0 0x00884000 0 0x4000>; 650 clock-names = "se"; 651 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 652 pinctrl-names = "default"; 653 pinctrl-0 = <&qup_spi1_default>; 654 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 655 #address-cells = <1>; 656 #size-cells = <0>; 657 status = "disabled"; 658 }; 659 660 uart1: serial@884000 { 661 compatible = "qcom,geni-uart"; 662 reg = <0 0x00884000 0 0x4000>; 663 clock-names = "se"; 664 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 665 pinctrl-names = "default"; 666 pinctrl-0 = <&qup_uart1_default>; 667 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 668 status = "disabled"; 669 }; 670 671 i2c2: i2c@888000 { 672 compatible = "qcom,geni-i2c"; 673 reg = <0 0x00888000 0 0x4000>; 674 clock-names = "se"; 675 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 676 pinctrl-names = "default"; 677 pinctrl-0 = <&qup_i2c2_default>; 678 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 679 #address-cells = <1>; 680 #size-cells = <0>; 681 status = "disabled"; 682 }; 683 684 spi2: spi@888000 { 685 compatible = "qcom,geni-spi"; 686 reg = <0 0x00888000 0 0x4000>; 687 clock-names = "se"; 688 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 689 pinctrl-names = "default"; 690 pinctrl-0 = <&qup_spi2_default>; 691 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 692 #address-cells = <1>; 693 #size-cells = <0>; 694 status = "disabled"; 695 }; 696 697 uart2: serial@888000 { 698 compatible = "qcom,geni-uart"; 699 reg = <0 0x00888000 0 0x4000>; 700 clock-names = "se"; 701 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 702 pinctrl-names = "default"; 703 pinctrl-0 = <&qup_uart2_default>; 704 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 705 status = "disabled"; 706 }; 707 708 i2c3: i2c@88c000 { 709 compatible = "qcom,geni-i2c"; 710 reg = <0 0x0088c000 0 0x4000>; 711 clock-names = "se"; 712 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 713 pinctrl-names = "default"; 714 pinctrl-0 = <&qup_i2c3_default>; 715 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 716 #address-cells = <1>; 717 #size-cells = <0>; 718 status = "disabled"; 719 }; 720 721 spi3: spi@88c000 { 722 compatible = "qcom,geni-spi"; 723 reg = <0 0x0088c000 0 0x4000>; 724 clock-names = "se"; 725 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 726 pinctrl-names = "default"; 727 pinctrl-0 = <&qup_spi3_default>; 728 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 729 #address-cells = <1>; 730 #size-cells = <0>; 731 status = "disabled"; 732 }; 733 734 uart3: serial@88c000 { 735 compatible = "qcom,geni-uart"; 736 reg = <0 0x0088c000 0 0x4000>; 737 clock-names = "se"; 738 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 739 pinctrl-names = "default"; 740 pinctrl-0 = <&qup_uart3_default>; 741 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 742 status = "disabled"; 743 }; 744 745 i2c4: i2c@890000 { 746 compatible = "qcom,geni-i2c"; 747 reg = <0 0x00890000 0 0x4000>; 748 clock-names = "se"; 749 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 750 pinctrl-names = "default"; 751 pinctrl-0 = <&qup_i2c4_default>; 752 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 753 #address-cells = <1>; 754 #size-cells = <0>; 755 status = "disabled"; 756 }; 757 758 spi4: spi@890000 { 759 compatible = "qcom,geni-spi"; 760 reg = <0 0x00890000 0 0x4000>; 761 clock-names = "se"; 762 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 763 pinctrl-names = "default"; 764 pinctrl-0 = <&qup_spi4_default>; 765 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 766 #address-cells = <1>; 767 #size-cells = <0>; 768 status = "disabled"; 769 }; 770 771 uart4: serial@890000 { 772 compatible = "qcom,geni-uart"; 773 reg = <0 0x00890000 0 0x4000>; 774 clock-names = "se"; 775 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 776 pinctrl-names = "default"; 777 pinctrl-0 = <&qup_uart4_default>; 778 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 779 status = "disabled"; 780 }; 781 782 i2c5: i2c@894000 { 783 compatible = "qcom,geni-i2c"; 784 reg = <0 0x00894000 0 0x4000>; 785 clock-names = "se"; 786 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 787 pinctrl-names = "default"; 788 pinctrl-0 = <&qup_i2c5_default>; 789 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 790 #address-cells = <1>; 791 #size-cells = <0>; 792 status = "disabled"; 793 }; 794 795 spi5: spi@894000 { 796 compatible = "qcom,geni-spi"; 797 reg = <0 0x00894000 0 0x4000>; 798 clock-names = "se"; 799 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 800 pinctrl-names = "default"; 801 pinctrl-0 = <&qup_spi5_default>; 802 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 803 #address-cells = <1>; 804 #size-cells = <0>; 805 status = "disabled"; 806 }; 807 808 uart5: serial@894000 { 809 compatible = "qcom,geni-uart"; 810 reg = <0 0x00894000 0 0x4000>; 811 clock-names = "se"; 812 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 813 pinctrl-names = "default"; 814 pinctrl-0 = <&qup_uart5_default>; 815 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 816 status = "disabled"; 817 }; 818 819 i2c6: i2c@898000 { 820 compatible = "qcom,geni-i2c"; 821 reg = <0 0x00898000 0 0x4000>; 822 clock-names = "se"; 823 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 824 pinctrl-names = "default"; 825 pinctrl-0 = <&qup_i2c6_default>; 826 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 827 #address-cells = <1>; 828 #size-cells = <0>; 829 status = "disabled"; 830 }; 831 832 spi6: spi@898000 { 833 compatible = "qcom,geni-spi"; 834 reg = <0 0x00898000 0 0x4000>; 835 clock-names = "se"; 836 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 837 pinctrl-names = "default"; 838 pinctrl-0 = <&qup_spi6_default>; 839 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 status = "disabled"; 843 }; 844 845 uart6: serial@898000 { 846 compatible = "qcom,geni-uart"; 847 reg = <0 0x00898000 0 0x4000>; 848 clock-names = "se"; 849 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 850 pinctrl-names = "default"; 851 pinctrl-0 = <&qup_uart6_default>; 852 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 853 status = "disabled"; 854 }; 855 856 i2c7: i2c@89c000 { 857 compatible = "qcom,geni-i2c"; 858 reg = <0 0x0089c000 0 0x4000>; 859 clock-names = "se"; 860 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 861 pinctrl-names = "default"; 862 pinctrl-0 = <&qup_i2c7_default>; 863 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 864 #address-cells = <1>; 865 #size-cells = <0>; 866 status = "disabled"; 867 }; 868 869 spi7: spi@89c000 { 870 compatible = "qcom,geni-spi"; 871 reg = <0 0x0089c000 0 0x4000>; 872 clock-names = "se"; 873 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 874 pinctrl-names = "default"; 875 pinctrl-0 = <&qup_spi7_default>; 876 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 877 #address-cells = <1>; 878 #size-cells = <0>; 879 status = "disabled"; 880 }; 881 882 uart7: serial@89c000 { 883 compatible = "qcom,geni-uart"; 884 reg = <0 0x0089c000 0 0x4000>; 885 clock-names = "se"; 886 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 887 pinctrl-names = "default"; 888 pinctrl-0 = <&qup_uart7_default>; 889 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 890 status = "disabled"; 891 }; 892 }; 893 894 qupv3_id_1: geniqup@ac0000 { 895 compatible = "qcom,geni-se-qup"; 896 reg = <0 0x00ac0000 0 0x6000>; 897 clock-names = "m-ahb", "s-ahb"; 898 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 899 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 900 #address-cells = <2>; 901 #size-cells = <2>; 902 ranges; 903 status = "disabled"; 904 905 i2c8: i2c@a80000 { 906 compatible = "qcom,geni-i2c"; 907 reg = <0 0x00a80000 0 0x4000>; 908 clock-names = "se"; 909 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 910 pinctrl-names = "default"; 911 pinctrl-0 = <&qup_i2c8_default>; 912 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 status = "disabled"; 916 }; 917 918 spi8: spi@a80000 { 919 compatible = "qcom,geni-spi"; 920 reg = <0 0x00a80000 0 0x4000>; 921 clock-names = "se"; 922 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 923 pinctrl-names = "default"; 924 pinctrl-0 = <&qup_spi8_default>; 925 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 926 #address-cells = <1>; 927 #size-cells = <0>; 928 status = "disabled"; 929 }; 930 931 uart8: serial@a80000 { 932 compatible = "qcom,geni-uart"; 933 reg = <0 0x00a80000 0 0x4000>; 934 clock-names = "se"; 935 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 936 pinctrl-names = "default"; 937 pinctrl-0 = <&qup_uart8_default>; 938 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 939 status = "disabled"; 940 }; 941 942 i2c9: i2c@a84000 { 943 compatible = "qcom,geni-i2c"; 944 reg = <0 0x00a84000 0 0x4000>; 945 clock-names = "se"; 946 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 947 pinctrl-names = "default"; 948 pinctrl-0 = <&qup_i2c9_default>; 949 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 950 #address-cells = <1>; 951 #size-cells = <0>; 952 status = "disabled"; 953 }; 954 955 spi9: spi@a84000 { 956 compatible = "qcom,geni-spi"; 957 reg = <0 0x00a84000 0 0x4000>; 958 clock-names = "se"; 959 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 960 pinctrl-names = "default"; 961 pinctrl-0 = <&qup_spi9_default>; 962 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 963 #address-cells = <1>; 964 #size-cells = <0>; 965 status = "disabled"; 966 }; 967 968 uart9: serial@a84000 { 969 compatible = "qcom,geni-debug-uart"; 970 reg = <0 0x00a84000 0 0x4000>; 971 clock-names = "se"; 972 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 973 pinctrl-names = "default"; 974 pinctrl-0 = <&qup_uart9_default>; 975 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 976 status = "disabled"; 977 }; 978 979 i2c10: i2c@a88000 { 980 compatible = "qcom,geni-i2c"; 981 reg = <0 0x00a88000 0 0x4000>; 982 clock-names = "se"; 983 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 984 pinctrl-names = "default"; 985 pinctrl-0 = <&qup_i2c10_default>; 986 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 status = "disabled"; 990 }; 991 992 spi10: spi@a88000 { 993 compatible = "qcom,geni-spi"; 994 reg = <0 0x00a88000 0 0x4000>; 995 clock-names = "se"; 996 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 997 pinctrl-names = "default"; 998 pinctrl-0 = <&qup_spi10_default>; 999 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 status = "disabled"; 1003 }; 1004 1005 uart10: serial@a88000 { 1006 compatible = "qcom,geni-uart"; 1007 reg = <0 0x00a88000 0 0x4000>; 1008 clock-names = "se"; 1009 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1010 pinctrl-names = "default"; 1011 pinctrl-0 = <&qup_uart10_default>; 1012 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1013 status = "disabled"; 1014 }; 1015 1016 i2c11: i2c@a8c000 { 1017 compatible = "qcom,geni-i2c"; 1018 reg = <0 0x00a8c000 0 0x4000>; 1019 clock-names = "se"; 1020 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1021 pinctrl-names = "default"; 1022 pinctrl-0 = <&qup_i2c11_default>; 1023 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 status = "disabled"; 1027 }; 1028 1029 spi11: spi@a8c000 { 1030 compatible = "qcom,geni-spi"; 1031 reg = <0 0x00a8c000 0 0x4000>; 1032 clock-names = "se"; 1033 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1034 pinctrl-names = "default"; 1035 pinctrl-0 = <&qup_spi11_default>; 1036 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 status = "disabled"; 1040 }; 1041 1042 uart11: serial@a8c000 { 1043 compatible = "qcom,geni-uart"; 1044 reg = <0 0x00a8c000 0 0x4000>; 1045 clock-names = "se"; 1046 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1047 pinctrl-names = "default"; 1048 pinctrl-0 = <&qup_uart11_default>; 1049 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1050 status = "disabled"; 1051 }; 1052 1053 i2c12: i2c@a90000 { 1054 compatible = "qcom,geni-i2c"; 1055 reg = <0 0x00a90000 0 0x4000>; 1056 clock-names = "se"; 1057 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1058 pinctrl-names = "default"; 1059 pinctrl-0 = <&qup_i2c12_default>; 1060 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 status = "disabled"; 1064 }; 1065 1066 spi12: spi@a90000 { 1067 compatible = "qcom,geni-spi"; 1068 reg = <0 0x00a90000 0 0x4000>; 1069 clock-names = "se"; 1070 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1071 pinctrl-names = "default"; 1072 pinctrl-0 = <&qup_spi12_default>; 1073 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 status = "disabled"; 1077 }; 1078 1079 uart12: serial@a90000 { 1080 compatible = "qcom,geni-uart"; 1081 reg = <0 0x00a90000 0 0x4000>; 1082 clock-names = "se"; 1083 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1084 pinctrl-names = "default"; 1085 pinctrl-0 = <&qup_uart12_default>; 1086 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1087 status = "disabled"; 1088 }; 1089 1090 i2c13: i2c@a94000 { 1091 compatible = "qcom,geni-i2c"; 1092 reg = <0 0x00a94000 0 0x4000>; 1093 clock-names = "se"; 1094 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1095 pinctrl-names = "default"; 1096 pinctrl-0 = <&qup_i2c13_default>; 1097 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 status = "disabled"; 1101 }; 1102 1103 spi13: spi@a94000 { 1104 compatible = "qcom,geni-spi"; 1105 reg = <0 0x00a94000 0 0x4000>; 1106 clock-names = "se"; 1107 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1108 pinctrl-names = "default"; 1109 pinctrl-0 = <&qup_spi13_default>; 1110 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1111 #address-cells = <1>; 1112 #size-cells = <0>; 1113 status = "disabled"; 1114 }; 1115 1116 uart13: serial@a94000 { 1117 compatible = "qcom,geni-uart"; 1118 reg = <0 0x00a94000 0 0x4000>; 1119 clock-names = "se"; 1120 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1121 pinctrl-names = "default"; 1122 pinctrl-0 = <&qup_uart13_default>; 1123 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1124 status = "disabled"; 1125 }; 1126 1127 i2c14: i2c@a98000 { 1128 compatible = "qcom,geni-i2c"; 1129 reg = <0 0x00a98000 0 0x4000>; 1130 clock-names = "se"; 1131 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1132 pinctrl-names = "default"; 1133 pinctrl-0 = <&qup_i2c14_default>; 1134 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 status = "disabled"; 1138 }; 1139 1140 spi14: spi@a98000 { 1141 compatible = "qcom,geni-spi"; 1142 reg = <0 0x00a98000 0 0x4000>; 1143 clock-names = "se"; 1144 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1145 pinctrl-names = "default"; 1146 pinctrl-0 = <&qup_spi14_default>; 1147 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 status = "disabled"; 1151 }; 1152 1153 uart14: serial@a98000 { 1154 compatible = "qcom,geni-uart"; 1155 reg = <0 0x00a98000 0 0x4000>; 1156 clock-names = "se"; 1157 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1158 pinctrl-names = "default"; 1159 pinctrl-0 = <&qup_uart14_default>; 1160 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1161 status = "disabled"; 1162 }; 1163 1164 i2c15: i2c@a9c000 { 1165 compatible = "qcom,geni-i2c"; 1166 reg = <0 0x00a9c000 0 0x4000>; 1167 clock-names = "se"; 1168 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1169 pinctrl-names = "default"; 1170 pinctrl-0 = <&qup_i2c15_default>; 1171 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 status = "disabled"; 1175 }; 1176 1177 spi15: spi@a9c000 { 1178 compatible = "qcom,geni-spi"; 1179 reg = <0 0x00a9c000 0 0x4000>; 1180 clock-names = "se"; 1181 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1182 pinctrl-names = "default"; 1183 pinctrl-0 = <&qup_spi15_default>; 1184 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 status = "disabled"; 1188 }; 1189 1190 uart15: serial@a9c000 { 1191 compatible = "qcom,geni-uart"; 1192 reg = <0 0x00a9c000 0 0x4000>; 1193 clock-names = "se"; 1194 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1195 pinctrl-names = "default"; 1196 pinctrl-0 = <&qup_uart15_default>; 1197 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1198 status = "disabled"; 1199 }; 1200 }; 1201 1202 ufs_mem_hc: ufshc@1d84000 { 1203 compatible = "qcom,sdm845-ufshc", "qcom,ufshc", 1204 "jedec,ufs-2.0"; 1205 reg = <0 0x01d84000 0 0x2500>; 1206 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1207 phys = <&ufs_mem_phy_lanes>; 1208 phy-names = "ufsphy"; 1209 lanes-per-direction = <2>; 1210 power-domains = <&gcc UFS_PHY_GDSC>; 1211 #reset-cells = <1>; 1212 1213 iommus = <&apps_smmu 0x100 0xf>; 1214 1215 clock-names = 1216 "core_clk", 1217 "bus_aggr_clk", 1218 "iface_clk", 1219 "core_clk_unipro", 1220 "ref_clk", 1221 "tx_lane0_sync_clk", 1222 "rx_lane0_sync_clk", 1223 "rx_lane1_sync_clk"; 1224 clocks = 1225 <&gcc GCC_UFS_PHY_AXI_CLK>, 1226 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1227 <&gcc GCC_UFS_PHY_AHB_CLK>, 1228 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1229 <&rpmhcc RPMH_CXO_CLK>, 1230 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1231 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1232 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1233 freq-table-hz = 1234 <50000000 200000000>, 1235 <0 0>, 1236 <0 0>, 1237 <37500000 150000000>, 1238 <0 0>, 1239 <0 0>, 1240 <0 0>, 1241 <0 0>; 1242 1243 status = "disabled"; 1244 }; 1245 1246 ufs_mem_phy: phy@1d87000 { 1247 compatible = "qcom,sdm845-qmp-ufs-phy"; 1248 reg = <0 0x01d87000 0 0x18c>; 1249 #address-cells = <2>; 1250 #size-cells = <2>; 1251 ranges; 1252 clock-names = "ref", 1253 "ref_aux"; 1254 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 1255 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1256 1257 resets = <&ufs_mem_hc 0>; 1258 reset-names = "ufsphy"; 1259 status = "disabled"; 1260 1261 ufs_mem_phy_lanes: lanes@1d87400 { 1262 reg = <0 0x01d87400 0 0x108>, 1263 <0 0x01d87600 0 0x1e0>, 1264 <0 0x01d87c00 0 0x1dc>, 1265 <0 0x01d87800 0 0x108>, 1266 <0 0x01d87a00 0 0x1e0>; 1267 #phy-cells = <0>; 1268 }; 1269 }; 1270 1271 tcsr_mutex_regs: syscon@1f40000 { 1272 compatible = "syscon"; 1273 reg = <0 0x01f40000 0 0x40000>; 1274 }; 1275 1276 tlmm: pinctrl@3400000 { 1277 compatible = "qcom,sdm845-pinctrl"; 1278 reg = <0 0x03400000 0 0xc00000>; 1279 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1280 gpio-controller; 1281 #gpio-cells = <2>; 1282 interrupt-controller; 1283 #interrupt-cells = <2>; 1284 gpio-ranges = <&tlmm 0 0 150>; 1285 1286 qspi_clk: qspi-clk { 1287 pinmux { 1288 pins = "gpio95"; 1289 function = "qspi_clk"; 1290 }; 1291 }; 1292 1293 qspi_cs0: qspi-cs0 { 1294 pinmux { 1295 pins = "gpio90"; 1296 function = "qspi_cs"; 1297 }; 1298 }; 1299 1300 qspi_cs1: qspi-cs1 { 1301 pinmux { 1302 pins = "gpio89"; 1303 function = "qspi_cs"; 1304 }; 1305 }; 1306 1307 qspi_data01: qspi-data01 { 1308 pinmux-data { 1309 pins = "gpio91", "gpio92"; 1310 function = "qspi_data"; 1311 }; 1312 }; 1313 1314 qspi_data12: qspi-data12 { 1315 pinmux-data { 1316 pins = "gpio93", "gpio94"; 1317 function = "qspi_data"; 1318 }; 1319 }; 1320 1321 qup_i2c0_default: qup-i2c0-default { 1322 pinmux { 1323 pins = "gpio0", "gpio1"; 1324 function = "qup0"; 1325 }; 1326 }; 1327 1328 qup_i2c1_default: qup-i2c1-default { 1329 pinmux { 1330 pins = "gpio17", "gpio18"; 1331 function = "qup1"; 1332 }; 1333 }; 1334 1335 qup_i2c2_default: qup-i2c2-default { 1336 pinmux { 1337 pins = "gpio27", "gpio28"; 1338 function = "qup2"; 1339 }; 1340 }; 1341 1342 qup_i2c3_default: qup-i2c3-default { 1343 pinmux { 1344 pins = "gpio41", "gpio42"; 1345 function = "qup3"; 1346 }; 1347 }; 1348 1349 qup_i2c4_default: qup-i2c4-default { 1350 pinmux { 1351 pins = "gpio89", "gpio90"; 1352 function = "qup4"; 1353 }; 1354 }; 1355 1356 qup_i2c5_default: qup-i2c5-default { 1357 pinmux { 1358 pins = "gpio85", "gpio86"; 1359 function = "qup5"; 1360 }; 1361 }; 1362 1363 qup_i2c6_default: qup-i2c6-default { 1364 pinmux { 1365 pins = "gpio45", "gpio46"; 1366 function = "qup6"; 1367 }; 1368 }; 1369 1370 qup_i2c7_default: qup-i2c7-default { 1371 pinmux { 1372 pins = "gpio93", "gpio94"; 1373 function = "qup7"; 1374 }; 1375 }; 1376 1377 qup_i2c8_default: qup-i2c8-default { 1378 pinmux { 1379 pins = "gpio65", "gpio66"; 1380 function = "qup8"; 1381 }; 1382 }; 1383 1384 qup_i2c9_default: qup-i2c9-default { 1385 pinmux { 1386 pins = "gpio6", "gpio7"; 1387 function = "qup9"; 1388 }; 1389 }; 1390 1391 qup_i2c10_default: qup-i2c10-default { 1392 pinmux { 1393 pins = "gpio55", "gpio56"; 1394 function = "qup10"; 1395 }; 1396 }; 1397 1398 qup_i2c11_default: qup-i2c11-default { 1399 pinmux { 1400 pins = "gpio31", "gpio32"; 1401 function = "qup11"; 1402 }; 1403 }; 1404 1405 qup_i2c12_default: qup-i2c12-default { 1406 pinmux { 1407 pins = "gpio49", "gpio50"; 1408 function = "qup12"; 1409 }; 1410 }; 1411 1412 qup_i2c13_default: qup-i2c13-default { 1413 pinmux { 1414 pins = "gpio105", "gpio106"; 1415 function = "qup13"; 1416 }; 1417 }; 1418 1419 qup_i2c14_default: qup-i2c14-default { 1420 pinmux { 1421 pins = "gpio33", "gpio34"; 1422 function = "qup14"; 1423 }; 1424 }; 1425 1426 qup_i2c15_default: qup-i2c15-default { 1427 pinmux { 1428 pins = "gpio81", "gpio82"; 1429 function = "qup15"; 1430 }; 1431 }; 1432 1433 qup_spi0_default: qup-spi0-default { 1434 pinmux { 1435 pins = "gpio0", "gpio1", 1436 "gpio2", "gpio3"; 1437 function = "qup0"; 1438 }; 1439 }; 1440 1441 qup_spi1_default: qup-spi1-default { 1442 pinmux { 1443 pins = "gpio17", "gpio18", 1444 "gpio19", "gpio20"; 1445 function = "qup1"; 1446 }; 1447 }; 1448 1449 qup_spi2_default: qup-spi2-default { 1450 pinmux { 1451 pins = "gpio27", "gpio28", 1452 "gpio29", "gpio30"; 1453 function = "qup2"; 1454 }; 1455 }; 1456 1457 qup_spi3_default: qup-spi3-default { 1458 pinmux { 1459 pins = "gpio41", "gpio42", 1460 "gpio43", "gpio44"; 1461 function = "qup3"; 1462 }; 1463 }; 1464 1465 qup_spi4_default: qup-spi4-default { 1466 pinmux { 1467 pins = "gpio89", "gpio90", 1468 "gpio91", "gpio92"; 1469 function = "qup4"; 1470 }; 1471 }; 1472 1473 qup_spi5_default: qup-spi5-default { 1474 pinmux { 1475 pins = "gpio85", "gpio86", 1476 "gpio87", "gpio88"; 1477 function = "qup5"; 1478 }; 1479 }; 1480 1481 qup_spi6_default: qup-spi6-default { 1482 pinmux { 1483 pins = "gpio45", "gpio46", 1484 "gpio47", "gpio48"; 1485 function = "qup6"; 1486 }; 1487 }; 1488 1489 qup_spi7_default: qup-spi7-default { 1490 pinmux { 1491 pins = "gpio93", "gpio94", 1492 "gpio95", "gpio96"; 1493 function = "qup7"; 1494 }; 1495 }; 1496 1497 qup_spi8_default: qup-spi8-default { 1498 pinmux { 1499 pins = "gpio65", "gpio66", 1500 "gpio67", "gpio68"; 1501 function = "qup8"; 1502 }; 1503 }; 1504 1505 qup_spi9_default: qup-spi9-default { 1506 pinmux { 1507 pins = "gpio6", "gpio7", 1508 "gpio4", "gpio5"; 1509 function = "qup9"; 1510 }; 1511 }; 1512 1513 qup_spi10_default: qup-spi10-default { 1514 pinmux { 1515 pins = "gpio55", "gpio56", 1516 "gpio53", "gpio54"; 1517 function = "qup10"; 1518 }; 1519 }; 1520 1521 qup_spi11_default: qup-spi11-default { 1522 pinmux { 1523 pins = "gpio31", "gpio32", 1524 "gpio33", "gpio34"; 1525 function = "qup11"; 1526 }; 1527 }; 1528 1529 qup_spi12_default: qup-spi12-default { 1530 pinmux { 1531 pins = "gpio49", "gpio50", 1532 "gpio51", "gpio52"; 1533 function = "qup12"; 1534 }; 1535 }; 1536 1537 qup_spi13_default: qup-spi13-default { 1538 pinmux { 1539 pins = "gpio105", "gpio106", 1540 "gpio107", "gpio108"; 1541 function = "qup13"; 1542 }; 1543 }; 1544 1545 qup_spi14_default: qup-spi14-default { 1546 pinmux { 1547 pins = "gpio33", "gpio34", 1548 "gpio31", "gpio32"; 1549 function = "qup14"; 1550 }; 1551 }; 1552 1553 qup_spi15_default: qup-spi15-default { 1554 pinmux { 1555 pins = "gpio81", "gpio82", 1556 "gpio83", "gpio84"; 1557 function = "qup15"; 1558 }; 1559 }; 1560 1561 qup_uart0_default: qup-uart0-default { 1562 pinmux { 1563 pins = "gpio2", "gpio3"; 1564 function = "qup0"; 1565 }; 1566 }; 1567 1568 qup_uart1_default: qup-uart1-default { 1569 pinmux { 1570 pins = "gpio19", "gpio20"; 1571 function = "qup1"; 1572 }; 1573 }; 1574 1575 qup_uart2_default: qup-uart2-default { 1576 pinmux { 1577 pins = "gpio29", "gpio30"; 1578 function = "qup2"; 1579 }; 1580 }; 1581 1582 qup_uart3_default: qup-uart3-default { 1583 pinmux { 1584 pins = "gpio43", "gpio44"; 1585 function = "qup3"; 1586 }; 1587 }; 1588 1589 qup_uart4_default: qup-uart4-default { 1590 pinmux { 1591 pins = "gpio91", "gpio92"; 1592 function = "qup4"; 1593 }; 1594 }; 1595 1596 qup_uart5_default: qup-uart5-default { 1597 pinmux { 1598 pins = "gpio87", "gpio88"; 1599 function = "qup5"; 1600 }; 1601 }; 1602 1603 qup_uart6_default: qup-uart6-default { 1604 pinmux { 1605 pins = "gpio47", "gpio48"; 1606 function = "qup6"; 1607 }; 1608 }; 1609 1610 qup_uart7_default: qup-uart7-default { 1611 pinmux { 1612 pins = "gpio95", "gpio96"; 1613 function = "qup7"; 1614 }; 1615 }; 1616 1617 qup_uart8_default: qup-uart8-default { 1618 pinmux { 1619 pins = "gpio67", "gpio68"; 1620 function = "qup8"; 1621 }; 1622 }; 1623 1624 qup_uart9_default: qup-uart9-default { 1625 pinmux { 1626 pins = "gpio4", "gpio5"; 1627 function = "qup9"; 1628 }; 1629 }; 1630 1631 qup_uart10_default: qup-uart10-default { 1632 pinmux { 1633 pins = "gpio53", "gpio54"; 1634 function = "qup10"; 1635 }; 1636 }; 1637 1638 qup_uart11_default: qup-uart11-default { 1639 pinmux { 1640 pins = "gpio33", "gpio34"; 1641 function = "qup11"; 1642 }; 1643 }; 1644 1645 qup_uart12_default: qup-uart12-default { 1646 pinmux { 1647 pins = "gpio51", "gpio52"; 1648 function = "qup12"; 1649 }; 1650 }; 1651 1652 qup_uart13_default: qup-uart13-default { 1653 pinmux { 1654 pins = "gpio107", "gpio108"; 1655 function = "qup13"; 1656 }; 1657 }; 1658 1659 qup_uart14_default: qup-uart14-default { 1660 pinmux { 1661 pins = "gpio31", "gpio32"; 1662 function = "qup14"; 1663 }; 1664 }; 1665 1666 qup_uart15_default: qup-uart15-default { 1667 pinmux { 1668 pins = "gpio83", "gpio84"; 1669 function = "qup15"; 1670 }; 1671 }; 1672 }; 1673 1674 gpucc: clock-controller@5090000 { 1675 compatible = "qcom,sdm845-gpucc"; 1676 reg = <0 0x05090000 0 0x9000>; 1677 #clock-cells = <1>; 1678 #reset-cells = <1>; 1679 #power-domain-cells = <1>; 1680 clocks = <&rpmhcc RPMH_CXO_CLK>; 1681 clock-names = "xo"; 1682 }; 1683 1684 sdhc_2: sdhci@8804000 { 1685 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 1686 reg = <0 0x08804000 0 0x1000>; 1687 1688 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1689 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1690 interrupt-names = "hc_irq", "pwr_irq"; 1691 1692 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1693 <&gcc GCC_SDCC2_APPS_CLK>; 1694 clock-names = "iface", "core"; 1695 iommus = <&apps_smmu 0xa0 0xf>; 1696 1697 status = "disabled"; 1698 }; 1699 1700 qspi: spi@88df000 { 1701 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 1702 reg = <0 0x088df000 0 0x600>; 1703 #address-cells = <1>; 1704 #size-cells = <0>; 1705 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1706 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 1707 <&gcc GCC_QSPI_CORE_CLK>; 1708 clock-names = "iface", "core"; 1709 status = "disabled"; 1710 }; 1711 1712 usb_1_hsphy: phy@88e2000 { 1713 compatible = "qcom,sdm845-qusb2-phy"; 1714 reg = <0 0x088e2000 0 0x400>; 1715 status = "disabled"; 1716 #phy-cells = <0>; 1717 1718 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1719 <&rpmhcc RPMH_CXO_CLK>; 1720 clock-names = "cfg_ahb", "ref"; 1721 1722 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1723 1724 nvmem-cells = <&qusb2p_hstx_trim>; 1725 }; 1726 1727 usb_2_hsphy: phy@88e3000 { 1728 compatible = "qcom,sdm845-qusb2-phy"; 1729 reg = <0 0x088e3000 0 0x400>; 1730 status = "disabled"; 1731 #phy-cells = <0>; 1732 1733 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1734 <&rpmhcc RPMH_CXO_CLK>; 1735 clock-names = "cfg_ahb", "ref"; 1736 1737 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1738 1739 nvmem-cells = <&qusb2s_hstx_trim>; 1740 }; 1741 1742 usb_1_qmpphy: phy@88e9000 { 1743 compatible = "qcom,sdm845-qmp-usb3-phy"; 1744 reg = <0 0x088e9000 0 0x18c>, 1745 <0 0x088e8000 0 0x10>; 1746 reg-names = "reg-base", "dp_com"; 1747 status = "disabled"; 1748 #clock-cells = <1>; 1749 #address-cells = <2>; 1750 #size-cells = <2>; 1751 ranges; 1752 1753 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1754 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1755 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 1756 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 1757 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 1758 1759 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 1760 <&gcc GCC_USB3_PHY_PRIM_BCR>; 1761 reset-names = "phy", "common"; 1762 1763 usb_1_ssphy: lanes@88e9200 { 1764 reg = <0 0x088e9200 0 0x128>, 1765 <0 0x088e9400 0 0x200>, 1766 <0 0x088e9c00 0 0x218>, 1767 <0 0x088e9600 0 0x128>, 1768 <0 0x088e9800 0 0x200>, 1769 <0 0x088e9a00 0 0x100>; 1770 #phy-cells = <0>; 1771 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1772 clock-names = "pipe0"; 1773 clock-output-names = "usb3_phy_pipe_clk_src"; 1774 }; 1775 }; 1776 1777 usb_2_qmpphy: phy@88eb000 { 1778 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 1779 reg = <0 0x088eb000 0 0x18c>; 1780 status = "disabled"; 1781 #clock-cells = <1>; 1782 #address-cells = <2>; 1783 #size-cells = <2>; 1784 ranges; 1785 1786 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 1787 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1788 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 1789 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 1790 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 1791 1792 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 1793 <&gcc GCC_USB3_PHY_SEC_BCR>; 1794 reset-names = "phy", "common"; 1795 1796 usb_2_ssphy: lane@88eb200 { 1797 reg = <0 0x088eb200 0 0x128>, 1798 <0 0x088eb400 0 0x1fc>, 1799 <0 0x088eb800 0 0x218>, 1800 <0 0x088eb600 0 0x70>; 1801 #phy-cells = <0>; 1802 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 1803 clock-names = "pipe0"; 1804 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 1805 }; 1806 }; 1807 1808 usb_1: usb@a6f8800 { 1809 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 1810 reg = <0 0x0a6f8800 0 0x400>; 1811 status = "disabled"; 1812 #address-cells = <2>; 1813 #size-cells = <2>; 1814 ranges; 1815 dma-ranges; 1816 1817 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1818 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1819 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1820 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1821 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 1822 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1823 "sleep"; 1824 1825 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1826 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1827 assigned-clock-rates = <19200000>, <150000000>; 1828 1829 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 1833 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1834 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1835 1836 power-domains = <&gcc USB30_PRIM_GDSC>; 1837 1838 resets = <&gcc GCC_USB30_PRIM_BCR>; 1839 1840 usb_1_dwc3: dwc3@a600000 { 1841 compatible = "snps,dwc3"; 1842 reg = <0 0x0a600000 0 0xcd00>; 1843 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1844 iommus = <&apps_smmu 0x740 0>; 1845 snps,dis_u2_susphy_quirk; 1846 snps,dis_enblslpm_quirk; 1847 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1848 phy-names = "usb2-phy", "usb3-phy"; 1849 }; 1850 }; 1851 1852 usb_2: usb@a8f8800 { 1853 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 1854 reg = <0 0x0a8f8800 0 0x400>; 1855 status = "disabled"; 1856 #address-cells = <2>; 1857 #size-cells = <2>; 1858 ranges; 1859 dma-ranges; 1860 1861 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 1862 <&gcc GCC_USB30_SEC_MASTER_CLK>, 1863 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 1864 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1865 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 1866 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1867 "sleep"; 1868 1869 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1870 <&gcc GCC_USB30_SEC_MASTER_CLK>; 1871 assigned-clock-rates = <19200000>, <150000000>; 1872 1873 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 1877 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1878 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1879 1880 power-domains = <&gcc USB30_SEC_GDSC>; 1881 1882 resets = <&gcc GCC_USB30_SEC_BCR>; 1883 1884 usb_2_dwc3: dwc3@a800000 { 1885 compatible = "snps,dwc3"; 1886 reg = <0 0x0a800000 0 0xcd00>; 1887 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1888 iommus = <&apps_smmu 0x760 0>; 1889 snps,dis_u2_susphy_quirk; 1890 snps,dis_enblslpm_quirk; 1891 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 1892 phy-names = "usb2-phy", "usb3-phy"; 1893 }; 1894 }; 1895 1896 videocc: clock-controller@ab00000 { 1897 compatible = "qcom,sdm845-videocc"; 1898 reg = <0 0x0ab00000 0 0x10000>; 1899 #clock-cells = <1>; 1900 #power-domain-cells = <1>; 1901 #reset-cells = <1>; 1902 }; 1903 1904 mdss: mdss@ae00000 { 1905 compatible = "qcom,sdm845-mdss"; 1906 reg = <0 0x0ae00000 0 0x1000>; 1907 reg-names = "mdss"; 1908 1909 power-domains = <&dispcc MDSS_GDSC>; 1910 1911 clocks = <&gcc GCC_DISP_AHB_CLK>, 1912 <&gcc GCC_DISP_AXI_CLK>, 1913 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1914 clock-names = "iface", "bus", "core"; 1915 1916 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 1917 assigned-clock-rates = <300000000>; 1918 1919 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1920 interrupt-controller; 1921 #interrupt-cells = <1>; 1922 1923 iommus = <&apps_smmu 0x880 0x8>, 1924 <&apps_smmu 0xc80 0x8>; 1925 1926 status = "disabled"; 1927 1928 #address-cells = <2>; 1929 #size-cells = <2>; 1930 ranges; 1931 1932 mdss_mdp: mdp@ae01000 { 1933 compatible = "qcom,sdm845-dpu"; 1934 reg = <0 0x0ae01000 0 0x8f000>, 1935 <0 0x0aeb0000 0 0x2008>; 1936 reg-names = "mdp", "vbif"; 1937 1938 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1939 <&dispcc DISP_CC_MDSS_AXI_CLK>, 1940 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1941 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1942 clock-names = "iface", "bus", "core", "vsync"; 1943 1944 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 1945 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1946 assigned-clock-rates = <300000000>, 1947 <19200000>; 1948 1949 interrupt-parent = <&mdss>; 1950 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 1951 1952 status = "disabled"; 1953 1954 ports { 1955 #address-cells = <1>; 1956 #size-cells = <0>; 1957 1958 port@0 { 1959 reg = <0>; 1960 dpu_intf1_out: endpoint { 1961 remote-endpoint = <&dsi0_in>; 1962 }; 1963 }; 1964 1965 port@1 { 1966 reg = <1>; 1967 dpu_intf2_out: endpoint { 1968 remote-endpoint = <&dsi1_in>; 1969 }; 1970 }; 1971 }; 1972 }; 1973 1974 dsi0: dsi@ae94000 { 1975 compatible = "qcom,mdss-dsi-ctrl"; 1976 reg = <0 0x0ae94000 0 0x400>; 1977 reg-names = "dsi_ctrl"; 1978 1979 interrupt-parent = <&mdss>; 1980 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 1981 1982 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1983 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1984 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1985 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1986 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1987 <&dispcc DISP_CC_MDSS_AXI_CLK>; 1988 clock-names = "byte", 1989 "byte_intf", 1990 "pixel", 1991 "core", 1992 "iface", 1993 "bus"; 1994 1995 phys = <&dsi0_phy>; 1996 phy-names = "dsi"; 1997 1998 status = "disabled"; 1999 2000 #address-cells = <1>; 2001 #size-cells = <0>; 2002 2003 ports { 2004 #address-cells = <1>; 2005 #size-cells = <0>; 2006 2007 port@0 { 2008 reg = <0>; 2009 dsi0_in: endpoint { 2010 remote-endpoint = <&dpu_intf1_out>; 2011 }; 2012 }; 2013 2014 port@1 { 2015 reg = <1>; 2016 dsi0_out: endpoint { 2017 }; 2018 }; 2019 }; 2020 }; 2021 2022 dsi0_phy: dsi-phy@ae94400 { 2023 compatible = "qcom,dsi-phy-10nm"; 2024 reg = <0 0x0ae94400 0 0x200>, 2025 <0 0x0ae94600 0 0x280>, 2026 <0 0x0ae94a00 0 0x1e0>; 2027 reg-names = "dsi_phy", 2028 "dsi_phy_lane", 2029 "dsi_pll"; 2030 2031 #clock-cells = <1>; 2032 #phy-cells = <0>; 2033 2034 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2035 <&rpmhcc RPMH_CXO_CLK>; 2036 clock-names = "iface", "ref"; 2037 2038 status = "disabled"; 2039 }; 2040 2041 dsi1: dsi@ae96000 { 2042 compatible = "qcom,mdss-dsi-ctrl"; 2043 reg = <0 0x0ae96000 0 0x400>; 2044 reg-names = "dsi_ctrl"; 2045 2046 interrupt-parent = <&mdss>; 2047 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 2048 2049 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2050 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2051 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2052 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2053 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2054 <&dispcc DISP_CC_MDSS_AXI_CLK>; 2055 clock-names = "byte", 2056 "byte_intf", 2057 "pixel", 2058 "core", 2059 "iface", 2060 "bus"; 2061 2062 phys = <&dsi1_phy>; 2063 phy-names = "dsi"; 2064 2065 status = "disabled"; 2066 2067 #address-cells = <1>; 2068 #size-cells = <0>; 2069 2070 ports { 2071 #address-cells = <1>; 2072 #size-cells = <0>; 2073 2074 port@0 { 2075 reg = <0>; 2076 dsi1_in: endpoint { 2077 remote-endpoint = <&dpu_intf2_out>; 2078 }; 2079 }; 2080 2081 port@1 { 2082 reg = <1>; 2083 dsi1_out: endpoint { 2084 }; 2085 }; 2086 }; 2087 }; 2088 2089 dsi1_phy: dsi-phy@ae96400 { 2090 compatible = "qcom,dsi-phy-10nm"; 2091 reg = <0 0x0ae96400 0 0x200>, 2092 <0 0x0ae96600 0 0x280>, 2093 <0 0x0ae96a00 0 0x10e>; 2094 reg-names = "dsi_phy", 2095 "dsi_phy_lane", 2096 "dsi_pll"; 2097 2098 #clock-cells = <1>; 2099 #phy-cells = <0>; 2100 2101 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2102 <&rpmhcc RPMH_CXO_CLK>; 2103 clock-names = "iface", "ref"; 2104 2105 status = "disabled"; 2106 }; 2107 }; 2108 2109 dispcc: clock-controller@af00000 { 2110 compatible = "qcom,sdm845-dispcc"; 2111 reg = <0 0x0af00000 0 0x10000>; 2112 #clock-cells = <1>; 2113 #reset-cells = <1>; 2114 #power-domain-cells = <1>; 2115 }; 2116 2117 pdc_reset: reset-controller@b2e0000 { 2118 compatible = "qcom,sdm845-pdc-global"; 2119 reg = <0 0x0b2e0000 0 0x20000>; 2120 #reset-cells = <1>; 2121 }; 2122 2123 tsens0: thermal-sensor@c263000 { 2124 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 2125 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2126 <0 0x0c222000 0 0x1ff>; /* SROT */ 2127 #qcom,sensors = <13>; 2128 #thermal-sensor-cells = <1>; 2129 }; 2130 2131 tsens1: thermal-sensor@c265000 { 2132 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 2133 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2134 <0 0x0c223000 0 0x1ff>; /* SROT */ 2135 #qcom,sensors = <8>; 2136 #thermal-sensor-cells = <1>; 2137 }; 2138 2139 aoss_reset: reset-controller@c2a0000 { 2140 compatible = "qcom,sdm845-aoss-cc"; 2141 reg = <0 0x0c2a0000 0 0x31000>; 2142 #reset-cells = <1>; 2143 }; 2144 2145 spmi_bus: spmi@c440000 { 2146 compatible = "qcom,spmi-pmic-arb"; 2147 reg = <0 0x0c440000 0 0x1100>, 2148 <0 0x0c600000 0 0x2000000>, 2149 <0 0x0e600000 0 0x100000>, 2150 <0 0x0e700000 0 0xa0000>, 2151 <0 0x0c40a000 0 0x26000>; 2152 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2153 interrupt-names = "periph_irq"; 2154 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 2155 qcom,ee = <0>; 2156 qcom,channel = <0>; 2157 #address-cells = <2>; 2158 #size-cells = <0>; 2159 interrupt-controller; 2160 #interrupt-cells = <4>; 2161 cell-index = <0>; 2162 }; 2163 2164 apps_smmu: iommu@15000000 { 2165 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; 2166 reg = <0 0x15000000 0 0x80000>; 2167 #iommu-cells = <2>; 2168 #global-interrupts = <1>; 2169 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2170 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2171 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2172 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2173 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2174 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2175 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2176 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2177 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2178 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2179 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2180 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2181 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2182 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2183 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2184 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2185 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2186 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2187 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2188 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2189 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2190 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2191 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2192 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2193 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2194 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2195 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2196 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2197 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2198 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2199 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2200 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2201 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2202 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2203 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2204 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2205 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2206 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2207 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2208 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2209 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2210 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2211 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2212 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2213 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2214 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2215 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2216 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2217 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2218 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2219 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2220 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2221 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2222 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2223 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2224 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2225 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2226 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2227 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2228 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2229 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2230 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2231 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2232 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2233 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 2234 }; 2235 2236 lpasscc: clock-controller@17014000 { 2237 compatible = "qcom,sdm845-lpasscc"; 2238 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; 2239 reg-names = "cc", "qdsp6ss"; 2240 #clock-cells = <1>; 2241 status = "disabled"; 2242 }; 2243 2244 apss_shared: mailbox@17990000 { 2245 compatible = "qcom,sdm845-apss-shared"; 2246 reg = <0 0x17990000 0 0x1000>; 2247 #mbox-cells = <1>; 2248 }; 2249 2250 apps_rsc: rsc@179c0000 { 2251 label = "apps_rsc"; 2252 compatible = "qcom,rpmh-rsc"; 2253 reg = <0 0x179c0000 0 0x10000>, 2254 <0 0x179d0000 0 0x10000>, 2255 <0 0x179e0000 0 0x10000>; 2256 reg-names = "drv-0", "drv-1", "drv-2"; 2257 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2258 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2259 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2260 qcom,tcs-offset = <0xd00>; 2261 qcom,drv-id = <2>; 2262 qcom,tcs-config = <ACTIVE_TCS 2>, 2263 <SLEEP_TCS 3>, 2264 <WAKE_TCS 3>, 2265 <CONTROL_TCS 1>; 2266 2267 rpmhcc: clock-controller { 2268 compatible = "qcom,sdm845-rpmh-clk"; 2269 #clock-cells = <1>; 2270 }; 2271 2272 rpmhpd: power-controller { 2273 compatible = "qcom,sdm845-rpmhpd"; 2274 #power-domain-cells = <1>; 2275 operating-points-v2 = <&rpmhpd_opp_table>; 2276 2277 rpmhpd_opp_table: opp-table { 2278 compatible = "operating-points-v2"; 2279 2280 rpmhpd_opp_ret: opp1 { 2281 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2282 }; 2283 2284 rpmhpd_opp_min_svs: opp2 { 2285 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2286 }; 2287 2288 rpmhpd_opp_low_svs: opp3 { 2289 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2290 }; 2291 2292 rpmhpd_opp_svs: opp4 { 2293 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2294 }; 2295 2296 rpmhpd_opp_svs_l1: opp5 { 2297 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2298 }; 2299 2300 rpmhpd_opp_nom: opp6 { 2301 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2302 }; 2303 2304 rpmhpd_opp_nom_l1: opp7 { 2305 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2306 }; 2307 2308 rpmhpd_opp_nom_l2: opp8 { 2309 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 2310 }; 2311 2312 rpmhpd_opp_turbo: opp9 { 2313 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2314 }; 2315 2316 rpmhpd_opp_turbo_l1: opp10 { 2317 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2318 }; 2319 }; 2320 }; 2321 2322 rsc_hlos: interconnect { 2323 compatible = "qcom,sdm845-rsc-hlos"; 2324 #interconnect-cells = <1>; 2325 }; 2326 }; 2327 2328 intc: interrupt-controller@17a00000 { 2329 compatible = "arm,gic-v3"; 2330 #address-cells = <2>; 2331 #size-cells = <2>; 2332 ranges; 2333 #interrupt-cells = <3>; 2334 interrupt-controller; 2335 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 2336 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 2337 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2338 2339 gic-its@17a40000 { 2340 compatible = "arm,gic-v3-its"; 2341 msi-controller; 2342 #msi-cells = <1>; 2343 reg = <0 0x17a40000 0 0x20000>; 2344 status = "disabled"; 2345 }; 2346 }; 2347 2348 timer@17c90000 { 2349 #address-cells = <2>; 2350 #size-cells = <2>; 2351 ranges; 2352 compatible = "arm,armv7-timer-mem"; 2353 reg = <0 0x17c90000 0 0x1000>; 2354 2355 frame@17ca0000 { 2356 frame-number = <0>; 2357 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 2358 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2359 reg = <0 0x17ca0000 0 0x1000>, 2360 <0 0x17cb0000 0 0x1000>; 2361 }; 2362 2363 frame@17cc0000 { 2364 frame-number = <1>; 2365 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 2366 reg = <0 0x17cc0000 0 0x1000>; 2367 status = "disabled"; 2368 }; 2369 2370 frame@17cd0000 { 2371 frame-number = <2>; 2372 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2373 reg = <0 0x17cd0000 0 0x1000>; 2374 status = "disabled"; 2375 }; 2376 2377 frame@17ce0000 { 2378 frame-number = <3>; 2379 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2380 reg = <0 0x17ce0000 0 0x1000>; 2381 status = "disabled"; 2382 }; 2383 2384 frame@17cf0000 { 2385 frame-number = <4>; 2386 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2387 reg = <0 0x17cf0000 0 0x1000>; 2388 status = "disabled"; 2389 }; 2390 2391 frame@17d00000 { 2392 frame-number = <5>; 2393 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2394 reg = <0 0x17d00000 0 0x1000>; 2395 status = "disabled"; 2396 }; 2397 2398 frame@17d10000 { 2399 frame-number = <6>; 2400 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2401 reg = <0 0x17d10000 0 0x1000>; 2402 status = "disabled"; 2403 }; 2404 }; 2405 2406 cpufreq_hw: cpufreq@17d43000 { 2407 compatible = "qcom,cpufreq-hw"; 2408 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 2409 reg-names = "freq-domain0", "freq-domain1"; 2410 2411 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2412 clock-names = "xo", "alternate"; 2413 2414 #freq-domain-cells = <1>; 2415 }; 2416 2417 wifi: wifi@18800000 { 2418 compatible = "qcom,wcn3990-wifi"; 2419 status = "disabled"; 2420 reg = <0 0x18800000 0 0x800000>; 2421 reg-names = "membase"; 2422 memory-region = <&wlan_msa_mem>; 2423 clock-names = "cxo_ref_clk_pin"; 2424 clocks = <&rpmhcc RPMH_RF_CLK2>; 2425 interrupts = 2426 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2427 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2428 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2429 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2430 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2431 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 2432 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2433 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2434 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2435 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2436 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2437 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2438 iommus = <&apps_smmu 0x0040 0x1>; 2439 }; 2440 }; 2441 2442 thermal-zones { 2443 cpu0-thermal { 2444 polling-delay-passive = <250>; 2445 polling-delay = <1000>; 2446 2447 thermal-sensors = <&tsens0 1>; 2448 2449 trips { 2450 cpu0_alert0: trip-point@0 { 2451 temperature = <90000>; 2452 hysteresis = <2000>; 2453 type = "passive"; 2454 }; 2455 2456 cpu0_alert1: trip-point@1 { 2457 temperature = <95000>; 2458 hysteresis = <2000>; 2459 type = "passive"; 2460 }; 2461 2462 cpu0_crit: cpu_crit { 2463 temperature = <110000>; 2464 hysteresis = <1000>; 2465 type = "critical"; 2466 }; 2467 }; 2468 2469 cooling-maps { 2470 map0 { 2471 trip = <&cpu0_alert0>; 2472 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2473 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2474 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2475 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2476 }; 2477 map1 { 2478 trip = <&cpu0_alert1>; 2479 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2480 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2481 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2482 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2483 }; 2484 }; 2485 }; 2486 2487 cpu1-thermal { 2488 polling-delay-passive = <250>; 2489 polling-delay = <1000>; 2490 2491 thermal-sensors = <&tsens0 2>; 2492 2493 trips { 2494 cpu1_alert0: trip-point@0 { 2495 temperature = <90000>; 2496 hysteresis = <2000>; 2497 type = "passive"; 2498 }; 2499 2500 cpu1_alert1: trip-point@1 { 2501 temperature = <95000>; 2502 hysteresis = <2000>; 2503 type = "passive"; 2504 }; 2505 2506 cpu1_crit: cpu_crit { 2507 temperature = <110000>; 2508 hysteresis = <1000>; 2509 type = "critical"; 2510 }; 2511 }; 2512 2513 cooling-maps { 2514 map0 { 2515 trip = <&cpu1_alert0>; 2516 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2517 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2518 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2519 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2520 }; 2521 map1 { 2522 trip = <&cpu1_alert1>; 2523 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2524 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2525 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2526 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2527 }; 2528 }; 2529 }; 2530 2531 cpu2-thermal { 2532 polling-delay-passive = <250>; 2533 polling-delay = <1000>; 2534 2535 thermal-sensors = <&tsens0 3>; 2536 2537 trips { 2538 cpu2_alert0: trip-point@0 { 2539 temperature = <90000>; 2540 hysteresis = <2000>; 2541 type = "passive"; 2542 }; 2543 2544 cpu2_alert1: trip-point@1 { 2545 temperature = <95000>; 2546 hysteresis = <2000>; 2547 type = "passive"; 2548 }; 2549 2550 cpu2_crit: cpu_crit { 2551 temperature = <110000>; 2552 hysteresis = <1000>; 2553 type = "critical"; 2554 }; 2555 }; 2556 2557 cooling-maps { 2558 map0 { 2559 trip = <&cpu2_alert0>; 2560 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2561 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2562 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2563 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2564 }; 2565 map1 { 2566 trip = <&cpu2_alert1>; 2567 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2568 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2569 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2570 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2571 }; 2572 }; 2573 }; 2574 2575 cpu3-thermal { 2576 polling-delay-passive = <250>; 2577 polling-delay = <1000>; 2578 2579 thermal-sensors = <&tsens0 4>; 2580 2581 trips { 2582 cpu3_alert0: trip-point@0 { 2583 temperature = <90000>; 2584 hysteresis = <2000>; 2585 type = "passive"; 2586 }; 2587 2588 cpu3_alert1: trip-point@1 { 2589 temperature = <95000>; 2590 hysteresis = <2000>; 2591 type = "passive"; 2592 }; 2593 2594 cpu3_crit: cpu_crit { 2595 temperature = <110000>; 2596 hysteresis = <1000>; 2597 type = "critical"; 2598 }; 2599 }; 2600 2601 cooling-maps { 2602 map0 { 2603 trip = <&cpu3_alert0>; 2604 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2605 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2606 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2607 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2608 }; 2609 map1 { 2610 trip = <&cpu3_alert1>; 2611 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2612 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2613 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2614 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2615 }; 2616 }; 2617 }; 2618 2619 cpu4-thermal { 2620 polling-delay-passive = <250>; 2621 polling-delay = <1000>; 2622 2623 thermal-sensors = <&tsens0 7>; 2624 2625 trips { 2626 cpu4_alert0: trip-point@0 { 2627 temperature = <90000>; 2628 hysteresis = <2000>; 2629 type = "passive"; 2630 }; 2631 2632 cpu4_alert1: trip-point@1 { 2633 temperature = <95000>; 2634 hysteresis = <2000>; 2635 type = "passive"; 2636 }; 2637 2638 cpu4_crit: cpu_crit { 2639 temperature = <110000>; 2640 hysteresis = <1000>; 2641 type = "critical"; 2642 }; 2643 }; 2644 2645 cooling-maps { 2646 map0 { 2647 trip = <&cpu4_alert0>; 2648 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2649 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2650 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2651 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2652 }; 2653 map1 { 2654 trip = <&cpu4_alert1>; 2655 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2656 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2657 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2658 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2659 }; 2660 }; 2661 }; 2662 2663 cpu5-thermal { 2664 polling-delay-passive = <250>; 2665 polling-delay = <1000>; 2666 2667 thermal-sensors = <&tsens0 8>; 2668 2669 trips { 2670 cpu5_alert0: trip-point@0 { 2671 temperature = <90000>; 2672 hysteresis = <2000>; 2673 type = "passive"; 2674 }; 2675 2676 cpu5_alert1: trip-point@1 { 2677 temperature = <95000>; 2678 hysteresis = <2000>; 2679 type = "passive"; 2680 }; 2681 2682 cpu5_crit: cpu_crit { 2683 temperature = <110000>; 2684 hysteresis = <1000>; 2685 type = "critical"; 2686 }; 2687 }; 2688 2689 cooling-maps { 2690 map0 { 2691 trip = <&cpu5_alert0>; 2692 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2693 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2694 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2695 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2696 }; 2697 map1 { 2698 trip = <&cpu5_alert1>; 2699 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2700 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2701 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2702 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2703 }; 2704 }; 2705 }; 2706 2707 cpu6-thermal { 2708 polling-delay-passive = <250>; 2709 polling-delay = <1000>; 2710 2711 thermal-sensors = <&tsens0 9>; 2712 2713 trips { 2714 cpu6_alert0: trip-point@0 { 2715 temperature = <90000>; 2716 hysteresis = <2000>; 2717 type = "passive"; 2718 }; 2719 2720 cpu6_alert1: trip-point@1 { 2721 temperature = <95000>; 2722 hysteresis = <2000>; 2723 type = "passive"; 2724 }; 2725 2726 cpu6_crit: cpu_crit { 2727 temperature = <110000>; 2728 hysteresis = <1000>; 2729 type = "critical"; 2730 }; 2731 }; 2732 2733 cooling-maps { 2734 map0 { 2735 trip = <&cpu6_alert0>; 2736 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2737 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2738 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2739 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2740 }; 2741 map1 { 2742 trip = <&cpu6_alert1>; 2743 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2744 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2745 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2746 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2747 }; 2748 }; 2749 }; 2750 2751 cpu7-thermal { 2752 polling-delay-passive = <250>; 2753 polling-delay = <1000>; 2754 2755 thermal-sensors = <&tsens0 10>; 2756 2757 trips { 2758 cpu7_alert0: trip-point@0 { 2759 temperature = <90000>; 2760 hysteresis = <2000>; 2761 type = "passive"; 2762 }; 2763 2764 cpu7_alert1: trip-point@1 { 2765 temperature = <95000>; 2766 hysteresis = <2000>; 2767 type = "passive"; 2768 }; 2769 2770 cpu7_crit: cpu_crit { 2771 temperature = <110000>; 2772 hysteresis = <1000>; 2773 type = "critical"; 2774 }; 2775 }; 2776 2777 cooling-maps { 2778 map0 { 2779 trip = <&cpu7_alert0>; 2780 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2781 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2782 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2783 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2784 }; 2785 map1 { 2786 trip = <&cpu7_alert1>; 2787 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2788 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2789 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2790 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2791 }; 2792 }; 2793 }; 2794 2795 aoss0-thermal { 2796 polling-delay-passive = <250>; 2797 polling-delay = <1000>; 2798 2799 thermal-sensors = <&tsens0 0>; 2800 2801 trips { 2802 aoss0_alert0: trip-point@0 { 2803 temperature = <90000>; 2804 hysteresis = <2000>; 2805 type = "hot"; 2806 }; 2807 }; 2808 }; 2809 2810 cluster0-thermal { 2811 polling-delay-passive = <250>; 2812 polling-delay = <1000>; 2813 2814 thermal-sensors = <&tsens0 5>; 2815 2816 trips { 2817 cluster0_alert0: trip-point@0 { 2818 temperature = <90000>; 2819 hysteresis = <2000>; 2820 type = "hot"; 2821 }; 2822 cluster0_crit: cluster0_crit { 2823 temperature = <110000>; 2824 hysteresis = <2000>; 2825 type = "critical"; 2826 }; 2827 }; 2828 }; 2829 2830 cluster1-thermal { 2831 polling-delay-passive = <250>; 2832 polling-delay = <1000>; 2833 2834 thermal-sensors = <&tsens0 6>; 2835 2836 trips { 2837 cluster1_alert0: trip-point@0 { 2838 temperature = <90000>; 2839 hysteresis = <2000>; 2840 type = "hot"; 2841 }; 2842 cluster1_crit: cluster1_crit { 2843 temperature = <110000>; 2844 hysteresis = <2000>; 2845 type = "critical"; 2846 }; 2847 }; 2848 }; 2849 2850 gpu-thermal-top { 2851 polling-delay-passive = <250>; 2852 polling-delay = <1000>; 2853 2854 thermal-sensors = <&tsens0 11>; 2855 2856 trips { 2857 gpu1_alert0: trip-point@0 { 2858 temperature = <90000>; 2859 hysteresis = <2000>; 2860 type = "hot"; 2861 }; 2862 }; 2863 }; 2864 2865 gpu-thermal-bottom { 2866 polling-delay-passive = <250>; 2867 polling-delay = <1000>; 2868 2869 thermal-sensors = <&tsens0 12>; 2870 2871 trips { 2872 gpu2_alert0: trip-point@0 { 2873 temperature = <90000>; 2874 hysteresis = <2000>; 2875 type = "hot"; 2876 }; 2877 }; 2878 }; 2879 2880 aoss1-thermal { 2881 polling-delay-passive = <250>; 2882 polling-delay = <1000>; 2883 2884 thermal-sensors = <&tsens1 0>; 2885 2886 trips { 2887 aoss1_alert0: trip-point@0 { 2888 temperature = <90000>; 2889 hysteresis = <2000>; 2890 type = "hot"; 2891 }; 2892 }; 2893 }; 2894 2895 q6-modem-thermal { 2896 polling-delay-passive = <250>; 2897 polling-delay = <1000>; 2898 2899 thermal-sensors = <&tsens1 1>; 2900 2901 trips { 2902 q6_modem_alert0: trip-point@0 { 2903 temperature = <90000>; 2904 hysteresis = <2000>; 2905 type = "hot"; 2906 }; 2907 }; 2908 }; 2909 2910 mem-thermal { 2911 polling-delay-passive = <250>; 2912 polling-delay = <1000>; 2913 2914 thermal-sensors = <&tsens1 2>; 2915 2916 trips { 2917 mem_alert0: trip-point@0 { 2918 temperature = <90000>; 2919 hysteresis = <2000>; 2920 type = "hot"; 2921 }; 2922 }; 2923 }; 2924 2925 wlan-thermal { 2926 polling-delay-passive = <250>; 2927 polling-delay = <1000>; 2928 2929 thermal-sensors = <&tsens1 3>; 2930 2931 trips { 2932 wlan_alert0: trip-point@0 { 2933 temperature = <90000>; 2934 hysteresis = <2000>; 2935 type = "hot"; 2936 }; 2937 }; 2938 }; 2939 2940 q6-hvx-thermal { 2941 polling-delay-passive = <250>; 2942 polling-delay = <1000>; 2943 2944 thermal-sensors = <&tsens1 4>; 2945 2946 trips { 2947 q6_hvx_alert0: trip-point@0 { 2948 temperature = <90000>; 2949 hysteresis = <2000>; 2950 type = "hot"; 2951 }; 2952 }; 2953 }; 2954 2955 camera-thermal { 2956 polling-delay-passive = <250>; 2957 polling-delay = <1000>; 2958 2959 thermal-sensors = <&tsens1 5>; 2960 2961 trips { 2962 camera_alert0: trip-point@0 { 2963 temperature = <90000>; 2964 hysteresis = <2000>; 2965 type = "hot"; 2966 }; 2967 }; 2968 }; 2969 2970 video-thermal { 2971 polling-delay-passive = <250>; 2972 polling-delay = <1000>; 2973 2974 thermal-sensors = <&tsens1 6>; 2975 2976 trips { 2977 video_alert0: trip-point@0 { 2978 temperature = <90000>; 2979 hysteresis = <2000>; 2980 type = "hot"; 2981 }; 2982 }; 2983 }; 2984 2985 modem-thermal { 2986 polling-delay-passive = <250>; 2987 polling-delay = <1000>; 2988 2989 thermal-sensors = <&tsens1 7>; 2990 2991 trips { 2992 modem_alert0: trip-point@0 { 2993 temperature = <90000>; 2994 hysteresis = <2000>; 2995 type = "hot"; 2996 }; 2997 }; 2998 }; 2999 }; 3000}; 3001