1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 9#include <dt-bindings/clock/qcom,gcc-sdm845.h> 10#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 11#include <dt-bindings/clock/qcom,lpass-sdm845.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/clock/qcom,videocc-sdm845.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/phy/phy-qcom-qusb2.h> 16#include <dt-bindings/reset/qcom,sdm845-aoss.h> 17#include <dt-bindings/reset/qcom,sdm845-pdc.h> 18#include <dt-bindings/soc/qcom,rpmh-rsc.h> 19#include <dt-bindings/clock/qcom,gcc-sdm845.h> 20#include <dt-bindings/thermal/thermal.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 aliases { 29 i2c0 = &i2c0; 30 i2c1 = &i2c1; 31 i2c2 = &i2c2; 32 i2c3 = &i2c3; 33 i2c4 = &i2c4; 34 i2c5 = &i2c5; 35 i2c6 = &i2c6; 36 i2c7 = &i2c7; 37 i2c8 = &i2c8; 38 i2c9 = &i2c9; 39 i2c10 = &i2c10; 40 i2c11 = &i2c11; 41 i2c12 = &i2c12; 42 i2c13 = &i2c13; 43 i2c14 = &i2c14; 44 i2c15 = &i2c15; 45 spi0 = &spi0; 46 spi1 = &spi1; 47 spi2 = &spi2; 48 spi3 = &spi3; 49 spi4 = &spi4; 50 spi5 = &spi5; 51 spi6 = &spi6; 52 spi7 = &spi7; 53 spi8 = &spi8; 54 spi9 = &spi9; 55 spi10 = &spi10; 56 spi11 = &spi11; 57 spi12 = &spi12; 58 spi13 = &spi13; 59 spi14 = &spi14; 60 spi15 = &spi15; 61 }; 62 63 chosen { }; 64 65 memory@80000000 { 66 device_type = "memory"; 67 /* We expect the bootloader to fill in the size */ 68 reg = <0 0x80000000 0 0>; 69 }; 70 71 reserved-memory { 72 #address-cells = <2>; 73 #size-cells = <2>; 74 ranges; 75 76 memory@85fc0000 { 77 reg = <0 0x85fc0000 0 0x20000>; 78 no-map; 79 }; 80 81 memory@85fe0000 { 82 compatible = "qcom,cmd-db"; 83 reg = <0x0 0x85fe0000 0x0 0x20000>; 84 no-map; 85 }; 86 87 smem_mem: memory@86000000 { 88 reg = <0x0 0x86000000 0x0 0x200000>; 89 no-map; 90 }; 91 92 memory@86200000 { 93 reg = <0 0x86200000 0 0x2d00000>; 94 no-map; 95 }; 96 97 wlan_msa_mem: memory@96700000 { 98 reg = <0 0x96700000 0 0x100000>; 99 no-map; 100 }; 101 102 mpss_region: memory@8e000000 { 103 reg = <0 0x8e000000 0 0x7800000>; 104 no-map; 105 }; 106 107 mba_region: memory@96500000 { 108 reg = <0 0x96500000 0 0x200000>; 109 no-map; 110 }; 111 }; 112 113 cpus { 114 #address-cells = <2>; 115 #size-cells = <0>; 116 117 CPU0: cpu@0 { 118 device_type = "cpu"; 119 compatible = "qcom,kryo385"; 120 reg = <0x0 0x0>; 121 enable-method = "psci"; 122 qcom,freq-domain = <&cpufreq_hw 0>; 123 #cooling-cells = <2>; 124 next-level-cache = <&L2_0>; 125 L2_0: l2-cache { 126 compatible = "cache"; 127 next-level-cache = <&L3_0>; 128 L3_0: l3-cache { 129 compatible = "cache"; 130 }; 131 }; 132 }; 133 134 CPU1: cpu@100 { 135 device_type = "cpu"; 136 compatible = "qcom,kryo385"; 137 reg = <0x0 0x100>; 138 enable-method = "psci"; 139 qcom,freq-domain = <&cpufreq_hw 0>; 140 #cooling-cells = <2>; 141 next-level-cache = <&L2_100>; 142 L2_100: l2-cache { 143 compatible = "cache"; 144 next-level-cache = <&L3_0>; 145 }; 146 }; 147 148 CPU2: cpu@200 { 149 device_type = "cpu"; 150 compatible = "qcom,kryo385"; 151 reg = <0x0 0x200>; 152 enable-method = "psci"; 153 qcom,freq-domain = <&cpufreq_hw 0>; 154 #cooling-cells = <2>; 155 next-level-cache = <&L2_200>; 156 L2_200: l2-cache { 157 compatible = "cache"; 158 next-level-cache = <&L3_0>; 159 }; 160 }; 161 162 CPU3: cpu@300 { 163 device_type = "cpu"; 164 compatible = "qcom,kryo385"; 165 reg = <0x0 0x300>; 166 enable-method = "psci"; 167 qcom,freq-domain = <&cpufreq_hw 0>; 168 #cooling-cells = <2>; 169 next-level-cache = <&L2_300>; 170 L2_300: l2-cache { 171 compatible = "cache"; 172 next-level-cache = <&L3_0>; 173 }; 174 }; 175 176 CPU4: cpu@400 { 177 device_type = "cpu"; 178 compatible = "qcom,kryo385"; 179 reg = <0x0 0x400>; 180 enable-method = "psci"; 181 qcom,freq-domain = <&cpufreq_hw 1>; 182 #cooling-cells = <2>; 183 next-level-cache = <&L2_400>; 184 L2_400: l2-cache { 185 compatible = "cache"; 186 next-level-cache = <&L3_0>; 187 }; 188 }; 189 190 CPU5: cpu@500 { 191 device_type = "cpu"; 192 compatible = "qcom,kryo385"; 193 reg = <0x0 0x500>; 194 enable-method = "psci"; 195 qcom,freq-domain = <&cpufreq_hw 1>; 196 #cooling-cells = <2>; 197 next-level-cache = <&L2_500>; 198 L2_500: l2-cache { 199 compatible = "cache"; 200 next-level-cache = <&L3_0>; 201 }; 202 }; 203 204 CPU6: cpu@600 { 205 device_type = "cpu"; 206 compatible = "qcom,kryo385"; 207 reg = <0x0 0x600>; 208 enable-method = "psci"; 209 qcom,freq-domain = <&cpufreq_hw 1>; 210 #cooling-cells = <2>; 211 next-level-cache = <&L2_600>; 212 L2_600: l2-cache { 213 compatible = "cache"; 214 next-level-cache = <&L3_0>; 215 }; 216 }; 217 218 CPU7: cpu@700 { 219 device_type = "cpu"; 220 compatible = "qcom,kryo385"; 221 reg = <0x0 0x700>; 222 enable-method = "psci"; 223 qcom,freq-domain = <&cpufreq_hw 1>; 224 #cooling-cells = <2>; 225 next-level-cache = <&L2_700>; 226 L2_700: l2-cache { 227 compatible = "cache"; 228 next-level-cache = <&L3_0>; 229 }; 230 }; 231 }; 232 233 pmu { 234 compatible = "arm,armv8-pmuv3"; 235 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 236 }; 237 238 timer { 239 compatible = "arm,armv8-timer"; 240 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 241 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 242 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 243 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 244 }; 245 246 clocks { 247 xo_board: xo-board { 248 compatible = "fixed-clock"; 249 #clock-cells = <0>; 250 clock-frequency = <38400000>; 251 clock-output-names = "xo_board"; 252 }; 253 254 sleep_clk: sleep-clk { 255 compatible = "fixed-clock"; 256 #clock-cells = <0>; 257 clock-frequency = <32764>; 258 }; 259 }; 260 261 firmware { 262 scm { 263 compatible = "qcom,scm-sdm845", "qcom,scm"; 264 }; 265 }; 266 267 tcsr_mutex: hwlock { 268 compatible = "qcom,tcsr-mutex"; 269 syscon = <&tcsr_mutex_regs 0 0x1000>; 270 #hwlock-cells = <1>; 271 }; 272 273 smem { 274 compatible = "qcom,smem"; 275 memory-region = <&smem_mem>; 276 hwlocks = <&tcsr_mutex 3>; 277 }; 278 279 smp2p-cdsp { 280 compatible = "qcom,smp2p"; 281 qcom,smem = <94>, <432>; 282 283 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 284 285 mboxes = <&apss_shared 6>; 286 287 qcom,local-pid = <0>; 288 qcom,remote-pid = <5>; 289 290 cdsp_smp2p_out: master-kernel { 291 qcom,entry-name = "master-kernel"; 292 #qcom,smem-state-cells = <1>; 293 }; 294 295 cdsp_smp2p_in: slave-kernel { 296 qcom,entry-name = "slave-kernel"; 297 298 interrupt-controller; 299 #interrupt-cells = <2>; 300 }; 301 }; 302 303 smp2p-lpass { 304 compatible = "qcom,smp2p"; 305 qcom,smem = <443>, <429>; 306 307 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 308 309 mboxes = <&apss_shared 10>; 310 311 qcom,local-pid = <0>; 312 qcom,remote-pid = <2>; 313 314 adsp_smp2p_out: master-kernel { 315 qcom,entry-name = "master-kernel"; 316 #qcom,smem-state-cells = <1>; 317 }; 318 319 adsp_smp2p_in: slave-kernel { 320 qcom,entry-name = "slave-kernel"; 321 322 interrupt-controller; 323 #interrupt-cells = <2>; 324 }; 325 }; 326 327 smp2p-mpss { 328 compatible = "qcom,smp2p"; 329 qcom,smem = <435>, <428>; 330 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 331 mboxes = <&apss_shared 14>; 332 qcom,local-pid = <0>; 333 qcom,remote-pid = <1>; 334 335 modem_smp2p_out: master-kernel { 336 qcom,entry-name = "master-kernel"; 337 #qcom,smem-state-cells = <1>; 338 }; 339 340 modem_smp2p_in: slave-kernel { 341 qcom,entry-name = "slave-kernel"; 342 interrupt-controller; 343 #interrupt-cells = <2>; 344 }; 345 }; 346 347 smp2p-slpi { 348 compatible = "qcom,smp2p"; 349 qcom,smem = <481>, <430>; 350 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 351 mboxes = <&apss_shared 26>; 352 qcom,local-pid = <0>; 353 qcom,remote-pid = <3>; 354 355 slpi_smp2p_out: master-kernel { 356 qcom,entry-name = "master-kernel"; 357 #qcom,smem-state-cells = <1>; 358 }; 359 360 slpi_smp2p_in: slave-kernel { 361 qcom,entry-name = "slave-kernel"; 362 interrupt-controller; 363 #interrupt-cells = <2>; 364 }; 365 }; 366 367 psci { 368 compatible = "arm,psci-1.0"; 369 method = "smc"; 370 }; 371 372 soc: soc { 373 #address-cells = <2>; 374 #size-cells = <2>; 375 ranges = <0 0 0 0 0x10 0>; 376 dma-ranges = <0 0 0 0 0x10 0>; 377 compatible = "simple-bus"; 378 379 gcc: clock-controller@100000 { 380 compatible = "qcom,gcc-sdm845"; 381 reg = <0 0x00100000 0 0x1f0000>; 382 #clock-cells = <1>; 383 #reset-cells = <1>; 384 #power-domain-cells = <1>; 385 }; 386 387 qfprom@784000 { 388 compatible = "qcom,qfprom"; 389 reg = <0 0x00784000 0 0x8ff>; 390 #address-cells = <1>; 391 #size-cells = <1>; 392 393 qusb2p_hstx_trim: hstx-trim-primary@1eb { 394 reg = <0x1eb 0x1>; 395 bits = <1 4>; 396 }; 397 398 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 399 reg = <0x1eb 0x2>; 400 bits = <6 4>; 401 }; 402 }; 403 404 rng: rng@793000 { 405 compatible = "qcom,prng-ee"; 406 reg = <0 0x00793000 0 0x1000>; 407 clocks = <&gcc GCC_PRNG_AHB_CLK>; 408 clock-names = "core"; 409 }; 410 411 qupv3_id_0: geniqup@8c0000 { 412 compatible = "qcom,geni-se-qup"; 413 reg = <0 0x008c0000 0 0x6000>; 414 clock-names = "m-ahb", "s-ahb"; 415 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 416 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 417 #address-cells = <2>; 418 #size-cells = <2>; 419 ranges; 420 status = "disabled"; 421 422 i2c0: i2c@880000 { 423 compatible = "qcom,geni-i2c"; 424 reg = <0 0x00880000 0 0x4000>; 425 clock-names = "se"; 426 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 427 pinctrl-names = "default"; 428 pinctrl-0 = <&qup_i2c0_default>; 429 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 430 #address-cells = <1>; 431 #size-cells = <0>; 432 status = "disabled"; 433 }; 434 435 spi0: spi@880000 { 436 compatible = "qcom,geni-spi"; 437 reg = <0 0x00880000 0 0x4000>; 438 clock-names = "se"; 439 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 440 pinctrl-names = "default"; 441 pinctrl-0 = <&qup_spi0_default>; 442 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 status = "disabled"; 446 }; 447 448 uart0: serial@880000 { 449 compatible = "qcom,geni-uart"; 450 reg = <0 0x00880000 0 0x4000>; 451 clock-names = "se"; 452 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 453 pinctrl-names = "default"; 454 pinctrl-0 = <&qup_uart0_default>; 455 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 456 status = "disabled"; 457 }; 458 459 i2c1: i2c@884000 { 460 compatible = "qcom,geni-i2c"; 461 reg = <0 0x00884000 0 0x4000>; 462 clock-names = "se"; 463 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 464 pinctrl-names = "default"; 465 pinctrl-0 = <&qup_i2c1_default>; 466 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 status = "disabled"; 470 }; 471 472 spi1: spi@884000 { 473 compatible = "qcom,geni-spi"; 474 reg = <0 0x00884000 0 0x4000>; 475 clock-names = "se"; 476 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 477 pinctrl-names = "default"; 478 pinctrl-0 = <&qup_spi1_default>; 479 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 480 #address-cells = <1>; 481 #size-cells = <0>; 482 status = "disabled"; 483 }; 484 485 uart1: serial@884000 { 486 compatible = "qcom,geni-uart"; 487 reg = <0 0x00884000 0 0x4000>; 488 clock-names = "se"; 489 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 490 pinctrl-names = "default"; 491 pinctrl-0 = <&qup_uart1_default>; 492 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 493 status = "disabled"; 494 }; 495 496 i2c2: i2c@888000 { 497 compatible = "qcom,geni-i2c"; 498 reg = <0 0x00888000 0 0x4000>; 499 clock-names = "se"; 500 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 501 pinctrl-names = "default"; 502 pinctrl-0 = <&qup_i2c2_default>; 503 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 status = "disabled"; 507 }; 508 509 spi2: spi@888000 { 510 compatible = "qcom,geni-spi"; 511 reg = <0 0x00888000 0 0x4000>; 512 clock-names = "se"; 513 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 514 pinctrl-names = "default"; 515 pinctrl-0 = <&qup_spi2_default>; 516 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 status = "disabled"; 520 }; 521 522 uart2: serial@888000 { 523 compatible = "qcom,geni-uart"; 524 reg = <0 0x00888000 0 0x4000>; 525 clock-names = "se"; 526 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 527 pinctrl-names = "default"; 528 pinctrl-0 = <&qup_uart2_default>; 529 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 530 status = "disabled"; 531 }; 532 533 i2c3: i2c@88c000 { 534 compatible = "qcom,geni-i2c"; 535 reg = <0 0x0088c000 0 0x4000>; 536 clock-names = "se"; 537 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 538 pinctrl-names = "default"; 539 pinctrl-0 = <&qup_i2c3_default>; 540 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 541 #address-cells = <1>; 542 #size-cells = <0>; 543 status = "disabled"; 544 }; 545 546 spi3: spi@88c000 { 547 compatible = "qcom,geni-spi"; 548 reg = <0 0x0088c000 0 0x4000>; 549 clock-names = "se"; 550 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 551 pinctrl-names = "default"; 552 pinctrl-0 = <&qup_spi3_default>; 553 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 status = "disabled"; 557 }; 558 559 uart3: serial@88c000 { 560 compatible = "qcom,geni-uart"; 561 reg = <0 0x0088c000 0 0x4000>; 562 clock-names = "se"; 563 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 564 pinctrl-names = "default"; 565 pinctrl-0 = <&qup_uart3_default>; 566 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 567 status = "disabled"; 568 }; 569 570 i2c4: i2c@890000 { 571 compatible = "qcom,geni-i2c"; 572 reg = <0 0x00890000 0 0x4000>; 573 clock-names = "se"; 574 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 575 pinctrl-names = "default"; 576 pinctrl-0 = <&qup_i2c4_default>; 577 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 578 #address-cells = <1>; 579 #size-cells = <0>; 580 status = "disabled"; 581 }; 582 583 spi4: spi@890000 { 584 compatible = "qcom,geni-spi"; 585 reg = <0 0x00890000 0 0x4000>; 586 clock-names = "se"; 587 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 588 pinctrl-names = "default"; 589 pinctrl-0 = <&qup_spi4_default>; 590 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 status = "disabled"; 594 }; 595 596 uart4: serial@890000 { 597 compatible = "qcom,geni-uart"; 598 reg = <0 0x00890000 0 0x4000>; 599 clock-names = "se"; 600 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 601 pinctrl-names = "default"; 602 pinctrl-0 = <&qup_uart4_default>; 603 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 604 status = "disabled"; 605 }; 606 607 i2c5: i2c@894000 { 608 compatible = "qcom,geni-i2c"; 609 reg = <0 0x00894000 0 0x4000>; 610 clock-names = "se"; 611 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 612 pinctrl-names = "default"; 613 pinctrl-0 = <&qup_i2c5_default>; 614 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 615 #address-cells = <1>; 616 #size-cells = <0>; 617 status = "disabled"; 618 }; 619 620 spi5: spi@894000 { 621 compatible = "qcom,geni-spi"; 622 reg = <0 0x00894000 0 0x4000>; 623 clock-names = "se"; 624 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 625 pinctrl-names = "default"; 626 pinctrl-0 = <&qup_spi5_default>; 627 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 628 #address-cells = <1>; 629 #size-cells = <0>; 630 status = "disabled"; 631 }; 632 633 uart5: serial@894000 { 634 compatible = "qcom,geni-uart"; 635 reg = <0 0x00894000 0 0x4000>; 636 clock-names = "se"; 637 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 638 pinctrl-names = "default"; 639 pinctrl-0 = <&qup_uart5_default>; 640 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 641 status = "disabled"; 642 }; 643 644 i2c6: i2c@898000 { 645 compatible = "qcom,geni-i2c"; 646 reg = <0 0x00898000 0 0x4000>; 647 clock-names = "se"; 648 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 649 pinctrl-names = "default"; 650 pinctrl-0 = <&qup_i2c6_default>; 651 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 652 #address-cells = <1>; 653 #size-cells = <0>; 654 status = "disabled"; 655 }; 656 657 spi6: spi@898000 { 658 compatible = "qcom,geni-spi"; 659 reg = <0 0x00898000 0 0x4000>; 660 clock-names = "se"; 661 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 662 pinctrl-names = "default"; 663 pinctrl-0 = <&qup_spi6_default>; 664 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 665 #address-cells = <1>; 666 #size-cells = <0>; 667 status = "disabled"; 668 }; 669 670 uart6: serial@898000 { 671 compatible = "qcom,geni-uart"; 672 reg = <0 0x00898000 0 0x4000>; 673 clock-names = "se"; 674 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 675 pinctrl-names = "default"; 676 pinctrl-0 = <&qup_uart6_default>; 677 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 678 status = "disabled"; 679 }; 680 681 i2c7: i2c@89c000 { 682 compatible = "qcom,geni-i2c"; 683 reg = <0 0x0089c000 0 0x4000>; 684 clock-names = "se"; 685 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 686 pinctrl-names = "default"; 687 pinctrl-0 = <&qup_i2c7_default>; 688 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 status = "disabled"; 692 }; 693 694 spi7: spi@89c000 { 695 compatible = "qcom,geni-spi"; 696 reg = <0 0x0089c000 0 0x4000>; 697 clock-names = "se"; 698 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 699 pinctrl-names = "default"; 700 pinctrl-0 = <&qup_spi7_default>; 701 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 702 #address-cells = <1>; 703 #size-cells = <0>; 704 status = "disabled"; 705 }; 706 707 uart7: serial@89c000 { 708 compatible = "qcom,geni-uart"; 709 reg = <0 0x0089c000 0 0x4000>; 710 clock-names = "se"; 711 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 712 pinctrl-names = "default"; 713 pinctrl-0 = <&qup_uart7_default>; 714 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 715 status = "disabled"; 716 }; 717 }; 718 719 qupv3_id_1: geniqup@ac0000 { 720 compatible = "qcom,geni-se-qup"; 721 reg = <0 0x00ac0000 0 0x6000>; 722 clock-names = "m-ahb", "s-ahb"; 723 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 724 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 725 #address-cells = <2>; 726 #size-cells = <2>; 727 ranges; 728 status = "disabled"; 729 730 i2c8: i2c@a80000 { 731 compatible = "qcom,geni-i2c"; 732 reg = <0 0x00a80000 0 0x4000>; 733 clock-names = "se"; 734 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 735 pinctrl-names = "default"; 736 pinctrl-0 = <&qup_i2c8_default>; 737 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 738 #address-cells = <1>; 739 #size-cells = <0>; 740 status = "disabled"; 741 }; 742 743 spi8: spi@a80000 { 744 compatible = "qcom,geni-spi"; 745 reg = <0 0x00a80000 0 0x4000>; 746 clock-names = "se"; 747 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 748 pinctrl-names = "default"; 749 pinctrl-0 = <&qup_spi8_default>; 750 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 751 #address-cells = <1>; 752 #size-cells = <0>; 753 status = "disabled"; 754 }; 755 756 uart8: serial@a80000 { 757 compatible = "qcom,geni-uart"; 758 reg = <0 0x00a80000 0 0x4000>; 759 clock-names = "se"; 760 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 761 pinctrl-names = "default"; 762 pinctrl-0 = <&qup_uart8_default>; 763 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 764 status = "disabled"; 765 }; 766 767 i2c9: i2c@a84000 { 768 compatible = "qcom,geni-i2c"; 769 reg = <0 0x00a84000 0 0x4000>; 770 clock-names = "se"; 771 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 772 pinctrl-names = "default"; 773 pinctrl-0 = <&qup_i2c9_default>; 774 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 775 #address-cells = <1>; 776 #size-cells = <0>; 777 status = "disabled"; 778 }; 779 780 spi9: spi@a84000 { 781 compatible = "qcom,geni-spi"; 782 reg = <0 0x00a84000 0 0x4000>; 783 clock-names = "se"; 784 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 785 pinctrl-names = "default"; 786 pinctrl-0 = <&qup_spi9_default>; 787 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 788 #address-cells = <1>; 789 #size-cells = <0>; 790 status = "disabled"; 791 }; 792 793 uart9: serial@a84000 { 794 compatible = "qcom,geni-debug-uart"; 795 reg = <0 0x00a84000 0 0x4000>; 796 clock-names = "se"; 797 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 798 pinctrl-names = "default"; 799 pinctrl-0 = <&qup_uart9_default>; 800 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 801 status = "disabled"; 802 }; 803 804 i2c10: i2c@a88000 { 805 compatible = "qcom,geni-i2c"; 806 reg = <0 0x00a88000 0 0x4000>; 807 clock-names = "se"; 808 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 809 pinctrl-names = "default"; 810 pinctrl-0 = <&qup_i2c10_default>; 811 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 812 #address-cells = <1>; 813 #size-cells = <0>; 814 status = "disabled"; 815 }; 816 817 spi10: spi@a88000 { 818 compatible = "qcom,geni-spi"; 819 reg = <0 0x00a88000 0 0x4000>; 820 clock-names = "se"; 821 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 822 pinctrl-names = "default"; 823 pinctrl-0 = <&qup_spi10_default>; 824 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 825 #address-cells = <1>; 826 #size-cells = <0>; 827 status = "disabled"; 828 }; 829 830 uart10: serial@a88000 { 831 compatible = "qcom,geni-uart"; 832 reg = <0 0x00a88000 0 0x4000>; 833 clock-names = "se"; 834 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 835 pinctrl-names = "default"; 836 pinctrl-0 = <&qup_uart10_default>; 837 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 838 status = "disabled"; 839 }; 840 841 i2c11: i2c@a8c000 { 842 compatible = "qcom,geni-i2c"; 843 reg = <0 0x00a8c000 0 0x4000>; 844 clock-names = "se"; 845 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 846 pinctrl-names = "default"; 847 pinctrl-0 = <&qup_i2c11_default>; 848 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 status = "disabled"; 852 }; 853 854 spi11: spi@a8c000 { 855 compatible = "qcom,geni-spi"; 856 reg = <0 0x00a8c000 0 0x4000>; 857 clock-names = "se"; 858 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 859 pinctrl-names = "default"; 860 pinctrl-0 = <&qup_spi11_default>; 861 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 862 #address-cells = <1>; 863 #size-cells = <0>; 864 status = "disabled"; 865 }; 866 867 uart11: serial@a8c000 { 868 compatible = "qcom,geni-uart"; 869 reg = <0 0x00a8c000 0 0x4000>; 870 clock-names = "se"; 871 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 872 pinctrl-names = "default"; 873 pinctrl-0 = <&qup_uart11_default>; 874 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 875 status = "disabled"; 876 }; 877 878 i2c12: i2c@a90000 { 879 compatible = "qcom,geni-i2c"; 880 reg = <0 0x00a90000 0 0x4000>; 881 clock-names = "se"; 882 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 883 pinctrl-names = "default"; 884 pinctrl-0 = <&qup_i2c12_default>; 885 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 886 #address-cells = <1>; 887 #size-cells = <0>; 888 status = "disabled"; 889 }; 890 891 spi12: spi@a90000 { 892 compatible = "qcom,geni-spi"; 893 reg = <0 0x00a90000 0 0x4000>; 894 clock-names = "se"; 895 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 896 pinctrl-names = "default"; 897 pinctrl-0 = <&qup_spi12_default>; 898 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 899 #address-cells = <1>; 900 #size-cells = <0>; 901 status = "disabled"; 902 }; 903 904 uart12: serial@a90000 { 905 compatible = "qcom,geni-uart"; 906 reg = <0 0x00a90000 0 0x4000>; 907 clock-names = "se"; 908 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 909 pinctrl-names = "default"; 910 pinctrl-0 = <&qup_uart12_default>; 911 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 912 status = "disabled"; 913 }; 914 915 i2c13: i2c@a94000 { 916 compatible = "qcom,geni-i2c"; 917 reg = <0 0x00a94000 0 0x4000>; 918 clock-names = "se"; 919 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 920 pinctrl-names = "default"; 921 pinctrl-0 = <&qup_i2c13_default>; 922 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 923 #address-cells = <1>; 924 #size-cells = <0>; 925 status = "disabled"; 926 }; 927 928 spi13: spi@a94000 { 929 compatible = "qcom,geni-spi"; 930 reg = <0 0x00a94000 0 0x4000>; 931 clock-names = "se"; 932 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 933 pinctrl-names = "default"; 934 pinctrl-0 = <&qup_spi13_default>; 935 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 status = "disabled"; 939 }; 940 941 uart13: serial@a94000 { 942 compatible = "qcom,geni-uart"; 943 reg = <0 0x00a94000 0 0x4000>; 944 clock-names = "se"; 945 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 946 pinctrl-names = "default"; 947 pinctrl-0 = <&qup_uart13_default>; 948 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 949 status = "disabled"; 950 }; 951 952 i2c14: i2c@a98000 { 953 compatible = "qcom,geni-i2c"; 954 reg = <0 0x00a98000 0 0x4000>; 955 clock-names = "se"; 956 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 957 pinctrl-names = "default"; 958 pinctrl-0 = <&qup_i2c14_default>; 959 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 960 #address-cells = <1>; 961 #size-cells = <0>; 962 status = "disabled"; 963 }; 964 965 spi14: spi@a98000 { 966 compatible = "qcom,geni-spi"; 967 reg = <0 0x00a98000 0 0x4000>; 968 clock-names = "se"; 969 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 970 pinctrl-names = "default"; 971 pinctrl-0 = <&qup_spi14_default>; 972 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 973 #address-cells = <1>; 974 #size-cells = <0>; 975 status = "disabled"; 976 }; 977 978 uart14: serial@a98000 { 979 compatible = "qcom,geni-uart"; 980 reg = <0 0x00a98000 0 0x4000>; 981 clock-names = "se"; 982 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 983 pinctrl-names = "default"; 984 pinctrl-0 = <&qup_uart14_default>; 985 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 986 status = "disabled"; 987 }; 988 989 i2c15: i2c@a9c000 { 990 compatible = "qcom,geni-i2c"; 991 reg = <0 0x00a9c000 0 0x4000>; 992 clock-names = "se"; 993 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 994 pinctrl-names = "default"; 995 pinctrl-0 = <&qup_i2c15_default>; 996 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 997 #address-cells = <1>; 998 #size-cells = <0>; 999 status = "disabled"; 1000 }; 1001 1002 spi15: spi@a9c000 { 1003 compatible = "qcom,geni-spi"; 1004 reg = <0 0x00a9c000 0 0x4000>; 1005 clock-names = "se"; 1006 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1007 pinctrl-names = "default"; 1008 pinctrl-0 = <&qup_spi15_default>; 1009 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 status = "disabled"; 1013 }; 1014 1015 uart15: serial@a9c000 { 1016 compatible = "qcom,geni-uart"; 1017 reg = <0 0x00a9c000 0 0x4000>; 1018 clock-names = "se"; 1019 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&qup_uart15_default>; 1022 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1023 status = "disabled"; 1024 }; 1025 }; 1026 1027 ufs_mem_hc: ufshc@1d84000 { 1028 compatible = "qcom,sdm845-ufshc", "qcom,ufshc", 1029 "jedec,ufs-2.0"; 1030 reg = <0 0x01d84000 0 0x2500>; 1031 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1032 phys = <&ufs_mem_phy_lanes>; 1033 phy-names = "ufsphy"; 1034 lanes-per-direction = <2>; 1035 power-domains = <&gcc UFS_PHY_GDSC>; 1036 1037 iommus = <&apps_smmu 0x100 0xf>; 1038 1039 clock-names = 1040 "core_clk", 1041 "bus_aggr_clk", 1042 "iface_clk", 1043 "core_clk_unipro", 1044 "ref_clk", 1045 "tx_lane0_sync_clk", 1046 "rx_lane0_sync_clk", 1047 "rx_lane1_sync_clk"; 1048 clocks = 1049 <&gcc GCC_UFS_PHY_AXI_CLK>, 1050 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1051 <&gcc GCC_UFS_PHY_AHB_CLK>, 1052 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1053 <&rpmhcc RPMH_CXO_CLK>, 1054 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1055 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1056 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1057 freq-table-hz = 1058 <50000000 200000000>, 1059 <0 0>, 1060 <0 0>, 1061 <37500000 150000000>, 1062 <0 0>, 1063 <0 0>, 1064 <0 0>, 1065 <0 0>; 1066 1067 status = "disabled"; 1068 }; 1069 1070 ufs_mem_phy: phy@1d87000 { 1071 compatible = "qcom,sdm845-qmp-ufs-phy"; 1072 reg = <0 0x01d87000 0 0x18c>; 1073 #address-cells = <2>; 1074 #size-cells = <2>; 1075 ranges; 1076 clock-names = "ref", 1077 "ref_aux"; 1078 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 1079 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1080 1081 status = "disabled"; 1082 1083 ufs_mem_phy_lanes: lanes@1d87400 { 1084 reg = <0 0x01d87400 0 0x108>, 1085 <0 0x01d87600 0 0x1e0>, 1086 <0 0x01d87c00 0 0x1dc>, 1087 <0 0x01d87800 0 0x108>, 1088 <0 0x01d87a00 0 0x1e0>; 1089 #phy-cells = <0>; 1090 }; 1091 }; 1092 1093 tcsr_mutex_regs: syscon@1f40000 { 1094 compatible = "syscon"; 1095 reg = <0 0x01f40000 0 0x40000>; 1096 }; 1097 1098 tlmm: pinctrl@3400000 { 1099 compatible = "qcom,sdm845-pinctrl"; 1100 reg = <0 0x03400000 0 0xc00000>; 1101 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1102 gpio-controller; 1103 #gpio-cells = <2>; 1104 interrupt-controller; 1105 #interrupt-cells = <2>; 1106 gpio-ranges = <&tlmm 0 0 150>; 1107 1108 qspi_clk: qspi-clk { 1109 pinmux { 1110 pins = "gpio95"; 1111 function = "qspi_clk"; 1112 }; 1113 }; 1114 1115 qspi_cs0: qspi-cs0 { 1116 pinmux { 1117 pins = "gpio90"; 1118 function = "qspi_cs"; 1119 }; 1120 }; 1121 1122 qspi_cs1: qspi-cs1 { 1123 pinmux { 1124 pins = "gpio89"; 1125 function = "qspi_cs"; 1126 }; 1127 }; 1128 1129 qspi_data01: qspi-data01 { 1130 pinmux-data { 1131 pins = "gpio91", "gpio92"; 1132 function = "qspi_data"; 1133 }; 1134 }; 1135 1136 qspi_data12: qspi-data12 { 1137 pinmux-data { 1138 pins = "gpio93", "gpio94"; 1139 function = "qspi_data"; 1140 }; 1141 }; 1142 1143 qup_i2c0_default: qup-i2c0-default { 1144 pinmux { 1145 pins = "gpio0", "gpio1"; 1146 function = "qup0"; 1147 }; 1148 }; 1149 1150 qup_i2c1_default: qup-i2c1-default { 1151 pinmux { 1152 pins = "gpio17", "gpio18"; 1153 function = "qup1"; 1154 }; 1155 }; 1156 1157 qup_i2c2_default: qup-i2c2-default { 1158 pinmux { 1159 pins = "gpio27", "gpio28"; 1160 function = "qup2"; 1161 }; 1162 }; 1163 1164 qup_i2c3_default: qup-i2c3-default { 1165 pinmux { 1166 pins = "gpio41", "gpio42"; 1167 function = "qup3"; 1168 }; 1169 }; 1170 1171 qup_i2c4_default: qup-i2c4-default { 1172 pinmux { 1173 pins = "gpio89", "gpio90"; 1174 function = "qup4"; 1175 }; 1176 }; 1177 1178 qup_i2c5_default: qup-i2c5-default { 1179 pinmux { 1180 pins = "gpio85", "gpio86"; 1181 function = "qup5"; 1182 }; 1183 }; 1184 1185 qup_i2c6_default: qup-i2c6-default { 1186 pinmux { 1187 pins = "gpio45", "gpio46"; 1188 function = "qup6"; 1189 }; 1190 }; 1191 1192 qup_i2c7_default: qup-i2c7-default { 1193 pinmux { 1194 pins = "gpio93", "gpio94"; 1195 function = "qup7"; 1196 }; 1197 }; 1198 1199 qup_i2c8_default: qup-i2c8-default { 1200 pinmux { 1201 pins = "gpio65", "gpio66"; 1202 function = "qup8"; 1203 }; 1204 }; 1205 1206 qup_i2c9_default: qup-i2c9-default { 1207 pinmux { 1208 pins = "gpio6", "gpio7"; 1209 function = "qup9"; 1210 }; 1211 }; 1212 1213 qup_i2c10_default: qup-i2c10-default { 1214 pinmux { 1215 pins = "gpio55", "gpio56"; 1216 function = "qup10"; 1217 }; 1218 }; 1219 1220 qup_i2c11_default: qup-i2c11-default { 1221 pinmux { 1222 pins = "gpio31", "gpio32"; 1223 function = "qup11"; 1224 }; 1225 }; 1226 1227 qup_i2c12_default: qup-i2c12-default { 1228 pinmux { 1229 pins = "gpio49", "gpio50"; 1230 function = "qup12"; 1231 }; 1232 }; 1233 1234 qup_i2c13_default: qup-i2c13-default { 1235 pinmux { 1236 pins = "gpio105", "gpio106"; 1237 function = "qup13"; 1238 }; 1239 }; 1240 1241 qup_i2c14_default: qup-i2c14-default { 1242 pinmux { 1243 pins = "gpio33", "gpio34"; 1244 function = "qup14"; 1245 }; 1246 }; 1247 1248 qup_i2c15_default: qup-i2c15-default { 1249 pinmux { 1250 pins = "gpio81", "gpio82"; 1251 function = "qup15"; 1252 }; 1253 }; 1254 1255 qup_spi0_default: qup-spi0-default { 1256 pinmux { 1257 pins = "gpio0", "gpio1", 1258 "gpio2", "gpio3"; 1259 function = "qup0"; 1260 }; 1261 }; 1262 1263 qup_spi1_default: qup-spi1-default { 1264 pinmux { 1265 pins = "gpio17", "gpio18", 1266 "gpio19", "gpio20"; 1267 function = "qup1"; 1268 }; 1269 }; 1270 1271 qup_spi2_default: qup-spi2-default { 1272 pinmux { 1273 pins = "gpio27", "gpio28", 1274 "gpio29", "gpio30"; 1275 function = "qup2"; 1276 }; 1277 }; 1278 1279 qup_spi3_default: qup-spi3-default { 1280 pinmux { 1281 pins = "gpio41", "gpio42", 1282 "gpio43", "gpio44"; 1283 function = "qup3"; 1284 }; 1285 }; 1286 1287 qup_spi4_default: qup-spi4-default { 1288 pinmux { 1289 pins = "gpio89", "gpio90", 1290 "gpio91", "gpio92"; 1291 function = "qup4"; 1292 }; 1293 }; 1294 1295 qup_spi5_default: qup-spi5-default { 1296 pinmux { 1297 pins = "gpio85", "gpio86", 1298 "gpio87", "gpio88"; 1299 function = "qup5"; 1300 }; 1301 }; 1302 1303 qup_spi6_default: qup-spi6-default { 1304 pinmux { 1305 pins = "gpio45", "gpio46", 1306 "gpio47", "gpio48"; 1307 function = "qup6"; 1308 }; 1309 }; 1310 1311 qup_spi7_default: qup-spi7-default { 1312 pinmux { 1313 pins = "gpio93", "gpio94", 1314 "gpio95", "gpio96"; 1315 function = "qup7"; 1316 }; 1317 }; 1318 1319 qup_spi8_default: qup-spi8-default { 1320 pinmux { 1321 pins = "gpio65", "gpio66", 1322 "gpio67", "gpio68"; 1323 function = "qup8"; 1324 }; 1325 }; 1326 1327 qup_spi9_default: qup-spi9-default { 1328 pinmux { 1329 pins = "gpio6", "gpio7", 1330 "gpio4", "gpio5"; 1331 function = "qup9"; 1332 }; 1333 }; 1334 1335 qup_spi10_default: qup-spi10-default { 1336 pinmux { 1337 pins = "gpio55", "gpio56", 1338 "gpio53", "gpio54"; 1339 function = "qup10"; 1340 }; 1341 }; 1342 1343 qup_spi11_default: qup-spi11-default { 1344 pinmux { 1345 pins = "gpio31", "gpio32", 1346 "gpio33", "gpio34"; 1347 function = "qup11"; 1348 }; 1349 }; 1350 1351 qup_spi12_default: qup-spi12-default { 1352 pinmux { 1353 pins = "gpio49", "gpio50", 1354 "gpio51", "gpio52"; 1355 function = "qup12"; 1356 }; 1357 }; 1358 1359 qup_spi13_default: qup-spi13-default { 1360 pinmux { 1361 pins = "gpio105", "gpio106", 1362 "gpio107", "gpio108"; 1363 function = "qup13"; 1364 }; 1365 }; 1366 1367 qup_spi14_default: qup-spi14-default { 1368 pinmux { 1369 pins = "gpio33", "gpio34", 1370 "gpio31", "gpio32"; 1371 function = "qup14"; 1372 }; 1373 }; 1374 1375 qup_spi15_default: qup-spi15-default { 1376 pinmux { 1377 pins = "gpio81", "gpio82", 1378 "gpio83", "gpio84"; 1379 function = "qup15"; 1380 }; 1381 }; 1382 1383 qup_uart0_default: qup-uart0-default { 1384 pinmux { 1385 pins = "gpio2", "gpio3"; 1386 function = "qup0"; 1387 }; 1388 }; 1389 1390 qup_uart1_default: qup-uart1-default { 1391 pinmux { 1392 pins = "gpio19", "gpio20"; 1393 function = "qup1"; 1394 }; 1395 }; 1396 1397 qup_uart2_default: qup-uart2-default { 1398 pinmux { 1399 pins = "gpio29", "gpio30"; 1400 function = "qup2"; 1401 }; 1402 }; 1403 1404 qup_uart3_default: qup-uart3-default { 1405 pinmux { 1406 pins = "gpio43", "gpio44"; 1407 function = "qup3"; 1408 }; 1409 }; 1410 1411 qup_uart4_default: qup-uart4-default { 1412 pinmux { 1413 pins = "gpio91", "gpio92"; 1414 function = "qup4"; 1415 }; 1416 }; 1417 1418 qup_uart5_default: qup-uart5-default { 1419 pinmux { 1420 pins = "gpio87", "gpio88"; 1421 function = "qup5"; 1422 }; 1423 }; 1424 1425 qup_uart6_default: qup-uart6-default { 1426 pinmux { 1427 pins = "gpio47", "gpio48"; 1428 function = "qup6"; 1429 }; 1430 }; 1431 1432 qup_uart7_default: qup-uart7-default { 1433 pinmux { 1434 pins = "gpio95", "gpio96"; 1435 function = "qup7"; 1436 }; 1437 }; 1438 1439 qup_uart8_default: qup-uart8-default { 1440 pinmux { 1441 pins = "gpio67", "gpio68"; 1442 function = "qup8"; 1443 }; 1444 }; 1445 1446 qup_uart9_default: qup-uart9-default { 1447 pinmux { 1448 pins = "gpio4", "gpio5"; 1449 function = "qup9"; 1450 }; 1451 }; 1452 1453 qup_uart10_default: qup-uart10-default { 1454 pinmux { 1455 pins = "gpio53", "gpio54"; 1456 function = "qup10"; 1457 }; 1458 }; 1459 1460 qup_uart11_default: qup-uart11-default { 1461 pinmux { 1462 pins = "gpio33", "gpio34"; 1463 function = "qup11"; 1464 }; 1465 }; 1466 1467 qup_uart12_default: qup-uart12-default { 1468 pinmux { 1469 pins = "gpio51", "gpio52"; 1470 function = "qup12"; 1471 }; 1472 }; 1473 1474 qup_uart13_default: qup-uart13-default { 1475 pinmux { 1476 pins = "gpio107", "gpio108"; 1477 function = "qup13"; 1478 }; 1479 }; 1480 1481 qup_uart14_default: qup-uart14-default { 1482 pinmux { 1483 pins = "gpio31", "gpio32"; 1484 function = "qup14"; 1485 }; 1486 }; 1487 1488 qup_uart15_default: qup-uart15-default { 1489 pinmux { 1490 pins = "gpio83", "gpio84"; 1491 function = "qup15"; 1492 }; 1493 }; 1494 }; 1495 1496 gpucc: clock-controller@5090000 { 1497 compatible = "qcom,sdm845-gpucc"; 1498 reg = <0 0x05090000 0 0x9000>; 1499 #clock-cells = <1>; 1500 #reset-cells = <1>; 1501 #power-domain-cells = <1>; 1502 clocks = <&rpmhcc RPMH_CXO_CLK>; 1503 clock-names = "xo"; 1504 }; 1505 1506 sdhc_2: sdhci@8804000 { 1507 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 1508 reg = <0 0x08804000 0 0x1000>; 1509 1510 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1512 interrupt-names = "hc_irq", "pwr_irq"; 1513 1514 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1515 <&gcc GCC_SDCC2_APPS_CLK>; 1516 clock-names = "iface", "core"; 1517 iommus = <&apps_smmu 0xa0 0xf>; 1518 1519 status = "disabled"; 1520 }; 1521 1522 qspi: spi@88df000 { 1523 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 1524 reg = <0 0x088df000 0 0x600>; 1525 #address-cells = <1>; 1526 #size-cells = <0>; 1527 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1528 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 1529 <&gcc GCC_QSPI_CORE_CLK>; 1530 clock-names = "iface", "core"; 1531 status = "disabled"; 1532 }; 1533 1534 usb_1_hsphy: phy@88e2000 { 1535 compatible = "qcom,sdm845-qusb2-phy"; 1536 reg = <0 0x088e2000 0 0x400>; 1537 status = "disabled"; 1538 #phy-cells = <0>; 1539 1540 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1541 <&rpmhcc RPMH_CXO_CLK>; 1542 clock-names = "cfg_ahb", "ref"; 1543 1544 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1545 1546 nvmem-cells = <&qusb2p_hstx_trim>; 1547 }; 1548 1549 usb_2_hsphy: phy@88e3000 { 1550 compatible = "qcom,sdm845-qusb2-phy"; 1551 reg = <0 0x088e3000 0 0x400>; 1552 status = "disabled"; 1553 #phy-cells = <0>; 1554 1555 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1556 <&rpmhcc RPMH_CXO_CLK>; 1557 clock-names = "cfg_ahb", "ref"; 1558 1559 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1560 1561 nvmem-cells = <&qusb2s_hstx_trim>; 1562 }; 1563 1564 usb_1_qmpphy: phy@88e9000 { 1565 compatible = "qcom,sdm845-qmp-usb3-phy"; 1566 reg = <0 0x088e9000 0 0x18c>, 1567 <0 0x088e8000 0 0x10>; 1568 reg-names = "reg-base", "dp_com"; 1569 status = "disabled"; 1570 #clock-cells = <1>; 1571 #address-cells = <2>; 1572 #size-cells = <2>; 1573 ranges; 1574 1575 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1576 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1577 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 1578 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 1579 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 1580 1581 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 1582 <&gcc GCC_USB3_PHY_PRIM_BCR>; 1583 reset-names = "phy", "common"; 1584 1585 usb_1_ssphy: lanes@88e9200 { 1586 reg = <0 0x088e9200 0 0x128>, 1587 <0 0x088e9400 0 0x200>, 1588 <0 0x088e9c00 0 0x218>, 1589 <0 0x088e9600 0 0x128>, 1590 <0 0x088e9800 0 0x200>, 1591 <0 0x088e9a00 0 0x100>; 1592 #phy-cells = <0>; 1593 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1594 clock-names = "pipe0"; 1595 clock-output-names = "usb3_phy_pipe_clk_src"; 1596 }; 1597 }; 1598 1599 usb_2_qmpphy: phy@88eb000 { 1600 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 1601 reg = <0 0x088eb000 0 0x18c>; 1602 status = "disabled"; 1603 #clock-cells = <1>; 1604 #address-cells = <2>; 1605 #size-cells = <2>; 1606 ranges; 1607 1608 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 1609 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1610 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 1611 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 1612 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 1613 1614 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 1615 <&gcc GCC_USB3_PHY_SEC_BCR>; 1616 reset-names = "phy", "common"; 1617 1618 usb_2_ssphy: lane@88eb200 { 1619 reg = <0 0x088eb200 0 0x128>, 1620 <0 0x088eb400 0 0x1fc>, 1621 <0 0x088eb800 0 0x218>, 1622 <0 0x088eb600 0 0x70>; 1623 #phy-cells = <0>; 1624 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 1625 clock-names = "pipe0"; 1626 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 1627 }; 1628 }; 1629 1630 usb_1: usb@a6f8800 { 1631 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 1632 reg = <0 0x0a6f8800 0 0x400>; 1633 status = "disabled"; 1634 #address-cells = <2>; 1635 #size-cells = <2>; 1636 ranges; 1637 dma-ranges; 1638 1639 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1640 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1641 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1642 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1643 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 1644 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1645 "sleep"; 1646 1647 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1648 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1649 assigned-clock-rates = <19200000>, <150000000>; 1650 1651 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1652 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 1653 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 1655 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1656 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1657 1658 power-domains = <&gcc USB30_PRIM_GDSC>; 1659 1660 resets = <&gcc GCC_USB30_PRIM_BCR>; 1661 1662 usb_1_dwc3: dwc3@a600000 { 1663 compatible = "snps,dwc3"; 1664 reg = <0 0x0a600000 0 0xcd00>; 1665 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1666 iommus = <&apps_smmu 0x740 0>; 1667 snps,dis_u2_susphy_quirk; 1668 snps,dis_enblslpm_quirk; 1669 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1670 phy-names = "usb2-phy", "usb3-phy"; 1671 }; 1672 }; 1673 1674 usb_2: usb@a8f8800 { 1675 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 1676 reg = <0 0x0a8f8800 0 0x400>; 1677 status = "disabled"; 1678 #address-cells = <2>; 1679 #size-cells = <2>; 1680 ranges; 1681 dma-ranges; 1682 1683 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 1684 <&gcc GCC_USB30_SEC_MASTER_CLK>, 1685 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 1686 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1687 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 1688 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1689 "sleep"; 1690 1691 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1692 <&gcc GCC_USB30_SEC_MASTER_CLK>; 1693 assigned-clock-rates = <19200000>, <150000000>; 1694 1695 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1696 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 1697 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 1698 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 1699 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1700 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1701 1702 power-domains = <&gcc USB30_SEC_GDSC>; 1703 1704 resets = <&gcc GCC_USB30_SEC_BCR>; 1705 1706 usb_2_dwc3: dwc3@a800000 { 1707 compatible = "snps,dwc3"; 1708 reg = <0 0x0a800000 0 0xcd00>; 1709 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1710 iommus = <&apps_smmu 0x760 0>; 1711 snps,dis_u2_susphy_quirk; 1712 snps,dis_enblslpm_quirk; 1713 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 1714 phy-names = "usb2-phy", "usb3-phy"; 1715 }; 1716 }; 1717 1718 videocc: clock-controller@ab00000 { 1719 compatible = "qcom,sdm845-videocc"; 1720 reg = <0 0x0ab00000 0 0x10000>; 1721 #clock-cells = <1>; 1722 #power-domain-cells = <1>; 1723 #reset-cells = <1>; 1724 }; 1725 1726 mdss: mdss@ae00000 { 1727 compatible = "qcom,sdm845-mdss"; 1728 reg = <0 0x0ae00000 0 0x1000>; 1729 reg-names = "mdss"; 1730 1731 power-domains = <&dispcc MDSS_GDSC>; 1732 1733 clocks = <&gcc GCC_DISP_AHB_CLK>, 1734 <&gcc GCC_DISP_AXI_CLK>, 1735 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1736 clock-names = "iface", "bus", "core"; 1737 1738 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 1739 assigned-clock-rates = <300000000>; 1740 1741 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1742 interrupt-controller; 1743 #interrupt-cells = <1>; 1744 1745 iommus = <&apps_smmu 0x880 0x8>, 1746 <&apps_smmu 0xc80 0x8>; 1747 1748 status = "disabled"; 1749 1750 #address-cells = <2>; 1751 #size-cells = <2>; 1752 ranges; 1753 1754 mdss_mdp: mdp@ae01000 { 1755 compatible = "qcom,sdm845-dpu"; 1756 reg = <0 0x0ae01000 0 0x8f000>, 1757 <0 0x0aeb0000 0 0x2008>; 1758 reg-names = "mdp", "vbif"; 1759 1760 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1761 <&dispcc DISP_CC_MDSS_AXI_CLK>, 1762 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1763 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1764 clock-names = "iface", "bus", "core", "vsync"; 1765 1766 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 1767 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1768 assigned-clock-rates = <300000000>, 1769 <19200000>; 1770 1771 interrupt-parent = <&mdss>; 1772 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 1773 1774 status = "disabled"; 1775 1776 ports { 1777 #address-cells = <1>; 1778 #size-cells = <0>; 1779 1780 port@0 { 1781 reg = <0>; 1782 dpu_intf1_out: endpoint { 1783 remote-endpoint = <&dsi0_in>; 1784 }; 1785 }; 1786 1787 port@1 { 1788 reg = <1>; 1789 dpu_intf2_out: endpoint { 1790 remote-endpoint = <&dsi1_in>; 1791 }; 1792 }; 1793 }; 1794 }; 1795 1796 dsi0: dsi@ae94000 { 1797 compatible = "qcom,mdss-dsi-ctrl"; 1798 reg = <0 0x0ae94000 0 0x400>; 1799 reg-names = "dsi_ctrl"; 1800 1801 interrupt-parent = <&mdss>; 1802 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 1803 1804 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1805 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1806 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1807 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1808 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1809 <&dispcc DISP_CC_MDSS_AXI_CLK>; 1810 clock-names = "byte", 1811 "byte_intf", 1812 "pixel", 1813 "core", 1814 "iface", 1815 "bus"; 1816 1817 phys = <&dsi0_phy>; 1818 phy-names = "dsi"; 1819 1820 status = "disabled"; 1821 1822 #address-cells = <1>; 1823 #size-cells = <0>; 1824 1825 ports { 1826 #address-cells = <1>; 1827 #size-cells = <0>; 1828 1829 port@0 { 1830 reg = <0>; 1831 dsi0_in: endpoint { 1832 remote-endpoint = <&dpu_intf1_out>; 1833 }; 1834 }; 1835 1836 port@1 { 1837 reg = <1>; 1838 dsi0_out: endpoint { 1839 }; 1840 }; 1841 }; 1842 }; 1843 1844 dsi0_phy: dsi-phy@ae94400 { 1845 compatible = "qcom,dsi-phy-10nm"; 1846 reg = <0 0x0ae94400 0 0x200>, 1847 <0 0x0ae94600 0 0x280>, 1848 <0 0x0ae94a00 0 0x1e0>; 1849 reg-names = "dsi_phy", 1850 "dsi_phy_lane", 1851 "dsi_pll"; 1852 1853 #clock-cells = <1>; 1854 #phy-cells = <0>; 1855 1856 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; 1857 clock-names = "iface"; 1858 1859 status = "disabled"; 1860 }; 1861 1862 dsi1: dsi@ae96000 { 1863 compatible = "qcom,mdss-dsi-ctrl"; 1864 reg = <0 0x0ae96000 0 0x400>; 1865 reg-names = "dsi_ctrl"; 1866 1867 interrupt-parent = <&mdss>; 1868 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 1869 1870 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 1871 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 1872 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 1873 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 1874 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1875 <&dispcc DISP_CC_MDSS_AXI_CLK>; 1876 clock-names = "byte", 1877 "byte_intf", 1878 "pixel", 1879 "core", 1880 "iface", 1881 "bus"; 1882 1883 phys = <&dsi1_phy>; 1884 phy-names = "dsi"; 1885 1886 status = "disabled"; 1887 1888 #address-cells = <1>; 1889 #size-cells = <0>; 1890 1891 ports { 1892 #address-cells = <1>; 1893 #size-cells = <0>; 1894 1895 port@0 { 1896 reg = <0>; 1897 dsi1_in: endpoint { 1898 remote-endpoint = <&dpu_intf2_out>; 1899 }; 1900 }; 1901 1902 port@1 { 1903 reg = <1>; 1904 dsi1_out: endpoint { 1905 }; 1906 }; 1907 }; 1908 }; 1909 1910 dsi1_phy: dsi-phy@ae96400 { 1911 compatible = "qcom,dsi-phy-10nm"; 1912 reg = <0 0x0ae96400 0 0x200>, 1913 <0 0x0ae96600 0 0x280>, 1914 <0 0x0ae96a00 0 0x10e>; 1915 reg-names = "dsi_phy", 1916 "dsi_phy_lane", 1917 "dsi_pll"; 1918 1919 #clock-cells = <1>; 1920 #phy-cells = <0>; 1921 1922 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; 1923 clock-names = "iface"; 1924 1925 status = "disabled"; 1926 }; 1927 }; 1928 1929 dispcc: clock-controller@af00000 { 1930 compatible = "qcom,sdm845-dispcc"; 1931 reg = <0 0x0af00000 0 0x10000>; 1932 #clock-cells = <1>; 1933 #reset-cells = <1>; 1934 #power-domain-cells = <1>; 1935 }; 1936 1937 pdc_reset: reset-controller@b2e0000 { 1938 compatible = "qcom,sdm845-pdc-global"; 1939 reg = <0 0x0b2e0000 0 0x20000>; 1940 #reset-cells = <1>; 1941 }; 1942 1943 tsens0: thermal-sensor@c263000 { 1944 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 1945 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1946 <0 0x0c222000 0 0x1ff>; /* SROT */ 1947 #qcom,sensors = <13>; 1948 #thermal-sensor-cells = <1>; 1949 }; 1950 1951 tsens1: thermal-sensor@c265000 { 1952 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 1953 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1954 <0 0x0c223000 0 0x1ff>; /* SROT */ 1955 #qcom,sensors = <8>; 1956 #thermal-sensor-cells = <1>; 1957 }; 1958 1959 aoss_reset: reset-controller@c2a0000 { 1960 compatible = "qcom,sdm845-aoss-cc"; 1961 reg = <0 0x0c2a0000 0 0x31000>; 1962 #reset-cells = <1>; 1963 }; 1964 1965 spmi_bus: spmi@c440000 { 1966 compatible = "qcom,spmi-pmic-arb"; 1967 reg = <0 0x0c440000 0 0x1100>, 1968 <0 0x0c600000 0 0x2000000>, 1969 <0 0x0e600000 0 0x100000>, 1970 <0 0x0e700000 0 0xa0000>, 1971 <0 0x0c40a000 0 0x26000>; 1972 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1973 interrupt-names = "periph_irq"; 1974 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 1975 qcom,ee = <0>; 1976 qcom,channel = <0>; 1977 #address-cells = <2>; 1978 #size-cells = <0>; 1979 interrupt-controller; 1980 #interrupt-cells = <4>; 1981 cell-index = <0>; 1982 }; 1983 1984 apps_smmu: iommu@15000000 { 1985 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; 1986 reg = <0 0x15000000 0 0x80000>; 1987 #iommu-cells = <2>; 1988 #global-interrupts = <1>; 1989 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1990 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1991 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1992 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1993 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1994 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1995 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1996 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1997 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1998 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1999 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2000 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2001 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2002 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2003 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2004 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2005 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2006 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2007 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2008 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2009 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2010 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2011 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2012 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2013 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2014 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2015 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2016 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2017 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2018 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2019 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2020 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2021 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2022 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2023 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2024 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2025 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2026 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2027 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2028 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2029 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2030 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2031 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2032 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2033 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2034 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2035 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2036 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2037 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2038 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2039 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2040 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2041 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2042 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2043 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2044 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2045 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2046 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2047 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2048 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2049 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2050 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2051 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2052 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2053 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 2054 }; 2055 2056 lpasscc: clock-controller@17014000 { 2057 compatible = "qcom,sdm845-lpasscc"; 2058 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; 2059 reg-names = "cc", "qdsp6ss"; 2060 #clock-cells = <1>; 2061 status = "disabled"; 2062 }; 2063 2064 apss_shared: mailbox@17990000 { 2065 compatible = "qcom,sdm845-apss-shared"; 2066 reg = <0 0x17990000 0 0x1000>; 2067 #mbox-cells = <1>; 2068 }; 2069 2070 apps_rsc: rsc@179c0000 { 2071 label = "apps_rsc"; 2072 compatible = "qcom,rpmh-rsc"; 2073 reg = <0 0x179c0000 0 0x10000>, 2074 <0 0x179d0000 0 0x10000>, 2075 <0 0x179e0000 0 0x10000>; 2076 reg-names = "drv-0", "drv-1", "drv-2"; 2077 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2078 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2079 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2080 qcom,tcs-offset = <0xd00>; 2081 qcom,drv-id = <2>; 2082 qcom,tcs-config = <ACTIVE_TCS 2>, 2083 <SLEEP_TCS 3>, 2084 <WAKE_TCS 3>, 2085 <CONTROL_TCS 1>; 2086 2087 rpmhcc: clock-controller { 2088 compatible = "qcom,sdm845-rpmh-clk"; 2089 #clock-cells = <1>; 2090 }; 2091 2092 rpmhpd: power-controller { 2093 compatible = "qcom,sdm845-rpmhpd"; 2094 #power-domain-cells = <1>; 2095 operating-points-v2 = <&rpmhpd_opp_table>; 2096 2097 rpmhpd_opp_table: opp-table { 2098 compatible = "operating-points-v2"; 2099 2100 rpmhpd_opp_ret: opp1 { 2101 opp-level = <16>; 2102 }; 2103 2104 rpmhpd_opp_min_svs: opp2 { 2105 opp-level = <48>; 2106 }; 2107 2108 rpmhpd_opp_low_svs: opp3 { 2109 opp-level = <64>; 2110 }; 2111 2112 rpmhpd_opp_svs: opp4 { 2113 opp-level = <128>; 2114 }; 2115 2116 rpmhpd_opp_svs_l1: opp5 { 2117 opp-level = <192>; 2118 }; 2119 2120 rpmhpd_opp_nom: opp6 { 2121 opp-level = <256>; 2122 }; 2123 2124 rpmhpd_opp_nom_l1: opp7 { 2125 opp-level = <320>; 2126 }; 2127 2128 rpmhpd_opp_nom_l2: opp8 { 2129 opp-level = <336>; 2130 }; 2131 2132 rpmhpd_opp_turbo: opp9 { 2133 opp-level = <384>; 2134 }; 2135 2136 rpmhpd_opp_turbo_l1: opp10 { 2137 opp-level = <416>; 2138 }; 2139 }; 2140 }; 2141 2142 rsc_hlos: interconnect { 2143 compatible = "qcom,sdm845-rsc-hlos"; 2144 #interconnect-cells = <1>; 2145 }; 2146 }; 2147 2148 intc: interrupt-controller@17a00000 { 2149 compatible = "arm,gic-v3"; 2150 #address-cells = <2>; 2151 #size-cells = <2>; 2152 ranges; 2153 #interrupt-cells = <3>; 2154 interrupt-controller; 2155 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 2156 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 2157 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2158 2159 gic-its@17a40000 { 2160 compatible = "arm,gic-v3-its"; 2161 msi-controller; 2162 #msi-cells = <1>; 2163 reg = <0 0x17a40000 0 0x20000>; 2164 status = "disabled"; 2165 }; 2166 }; 2167 2168 timer@17c90000 { 2169 #address-cells = <2>; 2170 #size-cells = <2>; 2171 ranges; 2172 compatible = "arm,armv7-timer-mem"; 2173 reg = <0 0x17c90000 0 0x1000>; 2174 2175 frame@17ca0000 { 2176 frame-number = <0>; 2177 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 2178 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2179 reg = <0 0x17ca0000 0 0x1000>, 2180 <0 0x17cb0000 0 0x1000>; 2181 }; 2182 2183 frame@17cc0000 { 2184 frame-number = <1>; 2185 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 2186 reg = <0 0x17cc0000 0 0x1000>; 2187 status = "disabled"; 2188 }; 2189 2190 frame@17cd0000 { 2191 frame-number = <2>; 2192 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2193 reg = <0 0x17cd0000 0 0x1000>; 2194 status = "disabled"; 2195 }; 2196 2197 frame@17ce0000 { 2198 frame-number = <3>; 2199 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2200 reg = <0 0x17ce0000 0 0x1000>; 2201 status = "disabled"; 2202 }; 2203 2204 frame@17cf0000 { 2205 frame-number = <4>; 2206 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2207 reg = <0 0x17cf0000 0 0x1000>; 2208 status = "disabled"; 2209 }; 2210 2211 frame@17d00000 { 2212 frame-number = <5>; 2213 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2214 reg = <0 0x17d00000 0 0x1000>; 2215 status = "disabled"; 2216 }; 2217 2218 frame@17d10000 { 2219 frame-number = <6>; 2220 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2221 reg = <0 0x17d10000 0 0x1000>; 2222 status = "disabled"; 2223 }; 2224 }; 2225 2226 cpufreq_hw: cpufreq@17d43000 { 2227 compatible = "qcom,cpufreq-hw"; 2228 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 2229 reg-names = "freq-domain0", "freq-domain1"; 2230 2231 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2232 clock-names = "xo", "alternate"; 2233 2234 #freq-domain-cells = <1>; 2235 }; 2236 2237 wifi: wifi@18800000 { 2238 compatible = "qcom,wcn3990-wifi"; 2239 status = "disabled"; 2240 reg = <0 0x18800000 0 0x800000>; 2241 reg-names = "membase"; 2242 memory-region = <&wlan_msa_mem>; 2243 clock-names = "cxo_ref_clk_pin"; 2244 clocks = <&rpmhcc RPMH_RF_CLK2>; 2245 interrupts = 2246 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2247 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2248 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2249 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2250 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2251 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 2252 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2253 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2254 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2255 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2256 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2257 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2258 iommus = <&apps_smmu 0x0040 0x1>; 2259 }; 2260 }; 2261 2262 thermal-zones { 2263 cpu0-thermal { 2264 polling-delay-passive = <250>; 2265 polling-delay = <1000>; 2266 2267 thermal-sensors = <&tsens0 1>; 2268 2269 trips { 2270 cpu0_alert0: trip-point@0 { 2271 temperature = <90000>; 2272 hysteresis = <2000>; 2273 type = "passive"; 2274 }; 2275 2276 cpu0_alert1: trip-point@1 { 2277 temperature = <95000>; 2278 hysteresis = <2000>; 2279 type = "passive"; 2280 }; 2281 2282 cpu0_crit: cpu_crit { 2283 temperature = <110000>; 2284 hysteresis = <1000>; 2285 type = "critical"; 2286 }; 2287 }; 2288 2289 cooling-maps { 2290 map0 { 2291 trip = <&cpu0_alert0>; 2292 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2293 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2294 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2295 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2296 }; 2297 map1 { 2298 trip = <&cpu0_alert1>; 2299 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2300 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2301 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2302 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2303 }; 2304 }; 2305 }; 2306 2307 cpu1-thermal { 2308 polling-delay-passive = <250>; 2309 polling-delay = <1000>; 2310 2311 thermal-sensors = <&tsens0 2>; 2312 2313 trips { 2314 cpu1_alert0: trip-point@0 { 2315 temperature = <90000>; 2316 hysteresis = <2000>; 2317 type = "passive"; 2318 }; 2319 2320 cpu1_alert1: trip-point@1 { 2321 temperature = <95000>; 2322 hysteresis = <2000>; 2323 type = "passive"; 2324 }; 2325 2326 cpu1_crit: cpu_crit { 2327 temperature = <110000>; 2328 hysteresis = <1000>; 2329 type = "critical"; 2330 }; 2331 }; 2332 2333 cooling-maps { 2334 map0 { 2335 trip = <&cpu1_alert0>; 2336 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2337 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2338 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2339 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2340 }; 2341 map1 { 2342 trip = <&cpu1_alert1>; 2343 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2344 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2345 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2346 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2347 }; 2348 }; 2349 }; 2350 2351 cpu2-thermal { 2352 polling-delay-passive = <250>; 2353 polling-delay = <1000>; 2354 2355 thermal-sensors = <&tsens0 3>; 2356 2357 trips { 2358 cpu2_alert0: trip-point@0 { 2359 temperature = <90000>; 2360 hysteresis = <2000>; 2361 type = "passive"; 2362 }; 2363 2364 cpu2_alert1: trip-point@1 { 2365 temperature = <95000>; 2366 hysteresis = <2000>; 2367 type = "passive"; 2368 }; 2369 2370 cpu2_crit: cpu_crit { 2371 temperature = <110000>; 2372 hysteresis = <1000>; 2373 type = "critical"; 2374 }; 2375 }; 2376 2377 cooling-maps { 2378 map0 { 2379 trip = <&cpu2_alert0>; 2380 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2381 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2382 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2383 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2384 }; 2385 map1 { 2386 trip = <&cpu2_alert1>; 2387 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2388 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2389 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2390 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2391 }; 2392 }; 2393 }; 2394 2395 cpu3-thermal { 2396 polling-delay-passive = <250>; 2397 polling-delay = <1000>; 2398 2399 thermal-sensors = <&tsens0 4>; 2400 2401 trips { 2402 cpu3_alert0: trip-point@0 { 2403 temperature = <90000>; 2404 hysteresis = <2000>; 2405 type = "passive"; 2406 }; 2407 2408 cpu3_alert1: trip-point@1 { 2409 temperature = <95000>; 2410 hysteresis = <2000>; 2411 type = "passive"; 2412 }; 2413 2414 cpu3_crit: cpu_crit { 2415 temperature = <110000>; 2416 hysteresis = <1000>; 2417 type = "critical"; 2418 }; 2419 }; 2420 2421 cooling-maps { 2422 map0 { 2423 trip = <&cpu3_alert0>; 2424 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2425 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2426 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2427 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2428 }; 2429 map1 { 2430 trip = <&cpu3_alert1>; 2431 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2432 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2433 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2434 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2435 }; 2436 }; 2437 }; 2438 2439 cpu4-thermal { 2440 polling-delay-passive = <250>; 2441 polling-delay = <1000>; 2442 2443 thermal-sensors = <&tsens0 7>; 2444 2445 trips { 2446 cpu4_alert0: trip-point@0 { 2447 temperature = <90000>; 2448 hysteresis = <2000>; 2449 type = "passive"; 2450 }; 2451 2452 cpu4_alert1: trip-point@1 { 2453 temperature = <95000>; 2454 hysteresis = <2000>; 2455 type = "passive"; 2456 }; 2457 2458 cpu4_crit: cpu_crit { 2459 temperature = <110000>; 2460 hysteresis = <1000>; 2461 type = "critical"; 2462 }; 2463 }; 2464 2465 cooling-maps { 2466 map0 { 2467 trip = <&cpu4_alert0>; 2468 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2469 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2470 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2471 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2472 }; 2473 map1 { 2474 trip = <&cpu4_alert1>; 2475 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2476 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2477 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2478 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2479 }; 2480 }; 2481 }; 2482 2483 cpu5-thermal { 2484 polling-delay-passive = <250>; 2485 polling-delay = <1000>; 2486 2487 thermal-sensors = <&tsens0 8>; 2488 2489 trips { 2490 cpu5_alert0: trip-point@0 { 2491 temperature = <90000>; 2492 hysteresis = <2000>; 2493 type = "passive"; 2494 }; 2495 2496 cpu5_alert1: trip-point@1 { 2497 temperature = <95000>; 2498 hysteresis = <2000>; 2499 type = "passive"; 2500 }; 2501 2502 cpu5_crit: cpu_crit { 2503 temperature = <110000>; 2504 hysteresis = <1000>; 2505 type = "critical"; 2506 }; 2507 }; 2508 2509 cooling-maps { 2510 map0 { 2511 trip = <&cpu5_alert0>; 2512 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2513 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2514 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2515 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2516 }; 2517 map1 { 2518 trip = <&cpu5_alert1>; 2519 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2520 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2521 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2522 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2523 }; 2524 }; 2525 }; 2526 2527 cpu6-thermal { 2528 polling-delay-passive = <250>; 2529 polling-delay = <1000>; 2530 2531 thermal-sensors = <&tsens0 9>; 2532 2533 trips { 2534 cpu6_alert0: trip-point@0 { 2535 temperature = <90000>; 2536 hysteresis = <2000>; 2537 type = "passive"; 2538 }; 2539 2540 cpu6_alert1: trip-point@1 { 2541 temperature = <95000>; 2542 hysteresis = <2000>; 2543 type = "passive"; 2544 }; 2545 2546 cpu6_crit: cpu_crit { 2547 temperature = <110000>; 2548 hysteresis = <1000>; 2549 type = "critical"; 2550 }; 2551 }; 2552 2553 cooling-maps { 2554 map0 { 2555 trip = <&cpu6_alert0>; 2556 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2557 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2558 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2559 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2560 }; 2561 map1 { 2562 trip = <&cpu6_alert1>; 2563 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2564 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2565 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2566 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2567 }; 2568 }; 2569 }; 2570 2571 cpu7-thermal { 2572 polling-delay-passive = <250>; 2573 polling-delay = <1000>; 2574 2575 thermal-sensors = <&tsens0 10>; 2576 2577 trips { 2578 cpu7_alert0: trip-point@0 { 2579 temperature = <90000>; 2580 hysteresis = <2000>; 2581 type = "passive"; 2582 }; 2583 2584 cpu7_alert1: trip-point@1 { 2585 temperature = <95000>; 2586 hysteresis = <2000>; 2587 type = "passive"; 2588 }; 2589 2590 cpu7_crit: cpu_crit { 2591 temperature = <110000>; 2592 hysteresis = <1000>; 2593 type = "critical"; 2594 }; 2595 }; 2596 2597 cooling-maps { 2598 map0 { 2599 trip = <&cpu7_alert0>; 2600 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2601 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2602 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2603 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2604 }; 2605 map1 { 2606 trip = <&cpu7_alert1>; 2607 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2608 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2609 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2610 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2611 }; 2612 }; 2613 }; 2614 }; 2615}; 2616