1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 9#include <dt-bindings/clock/qcom,gcc-sdm845.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/phy/phy-qcom-qusb2.h> 13#include <dt-bindings/reset/qcom,sdm845-aoss.h> 14#include <dt-bindings/soc/qcom,rpmh-rsc.h> 15#include <dt-bindings/clock/qcom,gcc-sdm845.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 i2c4 = &i2c4; 29 i2c5 = &i2c5; 30 i2c6 = &i2c6; 31 i2c7 = &i2c7; 32 i2c8 = &i2c8; 33 i2c9 = &i2c9; 34 i2c10 = &i2c10; 35 i2c11 = &i2c11; 36 i2c12 = &i2c12; 37 i2c13 = &i2c13; 38 i2c14 = &i2c14; 39 i2c15 = &i2c15; 40 spi0 = &spi0; 41 spi1 = &spi1; 42 spi2 = &spi2; 43 spi3 = &spi3; 44 spi4 = &spi4; 45 spi5 = &spi5; 46 spi6 = &spi6; 47 spi7 = &spi7; 48 spi8 = &spi8; 49 spi9 = &spi9; 50 spi10 = &spi10; 51 spi11 = &spi11; 52 spi12 = &spi12; 53 spi13 = &spi13; 54 spi14 = &spi14; 55 spi15 = &spi15; 56 }; 57 58 chosen { }; 59 60 memory@80000000 { 61 device_type = "memory"; 62 /* We expect the bootloader to fill in the size */ 63 reg = <0 0x80000000 0 0>; 64 }; 65 66 reserved-memory { 67 #address-cells = <2>; 68 #size-cells = <2>; 69 ranges; 70 71 memory@85fc0000 { 72 reg = <0 0x85fc0000 0 0x20000>; 73 no-map; 74 }; 75 76 memory@85fe0000 { 77 compatible = "qcom,cmd-db"; 78 reg = <0x0 0x85fe0000 0x0 0x20000>; 79 no-map; 80 }; 81 82 smem_mem: memory@86000000 { 83 reg = <0x0 0x86000000 0x0 0x200000>; 84 no-map; 85 }; 86 87 memory@86200000 { 88 reg = <0 0x86200000 0 0x2d00000>; 89 no-map; 90 }; 91 }; 92 93 cpus { 94 #address-cells = <2>; 95 #size-cells = <0>; 96 97 CPU0: cpu@0 { 98 device_type = "cpu"; 99 compatible = "qcom,kryo385"; 100 reg = <0x0 0x0>; 101 enable-method = "psci"; 102 next-level-cache = <&L2_0>; 103 L2_0: l2-cache { 104 compatible = "cache"; 105 next-level-cache = <&L3_0>; 106 L3_0: l3-cache { 107 compatible = "cache"; 108 }; 109 }; 110 }; 111 112 CPU1: cpu@100 { 113 device_type = "cpu"; 114 compatible = "qcom,kryo385"; 115 reg = <0x0 0x100>; 116 enable-method = "psci"; 117 next-level-cache = <&L2_100>; 118 L2_100: l2-cache { 119 compatible = "cache"; 120 next-level-cache = <&L3_0>; 121 }; 122 }; 123 124 CPU2: cpu@200 { 125 device_type = "cpu"; 126 compatible = "qcom,kryo385"; 127 reg = <0x0 0x200>; 128 enable-method = "psci"; 129 next-level-cache = <&L2_200>; 130 L2_200: l2-cache { 131 compatible = "cache"; 132 next-level-cache = <&L3_0>; 133 }; 134 }; 135 136 CPU3: cpu@300 { 137 device_type = "cpu"; 138 compatible = "qcom,kryo385"; 139 reg = <0x0 0x300>; 140 enable-method = "psci"; 141 next-level-cache = <&L2_300>; 142 L2_300: l2-cache { 143 compatible = "cache"; 144 next-level-cache = <&L3_0>; 145 }; 146 }; 147 148 CPU4: cpu@400 { 149 device_type = "cpu"; 150 compatible = "qcom,kryo385"; 151 reg = <0x0 0x400>; 152 enable-method = "psci"; 153 next-level-cache = <&L2_400>; 154 L2_400: l2-cache { 155 compatible = "cache"; 156 next-level-cache = <&L3_0>; 157 }; 158 }; 159 160 CPU5: cpu@500 { 161 device_type = "cpu"; 162 compatible = "qcom,kryo385"; 163 reg = <0x0 0x500>; 164 enable-method = "psci"; 165 next-level-cache = <&L2_500>; 166 L2_500: l2-cache { 167 compatible = "cache"; 168 next-level-cache = <&L3_0>; 169 }; 170 }; 171 172 CPU6: cpu@600 { 173 device_type = "cpu"; 174 compatible = "qcom,kryo385"; 175 reg = <0x0 0x600>; 176 enable-method = "psci"; 177 next-level-cache = <&L2_600>; 178 L2_600: l2-cache { 179 compatible = "cache"; 180 next-level-cache = <&L3_0>; 181 }; 182 }; 183 184 CPU7: cpu@700 { 185 device_type = "cpu"; 186 compatible = "qcom,kryo385"; 187 reg = <0x0 0x700>; 188 enable-method = "psci"; 189 next-level-cache = <&L2_700>; 190 L2_700: l2-cache { 191 compatible = "cache"; 192 next-level-cache = <&L3_0>; 193 }; 194 }; 195 }; 196 197 pmu { 198 compatible = "arm,armv8-pmuv3"; 199 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 200 }; 201 202 timer { 203 compatible = "arm,armv8-timer"; 204 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 205 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 206 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 207 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 208 }; 209 210 clocks { 211 xo_board: xo-board { 212 compatible = "fixed-clock"; 213 #clock-cells = <0>; 214 clock-frequency = <38400000>; 215 clock-output-names = "xo_board"; 216 }; 217 218 sleep_clk: sleep-clk { 219 compatible = "fixed-clock"; 220 #clock-cells = <0>; 221 clock-frequency = <32764>; 222 }; 223 }; 224 225 tcsr_mutex: hwlock { 226 compatible = "qcom,tcsr-mutex"; 227 syscon = <&tcsr_mutex_regs 0 0x1000>; 228 #hwlock-cells = <1>; 229 }; 230 231 smem { 232 compatible = "qcom,smem"; 233 memory-region = <&smem_mem>; 234 hwlocks = <&tcsr_mutex 3>; 235 }; 236 237 smp2p-cdsp { 238 compatible = "qcom,smp2p"; 239 qcom,smem = <94>, <432>; 240 241 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 242 243 mboxes = <&apss_shared 6>; 244 245 qcom,local-pid = <0>; 246 qcom,remote-pid = <5>; 247 248 cdsp_smp2p_out: master-kernel { 249 qcom,entry-name = "master-kernel"; 250 #qcom,smem-state-cells = <1>; 251 }; 252 253 cdsp_smp2p_in: slave-kernel { 254 qcom,entry-name = "slave-kernel"; 255 256 interrupt-controller; 257 #interrupt-cells = <2>; 258 }; 259 }; 260 261 smp2p-lpass { 262 compatible = "qcom,smp2p"; 263 qcom,smem = <443>, <429>; 264 265 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 266 267 mboxes = <&apss_shared 10>; 268 269 qcom,local-pid = <0>; 270 qcom,remote-pid = <2>; 271 272 adsp_smp2p_out: master-kernel { 273 qcom,entry-name = "master-kernel"; 274 #qcom,smem-state-cells = <1>; 275 }; 276 277 adsp_smp2p_in: slave-kernel { 278 qcom,entry-name = "slave-kernel"; 279 280 interrupt-controller; 281 #interrupt-cells = <2>; 282 }; 283 }; 284 285 smp2p-mpss { 286 compatible = "qcom,smp2p"; 287 qcom,smem = <435>, <428>; 288 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 289 mboxes = <&apss_shared 14>; 290 qcom,local-pid = <0>; 291 qcom,remote-pid = <1>; 292 293 modem_smp2p_out: master-kernel { 294 qcom,entry-name = "master-kernel"; 295 #qcom,smem-state-cells = <1>; 296 }; 297 298 modem_smp2p_in: slave-kernel { 299 qcom,entry-name = "slave-kernel"; 300 interrupt-controller; 301 #interrupt-cells = <2>; 302 }; 303 }; 304 305 smp2p-slpi { 306 compatible = "qcom,smp2p"; 307 qcom,smem = <481>, <430>; 308 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 309 mboxes = <&apss_shared 26>; 310 qcom,local-pid = <0>; 311 qcom,remote-pid = <3>; 312 313 slpi_smp2p_out: master-kernel { 314 qcom,entry-name = "master-kernel"; 315 #qcom,smem-state-cells = <1>; 316 }; 317 318 slpi_smp2p_in: slave-kernel { 319 qcom,entry-name = "slave-kernel"; 320 interrupt-controller; 321 #interrupt-cells = <2>; 322 }; 323 }; 324 325 psci { 326 compatible = "arm,psci-1.0"; 327 method = "smc"; 328 }; 329 330 soc: soc { 331 #address-cells = <1>; 332 #size-cells = <1>; 333 ranges = <0 0 0 0xffffffff>; 334 compatible = "simple-bus"; 335 336 gcc: clock-controller@100000 { 337 compatible = "qcom,gcc-sdm845"; 338 reg = <0x100000 0x1f0000>; 339 #clock-cells = <1>; 340 #reset-cells = <1>; 341 #power-domain-cells = <1>; 342 }; 343 344 qfprom@784000 { 345 compatible = "qcom,qfprom"; 346 reg = <0x784000 0x8ff>; 347 #address-cells = <1>; 348 #size-cells = <1>; 349 350 qusb2p_hstx_trim: hstx-trim-primary@1eb { 351 reg = <0x1eb 0x1>; 352 bits = <1 4>; 353 }; 354 355 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 356 reg = <0x1eb 0x2>; 357 bits = <6 4>; 358 }; 359 }; 360 361 rng: rng@793000 { 362 compatible = "qcom,prng-ee"; 363 reg = <0x00793000 0x1000>; 364 clocks = <&gcc GCC_PRNG_AHB_CLK>; 365 clock-names = "core"; 366 }; 367 368 qupv3_id_0: geniqup@8c0000 { 369 compatible = "qcom,geni-se-qup"; 370 reg = <0x8c0000 0x6000>; 371 clock-names = "m-ahb", "s-ahb"; 372 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 373 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 374 #address-cells = <1>; 375 #size-cells = <1>; 376 ranges; 377 status = "disabled"; 378 379 i2c0: i2c@880000 { 380 compatible = "qcom,geni-i2c"; 381 reg = <0x880000 0x4000>; 382 clock-names = "se"; 383 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 384 pinctrl-names = "default"; 385 pinctrl-0 = <&qup_i2c0_default>; 386 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 status = "disabled"; 390 }; 391 392 spi0: spi@880000 { 393 compatible = "qcom,geni-spi"; 394 reg = <0x880000 0x4000>; 395 clock-names = "se"; 396 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 397 pinctrl-names = "default"; 398 pinctrl-0 = <&qup_spi0_default>; 399 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 status = "disabled"; 403 }; 404 405 uart0: serial@880000 { 406 compatible = "qcom,geni-uart"; 407 reg = <0x880000 0x4000>; 408 clock-names = "se"; 409 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 410 pinctrl-names = "default"; 411 pinctrl-0 = <&qup_uart0_default>; 412 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 413 status = "disabled"; 414 }; 415 416 i2c1: i2c@884000 { 417 compatible = "qcom,geni-i2c"; 418 reg = <0x884000 0x4000>; 419 clock-names = "se"; 420 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 421 pinctrl-names = "default"; 422 pinctrl-0 = <&qup_i2c1_default>; 423 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 status = "disabled"; 427 }; 428 429 spi1: spi@884000 { 430 compatible = "qcom,geni-spi"; 431 reg = <0x884000 0x4000>; 432 clock-names = "se"; 433 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 434 pinctrl-names = "default"; 435 pinctrl-0 = <&qup_spi1_default>; 436 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 437 #address-cells = <1>; 438 #size-cells = <0>; 439 status = "disabled"; 440 }; 441 442 uart1: serial@884000 { 443 compatible = "qcom,geni-uart"; 444 reg = <0x884000 0x4000>; 445 clock-names = "se"; 446 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 447 pinctrl-names = "default"; 448 pinctrl-0 = <&qup_uart1_default>; 449 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 450 status = "disabled"; 451 }; 452 453 i2c2: i2c@888000 { 454 compatible = "qcom,geni-i2c"; 455 reg = <0x888000 0x4000>; 456 clock-names = "se"; 457 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 458 pinctrl-names = "default"; 459 pinctrl-0 = <&qup_i2c2_default>; 460 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 461 #address-cells = <1>; 462 #size-cells = <0>; 463 status = "disabled"; 464 }; 465 466 spi2: spi@888000 { 467 compatible = "qcom,geni-spi"; 468 reg = <0x888000 0x4000>; 469 clock-names = "se"; 470 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 471 pinctrl-names = "default"; 472 pinctrl-0 = <&qup_spi2_default>; 473 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 474 #address-cells = <1>; 475 #size-cells = <0>; 476 status = "disabled"; 477 }; 478 479 uart2: serial@888000 { 480 compatible = "qcom,geni-uart"; 481 reg = <0x888000 0x4000>; 482 clock-names = "se"; 483 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 484 pinctrl-names = "default"; 485 pinctrl-0 = <&qup_uart2_default>; 486 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 487 status = "disabled"; 488 }; 489 490 i2c3: i2c@88c000 { 491 compatible = "qcom,geni-i2c"; 492 reg = <0x88c000 0x4000>; 493 clock-names = "se"; 494 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 495 pinctrl-names = "default"; 496 pinctrl-0 = <&qup_i2c3_default>; 497 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 498 #address-cells = <1>; 499 #size-cells = <0>; 500 status = "disabled"; 501 }; 502 503 spi3: spi@88c000 { 504 compatible = "qcom,geni-spi"; 505 reg = <0x88c000 0x4000>; 506 clock-names = "se"; 507 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 508 pinctrl-names = "default"; 509 pinctrl-0 = <&qup_spi3_default>; 510 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 status = "disabled"; 514 }; 515 516 uart3: serial@88c000 { 517 compatible = "qcom,geni-uart"; 518 reg = <0x88c000 0x4000>; 519 clock-names = "se"; 520 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 521 pinctrl-names = "default"; 522 pinctrl-0 = <&qup_uart3_default>; 523 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 524 status = "disabled"; 525 }; 526 527 i2c4: i2c@890000 { 528 compatible = "qcom,geni-i2c"; 529 reg = <0x890000 0x4000>; 530 clock-names = "se"; 531 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 532 pinctrl-names = "default"; 533 pinctrl-0 = <&qup_i2c4_default>; 534 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 status = "disabled"; 538 }; 539 540 spi4: spi@890000 { 541 compatible = "qcom,geni-spi"; 542 reg = <0x890000 0x4000>; 543 clock-names = "se"; 544 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 545 pinctrl-names = "default"; 546 pinctrl-0 = <&qup_spi4_default>; 547 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 status = "disabled"; 551 }; 552 553 uart4: serial@890000 { 554 compatible = "qcom,geni-uart"; 555 reg = <0x890000 0x4000>; 556 clock-names = "se"; 557 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 558 pinctrl-names = "default"; 559 pinctrl-0 = <&qup_uart4_default>; 560 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 561 status = "disabled"; 562 }; 563 564 i2c5: i2c@894000 { 565 compatible = "qcom,geni-i2c"; 566 reg = <0x894000 0x4000>; 567 clock-names = "se"; 568 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 569 pinctrl-names = "default"; 570 pinctrl-0 = <&qup_i2c5_default>; 571 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 572 #address-cells = <1>; 573 #size-cells = <0>; 574 status = "disabled"; 575 }; 576 577 spi5: spi@894000 { 578 compatible = "qcom,geni-spi"; 579 reg = <0x894000 0x4000>; 580 clock-names = "se"; 581 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 582 pinctrl-names = "default"; 583 pinctrl-0 = <&qup_spi5_default>; 584 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 status = "disabled"; 588 }; 589 590 uart5: serial@894000 { 591 compatible = "qcom,geni-uart"; 592 reg = <0x894000 0x4000>; 593 clock-names = "se"; 594 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 595 pinctrl-names = "default"; 596 pinctrl-0 = <&qup_uart5_default>; 597 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 598 status = "disabled"; 599 }; 600 601 i2c6: i2c@898000 { 602 compatible = "qcom,geni-i2c"; 603 reg = <0x898000 0x4000>; 604 clock-names = "se"; 605 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 606 pinctrl-names = "default"; 607 pinctrl-0 = <&qup_i2c6_default>; 608 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 status = "disabled"; 612 }; 613 614 spi6: spi@898000 { 615 compatible = "qcom,geni-spi"; 616 reg = <0x898000 0x4000>; 617 clock-names = "se"; 618 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 619 pinctrl-names = "default"; 620 pinctrl-0 = <&qup_spi6_default>; 621 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 status = "disabled"; 625 }; 626 627 uart6: serial@898000 { 628 compatible = "qcom,geni-uart"; 629 reg = <0x898000 0x4000>; 630 clock-names = "se"; 631 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 632 pinctrl-names = "default"; 633 pinctrl-0 = <&qup_uart6_default>; 634 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 635 status = "disabled"; 636 }; 637 638 i2c7: i2c@89c000 { 639 compatible = "qcom,geni-i2c"; 640 reg = <0x89c000 0x4000>; 641 clock-names = "se"; 642 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 643 pinctrl-names = "default"; 644 pinctrl-0 = <&qup_i2c7_default>; 645 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 646 #address-cells = <1>; 647 #size-cells = <0>; 648 status = "disabled"; 649 }; 650 651 spi7: spi@89c000 { 652 compatible = "qcom,geni-spi"; 653 reg = <0x89c000 0x4000>; 654 clock-names = "se"; 655 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 656 pinctrl-names = "default"; 657 pinctrl-0 = <&qup_spi7_default>; 658 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 659 #address-cells = <1>; 660 #size-cells = <0>; 661 status = "disabled"; 662 }; 663 664 uart7: serial@89c000 { 665 compatible = "qcom,geni-uart"; 666 reg = <0x89c000 0x4000>; 667 clock-names = "se"; 668 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 669 pinctrl-names = "default"; 670 pinctrl-0 = <&qup_uart7_default>; 671 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 672 status = "disabled"; 673 }; 674 }; 675 676 qupv3_id_1: geniqup@ac0000 { 677 compatible = "qcom,geni-se-qup"; 678 reg = <0xac0000 0x6000>; 679 clock-names = "m-ahb", "s-ahb"; 680 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 681 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 682 #address-cells = <1>; 683 #size-cells = <1>; 684 ranges; 685 status = "disabled"; 686 687 i2c8: i2c@a80000 { 688 compatible = "qcom,geni-i2c"; 689 reg = <0xa80000 0x4000>; 690 clock-names = "se"; 691 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 692 pinctrl-names = "default"; 693 pinctrl-0 = <&qup_i2c8_default>; 694 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 695 #address-cells = <1>; 696 #size-cells = <0>; 697 status = "disabled"; 698 }; 699 700 spi8: spi@a80000 { 701 compatible = "qcom,geni-spi"; 702 reg = <0xa80000 0x4000>; 703 clock-names = "se"; 704 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 705 pinctrl-names = "default"; 706 pinctrl-0 = <&qup_spi8_default>; 707 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 status = "disabled"; 711 }; 712 713 uart8: serial@a80000 { 714 compatible = "qcom,geni-uart"; 715 reg = <0xa80000 0x4000>; 716 clock-names = "se"; 717 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 718 pinctrl-names = "default"; 719 pinctrl-0 = <&qup_uart8_default>; 720 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 721 status = "disabled"; 722 }; 723 724 i2c9: i2c@a84000 { 725 compatible = "qcom,geni-i2c"; 726 reg = <0xa84000 0x4000>; 727 clock-names = "se"; 728 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 729 pinctrl-names = "default"; 730 pinctrl-0 = <&qup_i2c9_default>; 731 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 732 #address-cells = <1>; 733 #size-cells = <0>; 734 status = "disabled"; 735 }; 736 737 spi9: spi@a84000 { 738 compatible = "qcom,geni-spi"; 739 reg = <0xa84000 0x4000>; 740 clock-names = "se"; 741 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 742 pinctrl-names = "default"; 743 pinctrl-0 = <&qup_spi9_default>; 744 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 745 #address-cells = <1>; 746 #size-cells = <0>; 747 status = "disabled"; 748 }; 749 750 uart9: serial@a84000 { 751 compatible = "qcom,geni-debug-uart"; 752 reg = <0xa84000 0x4000>; 753 clock-names = "se"; 754 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 755 pinctrl-names = "default"; 756 pinctrl-0 = <&qup_uart9_default>; 757 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 758 status = "disabled"; 759 }; 760 761 i2c10: i2c@a88000 { 762 compatible = "qcom,geni-i2c"; 763 reg = <0xa88000 0x4000>; 764 clock-names = "se"; 765 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 766 pinctrl-names = "default"; 767 pinctrl-0 = <&qup_i2c10_default>; 768 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 769 #address-cells = <1>; 770 #size-cells = <0>; 771 status = "disabled"; 772 }; 773 774 spi10: spi@a88000 { 775 compatible = "qcom,geni-spi"; 776 reg = <0xa88000 0x4000>; 777 clock-names = "se"; 778 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 779 pinctrl-names = "default"; 780 pinctrl-0 = <&qup_spi10_default>; 781 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 782 #address-cells = <1>; 783 #size-cells = <0>; 784 status = "disabled"; 785 }; 786 787 uart10: serial@a88000 { 788 compatible = "qcom,geni-uart"; 789 reg = <0xa88000 0x4000>; 790 clock-names = "se"; 791 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 792 pinctrl-names = "default"; 793 pinctrl-0 = <&qup_uart10_default>; 794 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 795 status = "disabled"; 796 }; 797 798 i2c11: i2c@a8c000 { 799 compatible = "qcom,geni-i2c"; 800 reg = <0xa8c000 0x4000>; 801 clock-names = "se"; 802 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 803 pinctrl-names = "default"; 804 pinctrl-0 = <&qup_i2c11_default>; 805 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 status = "disabled"; 809 }; 810 811 spi11: spi@a8c000 { 812 compatible = "qcom,geni-spi"; 813 reg = <0xa8c000 0x4000>; 814 clock-names = "se"; 815 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 816 pinctrl-names = "default"; 817 pinctrl-0 = <&qup_spi11_default>; 818 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 819 #address-cells = <1>; 820 #size-cells = <0>; 821 status = "disabled"; 822 }; 823 824 uart11: serial@a8c000 { 825 compatible = "qcom,geni-uart"; 826 reg = <0xa8c000 0x4000>; 827 clock-names = "se"; 828 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 829 pinctrl-names = "default"; 830 pinctrl-0 = <&qup_uart11_default>; 831 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 832 status = "disabled"; 833 }; 834 835 i2c12: i2c@a90000 { 836 compatible = "qcom,geni-i2c"; 837 reg = <0xa90000 0x4000>; 838 clock-names = "se"; 839 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 840 pinctrl-names = "default"; 841 pinctrl-0 = <&qup_i2c12_default>; 842 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 843 #address-cells = <1>; 844 #size-cells = <0>; 845 status = "disabled"; 846 }; 847 848 spi12: spi@a90000 { 849 compatible = "qcom,geni-spi"; 850 reg = <0xa90000 0x4000>; 851 clock-names = "se"; 852 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 853 pinctrl-names = "default"; 854 pinctrl-0 = <&qup_spi12_default>; 855 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 856 #address-cells = <1>; 857 #size-cells = <0>; 858 status = "disabled"; 859 }; 860 861 uart12: serial@a90000 { 862 compatible = "qcom,geni-uart"; 863 reg = <0xa90000 0x4000>; 864 clock-names = "se"; 865 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 866 pinctrl-names = "default"; 867 pinctrl-0 = <&qup_uart12_default>; 868 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 869 status = "disabled"; 870 }; 871 872 i2c13: i2c@a94000 { 873 compatible = "qcom,geni-i2c"; 874 reg = <0xa94000 0x4000>; 875 clock-names = "se"; 876 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 877 pinctrl-names = "default"; 878 pinctrl-0 = <&qup_i2c13_default>; 879 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 880 #address-cells = <1>; 881 #size-cells = <0>; 882 status = "disabled"; 883 }; 884 885 spi13: spi@a94000 { 886 compatible = "qcom,geni-spi"; 887 reg = <0xa94000 0x4000>; 888 clock-names = "se"; 889 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 890 pinctrl-names = "default"; 891 pinctrl-0 = <&qup_spi13_default>; 892 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 893 #address-cells = <1>; 894 #size-cells = <0>; 895 status = "disabled"; 896 }; 897 898 uart13: serial@a94000 { 899 compatible = "qcom,geni-uart"; 900 reg = <0xa94000 0x4000>; 901 clock-names = "se"; 902 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 903 pinctrl-names = "default"; 904 pinctrl-0 = <&qup_uart13_default>; 905 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 906 status = "disabled"; 907 }; 908 909 i2c14: i2c@a98000 { 910 compatible = "qcom,geni-i2c"; 911 reg = <0xa98000 0x4000>; 912 clock-names = "se"; 913 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 914 pinctrl-names = "default"; 915 pinctrl-0 = <&qup_i2c14_default>; 916 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 status = "disabled"; 920 }; 921 922 spi14: spi@a98000 { 923 compatible = "qcom,geni-spi"; 924 reg = <0xa98000 0x4000>; 925 clock-names = "se"; 926 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 927 pinctrl-names = "default"; 928 pinctrl-0 = <&qup_spi14_default>; 929 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 930 #address-cells = <1>; 931 #size-cells = <0>; 932 status = "disabled"; 933 }; 934 935 uart14: serial@a98000 { 936 compatible = "qcom,geni-uart"; 937 reg = <0xa98000 0x4000>; 938 clock-names = "se"; 939 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 940 pinctrl-names = "default"; 941 pinctrl-0 = <&qup_uart14_default>; 942 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 943 status = "disabled"; 944 }; 945 946 i2c15: i2c@a9c000 { 947 compatible = "qcom,geni-i2c"; 948 reg = <0xa9c000 0x4000>; 949 clock-names = "se"; 950 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 951 pinctrl-names = "default"; 952 pinctrl-0 = <&qup_i2c15_default>; 953 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 954 #address-cells = <1>; 955 #size-cells = <0>; 956 status = "disabled"; 957 }; 958 959 spi15: spi@a9c000 { 960 compatible = "qcom,geni-spi"; 961 reg = <0xa9c000 0x4000>; 962 clock-names = "se"; 963 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 964 pinctrl-names = "default"; 965 pinctrl-0 = <&qup_spi15_default>; 966 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 967 #address-cells = <1>; 968 #size-cells = <0>; 969 status = "disabled"; 970 }; 971 972 uart15: serial@a9c000 { 973 compatible = "qcom,geni-uart"; 974 reg = <0xa9c000 0x4000>; 975 clock-names = "se"; 976 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 977 pinctrl-names = "default"; 978 pinctrl-0 = <&qup_uart15_default>; 979 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 980 status = "disabled"; 981 }; 982 }; 983 984 tcsr_mutex_regs: syscon@1f40000 { 985 compatible = "syscon"; 986 reg = <0x1f40000 0x40000>; 987 }; 988 989 tlmm: pinctrl@3400000 { 990 compatible = "qcom,sdm845-pinctrl"; 991 reg = <0x03400000 0xc00000>; 992 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 993 gpio-controller; 994 #gpio-cells = <2>; 995 interrupt-controller; 996 #interrupt-cells = <2>; 997 998 qup_i2c0_default: qup-i2c0-default { 999 pinmux { 1000 pins = "gpio0", "gpio1"; 1001 function = "qup0"; 1002 }; 1003 }; 1004 1005 qup_i2c1_default: qup-i2c1-default { 1006 pinmux { 1007 pins = "gpio17", "gpio18"; 1008 function = "qup1"; 1009 }; 1010 }; 1011 1012 qup_i2c2_default: qup-i2c2-default { 1013 pinmux { 1014 pins = "gpio27", "gpio28"; 1015 function = "qup2"; 1016 }; 1017 }; 1018 1019 qup_i2c3_default: qup-i2c3-default { 1020 pinmux { 1021 pins = "gpio41", "gpio42"; 1022 function = "qup3"; 1023 }; 1024 }; 1025 1026 qup_i2c4_default: qup-i2c4-default { 1027 pinmux { 1028 pins = "gpio89", "gpio90"; 1029 function = "qup4"; 1030 }; 1031 }; 1032 1033 qup_i2c5_default: qup-i2c5-default { 1034 pinmux { 1035 pins = "gpio85", "gpio86"; 1036 function = "qup5"; 1037 }; 1038 }; 1039 1040 qup_i2c6_default: qup-i2c6-default { 1041 pinmux { 1042 pins = "gpio45", "gpio46"; 1043 function = "qup6"; 1044 }; 1045 }; 1046 1047 qup_i2c7_default: qup-i2c7-default { 1048 pinmux { 1049 pins = "gpio93", "gpio94"; 1050 function = "qup7"; 1051 }; 1052 }; 1053 1054 qup_i2c8_default: qup-i2c8-default { 1055 pinmux { 1056 pins = "gpio65", "gpio66"; 1057 function = "qup8"; 1058 }; 1059 }; 1060 1061 qup_i2c9_default: qup-i2c9-default { 1062 pinmux { 1063 pins = "gpio6", "gpio7"; 1064 function = "qup9"; 1065 }; 1066 }; 1067 1068 qup_i2c10_default: qup-i2c10-default { 1069 pinmux { 1070 pins = "gpio55", "gpio56"; 1071 function = "qup10"; 1072 }; 1073 }; 1074 1075 qup_i2c11_default: qup-i2c11-default { 1076 pinmux { 1077 pins = "gpio31", "gpio32"; 1078 function = "qup11"; 1079 }; 1080 }; 1081 1082 qup_i2c12_default: qup-i2c12-default { 1083 pinmux { 1084 pins = "gpio49", "gpio50"; 1085 function = "qup12"; 1086 }; 1087 }; 1088 1089 qup_i2c13_default: qup-i2c13-default { 1090 pinmux { 1091 pins = "gpio105", "gpio106"; 1092 function = "qup13"; 1093 }; 1094 }; 1095 1096 qup_i2c14_default: qup-i2c14-default { 1097 pinmux { 1098 pins = "gpio33", "gpio34"; 1099 function = "qup14"; 1100 }; 1101 }; 1102 1103 qup_i2c15_default: qup-i2c15-default { 1104 pinmux { 1105 pins = "gpio81", "gpio82"; 1106 function = "qup15"; 1107 }; 1108 }; 1109 1110 qup_spi0_default: qup-spi0-default { 1111 pinmux { 1112 pins = "gpio0", "gpio1", 1113 "gpio2", "gpio3"; 1114 function = "qup0"; 1115 }; 1116 }; 1117 1118 qup_spi1_default: qup-spi1-default { 1119 pinmux { 1120 pins = "gpio17", "gpio18", 1121 "gpio19", "gpio20"; 1122 function = "qup1"; 1123 }; 1124 }; 1125 1126 qup_spi2_default: qup-spi2-default { 1127 pinmux { 1128 pins = "gpio27", "gpio28", 1129 "gpio29", "gpio30"; 1130 function = "qup2"; 1131 }; 1132 }; 1133 1134 qup_spi3_default: qup-spi3-default { 1135 pinmux { 1136 pins = "gpio41", "gpio42", 1137 "gpio43", "gpio44"; 1138 function = "qup3"; 1139 }; 1140 }; 1141 1142 qup_spi4_default: qup-spi4-default { 1143 pinmux { 1144 pins = "gpio89", "gpio90", 1145 "gpio91", "gpio92"; 1146 function = "qup4"; 1147 }; 1148 }; 1149 1150 qup_spi5_default: qup-spi5-default { 1151 pinmux { 1152 pins = "gpio85", "gpio86", 1153 "gpio87", "gpio88"; 1154 function = "qup5"; 1155 }; 1156 }; 1157 1158 qup_spi6_default: qup-spi6-default { 1159 pinmux { 1160 pins = "gpio45", "gpio46", 1161 "gpio47", "gpio48"; 1162 function = "qup6"; 1163 }; 1164 }; 1165 1166 qup_spi7_default: qup-spi7-default { 1167 pinmux { 1168 pins = "gpio93", "gpio94", 1169 "gpio95", "gpio96"; 1170 function = "qup7"; 1171 }; 1172 }; 1173 1174 qup_spi8_default: qup-spi8-default { 1175 pinmux { 1176 pins = "gpio65", "gpio66", 1177 "gpio67", "gpio68"; 1178 function = "qup8"; 1179 }; 1180 }; 1181 1182 qup_spi9_default: qup-spi9-default { 1183 pinmux { 1184 pins = "gpio6", "gpio7", 1185 "gpio4", "gpio5"; 1186 function = "qup9"; 1187 }; 1188 }; 1189 1190 qup_spi10_default: qup-spi10-default { 1191 pinmux { 1192 pins = "gpio55", "gpio56", 1193 "gpio53", "gpio54"; 1194 function = "qup10"; 1195 }; 1196 }; 1197 1198 qup_spi11_default: qup-spi11-default { 1199 pinmux { 1200 pins = "gpio31", "gpio32", 1201 "gpio33", "gpio34"; 1202 function = "qup11"; 1203 }; 1204 }; 1205 1206 qup_spi12_default: qup-spi12-default { 1207 pinmux { 1208 pins = "gpio49", "gpio50", 1209 "gpio51", "gpio52"; 1210 function = "qup12"; 1211 }; 1212 }; 1213 1214 qup_spi13_default: qup-spi13-default { 1215 pinmux { 1216 pins = "gpio105", "gpio106", 1217 "gpio107", "gpio108"; 1218 function = "qup13"; 1219 }; 1220 }; 1221 1222 qup_spi14_default: qup-spi14-default { 1223 pinmux { 1224 pins = "gpio33", "gpio34", 1225 "gpio31", "gpio32"; 1226 function = "qup14"; 1227 }; 1228 }; 1229 1230 qup_spi15_default: qup-spi15-default { 1231 pinmux { 1232 pins = "gpio81", "gpio82", 1233 "gpio83", "gpio84"; 1234 function = "qup15"; 1235 }; 1236 }; 1237 1238 qup_uart0_default: qup-uart0-default { 1239 pinmux { 1240 pins = "gpio2", "gpio3"; 1241 function = "qup0"; 1242 }; 1243 }; 1244 1245 qup_uart1_default: qup-uart1-default { 1246 pinmux { 1247 pins = "gpio19", "gpio20"; 1248 function = "qup1"; 1249 }; 1250 }; 1251 1252 qup_uart2_default: qup-uart2-default { 1253 pinmux { 1254 pins = "gpio29", "gpio30"; 1255 function = "qup2"; 1256 }; 1257 }; 1258 1259 qup_uart3_default: qup-uart3-default { 1260 pinmux { 1261 pins = "gpio43", "gpio44"; 1262 function = "qup3"; 1263 }; 1264 }; 1265 1266 qup_uart4_default: qup-uart4-default { 1267 pinmux { 1268 pins = "gpio91", "gpio92"; 1269 function = "qup4"; 1270 }; 1271 }; 1272 1273 qup_uart5_default: qup-uart5-default { 1274 pinmux { 1275 pins = "gpio87", "gpio88"; 1276 function = "qup5"; 1277 }; 1278 }; 1279 1280 qup_uart6_default: qup-uart6-default { 1281 pinmux { 1282 pins = "gpio47", "gpio48"; 1283 function = "qup6"; 1284 }; 1285 }; 1286 1287 qup_uart7_default: qup-uart7-default { 1288 pinmux { 1289 pins = "gpio95", "gpio96"; 1290 function = "qup7"; 1291 }; 1292 }; 1293 1294 qup_uart8_default: qup-uart8-default { 1295 pinmux { 1296 pins = "gpio67", "gpio68"; 1297 function = "qup8"; 1298 }; 1299 }; 1300 1301 qup_uart9_default: qup-uart9-default { 1302 pinmux { 1303 pins = "gpio4", "gpio5"; 1304 function = "qup9"; 1305 }; 1306 }; 1307 1308 qup_uart10_default: qup-uart10-default { 1309 pinmux { 1310 pins = "gpio53", "gpio54"; 1311 function = "qup10"; 1312 }; 1313 }; 1314 1315 qup_uart11_default: qup-uart11-default { 1316 pinmux { 1317 pins = "gpio33", "gpio34"; 1318 function = "qup11"; 1319 }; 1320 }; 1321 1322 qup_uart12_default: qup-uart12-default { 1323 pinmux { 1324 pins = "gpio51", "gpio52"; 1325 function = "qup12"; 1326 }; 1327 }; 1328 1329 qup_uart13_default: qup-uart13-default { 1330 pinmux { 1331 pins = "gpio107", "gpio108"; 1332 function = "qup13"; 1333 }; 1334 }; 1335 1336 qup_uart14_default: qup-uart14-default { 1337 pinmux { 1338 pins = "gpio31", "gpio32"; 1339 function = "qup14"; 1340 }; 1341 }; 1342 1343 qup_uart15_default: qup-uart15-default { 1344 pinmux { 1345 pins = "gpio83", "gpio84"; 1346 function = "qup15"; 1347 }; 1348 }; 1349 }; 1350 1351 usb_1_hsphy: phy@88e2000 { 1352 compatible = "qcom,sdm845-qusb2-phy"; 1353 reg = <0x88e2000 0x400>; 1354 status = "disabled"; 1355 #phy-cells = <0>; 1356 1357 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1358 <&rpmhcc RPMH_CXO_CLK>; 1359 clock-names = "cfg_ahb", "ref"; 1360 1361 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1362 1363 nvmem-cells = <&qusb2p_hstx_trim>; 1364 }; 1365 1366 usb_2_hsphy: phy@88e3000 { 1367 compatible = "qcom,sdm845-qusb2-phy"; 1368 reg = <0x88e3000 0x400>; 1369 status = "disabled"; 1370 #phy-cells = <0>; 1371 1372 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1373 <&rpmhcc RPMH_CXO_CLK>; 1374 clock-names = "cfg_ahb", "ref"; 1375 1376 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1377 1378 nvmem-cells = <&qusb2s_hstx_trim>; 1379 }; 1380 1381 usb_1_qmpphy: phy@88e9000 { 1382 compatible = "qcom,sdm845-qmp-usb3-phy"; 1383 reg = <0x88e9000 0x18c>, 1384 <0x88e8000 0x10>; 1385 reg-names = "reg-base", "dp_com"; 1386 status = "disabled"; 1387 #clock-cells = <1>; 1388 #address-cells = <1>; 1389 #size-cells = <1>; 1390 ranges; 1391 1392 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1393 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1394 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 1395 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 1396 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 1397 1398 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 1399 <&gcc GCC_USB3_PHY_PRIM_BCR>; 1400 reset-names = "phy", "common"; 1401 1402 usb_1_ssphy: lane@88e9200 { 1403 reg = <0x88e9200 0x128>, 1404 <0x88e9400 0x200>, 1405 <0x88e9c00 0x218>, 1406 <0x88e9a00 0x100>; 1407 #phy-cells = <0>; 1408 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1409 clock-names = "pipe0"; 1410 clock-output-names = "usb3_phy_pipe_clk_src"; 1411 }; 1412 }; 1413 1414 usb_2_qmpphy: phy@88eb000 { 1415 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 1416 reg = <0x88eb000 0x18c>; 1417 status = "disabled"; 1418 #clock-cells = <1>; 1419 #address-cells = <1>; 1420 #size-cells = <1>; 1421 ranges; 1422 1423 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 1424 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1425 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 1426 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 1427 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 1428 1429 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 1430 <&gcc GCC_USB3_PHY_SEC_BCR>; 1431 reset-names = "phy", "common"; 1432 1433 usb_2_ssphy: lane@88eb200 { 1434 reg = <0x88eb200 0x128>, 1435 <0x88eb400 0x1fc>, 1436 <0x88eb800 0x218>, 1437 <0x88e9600 0x70>; 1438 #phy-cells = <0>; 1439 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 1440 clock-names = "pipe0"; 1441 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 1442 }; 1443 }; 1444 1445 usb_1: usb@a6f8800 { 1446 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 1447 reg = <0xa6f8800 0x400>; 1448 status = "disabled"; 1449 #address-cells = <1>; 1450 #size-cells = <1>; 1451 ranges; 1452 1453 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1454 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1455 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1456 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1457 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 1458 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1459 "sleep"; 1460 1461 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1462 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1463 assigned-clock-rates = <19200000>, <150000000>; 1464 1465 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 1469 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1470 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1471 1472 power-domains = <&gcc USB30_PRIM_GDSC>; 1473 1474 resets = <&gcc GCC_USB30_PRIM_BCR>; 1475 1476 usb_1_dwc3: dwc3@a600000 { 1477 compatible = "snps,dwc3"; 1478 reg = <0xa600000 0xcd00>; 1479 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1480 snps,dis_u2_susphy_quirk; 1481 snps,dis_enblslpm_quirk; 1482 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1483 phy-names = "usb2-phy", "usb3-phy"; 1484 }; 1485 }; 1486 1487 usb_2: usb@a8f8800 { 1488 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 1489 reg = <0xa8f8800 0x400>; 1490 status = "disabled"; 1491 #address-cells = <1>; 1492 #size-cells = <1>; 1493 ranges; 1494 1495 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 1496 <&gcc GCC_USB30_SEC_MASTER_CLK>, 1497 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 1498 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1499 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 1500 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1501 "sleep"; 1502 1503 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1504 <&gcc GCC_USB30_SEC_MASTER_CLK>; 1505 assigned-clock-rates = <19200000>, <150000000>; 1506 1507 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1508 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 1511 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1512 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1513 1514 power-domains = <&gcc USB30_SEC_GDSC>; 1515 1516 resets = <&gcc GCC_USB30_SEC_BCR>; 1517 1518 usb_2_dwc3: dwc3@a800000 { 1519 compatible = "snps,dwc3"; 1520 reg = <0xa800000 0xcd00>; 1521 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1522 snps,dis_u2_susphy_quirk; 1523 snps,dis_enblslpm_quirk; 1524 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 1525 phy-names = "usb2-phy", "usb3-phy"; 1526 }; 1527 }; 1528 1529 dispcc: clock-controller@af00000 { 1530 compatible = "qcom,sdm845-dispcc"; 1531 reg = <0xaf00000 0x10000>; 1532 #clock-cells = <1>; 1533 #reset-cells = <1>; 1534 #power-domain-cells = <1>; 1535 }; 1536 1537 tsens0: thermal-sensor@c263000 { 1538 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 1539 reg = <0xc263000 0x1ff>, /* TM */ 1540 <0xc222000 0x1ff>; /* SROT */ 1541 #qcom,sensors = <13>; 1542 #thermal-sensor-cells = <1>; 1543 }; 1544 1545 tsens1: thermal-sensor@c265000 { 1546 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 1547 reg = <0xc265000 0x1ff>, /* TM */ 1548 <0xc223000 0x1ff>; /* SROT */ 1549 #qcom,sensors = <8>; 1550 #thermal-sensor-cells = <1>; 1551 }; 1552 1553 aoss_reset: reset-controller@c2a0000 { 1554 compatible = "qcom,sdm845-aoss-cc"; 1555 reg = <0xc2a0000 0x31000>; 1556 #reset-cells = <1>; 1557 }; 1558 1559 spmi_bus: spmi@c440000 { 1560 compatible = "qcom,spmi-pmic-arb"; 1561 reg = <0xc440000 0x1100>, 1562 <0xc600000 0x2000000>, 1563 <0xe600000 0x100000>, 1564 <0xe700000 0xa0000>, 1565 <0xc40a000 0x26000>; 1566 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1567 interrupt-names = "periph_irq"; 1568 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 1569 qcom,ee = <0>; 1570 qcom,channel = <0>; 1571 #address-cells = <2>; 1572 #size-cells = <0>; 1573 interrupt-controller; 1574 #interrupt-cells = <4>; 1575 cell-index = <0>; 1576 }; 1577 1578 apss_shared: mailbox@17990000 { 1579 compatible = "qcom,sdm845-apss-shared"; 1580 reg = <0x17990000 0x1000>; 1581 #mbox-cells = <1>; 1582 }; 1583 1584 apps_rsc: rsc@179c0000 { 1585 label = "apps_rsc"; 1586 compatible = "qcom,rpmh-rsc"; 1587 reg = <0x179c0000 0x10000>, 1588 <0x179d0000 0x10000>, 1589 <0x179e0000 0x10000>; 1590 reg-names = "drv-0", "drv-1", "drv-2"; 1591 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1594 qcom,tcs-offset = <0xd00>; 1595 qcom,drv-id = <2>; 1596 qcom,tcs-config = <ACTIVE_TCS 2>, 1597 <SLEEP_TCS 3>, 1598 <WAKE_TCS 3>, 1599 <CONTROL_TCS 1>; 1600 1601 rpmhcc: clock-controller { 1602 compatible = "qcom,sdm845-rpmh-clk"; 1603 #clock-cells = <1>; 1604 }; 1605 }; 1606 1607 intc: interrupt-controller@17a00000 { 1608 compatible = "arm,gic-v3"; 1609 #address-cells = <1>; 1610 #size-cells = <1>; 1611 ranges; 1612 #interrupt-cells = <3>; 1613 interrupt-controller; 1614 reg = <0x17a00000 0x10000>, /* GICD */ 1615 <0x17a60000 0x100000>; /* GICR * 8 */ 1616 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1617 1618 gic-its@17a40000 { 1619 compatible = "arm,gic-v3-its"; 1620 msi-controller; 1621 #msi-cells = <1>; 1622 reg = <0x17a40000 0x20000>; 1623 status = "disabled"; 1624 }; 1625 }; 1626 1627 timer@17c90000 { 1628 #address-cells = <1>; 1629 #size-cells = <1>; 1630 ranges; 1631 compatible = "arm,armv7-timer-mem"; 1632 reg = <0x17c90000 0x1000>; 1633 1634 frame@17ca0000 { 1635 frame-number = <0>; 1636 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1638 reg = <0x17ca0000 0x1000>, 1639 <0x17cb0000 0x1000>; 1640 }; 1641 1642 frame@17cc0000 { 1643 frame-number = <1>; 1644 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1645 reg = <0x17cc0000 0x1000>; 1646 status = "disabled"; 1647 }; 1648 1649 frame@17cd0000 { 1650 frame-number = <2>; 1651 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1652 reg = <0x17cd0000 0x1000>; 1653 status = "disabled"; 1654 }; 1655 1656 frame@17ce0000 { 1657 frame-number = <3>; 1658 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1659 reg = <0x17ce0000 0x1000>; 1660 status = "disabled"; 1661 }; 1662 1663 frame@17cf0000 { 1664 frame-number = <4>; 1665 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1666 reg = <0x17cf0000 0x1000>; 1667 status = "disabled"; 1668 }; 1669 1670 frame@17d00000 { 1671 frame-number = <5>; 1672 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1673 reg = <0x17d00000 0x1000>; 1674 status = "disabled"; 1675 }; 1676 1677 frame@17d10000 { 1678 frame-number = <6>; 1679 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1680 reg = <0x17d10000 0x1000>; 1681 status = "disabled"; 1682 }; 1683 }; 1684 }; 1685 1686 thermal-zones { 1687 cpu0-thermal { 1688 polling-delay-passive = <250>; 1689 polling-delay = <1000>; 1690 1691 thermal-sensors = <&tsens0 1>; 1692 1693 trips { 1694 cpu_alert0: trip0 { 1695 temperature = <75000>; 1696 hysteresis = <2000>; 1697 type = "passive"; 1698 }; 1699 1700 cpu_crit0: trip1 { 1701 temperature = <110000>; 1702 hysteresis = <1000>; 1703 type = "critical"; 1704 }; 1705 }; 1706 }; 1707 1708 cpu1-thermal { 1709 polling-delay-passive = <250>; 1710 polling-delay = <1000>; 1711 1712 thermal-sensors = <&tsens0 2>; 1713 1714 trips { 1715 cpu_alert1: trip0 { 1716 temperature = <75000>; 1717 hysteresis = <2000>; 1718 type = "passive"; 1719 }; 1720 1721 cpu_crit1: trip1 { 1722 temperature = <110000>; 1723 hysteresis = <1000>; 1724 type = "critical"; 1725 }; 1726 }; 1727 }; 1728 1729 cpu2-thermal { 1730 polling-delay-passive = <250>; 1731 polling-delay = <1000>; 1732 1733 thermal-sensors = <&tsens0 3>; 1734 1735 trips { 1736 cpu_alert2: trip0 { 1737 temperature = <75000>; 1738 hysteresis = <2000>; 1739 type = "passive"; 1740 }; 1741 1742 cpu_crit2: trip1 { 1743 temperature = <110000>; 1744 hysteresis = <1000>; 1745 type = "critical"; 1746 }; 1747 }; 1748 }; 1749 1750 cpu3-thermal { 1751 polling-delay-passive = <250>; 1752 polling-delay = <1000>; 1753 1754 thermal-sensors = <&tsens0 4>; 1755 1756 trips { 1757 cpu_alert3: trip0 { 1758 temperature = <75000>; 1759 hysteresis = <2000>; 1760 type = "passive"; 1761 }; 1762 1763 cpu_crit3: trip1 { 1764 temperature = <110000>; 1765 hysteresis = <1000>; 1766 type = "critical"; 1767 }; 1768 }; 1769 }; 1770 1771 cpu4-thermal { 1772 polling-delay-passive = <250>; 1773 polling-delay = <1000>; 1774 1775 thermal-sensors = <&tsens0 7>; 1776 1777 trips { 1778 cpu_alert4: trip0 { 1779 temperature = <75000>; 1780 hysteresis = <2000>; 1781 type = "passive"; 1782 }; 1783 1784 cpu_crit4: trip1 { 1785 temperature = <110000>; 1786 hysteresis = <1000>; 1787 type = "critical"; 1788 }; 1789 }; 1790 }; 1791 1792 cpu5-thermal { 1793 polling-delay-passive = <250>; 1794 polling-delay = <1000>; 1795 1796 thermal-sensors = <&tsens0 8>; 1797 1798 trips { 1799 cpu_alert5: trip0 { 1800 temperature = <75000>; 1801 hysteresis = <2000>; 1802 type = "passive"; 1803 }; 1804 1805 cpu_crit5: trip1 { 1806 temperature = <110000>; 1807 hysteresis = <1000>; 1808 type = "critical"; 1809 }; 1810 }; 1811 }; 1812 1813 cpu6-thermal { 1814 polling-delay-passive = <250>; 1815 polling-delay = <1000>; 1816 1817 thermal-sensors = <&tsens0 9>; 1818 1819 trips { 1820 cpu_alert6: trip0 { 1821 temperature = <75000>; 1822 hysteresis = <2000>; 1823 type = "passive"; 1824 }; 1825 1826 cpu_crit6: trip1 { 1827 temperature = <110000>; 1828 hysteresis = <1000>; 1829 type = "critical"; 1830 }; 1831 }; 1832 }; 1833 1834 cpu7-thermal { 1835 polling-delay-passive = <250>; 1836 polling-delay = <1000>; 1837 1838 thermal-sensors = <&tsens0 10>; 1839 1840 trips { 1841 cpu_alert7: trip0 { 1842 temperature = <75000>; 1843 hysteresis = <2000>; 1844 type = "passive"; 1845 }; 1846 1847 cpu_crit7: trip1 { 1848 temperature = <110000>; 1849 hysteresis = <1000>; 1850 type = "critical"; 1851 }; 1852 }; 1853 }; 1854 }; 1855}; 1856