1*e418346fSJishnu Prakash /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ 2*e418346fSJishnu Prakash /* 3*e418346fSJishnu Prakash * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4*e418346fSJishnu Prakash */ 5*e418346fSJishnu Prakash 6*e418346fSJishnu Prakash #ifndef __DTS_ARM64_QCOM_ADC5_GEN3_H__ 7*e418346fSJishnu Prakash #define __DTS_ARM64_QCOM_ADC5_GEN3_H__ 8*e418346fSJishnu Prakash 9*e418346fSJishnu Prakash /* ADC channels for PMIC5 Gen3 */ 10*e418346fSJishnu Prakash 11*e418346fSJishnu Prakash #define VIRT_CHAN(sid, chan) ((sid) << 8 | (chan)) 12*e418346fSJishnu Prakash 13*e418346fSJishnu Prakash #define ADC5_GEN3_REF_GND(sid) VIRT_CHAN(sid, 0x00) 14*e418346fSJishnu Prakash #define ADC5_GEN3_1P25VREF(sid) VIRT_CHAN(sid, 0x01) 15*e418346fSJishnu Prakash #define ADC5_GEN3_VREF_VADC(sid) VIRT_CHAN(sid, 0x02) 16*e418346fSJishnu Prakash #define ADC5_GEN3_DIE_TEMP(sid) VIRT_CHAN(sid, 0x03) 17*e418346fSJishnu Prakash 18*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX1_THM(sid) VIRT_CHAN(sid, 0x04) 19*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX2_THM(sid) VIRT_CHAN(sid, 0x05) 20*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX3_THM(sid) VIRT_CHAN(sid, 0x06) 21*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX4_THM(sid) VIRT_CHAN(sid, 0x07) 22*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX5_THM(sid) VIRT_CHAN(sid, 0x08) 23*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX6_THM(sid) VIRT_CHAN(sid, 0x09) 24*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX1_GPIO(sid) VIRT_CHAN(sid, 0x0a) 25*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX2_GPIO(sid) VIRT_CHAN(sid, 0x0b) 26*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX3_GPIO(sid) VIRT_CHAN(sid, 0x0c) 27*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX4_GPIO(sid) VIRT_CHAN(sid, 0x0d) 28*e418346fSJishnu Prakash 29*e418346fSJishnu Prakash #define ADC5_GEN3_CHG_TEMP(sid) VIRT_CHAN(sid, 0x10) 30*e418346fSJishnu Prakash #define ADC5_GEN3_USB_SNS_V_16(sid) VIRT_CHAN(sid, 0x11) 31*e418346fSJishnu Prakash #define ADC5_GEN3_VIN_DIV16_MUX(sid) VIRT_CHAN(sid, 0x12) 32*e418346fSJishnu Prakash #define ADC5_GEN3_VREF_BAT_THERM(sid) VIRT_CHAN(sid, 0x15) 33*e418346fSJishnu Prakash #define ADC5_GEN3_IIN_FB(sid) VIRT_CHAN(sid, 0x17) 34*e418346fSJishnu Prakash #define ADC5_GEN3_TEMP_ALARM_LITE(sid) VIRT_CHAN(sid, 0x18) 35*e418346fSJishnu Prakash #define ADC5_GEN3_IIN_SMB(sid) VIRT_CHAN(sid, 0x19) 36*e418346fSJishnu Prakash #define ADC5_GEN3_ICHG_SMB(sid) VIRT_CHAN(sid, 0x1b) 37*e418346fSJishnu Prakash #define ADC5_GEN3_ICHG_FB(sid) VIRT_CHAN(sid, 0xa1) 38*e418346fSJishnu Prakash 39*e418346fSJishnu Prakash /* 30k pull-up */ 40*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX1_THM_30K_PU(sid) VIRT_CHAN(sid, 0x24) 41*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX2_THM_30K_PU(sid) VIRT_CHAN(sid, 0x25) 42*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX3_THM_30K_PU(sid) VIRT_CHAN(sid, 0x26) 43*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX4_THM_30K_PU(sid) VIRT_CHAN(sid, 0x27) 44*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX5_THM_30K_PU(sid) VIRT_CHAN(sid, 0x28) 45*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX6_THM_30K_PU(sid) VIRT_CHAN(sid, 0x29) 46*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX1_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2a) 47*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX2_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2b) 48*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX3_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2c) 49*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX4_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2d) 50*e418346fSJishnu Prakash 51*e418346fSJishnu Prakash /* 100k pull-up */ 52*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX1_THM_100K_PU(sid) VIRT_CHAN(sid, 0x44) 53*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX2_THM_100K_PU(sid) VIRT_CHAN(sid, 0x45) 54*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX3_THM_100K_PU(sid) VIRT_CHAN(sid, 0x46) 55*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX4_THM_100K_PU(sid) VIRT_CHAN(sid, 0x47) 56*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX5_THM_100K_PU(sid) VIRT_CHAN(sid, 0x48) 57*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX6_THM_100K_PU(sid) VIRT_CHAN(sid, 0x49) 58*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX1_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4a) 59*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX2_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4b) 60*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX3_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4c) 61*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX4_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4d) 62*e418346fSJishnu Prakash 63*e418346fSJishnu Prakash /* 400k pull-up */ 64*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX1_THM_400K_PU(sid) VIRT_CHAN(sid, 0x64) 65*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX2_THM_400K_PU(sid) VIRT_CHAN(sid, 0x65) 66*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX3_THM_400K_PU(sid) VIRT_CHAN(sid, 0x66) 67*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX4_THM_400K_PU(sid) VIRT_CHAN(sid, 0x67) 68*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX5_THM_400K_PU(sid) VIRT_CHAN(sid, 0x68) 69*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX6_THM_400K_PU(sid) VIRT_CHAN(sid, 0x69) 70*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX1_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6a) 71*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX2_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6b) 72*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX3_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6c) 73*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX4_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6d) 74*e418346fSJishnu Prakash 75*e418346fSJishnu Prakash /* 1/3 Divider */ 76*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX1_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8a) 77*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX2_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8b) 78*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX3_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8c) 79*e418346fSJishnu Prakash #define ADC5_GEN3_AMUX4_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8d) 80*e418346fSJishnu Prakash 81*e418346fSJishnu Prakash #define ADC5_GEN3_VPH_PWR(sid) VIRT_CHAN(sid, 0x8e) 82*e418346fSJishnu Prakash #define ADC5_GEN3_VBAT_SNS_QBG(sid) VIRT_CHAN(sid, 0x8f) 83*e418346fSJishnu Prakash 84*e418346fSJishnu Prakash #define ADC5_GEN3_VBAT_SNS_CHGR(sid) VIRT_CHAN(sid, 0x94) 85*e418346fSJishnu Prakash #define ADC5_GEN3_VBAT_2S_MID_QBG(sid) VIRT_CHAN(sid, 0x96) 86*e418346fSJishnu Prakash #define ADC5_GEN3_VBAT_2S_MID_CHGR(sid) VIRT_CHAN(sid, 0x9d) 87*e418346fSJishnu Prakash 88*e418346fSJishnu Prakash #endif /* __DTS_ARM64_QCOM_ADC5_GEN3_H__ */ 89