1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,qcs8300-gcc.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/clock/qcom,sa8775p-camcc.h> 9#include <dt-bindings/clock/qcom,sa8775p-dispcc.h> 10#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 11#include <dt-bindings/clock/qcom,sa8775p-videocc.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/firmware/qcom,scm.h> 14#include <dt-bindings/interconnect/qcom,icc.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/mailbox/qcom-ipcc.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/soc/qcom,gpr.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/thermal/thermal.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 clocks { 31 xo_board_clk: xo-board-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <38400000>; 35 }; 36 37 sleep_clk: sleep-clk { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <32000>; 41 }; 42 }; 43 44 cpus { 45 #address-cells = <2>; 46 #size-cells = <0>; 47 48 cpu0: cpu@0 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a78c"; 51 reg = <0x0 0x0>; 52 enable-method = "psci"; 53 next-level-cache = <&l2_0>; 54 power-domains = <&cpu_pd0>; 55 power-domain-names = "psci"; 56 capacity-dmips-mhz = <1946>; 57 dynamic-power-coefficient = <472>; 58 #cooling-cells = <2>; 59 qcom,freq-domain = <&cpufreq_hw 0>; 60 operating-points-v2 = <&cpu0_opp_table>; 61 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 62 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 63 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 64 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 65 66 l2_0: l2-cache { 67 compatible = "cache"; 68 cache-level = <2>; 69 cache-unified; 70 next-level-cache = <&l3_0>; 71 }; 72 }; 73 74 cpu1: cpu@100 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a78c"; 77 reg = <0x0 0x100>; 78 enable-method = "psci"; 79 next-level-cache = <&l2_1>; 80 power-domains = <&cpu_pd1>; 81 power-domain-names = "psci"; 82 capacity-dmips-mhz = <1946>; 83 #cooling-cells = <2>; 84 dynamic-power-coefficient = <472>; 85 qcom,freq-domain = <&cpufreq_hw 0>; 86 operating-points-v2 = <&cpu0_opp_table>; 87 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 88 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 89 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 90 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 91 92 l2_1: l2-cache { 93 compatible = "cache"; 94 cache-level = <2>; 95 cache-unified; 96 next-level-cache = <&l3_0>; 97 }; 98 }; 99 100 cpu2: cpu@200 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a78c"; 103 reg = <0x0 0x200>; 104 enable-method = "psci"; 105 next-level-cache = <&l2_2>; 106 power-domains = <&cpu_pd2>; 107 power-domain-names = "psci"; 108 capacity-dmips-mhz = <1946>; 109 #cooling-cells = <2>; 110 dynamic-power-coefficient = <507>; 111 qcom,freq-domain = <&cpufreq_hw 2>; 112 operating-points-v2 = <&cpu2_opp_table>; 113 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 114 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 115 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 116 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 117 118 l2_2: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 cache-unified; 122 next-level-cache = <&l3_0>; 123 }; 124 }; 125 126 cpu3: cpu@300 { 127 device_type = "cpu"; 128 compatible = "arm,cortex-a78c"; 129 reg = <0x0 0x300>; 130 enable-method = "psci"; 131 next-level-cache = <&l2_3>; 132 power-domains = <&cpu_pd3>; 133 power-domain-names = "psci"; 134 capacity-dmips-mhz = <1946>; 135 #cooling-cells = <2>; 136 dynamic-power-coefficient = <507>; 137 qcom,freq-domain = <&cpufreq_hw 2>; 138 operating-points-v2 = <&cpu2_opp_table>; 139 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 140 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 141 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 142 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 143 144 l2_3: l2-cache { 145 compatible = "cache"; 146 cache-level = <2>; 147 cache-unified; 148 next-level-cache = <&l3_0>; 149 }; 150 }; 151 152 cpu4: cpu@10000 { 153 device_type = "cpu"; 154 compatible = "arm,cortex-a55"; 155 reg = <0x0 0x10000>; 156 enable-method = "psci"; 157 next-level-cache = <&l2_4>; 158 power-domains = <&cpu_pd4>; 159 power-domain-names = "psci"; 160 capacity-dmips-mhz = <1024>; 161 #cooling-cells = <2>; 162 dynamic-power-coefficient = <100>; 163 qcom,freq-domain = <&cpufreq_hw 1>; 164 operating-points-v2 = <&cpu4_opp_table>; 165 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 166 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 167 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 168 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 169 170 l2_4: l2-cache { 171 compatible = "cache"; 172 cache-level = <2>; 173 cache-unified; 174 next-level-cache = <&l3_1>; 175 }; 176 }; 177 178 cpu5: cpu@10100 { 179 device_type = "cpu"; 180 compatible = "arm,cortex-a55"; 181 reg = <0x0 0x10100>; 182 enable-method = "psci"; 183 next-level-cache = <&l2_5>; 184 power-domains = <&cpu_pd5>; 185 power-domain-names = "psci"; 186 capacity-dmips-mhz = <1024>; 187 #cooling-cells = <2>; 188 dynamic-power-coefficient = <100>; 189 qcom,freq-domain = <&cpufreq_hw 1>; 190 operating-points-v2 = <&cpu4_opp_table>; 191 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 192 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 193 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 194 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 195 196 l2_5: l2-cache { 197 compatible = "cache"; 198 cache-level = <2>; 199 cache-unified; 200 next-level-cache = <&l3_1>; 201 }; 202 }; 203 204 cpu6: cpu@10200 { 205 device_type = "cpu"; 206 compatible = "arm,cortex-a55"; 207 reg = <0x0 0x10200>; 208 enable-method = "psci"; 209 next-level-cache = <&l2_6>; 210 power-domains = <&cpu_pd6>; 211 power-domain-names = "psci"; 212 capacity-dmips-mhz = <1024>; 213 #cooling-cells = <2>; 214 dynamic-power-coefficient = <100>; 215 qcom,freq-domain = <&cpufreq_hw 1>; 216 operating-points-v2 = <&cpu4_opp_table>; 217 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 218 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 219 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 220 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 221 222 l2_6: l2-cache { 223 compatible = "cache"; 224 cache-level = <2>; 225 cache-unified; 226 next-level-cache = <&l3_1>; 227 }; 228 }; 229 230 cpu7: cpu@10300 { 231 device_type = "cpu"; 232 compatible = "arm,cortex-a55"; 233 reg = <0x0 0x10300>; 234 enable-method = "psci"; 235 next-level-cache = <&l2_7>; 236 power-domains = <&cpu_pd7>; 237 power-domain-names = "psci"; 238 capacity-dmips-mhz = <1024>; 239 #cooling-cells = <2>; 240 dynamic-power-coefficient = <100>; 241 qcom,freq-domain = <&cpufreq_hw 1>; 242 operating-points-v2 = <&cpu4_opp_table>; 243 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 244 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 245 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 246 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 247 248 l2_7: l2-cache { 249 compatible = "cache"; 250 cache-level = <2>; 251 cache-unified; 252 next-level-cache = <&l3_1>; 253 }; 254 }; 255 256 cpu-map { 257 cluster0 { 258 core0 { 259 cpu = <&cpu0>; 260 }; 261 262 core1 { 263 cpu = <&cpu1>; 264 }; 265 266 core2 { 267 cpu = <&cpu2>; 268 }; 269 270 core3 { 271 cpu = <&cpu3>; 272 }; 273 }; 274 275 cluster1 { 276 core0 { 277 cpu = <&cpu4>; 278 }; 279 280 core1 { 281 cpu = <&cpu5>; 282 }; 283 284 core2 { 285 cpu = <&cpu6>; 286 }; 287 288 core3 { 289 cpu = <&cpu7>; 290 }; 291 }; 292 }; 293 294 l3_0: l3-cache-0 { 295 compatible = "cache"; 296 cache-level = <3>; 297 cache-unified; 298 }; 299 300 l3_1: l3-cache-1 { 301 compatible = "cache"; 302 cache-level = <3>; 303 cache-unified; 304 }; 305 306 idle-states { 307 entry-method = "psci"; 308 309 little_cpu_sleep_0: cpu-sleep-0-0 { 310 compatible = "arm,idle-state"; 311 idle-state-name = "silver-power-collapse"; 312 arm,psci-suspend-param = <0x40000003>; 313 entry-latency-us = <449>; 314 exit-latency-us = <801>; 315 min-residency-us = <1574>; 316 local-timer-stop; 317 }; 318 319 little_cpu_sleep_1: cpu-sleep-0-1 { 320 compatible = "arm,idle-state"; 321 idle-state-name = "silver-rail-power-collapse"; 322 arm,psci-suspend-param = <0x40000004>; 323 entry-latency-us = <602>; 324 exit-latency-us = <961>; 325 min-residency-us = <4288>; 326 local-timer-stop; 327 }; 328 329 big_cpu_sleep_0: cpu-sleep-1-0 { 330 compatible = "arm,idle-state"; 331 idle-state-name = "gold-power-collapse"; 332 arm,psci-suspend-param = <0x40000003>; 333 entry-latency-us = <549>; 334 exit-latency-us = <901>; 335 min-residency-us = <1774>; 336 local-timer-stop; 337 }; 338 339 big_cpu_sleep_1: cpu-sleep-1-1 { 340 compatible = "arm,idle-state"; 341 idle-state-name = "gold-rail-power-collapse"; 342 arm,psci-suspend-param = <0x40000004>; 343 entry-latency-us = <702>; 344 exit-latency-us = <1061>; 345 min-residency-us = <4488>; 346 local-timer-stop; 347 }; 348 }; 349 350 domain-idle-states { 351 silver_cluster_sleep: cluster-sleep-0 { 352 compatible = "domain-idle-state"; 353 arm,psci-suspend-param = <0x41000044>; 354 entry-latency-us = <2552>; 355 exit-latency-us = <2848>; 356 min-residency-us = <5908>; 357 }; 358 359 gold_cluster_sleep: cluster-sleep-1 { 360 compatible = "domain-idle-state"; 361 arm,psci-suspend-param = <0x41000044>; 362 entry-latency-us = <2752>; 363 exit-latency-us = <3048>; 364 min-residency-us = <6118>; 365 }; 366 367 system_sleep: domain-sleep { 368 compatible = "domain-idle-state"; 369 arm,psci-suspend-param = <0x42000144>; 370 entry-latency-us = <3263>; 371 exit-latency-us = <6562>; 372 min-residency-us = <9987>; 373 }; 374 }; 375 }; 376 377 cpu0_opp_table: opp-table-cpu0 { 378 compatible = "operating-points-v2"; 379 opp-shared; 380 381 opp-902400000 { 382 opp-hz = /bits/ 64 <902400000>; 383 opp-peak-kBps = <(681600 * 4) (921600 * 32)>; 384 }; 385 386 opp-1017600000 { 387 opp-hz = /bits/ 64 <1017600000>; 388 opp-peak-kBps = <(1017600 * 4) (921600 * 32)>; 389 }; 390 391 opp-1190400000 { 392 opp-hz = /bits/ 64 <1190400000>; 393 opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; 394 }; 395 396 opp-1267200000 { 397 opp-hz = /bits/ 64 <1267200000>; 398 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 399 }; 400 401 opp-1344000000 { 402 opp-hz = /bits/ 64 <1344000000>; 403 opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; 404 }; 405 406 opp-1420800000 { 407 opp-hz = /bits/ 64 <1420800000>; 408 opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; 409 }; 410 411 opp-1497600000 { 412 opp-hz = /bits/ 64 <1497600000>; 413 opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; 414 }; 415 416 opp-1574400000 { 417 opp-hz = /bits/ 64 <1574400000>; 418 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 419 }; 420 421 opp-1670400000 { 422 opp-hz = /bits/ 64 <1670400000>; 423 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 424 }; 425 426 opp-1747200000 { 427 opp-hz = /bits/ 64 <1747200000>; 428 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 429 }; 430 431 opp-1824000000 { 432 opp-hz = /bits/ 64 <1824000000>; 433 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 434 }; 435 436 opp-1900800000 { 437 opp-hz = /bits/ 64 <1900800000>; 438 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 439 }; 440 441 opp-1977600000 { 442 opp-hz = /bits/ 64 <1977600000>; 443 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 444 }; 445 446 opp-2054400000 { 447 opp-hz = /bits/ 64 <2054400000>; 448 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 449 }; 450 451 opp-2112000000 { 452 opp-hz = /bits/ 64 <2112000000>; 453 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 454 }; 455 456 }; 457 458 cpu2_opp_table: opp-table-cpu2 { 459 compatible = "operating-points-v2"; 460 opp-shared; 461 462 opp-940800000 { 463 opp-hz = /bits/ 64 <940800000>; 464 opp-peak-kBps = <(681600 * 4) (921600 * 32)>; 465 }; 466 467 opp-1094400000 { 468 opp-hz = /bits/ 64 <1094400000>; 469 opp-peak-kBps = <(1017600 * 4) (921600 * 32)>; 470 }; 471 472 opp-1267200000 { 473 opp-hz = /bits/ 64 <1267200000>; 474 opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; 475 }; 476 477 opp-1344000000 { 478 opp-hz = /bits/ 64 <1344000000>; 479 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 480 }; 481 482 opp-1420800000 { 483 opp-hz = /bits/ 64 <1420800000>; 484 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 485 }; 486 487 opp-1497600000 { 488 opp-hz = /bits/ 64 <1497600000>; 489 opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; 490 }; 491 492 opp-1574400000 { 493 opp-hz = /bits/ 64 <1574400000>; 494 opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; 495 }; 496 497 opp-1632000000 { 498 opp-hz = /bits/ 64 <1632000000>; 499 opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; 500 }; 501 502 opp-1708800000 { 503 opp-hz = /bits/ 64 <1708800000>; 504 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 505 }; 506 507 opp-1804800000 { 508 opp-hz = /bits/ 64 <1804800000>; 509 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 510 }; 511 512 opp-1900800000 { 513 opp-hz = /bits/ 64 <1900800000>; 514 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 515 }; 516 517 opp-1977600000 { 518 opp-hz = /bits/ 64 <1977600000>; 519 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 520 }; 521 522 opp-2054400000 { 523 opp-hz = /bits/ 64 <2054400000>; 524 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 525 }; 526 527 opp-2131200000 { 528 opp-hz = /bits/ 64 <2131200000>; 529 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 530 }; 531 532 opp-2208000000 { 533 opp-hz = /bits/ 64 <2208000000>; 534 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 535 }; 536 537 opp-2284800000 { 538 opp-hz = /bits/ 64 <2284800000>; 539 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 540 }; 541 542 opp-2361600000 { 543 opp-hz = /bits/ 64 <2361600000>; 544 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 545 }; 546 547 }; 548 549 cpu4_opp_table: opp-table-cpu4 { 550 compatible = "operating-points-v2"; 551 opp-shared; 552 553 opp-844800000 { 554 opp-hz = /bits/ 64 <844800000>; 555 opp-peak-kBps = <(681600 * 4) (921600 * 32)>; 556 }; 557 558 opp-1113600000 { 559 opp-hz = /bits/ 64 <1113600000>; 560 opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; 561 }; 562 563 opp-1209600000 { 564 opp-hz = /bits/ 64 <1209600000>; 565 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 566 }; 567 568 opp-1305600000 { 569 opp-hz = /bits/ 64 <1305600000>; 570 opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; 571 }; 572 573 opp-1382400000 { 574 opp-hz = /bits/ 64 <1382400000>; 575 opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; 576 }; 577 578 opp-1459200000 { 579 opp-hz = /bits/ 64 <1459200000>; 580 opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; 581 }; 582 583 opp-1497600000 { 584 opp-hz = /bits/ 64 <1497600000>; 585 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 586 }; 587 588 opp-1574400000 { 589 opp-hz = /bits/ 64 <1574400000>; 590 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 591 }; 592 593 opp-1651200000 { 594 opp-hz = /bits/ 64 <1651200000>; 595 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 596 }; 597 598 opp-1728000000 { 599 opp-hz = /bits/ 64 <1728000000>; 600 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 601 }; 602 603 opp-1804800000 { 604 opp-hz = /bits/ 64 <1804800000>; 605 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 606 }; 607 608 opp-1881600000 { 609 opp-hz = /bits/ 64 <1881600000>; 610 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 611 }; 612 613 opp-1958400000 { 614 opp-hz = /bits/ 64 <1958400000>; 615 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 616 }; 617 }; 618 619 dummy_eud: dummy-sink { 620 compatible = "arm,coresight-dummy-sink"; 621 622 in-ports { 623 port { 624 eud_in: endpoint { 625 remote-endpoint = <&swao_rep_out1>; 626 }; 627 }; 628 }; 629 }; 630 631 firmware { 632 scm: scm { 633 compatible = "qcom,scm-qcs8300", "qcom,scm"; 634 qcom,dload-mode = <&tcsr 0x13000>; 635 }; 636 }; 637 638 memory@80000000 { 639 device_type = "memory"; 640 /* We expect the bootloader to fill in the size */ 641 reg = <0x0 0x80000000 0x0 0x0>; 642 }; 643 644 clk_virt: interconnect-0 { 645 compatible = "qcom,qcs8300-clk-virt"; 646 #interconnect-cells = <2>; 647 qcom,bcm-voters = <&apps_bcm_voter>; 648 }; 649 650 mc_virt: interconnect-1 { 651 compatible = "qcom,qcs8300-mc-virt"; 652 #interconnect-cells = <2>; 653 qcom,bcm-voters = <&apps_bcm_voter>; 654 }; 655 656 qup_opp_table: opp-table-qup { 657 compatible = "operating-points-v2"; 658 659 opp-120000000 { 660 opp-hz = /bits/ 64 <120000000>; 661 required-opps = <&rpmhpd_opp_svs_l1>; 662 }; 663 }; 664 665 pmu-a55 { 666 compatible = "arm,cortex-a55-pmu"; 667 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 668 }; 669 670 pmu-a78 { 671 compatible = "arm,cortex-a78-pmu"; 672 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 673 }; 674 675 psci { 676 compatible = "arm,psci-1.0"; 677 method = "smc"; 678 679 cpu_pd0: power-domain-cpu0 { 680 #power-domain-cells = <0>; 681 power-domains = <&cluster_pd0>; 682 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 683 }; 684 685 cpu_pd1: power-domain-cpu1 { 686 #power-domain-cells = <0>; 687 power-domains = <&cluster_pd0>; 688 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 689 }; 690 691 cpu_pd2: power-domain-cpu2 { 692 #power-domain-cells = <0>; 693 power-domains = <&cluster_pd0>; 694 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 695 }; 696 697 cpu_pd3: power-domain-cpu3 { 698 #power-domain-cells = <0>; 699 power-domains = <&cluster_pd0>; 700 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 701 }; 702 703 cpu_pd4: power-domain-cpu4 { 704 #power-domain-cells = <0>; 705 power-domains = <&cluster_pd1>; 706 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 707 }; 708 709 cpu_pd5: power-domain-cpu5 { 710 #power-domain-cells = <0>; 711 power-domains = <&cluster_pd1>; 712 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 713 }; 714 715 cpu_pd6: power-domain-cpu6 { 716 #power-domain-cells = <0>; 717 power-domains = <&cluster_pd1>; 718 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 719 }; 720 721 cpu_pd7: power-domain-cpu7 { 722 #power-domain-cells = <0>; 723 power-domains = <&cluster_pd1>; 724 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 725 }; 726 727 cluster_pd0: power-domain-cluster0 { 728 #power-domain-cells = <0>; 729 power-domains = <&system_pd>; 730 domain-idle-states = <&gold_cluster_sleep>; 731 }; 732 733 cluster_pd1: power-domain-cluster1 { 734 #power-domain-cells = <0>; 735 power-domains = <&system_pd>; 736 domain-idle-states = <&silver_cluster_sleep>; 737 }; 738 739 system_pd: power-domain-system { 740 #power-domain-cells = <0>; 741 domain-idle-states = <&system_sleep>; 742 }; 743 }; 744 745 reserved-memory { 746 #address-cells = <2>; 747 #size-cells = <2>; 748 ranges; 749 750 aop_image_mem: aop-image-region@90800000 { 751 reg = <0x0 0x90800000 0x0 0x60000>; 752 no-map; 753 }; 754 755 aop_cmd_db_mem: aop-cmd-db-region@90860000 { 756 compatible = "qcom,cmd-db"; 757 reg = <0x0 0x90860000 0x0 0x20000>; 758 no-map; 759 }; 760 761 smem_mem: smem@90900000 { 762 compatible = "qcom,smem"; 763 reg = <0x0 0x90900000 0x0 0x200000>; 764 no-map; 765 hwlocks = <&tcsr_mutex 3>; 766 }; 767 768 lpass_machine_learning_mem: lpass-machine-learning-region@93b00000 { 769 reg = <0x0 0x93b00000 0x0 0xf00000>; 770 no-map; 771 }; 772 773 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap-region@94a00000 { 774 reg = <0x0 0x94a00000 0x0 0x800000>; 775 no-map; 776 }; 777 778 camera_mem: camera-region@95200000 { 779 reg = <0x0 0x95200000 0x0 0x500000>; 780 no-map; 781 }; 782 783 adsp_mem: adsp-region@95c00000 { 784 no-map; 785 reg = <0x0 0x95c00000 0x0 0x1e00000>; 786 }; 787 788 q6_adsp_dtb_mem: q6-adsp-dtb-region@97a00000 { 789 reg = <0x0 0x97a00000 0x0 0x80000>; 790 no-map; 791 }; 792 793 q6_gpdsp_dtb_mem: q6-gpdsp-dtb-region@97a80000 { 794 reg = <0x0 0x97a80000 0x0 0x80000>; 795 no-map; 796 }; 797 798 gpdsp_mem: gpdsp-region@97b00000 { 799 reg = <0x0 0x97b00000 0x0 0x1e00000>; 800 no-map; 801 }; 802 803 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@99900000 { 804 reg = <0x0 0x99900000 0x0 0x80000>; 805 no-map; 806 }; 807 808 cdsp_mem: cdsp-region@99980000 { 809 reg = <0x0 0x99980000 0x0 0x1e00000>; 810 no-map; 811 }; 812 813 gpu_microcode_mem: gpu-microcode-region@9b780000 { 814 reg = <0x0 0x9b780000 0x0 0x2000>; 815 no-map; 816 }; 817 818 cvp_mem: cvp-region@9b782000 { 819 reg = <0x0 0x9b782000 0x0 0x700000>; 820 no-map; 821 }; 822 823 video_mem: video-region@9be82000 { 824 reg = <0x0 0x9be82000 0x0 0x700000>; 825 no-map; 826 }; 827 }; 828 829 smp2p-adsp { 830 compatible = "qcom,smp2p"; 831 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 832 IPCC_MPROC_SIGNAL_SMP2P 833 IRQ_TYPE_EDGE_RISING>; 834 mboxes = <&ipcc IPCC_CLIENT_LPASS 835 IPCC_MPROC_SIGNAL_SMP2P>; 836 837 qcom,smem = <443>, <429>; 838 qcom,local-pid = <0>; 839 qcom,remote-pid = <2>; 840 841 smp2p_adsp_in: slave-kernel { 842 qcom,entry-name = "slave-kernel"; 843 interrupt-controller; 844 #interrupt-cells = <2>; 845 }; 846 847 smp2p_adsp_out: master-kernel { 848 qcom,entry-name = "master-kernel"; 849 #qcom,smem-state-cells = <1>; 850 }; 851 }; 852 853 smp2p-cdsp { 854 compatible = "qcom,smp2p"; 855 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 856 IPCC_MPROC_SIGNAL_SMP2P 857 IRQ_TYPE_EDGE_RISING>; 858 mboxes = <&ipcc IPCC_CLIENT_CDSP 859 IPCC_MPROC_SIGNAL_SMP2P>; 860 861 qcom,smem = <94>, <432>; 862 qcom,local-pid = <0>; 863 qcom,remote-pid = <5>; 864 865 smp2p_cdsp_in: slave-kernel { 866 qcom,entry-name = "slave-kernel"; 867 interrupt-controller; 868 #interrupt-cells = <2>; 869 }; 870 871 smp2p_cdsp_out: master-kernel { 872 qcom,entry-name = "master-kernel"; 873 #qcom,smem-state-cells = <1>; 874 }; 875 }; 876 877 smp2p-gpdsp { 878 compatible = "qcom,smp2p"; 879 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 880 IPCC_MPROC_SIGNAL_SMP2P 881 IRQ_TYPE_EDGE_RISING>; 882 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 883 IPCC_MPROC_SIGNAL_SMP2P>; 884 885 qcom,smem = <617>, <616>; 886 qcom,local-pid = <0>; 887 qcom,remote-pid = <17>; 888 889 smp2p_gpdsp_in: slave-kernel { 890 qcom,entry-name = "slave-kernel"; 891 interrupt-controller; 892 #interrupt-cells = <2>; 893 }; 894 895 smp2p_gpdsp_out: master-kernel { 896 qcom,entry-name = "master-kernel"; 897 #qcom,smem-state-cells = <1>; 898 }; 899 }; 900 901 soc: soc@0 { 902 compatible = "simple-bus"; 903 ranges = <0 0 0 0 0x10 0>; 904 #address-cells = <2>; 905 #size-cells = <2>; 906 907 gcc: clock-controller@100000 { 908 compatible = "qcom,qcs8300-gcc"; 909 reg = <0x0 0x00100000 0x0 0xc7018>; 910 #clock-cells = <1>; 911 #reset-cells = <1>; 912 #power-domain-cells = <1>; 913 clocks = <&rpmhcc RPMH_CXO_CLK>, 914 <&sleep_clk>, 915 <&pcie0_phy>, 916 <&pcie1_phy>, 917 <0>, 918 <0>, 919 <0>, 920 <0>, 921 <0>, 922 <0>; 923 }; 924 925 ipcc: mailbox@408000 { 926 compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; 927 reg = <0x0 0x408000 0x0 0x1000>; 928 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 929 interrupt-controller; 930 #interrupt-cells = <3>; 931 #mbox-cells = <2>; 932 }; 933 934 qfprom: efuse@784000 { 935 compatible = "qcom,qcs8300-qfprom", "qcom,qfprom"; 936 reg = <0x0 0x00784000 0x0 0x2410>; 937 #address-cells = <1>; 938 #size-cells = <1>; 939 940 gpu_speed_bin: gpu-speed-bin@240c { 941 reg = <0x240c 0x1>; 942 bits = <0 8>; 943 }; 944 }; 945 946 gpi_dma0: dma-controller@900000 { 947 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; 948 reg = <0x0 0x900000 0x0 0x60000>; 949 #dma-cells = <3>; 950 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 962 iommus = <&apps_smmu 0x416 0x0>; 963 dma-channels = <12>; 964 dma-channel-mask = <0xfff>; 965 dma-coherent; 966 status = "disabled"; 967 }; 968 969 qupv3_id_0: geniqup@9c0000 { 970 compatible = "qcom,geni-se-qup"; 971 reg = <0x0 0x9c0000 0x0 0x2000>; 972 ranges; 973 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 974 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 975 clock-names = "m-ahb", 976 "s-ahb"; 977 #address-cells = <2>; 978 #size-cells = <2>; 979 iommus = <&apps_smmu 0x403 0x0>; 980 dma-coherent; 981 status = "disabled"; 982 983 i2c0: i2c@980000 { 984 compatible = "qcom,geni-i2c"; 985 reg = <0x0 0x980000 0x0 0x4000>; 986 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 987 clock-names = "se"; 988 pinctrl-0 = <&qup_i2c0_data_clk>; 989 pinctrl-names = "default"; 990 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 991 #address-cells = <1>; 992 #size-cells = <0>; 993 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 994 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 995 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 996 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 997 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 998 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 999 interconnect-names = "qup-core", 1000 "qup-config", 1001 "qup-memory"; 1002 power-domains = <&rpmhpd RPMHPD_CX>; 1003 required-opps = <&rpmhpd_opp_low_svs>; 1004 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1005 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1006 dma-names = "tx", 1007 "rx"; 1008 status = "disabled"; 1009 }; 1010 1011 spi0: spi@980000 { 1012 compatible = "qcom,geni-spi"; 1013 reg = <0x0 0x980000 0x0 0x4000>; 1014 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1015 clock-names = "se"; 1016 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1017 pinctrl-names = "default"; 1018 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1022 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1023 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1024 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1025 interconnect-names = "qup-core", 1026 "qup-config"; 1027 power-domains = <&rpmhpd RPMHPD_CX>; 1028 operating-points-v2 = <&qup_opp_table>; 1029 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1030 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1031 dma-names = "tx", 1032 "rx"; 1033 status = "disabled"; 1034 }; 1035 1036 uart0: serial@980000 { 1037 compatible = "qcom,geni-uart"; 1038 reg = <0x0 0x980000 0x0 0x4000>; 1039 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1040 clock-names = "se"; 1041 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, 1042 <&qup_uart0_tx>, <&qup_uart0_rx>; 1043 pinctrl-names = "default"; 1044 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1045 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1046 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1047 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1048 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1049 interconnect-names = "qup-core", 1050 "qup-config"; 1051 power-domains = <&rpmhpd RPMHPD_CX>; 1052 operating-points-v2 = <&qup_opp_table>; 1053 status = "disabled"; 1054 }; 1055 1056 i2c1: i2c@984000 { 1057 compatible = "qcom,geni-i2c"; 1058 reg = <0x0 0x984000 0x0 0x4000>; 1059 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1060 clock-names = "se"; 1061 pinctrl-0 = <&qup_i2c1_data_clk>; 1062 pinctrl-names = "default"; 1063 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1067 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1068 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1069 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1070 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1071 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1072 interconnect-names = "qup-core", 1073 "qup-config", 1074 "qup-memory"; 1075 power-domains = <&rpmhpd RPMHPD_CX>; 1076 required-opps = <&rpmhpd_opp_low_svs>; 1077 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1078 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1079 dma-names = "tx", 1080 "rx"; 1081 status = "disabled"; 1082 }; 1083 1084 spi1: spi@984000 { 1085 compatible = "qcom,geni-spi"; 1086 reg = <0x0 0x984000 0x0 0x4000>; 1087 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1088 clock-names = "se"; 1089 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1090 pinctrl-names = "default"; 1091 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1092 #address-cells = <1>; 1093 #size-cells = <0>; 1094 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1095 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1096 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1097 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1098 interconnect-names = "qup-core", 1099 "qup-config"; 1100 power-domains = <&rpmhpd RPMHPD_CX>; 1101 operating-points-v2 = <&qup_opp_table>; 1102 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1103 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1104 dma-names = "tx", 1105 "rx"; 1106 status = "disabled"; 1107 }; 1108 1109 uart1: serial@984000 { 1110 compatible = "qcom,geni-uart"; 1111 reg = <0x0 0x984000 0x0 0x4000>; 1112 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1113 clock-names = "se"; 1114 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, 1115 <&qup_uart1_tx>, <&qup_uart1_rx>; 1116 pinctrl-names = "default"; 1117 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1118 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1119 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1120 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1121 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1122 interconnect-names = "qup-core", 1123 "qup-config"; 1124 power-domains = <&rpmhpd RPMHPD_CX>; 1125 operating-points-v2 = <&qup_opp_table>; 1126 status = "disabled"; 1127 }; 1128 1129 i2c2: i2c@988000 { 1130 compatible = "qcom,geni-i2c"; 1131 reg = <0x0 0x988000 0x0 0x4000>; 1132 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1133 clock-names = "se"; 1134 pinctrl-0 = <&qup_i2c2_data_clk>; 1135 pinctrl-names = "default"; 1136 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1140 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1141 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1142 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1143 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1144 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1145 interconnect-names = "qup-core", 1146 "qup-config", 1147 "qup-memory"; 1148 power-domains = <&rpmhpd RPMHPD_CX>; 1149 required-opps = <&rpmhpd_opp_low_svs>; 1150 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1151 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1152 dma-names = "tx", 1153 "rx"; 1154 status = "disabled"; 1155 }; 1156 1157 spi2: spi@988000 { 1158 compatible = "qcom,geni-spi"; 1159 reg = <0x0 0x988000 0x0 0x4000>; 1160 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1161 clock-names = "se"; 1162 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1163 pinctrl-names = "default"; 1164 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1168 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1169 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1170 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1171 interconnect-names = "qup-core", 1172 "qup-config"; 1173 power-domains = <&rpmhpd RPMHPD_CX>; 1174 operating-points-v2 = <&qup_opp_table>; 1175 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1176 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1177 dma-names = "tx", 1178 "rx"; 1179 status = "disabled"; 1180 }; 1181 1182 uart2: serial@988000 { 1183 compatible = "qcom,geni-uart"; 1184 reg = <0x0 0x988000 0x0 0x4000>; 1185 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1186 clock-names = "se"; 1187 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, 1188 <&qup_uart2_tx>, <&qup_uart2_rx>; 1189 pinctrl-names = "default"; 1190 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1191 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1192 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1193 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1194 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1195 interconnect-names = "qup-core", 1196 "qup-config"; 1197 power-domains = <&rpmhpd RPMHPD_CX>; 1198 operating-points-v2 = <&qup_opp_table>; 1199 status = "disabled"; 1200 }; 1201 1202 i2c3: i2c@98c000 { 1203 compatible = "qcom,geni-i2c"; 1204 reg = <0x0 0x98c000 0x0 0x4000>; 1205 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1206 clock-names = "se"; 1207 pinctrl-0 = <&qup_i2c3_data_clk>; 1208 pinctrl-names = "default"; 1209 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1210 #address-cells = <1>; 1211 #size-cells = <0>; 1212 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1213 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1214 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1215 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1216 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1217 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1218 interconnect-names = "qup-core", 1219 "qup-config", 1220 "qup-memory"; 1221 power-domains = <&rpmhpd RPMHPD_CX>; 1222 required-opps = <&rpmhpd_opp_low_svs>; 1223 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1224 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1225 dma-names = "tx", 1226 "rx"; 1227 status = "disabled"; 1228 }; 1229 1230 spi3: spi@98c000 { 1231 compatible = "qcom,geni-spi"; 1232 reg = <0x0 0x98c000 0x0 0x4000>; 1233 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1234 clock-names = "se"; 1235 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1236 pinctrl-names = "default"; 1237 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1238 #address-cells = <1>; 1239 #size-cells = <0>; 1240 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1241 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1242 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1243 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1244 interconnect-names = "qup-core", 1245 "qup-config"; 1246 power-domains = <&rpmhpd RPMHPD_CX>; 1247 operating-points-v2 = <&qup_opp_table>; 1248 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1249 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1250 dma-names = "tx", 1251 "rx"; 1252 status = "disabled"; 1253 }; 1254 1255 uart3: serial@98c000 { 1256 compatible = "qcom,geni-uart"; 1257 reg = <0x0 0x98c000 0x0 0x4000>; 1258 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1259 clock-names = "se"; 1260 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, 1261 <&qup_uart3_tx>, <&qup_uart3_rx>; 1262 pinctrl-names = "default"; 1263 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1264 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1265 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1266 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1267 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1268 interconnect-names = "qup-core", 1269 "qup-config"; 1270 power-domains = <&rpmhpd RPMHPD_CX>; 1271 operating-points-v2 = <&qup_opp_table>; 1272 status = "disabled"; 1273 }; 1274 1275 i2c4: i2c@990000 { 1276 compatible = "qcom,geni-i2c"; 1277 reg = <0x0 0x990000 0x0 0x4000>; 1278 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1279 clock-names = "se"; 1280 pinctrl-0 = <&qup_i2c4_data_clk>; 1281 pinctrl-names = "default"; 1282 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1283 #address-cells = <1>; 1284 #size-cells = <0>; 1285 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1286 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1287 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1288 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1289 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1290 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1291 interconnect-names = "qup-core", 1292 "qup-config", 1293 "qup-memory"; 1294 power-domains = <&rpmhpd RPMHPD_CX>; 1295 required-opps = <&rpmhpd_opp_low_svs>; 1296 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1297 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1298 dma-names = "tx", 1299 "rx"; 1300 status = "disabled"; 1301 }; 1302 1303 spi4: spi@990000 { 1304 compatible = "qcom,geni-spi"; 1305 reg = <0x0 0x990000 0x0 0x4000>; 1306 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1307 clock-names = "se"; 1308 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1309 pinctrl-names = "default"; 1310 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1314 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1315 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1316 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1317 interconnect-names = "qup-core", 1318 "qup-config"; 1319 power-domains = <&rpmhpd RPMHPD_CX>; 1320 operating-points-v2 = <&qup_opp_table>; 1321 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1322 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1323 dma-names = "tx", 1324 "rx"; 1325 status = "disabled"; 1326 }; 1327 1328 uart4: serial@990000 { 1329 compatible = "qcom,geni-uart"; 1330 reg = <0x0 0x990000 0x0 0x4000>; 1331 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1332 clock-names = "se"; 1333 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, 1334 <&qup_uart4_tx>, <&qup_uart4_rx>; 1335 pinctrl-names = "default"; 1336 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1337 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1338 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1339 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1340 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1341 interconnect-names = "qup-core", 1342 "qup-config"; 1343 power-domains = <&rpmhpd RPMHPD_CX>; 1344 operating-points-v2 = <&qup_opp_table>; 1345 status = "disabled"; 1346 }; 1347 1348 i2c5: i2c@994000 { 1349 compatible = "qcom,geni-i2c"; 1350 reg = <0x0 0x994000 0x0 0x4000>; 1351 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1352 clock-names = "se"; 1353 pinctrl-0 = <&qup_i2c5_data_clk>; 1354 pinctrl-names = "default"; 1355 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1356 #address-cells = <1>; 1357 #size-cells = <0>; 1358 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1359 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1360 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1361 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1362 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1363 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1364 interconnect-names = "qup-core", 1365 "qup-config", 1366 "qup-memory"; 1367 power-domains = <&rpmhpd RPMHPD_CX>; 1368 required-opps = <&rpmhpd_opp_low_svs>; 1369 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1370 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1371 dma-names = "tx", 1372 "rx"; 1373 status = "disabled"; 1374 }; 1375 1376 spi5: spi@994000 { 1377 compatible = "qcom,geni-spi"; 1378 reg = <0x0 0x994000 0x0 0x4000>; 1379 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1380 clock-names = "se"; 1381 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1382 pinctrl-names = "default"; 1383 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1384 #address-cells = <1>; 1385 #size-cells = <0>; 1386 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1387 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1388 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1389 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1390 interconnect-names = "qup-core", 1391 "qup-config"; 1392 power-domains = <&rpmhpd RPMHPD_CX>; 1393 operating-points-v2 = <&qup_opp_table>; 1394 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1395 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1396 dma-names = "tx", 1397 "rx"; 1398 status = "disabled"; 1399 }; 1400 1401 uart5: serial@994000 { 1402 compatible = "qcom,geni-uart"; 1403 reg = <0x0 0x994000 0x0 0x4000>; 1404 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1405 clock-names = "se"; 1406 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, 1407 <&qup_uart5_tx>, <&qup_uart5_rx>; 1408 pinctrl-names = "default"; 1409 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1410 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1411 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1412 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1413 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1414 interconnect-names = "qup-core", 1415 "qup-config"; 1416 power-domains = <&rpmhpd RPMHPD_CX>; 1417 operating-points-v2 = <&qup_opp_table>; 1418 status = "disabled"; 1419 }; 1420 1421 i2c6: i2c@998000 { 1422 compatible = "qcom,geni-i2c"; 1423 reg = <0x0 0x998000 0x0 0x4000>; 1424 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1425 clock-names = "se"; 1426 pinctrl-0 = <&qup_i2c6_data_clk>; 1427 pinctrl-names = "default"; 1428 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1429 #address-cells = <1>; 1430 #size-cells = <0>; 1431 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1432 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1433 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1434 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1435 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1436 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1437 interconnect-names = "qup-core", 1438 "qup-config", 1439 "qup-memory"; 1440 power-domains = <&rpmhpd RPMHPD_CX>; 1441 required-opps = <&rpmhpd_opp_low_svs>; 1442 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1443 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1444 dma-names = "tx", 1445 "rx"; 1446 status = "disabled"; 1447 }; 1448 1449 spi6: spi@998000 { 1450 compatible = "qcom,geni-spi"; 1451 reg = <0x0 0x998000 0x0 0x4000>; 1452 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1453 clock-names = "se"; 1454 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1455 pinctrl-names = "default"; 1456 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1457 #address-cells = <1>; 1458 #size-cells = <0>; 1459 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1460 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1461 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1462 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1463 interconnect-names = "qup-core", 1464 "qup-config"; 1465 power-domains = <&rpmhpd RPMHPD_CX>; 1466 operating-points-v2 = <&qup_opp_table>; 1467 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1468 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1469 dma-names = "tx", 1470 "rx"; 1471 status = "disabled"; 1472 }; 1473 1474 uart6: serial@998000 { 1475 compatible = "qcom,geni-uart"; 1476 reg = <0x0 0x998000 0x0 0x4000>; 1477 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1478 clock-names = "se"; 1479 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, 1480 <&qup_uart6_tx>, <&qup_uart6_rx>; 1481 pinctrl-names = "default"; 1482 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1483 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1484 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1485 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1486 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1487 interconnect-names = "qup-core", 1488 "qup-config"; 1489 power-domains = <&rpmhpd RPMHPD_CX>; 1490 operating-points-v2 = <&qup_opp_table>; 1491 status = "disabled"; 1492 }; 1493 1494 uart7: serial@99c000 { 1495 compatible = "qcom,geni-debug-uart"; 1496 reg = <0x0 0x0099c000 0x0 0x4000>; 1497 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1498 clock-names = "se"; 1499 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1500 pinctrl-names = "default"; 1501 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1502 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1503 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1504 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1505 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1506 interconnect-names = "qup-core", 1507 "qup-config"; 1508 power-domains = <&rpmhpd RPMHPD_CX>; 1509 operating-points-v2 = <&qup_opp_table>; 1510 status = "disabled"; 1511 }; 1512 }; 1513 1514 gpi_dma1: dma-controller@a00000 { 1515 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; 1516 reg = <0x0 0xa00000 0x0 0x60000>; 1517 #dma-cells = <3>; 1518 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1530 iommus = <&apps_smmu 0x456 0x0>; 1531 dma-channels = <12>; 1532 dma-channel-mask = <0xfff>; 1533 dma-coherent; 1534 status = "disabled"; 1535 }; 1536 1537 qupv3_id_1: geniqup@ac0000 { 1538 compatible = "qcom,geni-se-qup"; 1539 reg = <0x0 0xac0000 0x0 0x2000>; 1540 ranges; 1541 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1542 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1543 clock-names = "m-ahb", 1544 "s-ahb"; 1545 #address-cells = <2>; 1546 #size-cells = <2>; 1547 iommus = <&apps_smmu 0x443 0x0>; 1548 dma-coherent; 1549 status = "disabled"; 1550 1551 i2c8: i2c@a80000 { 1552 compatible = "qcom,geni-i2c"; 1553 reg = <0x0 0xa80000 0x0 0x4000>; 1554 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1555 clock-names = "se"; 1556 pinctrl-0 = <&qup_i2c8_data_clk>; 1557 pinctrl-names = "default"; 1558 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1559 #address-cells = <1>; 1560 #size-cells = <0>; 1561 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1562 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1563 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1564 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1565 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1566 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1567 interconnect-names = "qup-core", 1568 "qup-config", 1569 "qup-memory"; 1570 power-domains = <&rpmhpd RPMHPD_CX>; 1571 required-opps = <&rpmhpd_opp_low_svs>; 1572 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1573 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1574 dma-names = "tx", 1575 "rx"; 1576 status = "disabled"; 1577 }; 1578 1579 spi8: spi@a80000 { 1580 compatible = "qcom,geni-spi"; 1581 reg = <0x0 0xa80000 0x0 0x4000>; 1582 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1583 clock-names = "se"; 1584 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1585 pinctrl-names = "default"; 1586 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1587 #address-cells = <1>; 1588 #size-cells = <0>; 1589 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1590 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1591 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1592 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1593 interconnect-names = "qup-core", 1594 "qup-config"; 1595 power-domains = <&rpmhpd RPMHPD_CX>; 1596 operating-points-v2 = <&qup_opp_table>; 1597 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1598 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1599 dma-names = "tx", 1600 "rx"; 1601 status = "disabled"; 1602 }; 1603 1604 uart8: serial@a80000 { 1605 compatible = "qcom,geni-uart"; 1606 reg = <0x0 0xa80000 0x0 0x4000>; 1607 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1608 clock-names = "se"; 1609 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, 1610 <&qup_uart8_tx>, <&qup_uart8_rx>; 1611 pinctrl-names = "default"; 1612 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1613 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1614 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1615 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1616 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1617 interconnect-names = "qup-core", 1618 "qup-config"; 1619 power-domains = <&rpmhpd RPMHPD_CX>; 1620 operating-points-v2 = <&qup_opp_table>; 1621 status = "disabled"; 1622 }; 1623 1624 i2c9: i2c@a84000 { 1625 compatible = "qcom,geni-i2c"; 1626 reg = <0x0 0xa84000 0x0 0x4000>; 1627 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1628 clock-names = "se"; 1629 pinctrl-0 = <&qup_i2c9_data_clk>; 1630 pinctrl-names = "default"; 1631 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1632 #address-cells = <1>; 1633 #size-cells = <0>; 1634 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1635 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1636 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1637 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1638 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1639 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1640 interconnect-names = "qup-core", 1641 "qup-config", 1642 "qup-memory"; 1643 power-domains = <&rpmhpd RPMHPD_CX>; 1644 required-opps = <&rpmhpd_opp_low_svs>; 1645 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1646 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1647 dma-names = "tx", 1648 "rx"; 1649 status = "disabled"; 1650 }; 1651 1652 spi9: spi@a84000 { 1653 compatible = "qcom,geni-spi"; 1654 reg = <0x0 0xa84000 0x0 0x4000>; 1655 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1656 clock-names = "se"; 1657 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1658 pinctrl-names = "default"; 1659 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1660 #address-cells = <1>; 1661 #size-cells = <0>; 1662 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1663 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1664 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1665 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1666 interconnect-names = "qup-core", 1667 "qup-config"; 1668 power-domains = <&rpmhpd RPMHPD_CX>; 1669 operating-points-v2 = <&qup_opp_table>; 1670 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1671 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1672 dma-names = "tx", 1673 "rx"; 1674 status = "disabled"; 1675 }; 1676 1677 uart9: serial@a84000 { 1678 compatible = "qcom,geni-uart"; 1679 reg = <0x0 0xa84000 0x0 0x4000>; 1680 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1681 clock-names = "se"; 1682 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, 1683 <&qup_uart9_tx>, <&qup_uart9_rx>; 1684 pinctrl-names = "default"; 1685 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1686 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1687 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1688 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1689 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1690 interconnect-names = "qup-core", 1691 "qup-config"; 1692 power-domains = <&rpmhpd RPMHPD_CX>; 1693 operating-points-v2 = <&qup_opp_table>; 1694 status = "disabled"; 1695 }; 1696 1697 i2c10: i2c@a88000 { 1698 compatible = "qcom,geni-i2c"; 1699 reg = <0x0 0xa88000 0x0 0x4000>; 1700 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1701 clock-names = "se"; 1702 pinctrl-0 = <&qup_i2c10_data_clk>; 1703 pinctrl-names = "default"; 1704 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1705 #address-cells = <1>; 1706 #size-cells = <0>; 1707 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1708 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1709 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1710 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1711 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1712 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1713 interconnect-names = "qup-core", 1714 "qup-config", 1715 "qup-memory"; 1716 power-domains = <&rpmhpd RPMHPD_CX>; 1717 required-opps = <&rpmhpd_opp_low_svs>; 1718 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1719 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1720 dma-names = "tx", 1721 "rx"; 1722 status = "disabled"; 1723 }; 1724 1725 spi10: spi@a88000 { 1726 compatible = "qcom,geni-spi"; 1727 reg = <0x0 0xa88000 0x0 0x4000>; 1728 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1729 clock-names = "se"; 1730 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1731 pinctrl-names = "default"; 1732 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1733 #address-cells = <1>; 1734 #size-cells = <0>; 1735 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1736 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1737 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1738 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1739 interconnect-names = "qup-core", 1740 "qup-config"; 1741 power-domains = <&rpmhpd RPMHPD_CX>; 1742 operating-points-v2 = <&qup_opp_table>; 1743 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1744 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1745 dma-names = "tx", 1746 "rx"; 1747 status = "disabled"; 1748 }; 1749 1750 uart10: serial@a88000 { 1751 compatible = "qcom,geni-uart"; 1752 reg = <0x0 0xa88000 0x0 0x4000>; 1753 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1754 clock-names = "se"; 1755 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, 1756 <&qup_uart10_tx>, <&qup_uart10_rx>; 1757 pinctrl-names = "default"; 1758 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1759 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1760 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1761 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1762 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1763 interconnect-names = "qup-core", 1764 "qup-config"; 1765 power-domains = <&rpmhpd RPMHPD_CX>; 1766 operating-points-v2 = <&qup_opp_table>; 1767 status = "disabled"; 1768 }; 1769 1770 i2c11: i2c@a8c000 { 1771 compatible = "qcom,geni-i2c"; 1772 reg = <0x0 0xa8c000 0x0 0x4000>; 1773 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1774 clock-names = "se"; 1775 pinctrl-0 = <&qup_i2c11_data_clk>; 1776 pinctrl-names = "default"; 1777 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1778 #address-cells = <1>; 1779 #size-cells = <0>; 1780 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1781 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1782 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1783 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1784 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1785 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1786 interconnect-names = "qup-core", 1787 "qup-config", 1788 "qup-memory"; 1789 power-domains = <&rpmhpd RPMHPD_CX>; 1790 required-opps = <&rpmhpd_opp_low_svs>; 1791 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1792 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1793 dma-names = "tx", 1794 "rx"; 1795 status = "disabled"; 1796 }; 1797 1798 uart11: serial@a8c000 { 1799 compatible = "qcom,geni-uart"; 1800 reg = <0x0 0xa8c000 0x0 0x4000>; 1801 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1802 clock-names = "se"; 1803 pinctrl-0 = <&qup_uart11_tx>, <&qup_uart11_rx>; 1804 pinctrl-names = "default"; 1805 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1806 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1807 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1808 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1809 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1810 interconnect-names = "qup-core", 1811 "qup-config"; 1812 power-domains = <&rpmhpd RPMHPD_CX>; 1813 operating-points-v2 = <&qup_opp_table>; 1814 status = "disabled"; 1815 }; 1816 1817 i2c12: i2c@a90000 { 1818 compatible = "qcom,geni-i2c"; 1819 reg = <0x0 0xa90000 0x0 0x4000>; 1820 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1821 clock-names = "se"; 1822 pinctrl-0 = <&qup_i2c12_data_clk>; 1823 pinctrl-names = "default"; 1824 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1825 #address-cells = <1>; 1826 #size-cells = <0>; 1827 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1828 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1829 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1830 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1831 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1832 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1833 interconnect-names = "qup-core", 1834 "qup-config", 1835 "qup-memory"; 1836 power-domains = <&rpmhpd RPMHPD_CX>; 1837 required-opps = <&rpmhpd_opp_low_svs>; 1838 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1839 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1840 dma-names = "tx", 1841 "rx"; 1842 status = "disabled"; 1843 }; 1844 1845 spi12: spi@a90000 { 1846 compatible = "qcom,geni-spi"; 1847 reg = <0x0 0xa90000 0x0 0x4000>; 1848 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1849 clock-names = "se"; 1850 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1851 pinctrl-names = "default"; 1852 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1853 #address-cells = <1>; 1854 #size-cells = <0>; 1855 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1856 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1857 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1858 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1859 interconnect-names = "qup-core", 1860 "qup-config"; 1861 power-domains = <&rpmhpd RPMHPD_CX>; 1862 operating-points-v2 = <&qup_opp_table>; 1863 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1864 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1865 dma-names = "tx", 1866 "rx"; 1867 status = "disabled"; 1868 }; 1869 1870 uart12: serial@a90000 { 1871 compatible = "qcom,geni-uart"; 1872 reg = <0x0 0xa90000 0x0 0x4000>; 1873 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1874 clock-names = "se"; 1875 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, 1876 <&qup_uart12_tx>, <&qup_uart12_rx>; 1877 pinctrl-names = "default"; 1878 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1879 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1880 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1881 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1882 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1883 interconnect-names = "qup-core", 1884 "qup-config"; 1885 power-domains = <&rpmhpd RPMHPD_CX>; 1886 operating-points-v2 = <&qup_opp_table>; 1887 status = "disabled"; 1888 }; 1889 1890 i2c13: i2c@a94000 { 1891 compatible = "qcom,geni-i2c"; 1892 reg = <0x0 0xa94000 0x0 0x4000>; 1893 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1894 clock-names = "se"; 1895 pinctrl-0 = <&qup_i2c13_data_clk>; 1896 pinctrl-names = "default"; 1897 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1898 #address-cells = <1>; 1899 #size-cells = <0>; 1900 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1901 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1902 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1903 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1904 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1905 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1906 interconnect-names = "qup-core", 1907 "qup-config", 1908 "qup-memory"; 1909 power-domains = <&rpmhpd RPMHPD_CX>; 1910 required-opps = <&rpmhpd_opp_low_svs>; 1911 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1912 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1913 dma-names = "tx", 1914 "rx"; 1915 status = "disabled"; 1916 }; 1917 1918 spi13: spi@a94000 { 1919 compatible = "qcom,geni-spi"; 1920 reg = <0x0 0xa94000 0x0 0x4000>; 1921 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1922 clock-names = "se"; 1923 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1924 pinctrl-names = "default"; 1925 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1926 #address-cells = <1>; 1927 #size-cells = <0>; 1928 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1929 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1930 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1931 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1932 interconnect-names = "qup-core", 1933 "qup-config"; 1934 power-domains = <&rpmhpd RPMHPD_CX>; 1935 operating-points-v2 = <&qup_opp_table>; 1936 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1937 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1938 dma-names = "tx", 1939 "rx"; 1940 status = "disabled"; 1941 }; 1942 1943 uart13: serial@a94000 { 1944 compatible = "qcom,geni-uart"; 1945 reg = <0x0 0xa94000 0x0 0x4000>; 1946 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1947 clock-names = "se"; 1948 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, 1949 <&qup_uart13_tx>, <&qup_uart13_rx>; 1950 pinctrl-names = "default"; 1951 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1952 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1953 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1954 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1955 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1956 interconnect-names = "qup-core", 1957 "qup-config"; 1958 power-domains = <&rpmhpd RPMHPD_CX>; 1959 operating-points-v2 = <&qup_opp_table>; 1960 status = "disabled"; 1961 }; 1962 1963 i2c14: i2c@a98000 { 1964 compatible = "qcom,geni-i2c"; 1965 reg = <0x0 0xa98000 0x0 0x4000>; 1966 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1967 clock-names = "se"; 1968 pinctrl-0 = <&qup_i2c14_data_clk>; 1969 pinctrl-names = "default"; 1970 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1971 #address-cells = <1>; 1972 #size-cells = <0>; 1973 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1974 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1975 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1976 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1977 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1978 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1979 interconnect-names = "qup-core", 1980 "qup-config", 1981 "qup-memory"; 1982 power-domains = <&rpmhpd RPMHPD_CX>; 1983 required-opps = <&rpmhpd_opp_low_svs>; 1984 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1985 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1986 dma-names = "tx", 1987 "rx"; 1988 status = "disabled"; 1989 }; 1990 1991 spi14: spi@a98000 { 1992 compatible = "qcom,geni-spi"; 1993 reg = <0x0 0xa98000 0x0 0x4000>; 1994 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1995 clock-names = "se"; 1996 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1997 pinctrl-names = "default"; 1998 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1999 #address-cells = <1>; 2000 #size-cells = <0>; 2001 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2002 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2003 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2004 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2005 interconnect-names = "qup-core", 2006 "qup-config"; 2007 power-domains = <&rpmhpd RPMHPD_CX>; 2008 operating-points-v2 = <&qup_opp_table>; 2009 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2010 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2011 dma-names = "tx", 2012 "rx"; 2013 status = "disabled"; 2014 }; 2015 2016 uart14: serial@a98000 { 2017 compatible = "qcom,geni-uart"; 2018 reg = <0x0 0xa98000 0x0 0x4000>; 2019 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2020 clock-names = "se"; 2021 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, 2022 <&qup_uart14_tx>, <&qup_uart14_rx>; 2023 pinctrl-names = "default"; 2024 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 2025 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2026 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2027 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2028 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2029 interconnect-names = "qup-core", 2030 "qup-config"; 2031 power-domains = <&rpmhpd RPMHPD_CX>; 2032 operating-points-v2 = <&qup_opp_table>; 2033 status = "disabled"; 2034 }; 2035 2036 i2c15: i2c@a9c000 { 2037 compatible = "qcom,geni-i2c"; 2038 reg = <0x0 0xa9c000 0x0 0x4000>; 2039 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2040 clock-names = "se"; 2041 pinctrl-0 = <&qup_i2c15_data_clk>; 2042 pinctrl-names = "default"; 2043 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2044 #address-cells = <1>; 2045 #size-cells = <0>; 2046 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2047 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2048 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2049 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2050 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2051 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2052 interconnect-names = "qup-core", 2053 "qup-config", 2054 "qup-memory"; 2055 power-domains = <&rpmhpd RPMHPD_CX>; 2056 required-opps = <&rpmhpd_opp_low_svs>; 2057 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2058 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2059 dma-names = "tx", 2060 "rx"; 2061 status = "disabled"; 2062 }; 2063 2064 spi15: spi@a9c000 { 2065 compatible = "qcom,geni-spi"; 2066 reg = <0x0 0xa9c000 0x0 0x4000>; 2067 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2068 clock-names = "se"; 2069 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2070 pinctrl-names = "default"; 2071 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2072 #address-cells = <1>; 2073 #size-cells = <0>; 2074 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2075 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2076 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2077 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2078 interconnect-names = "qup-core", 2079 "qup-config"; 2080 power-domains = <&rpmhpd RPMHPD_CX>; 2081 operating-points-v2 = <&qup_opp_table>; 2082 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2083 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2084 dma-names = "tx", 2085 "rx"; 2086 status = "disabled"; 2087 }; 2088 2089 uart15: serial@a9c000 { 2090 compatible = "qcom,geni-uart"; 2091 reg = <0x0 0xa9c000 0x0 0x4000>; 2092 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2093 clock-names = "se"; 2094 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, 2095 <&qup_uart15_tx>, <&qup_uart15_rx>; 2096 pinctrl-names = "default"; 2097 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2098 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2099 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2100 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2101 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2102 interconnect-names = "qup-core", 2103 "qup-config"; 2104 power-domains = <&rpmhpd RPMHPD_CX>; 2105 operating-points-v2 = <&qup_opp_table>; 2106 status = "disabled"; 2107 }; 2108 }; 2109 2110 gpi_dma3: dma-controller@b00000 { 2111 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; 2112 reg = <0x0 0xb00000 0x0 0x60000>; 2113 #dma-cells = <3>; 2114 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2115 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 2116 <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 2117 <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>; 2118 iommus = <&apps_smmu 0x56 0x0>; 2119 dma-channels = <4>; 2120 dma-channel-mask = <0xf>; 2121 dma-coherent; 2122 status = "disabled"; 2123 }; 2124 2125 qupv3_id_3: geniqup@bc0000 { 2126 compatible = "qcom,geni-se-qup"; 2127 reg = <0x0 0xbc0000 0x0 0x2000>; 2128 ranges; 2129 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, 2130 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; 2131 clock-names = "m-ahb", 2132 "s-ahb"; 2133 #address-cells = <2>; 2134 #size-cells = <2>; 2135 iommus = <&apps_smmu 0x43 0x0>; 2136 dma-coherent; 2137 status = "disabled"; 2138 2139 i2c16: i2c@b80000 { 2140 compatible = "qcom,geni-i2c"; 2141 reg = <0x0 0xb80000 0x0 0x4000>; 2142 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2143 clock-names = "se"; 2144 pinctrl-0 = <&qup_i2c16_data_clk>; 2145 pinctrl-names = "default"; 2146 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 2147 #address-cells = <1>; 2148 #size-cells = <0>; 2149 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2150 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2151 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2152 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2153 <&aggre2_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2154 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2155 interconnect-names = "qup-core", 2156 "qup-config", 2157 "qup-memory"; 2158 power-domains = <&rpmhpd RPMHPD_CX>; 2159 required-opps = <&rpmhpd_opp_low_svs>; 2160 dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>, 2161 <&gpi_dma3 1 0 QCOM_GPI_I2C>; 2162 dma-names = "tx", 2163 "rx"; 2164 status = "disabled"; 2165 }; 2166 2167 spi16: spi@b80000 { 2168 compatible = "qcom,geni-spi"; 2169 reg = <0x0 0xb80000 0x0 0x4000>; 2170 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2171 clock-names = "se"; 2172 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 2173 pinctrl-names = "default"; 2174 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 2175 #address-cells = <1>; 2176 #size-cells = <0>; 2177 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2178 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2179 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2180 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 2181 interconnect-names = "qup-core", 2182 "qup-config"; 2183 power-domains = <&rpmhpd RPMHPD_CX>; 2184 operating-points-v2 = <&qup_opp_table>; 2185 dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>, 2186 <&gpi_dma3 1 0 QCOM_GPI_SPI>; 2187 dma-names = "tx", 2188 "rx"; 2189 status = "disabled"; 2190 }; 2191 2192 uart16: serial@b80000 { 2193 compatible = "qcom,geni-uart"; 2194 reg = <0x0 0xb80000 0x0 0x4000>; 2195 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2196 clock-names = "se"; 2197 pinctrl-0 = <&qup_uart16_cts>, <&qup_uart16_rts>, 2198 <&qup_uart16_tx>, <&qup_uart16_rx>; 2199 pinctrl-names = "default"; 2200 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 2201 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2202 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2203 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2204 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 2205 interconnect-names = "qup-core", 2206 "qup-config"; 2207 power-domains = <&rpmhpd RPMHPD_CX>; 2208 operating-points-v2 = <&qup_opp_table>; 2209 status = "disabled"; 2210 }; 2211 }; 2212 2213 rng: rng@10d2000 { 2214 compatible = "qcom,qcs8300-trng", "qcom,trng"; 2215 reg = <0x0 0x010d2000 0x0 0x1000>; 2216 }; 2217 2218 config_noc: interconnect@14c0000 { 2219 compatible = "qcom,qcs8300-config-noc"; 2220 reg = <0x0 0x014c0000 0x0 0x13080>; 2221 #interconnect-cells = <2>; 2222 qcom,bcm-voters = <&apps_bcm_voter>; 2223 }; 2224 2225 system_noc: interconnect@1680000 { 2226 compatible = "qcom,qcs8300-system-noc"; 2227 reg = <0x0 0x01680000 0x0 0x15080>; 2228 #interconnect-cells = <2>; 2229 qcom,bcm-voters = <&apps_bcm_voter>; 2230 }; 2231 2232 aggre1_noc: interconnect@16c0000 { 2233 compatible = "qcom,qcs8300-aggre1-noc"; 2234 reg = <0x0 0x016c0000 0x0 0x17080>; 2235 #interconnect-cells = <2>; 2236 qcom,bcm-voters = <&apps_bcm_voter>; 2237 }; 2238 2239 aggre2_noc: interconnect@1700000 { 2240 compatible = "qcom,qcs8300-aggre2-noc"; 2241 reg = <0x0 0x01700000 0x0 0x1a080>; 2242 #interconnect-cells = <2>; 2243 qcom,bcm-voters = <&apps_bcm_voter>; 2244 }; 2245 2246 pcie_anoc: interconnect@1760000 { 2247 compatible = "qcom,qcs8300-pcie-anoc"; 2248 reg = <0x0 0x01760000 0x0 0xc080>; 2249 #interconnect-cells = <2>; 2250 qcom,bcm-voters = <&apps_bcm_voter>; 2251 }; 2252 2253 gpdsp_anoc: interconnect@1780000 { 2254 compatible = "qcom,qcs8300-gpdsp-anoc"; 2255 reg = <0x0 0x01780000 0x0 0xd080>; 2256 #interconnect-cells = <2>; 2257 qcom,bcm-voters = <&apps_bcm_voter>; 2258 }; 2259 2260 mmss_noc: interconnect@17a0000 { 2261 compatible = "qcom,qcs8300-mmss-noc"; 2262 reg = <0x0 0x017a0000 0x0 0x40000>; 2263 #interconnect-cells = <2>; 2264 qcom,bcm-voters = <&apps_bcm_voter>; 2265 }; 2266 2267 pcie0: pci@1c00000 { 2268 device_type = "pci"; 2269 compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; 2270 reg = <0x0 0x01c00000 0x0 0x3000>, 2271 <0x0 0x40000000 0x0 0xf20>, 2272 <0x0 0x40000f20 0x0 0xa8>, 2273 <0x0 0x40001000 0x0 0x4000>, 2274 <0x0 0x40100000 0x0 0x100000>, 2275 <0x0 0x01c03000 0x0 0x1000>; 2276 reg-names = "parf", 2277 "dbi", 2278 "elbi", 2279 "atu", 2280 "config", 2281 "mhi"; 2282 #address-cells = <3>; 2283 #size-cells = <2>; 2284 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2285 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2286 bus-range = <0x00 0xff>; 2287 2288 dma-coherent; 2289 2290 linux,pci-domain = <0>; 2291 num-lanes = <2>; 2292 2293 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2294 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2295 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2296 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2297 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2298 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2299 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2300 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2301 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 2302 interrupt-names = "msi0", 2303 "msi1", 2304 "msi2", 2305 "msi3", 2306 "msi4", 2307 "msi5", 2308 "msi6", 2309 "msi7", 2310 "global"; 2311 2312 #interrupt-cells = <1>; 2313 interrupt-map-mask = <0 0 0 0x7>; 2314 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2315 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2316 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 2317 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; 2318 2319 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2320 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2321 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2322 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2323 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 2324 clock-names = "aux", 2325 "cfg", 2326 "bus_master", 2327 "bus_slave", 2328 "slave_q2a"; 2329 2330 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 2331 assigned-clock-rates = <19200000>; 2332 2333 interconnects = <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 2334 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2335 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2336 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 2337 interconnect-names = "pcie-mem", 2338 "cpu-pcie"; 2339 2340 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, 2341 <0x100 &pcie_smmu 0x0001 0x1>; 2342 2343 resets = <&gcc GCC_PCIE_0_BCR>, 2344 <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; 2345 reset-names = "pci", 2346 "link_down"; 2347 2348 power-domains = <&gcc GCC_PCIE_0_GDSC>; 2349 2350 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 2351 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 2352 2353 operating-points-v2 = <&pcie0_opp_table>; 2354 2355 status = "disabled"; 2356 2357 pcie0_opp_table: opp-table { 2358 compatible = "operating-points-v2"; 2359 2360 /* GEN 1 x1 */ 2361 opp-2500000 { 2362 opp-hz = /bits/ 64 <2500000>; 2363 required-opps = <&rpmhpd_opp_svs_l1>; 2364 opp-peak-kBps = <250000 1>; 2365 }; 2366 2367 /* GEN 1 x2 and GEN 2 x1 */ 2368 opp-5000000 { 2369 opp-hz = /bits/ 64 <5000000>; 2370 required-opps = <&rpmhpd_opp_svs_l1>; 2371 opp-peak-kBps = <500000 1>; 2372 }; 2373 2374 /* GEN 2 x2 */ 2375 opp-10000000 { 2376 opp-hz = /bits/ 64 <10000000>; 2377 required-opps = <&rpmhpd_opp_svs_l1>; 2378 opp-peak-kBps = <1000000 1>; 2379 }; 2380 2381 /* GEN 3 x1 */ 2382 opp-8000000 { 2383 opp-hz = /bits/ 64 <8000000>; 2384 required-opps = <&rpmhpd_opp_svs_l1>; 2385 opp-peak-kBps = <984500 1>; 2386 }; 2387 2388 /* GEN 3 x2 and GEN 4 x1 */ 2389 opp-16000000 { 2390 opp-hz = /bits/ 64 <16000000>; 2391 required-opps = <&rpmhpd_opp_nom>; 2392 opp-peak-kBps = <1969000 1>; 2393 }; 2394 2395 /* GEN 4 x2 */ 2396 opp-32000000 { 2397 opp-hz = /bits/ 64 <32000000>; 2398 required-opps = <&rpmhpd_opp_nom>; 2399 opp-peak-kBps = <3938000 1>; 2400 }; 2401 }; 2402 2403 pcieport0: pcie@0 { 2404 device_type = "pci"; 2405 reg = <0x0 0x0 0x0 0x0 0x0>; 2406 bus-range = <0x01 0xff>; 2407 2408 #address-cells = <3>; 2409 #size-cells = <2>; 2410 ranges; 2411 phys = <&pcie0_phy>; 2412 }; 2413 }; 2414 2415 pcie0_phy: phy@1c04000 { 2416 compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy"; 2417 reg = <0x0 0x01c04000 0x0 0x2000>; 2418 2419 clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, 2420 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2421 <&gcc GCC_PCIE_CLKREF_EN>, 2422 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 2423 <&gcc GCC_PCIE_0_PIPE_CLK>, 2424 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; 2425 clock-names = "aux", 2426 "cfg_ahb", 2427 "ref", 2428 "rchng", 2429 "pipe", 2430 "pipediv2"; 2431 2432 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2433 reset-names = "phy"; 2434 2435 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 2436 assigned-clock-rates = <100000000>; 2437 2438 #clock-cells = <0>; 2439 clock-output-names = "pcie_0_pipe_clk"; 2440 2441 #phy-cells = <0>; 2442 2443 status = "disabled"; 2444 }; 2445 2446 pcie1: pci@1c10000 { 2447 device_type = "pci"; 2448 compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; 2449 reg = <0x0 0x01c10000 0x0 0x3000>, 2450 <0x0 0x60000000 0x0 0xf20>, 2451 <0x0 0x60000f20 0x0 0xa8>, 2452 <0x0 0x60001000 0x0 0x4000>, 2453 <0x0 0x60100000 0x0 0x100000>, 2454 <0x0 0x01c13000 0x0 0x1000>; 2455 reg-names = "parf", 2456 "dbi", 2457 "elbi", 2458 "atu", 2459 "config", 2460 "mhi"; 2461 #address-cells = <3>; 2462 #size-cells = <2>; 2463 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 2464 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; 2465 bus-range = <0x00 0xff>; 2466 2467 dma-coherent; 2468 2469 linux,pci-domain = <1>; 2470 num-lanes = <4>; 2471 2472 interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 2473 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 2474 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2475 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2476 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2477 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2478 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2479 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2480 <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>; 2481 interrupt-names = "msi0", 2482 "msi1", 2483 "msi2", 2484 "msi3", 2485 "msi4", 2486 "msi5", 2487 "msi6", 2488 "msi7", 2489 "global"; 2490 #interrupt-cells = <1>; 2491 interrupt-map-mask = <0 0 0 0x7>; 2492 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2493 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2494 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2495 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 2496 2497 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2498 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2499 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2500 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2501 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 2502 clock-names = "aux", 2503 "cfg", 2504 "bus_master", 2505 "bus_slave", 2506 "slave_q2a"; 2507 2508 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2509 assigned-clock-rates = <19200000>; 2510 2511 interconnects = <&pcie_anoc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 2512 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2513 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2514 &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2515 interconnect-names = "pcie-mem", "cpu-pcie"; 2516 2517 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, 2518 <0x100 &pcie_smmu 0x0081 0x1>; 2519 2520 resets = <&gcc GCC_PCIE_1_BCR>, 2521 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 2522 reset-names = "pci", 2523 "link_down"; 2524 2525 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2526 2527 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 2528 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 2529 2530 operating-points-v2 = <&pcie1_opp_table>; 2531 2532 status = "disabled"; 2533 2534 pcie1_opp_table: opp-table { 2535 compatible = "operating-points-v2"; 2536 2537 /* GEN 1 x1 */ 2538 opp-2500000 { 2539 opp-hz = /bits/ 64 <2500000>; 2540 required-opps = <&rpmhpd_opp_svs_l1>; 2541 opp-peak-kBps = <250000 1>; 2542 }; 2543 2544 /* GEN 1 x2 and GEN 2 x1 */ 2545 opp-5000000 { 2546 opp-hz = /bits/ 64 <5000000>; 2547 required-opps = <&rpmhpd_opp_svs_l1>; 2548 opp-peak-kBps = <500000 1>; 2549 }; 2550 2551 /* GEN 1 x4 and GEN 2 x2 */ 2552 opp-10000000 { 2553 opp-hz = /bits/ 64 <10000000>; 2554 required-opps = <&rpmhpd_opp_svs_l1>; 2555 opp-peak-kBps = <1000000 1>; 2556 }; 2557 2558 /* GEN 2 x4 */ 2559 opp-20000000 { 2560 opp-hz = /bits/ 64 <20000000>; 2561 required-opps = <&rpmhpd_opp_low_svs>; 2562 opp-peak-kBps = <2000000 1>; 2563 }; 2564 2565 /* GEN 3 x1 */ 2566 opp-8000000 { 2567 opp-hz = /bits/ 64 <8000000>; 2568 required-opps = <&rpmhpd_opp_svs_l1>; 2569 opp-peak-kBps = <984500 1>; 2570 }; 2571 2572 /* GEN 3 x2 and GEN 4 x1 */ 2573 opp-16000000 { 2574 opp-hz = /bits/ 64 <16000000>; 2575 required-opps = <&rpmhpd_opp_nom>; 2576 opp-peak-kBps = <1969000 1>; 2577 }; 2578 2579 /* GEN 3 x4 and GEN 4 x2 */ 2580 opp-32000000 { 2581 opp-hz = /bits/ 64 <32000000>; 2582 required-opps = <&rpmhpd_opp_nom>; 2583 opp-peak-kBps = <3938000 1>; 2584 }; 2585 2586 /* GEN 4 x4 */ 2587 opp-64000000 { 2588 opp-hz = /bits/ 64 <64000000>; 2589 required-opps = <&rpmhpd_opp_nom>; 2590 opp-peak-kBps = <7876000 1>; 2591 }; 2592 }; 2593 2594 pcieport1: pcie@0 { 2595 device_type = "pci"; 2596 reg = <0x0 0x0 0x0 0x0 0x0>; 2597 bus-range = <0x01 0xff>; 2598 2599 #address-cells = <3>; 2600 #size-cells = <2>; 2601 ranges; 2602 phys = <&pcie1_phy>; 2603 }; 2604 }; 2605 2606 pcie1_phy: phy@1c14000 { 2607 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; 2608 reg = <0x0 0x01c14000 0x0 0x4000>; 2609 2610 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 2611 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2612 <&gcc GCC_PCIE_CLKREF_EN>, 2613 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 2614 <&gcc GCC_PCIE_1_PIPE_CLK>, 2615 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; 2616 clock-names = "aux", 2617 "cfg_ahb", 2618 "ref", 2619 "rchng", 2620 "pipe", 2621 "pipediv2"; 2622 2623 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 2624 assigned-clock-rates = <100000000>; 2625 2626 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2627 reset-names = "phy"; 2628 2629 #clock-cells = <0>; 2630 clock-output-names = "pcie_1_pipe_clk"; 2631 2632 #phy-cells = <0>; 2633 2634 status = "disabled"; 2635 }; 2636 2637 ufs_mem_hc: ufs@1d84000 { 2638 compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 2639 reg = <0x0 0x01d84000 0x0 0x3000>; 2640 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2641 phys = <&ufs_mem_phy>; 2642 phy-names = "ufsphy"; 2643 lanes-per-direction = <2>; 2644 #reset-cells = <1>; 2645 resets = <&gcc GCC_UFS_PHY_BCR>; 2646 reset-names = "rst"; 2647 2648 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2649 required-opps = <&rpmhpd_opp_nom>; 2650 2651 iommus = <&apps_smmu 0x100 0x0>; 2652 dma-coherent; 2653 2654 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2655 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2656 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2657 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 2658 interconnect-names = "ufs-ddr", 2659 "cpu-ufs"; 2660 2661 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2662 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2663 <&gcc GCC_UFS_PHY_AHB_CLK>, 2664 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2665 <&rpmhcc RPMH_CXO_CLK>, 2666 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2667 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2668 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2669 clock-names = "core_clk", 2670 "bus_aggr_clk", 2671 "iface_clk", 2672 "core_clk_unipro", 2673 "ref_clk", 2674 "tx_lane0_sync_clk", 2675 "rx_lane0_sync_clk", 2676 "rx_lane1_sync_clk"; 2677 freq-table-hz = <75000000 300000000>, 2678 <0 0>, 2679 <0 0>, 2680 <75000000 300000000>, 2681 <0 0>, 2682 <0 0>, 2683 <0 0>, 2684 <0 0>; 2685 qcom,ice = <&ice>; 2686 status = "disabled"; 2687 }; 2688 2689 ufs_mem_phy: phy@1d87000 { 2690 compatible = "qcom,qcs8300-qmp-ufs-phy", "qcom,sa8775p-qmp-ufs-phy"; 2691 reg = <0x0 0x01d87000 0x0 0xe10>; 2692 /* 2693 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It 2694 * enables the CXO clock to eDP *and* UFS PHY. 2695 */ 2696 clocks = <&rpmhcc RPMH_CXO_CLK>, 2697 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2698 <&gcc GCC_EDP_REF_CLKREF_EN>; 2699 clock-names = "ref", 2700 "ref_aux", 2701 "qref"; 2702 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2703 2704 resets = <&ufs_mem_hc 0>; 2705 reset-names = "ufsphy"; 2706 2707 #phy-cells = <0>; 2708 status = "disabled"; 2709 }; 2710 2711 cryptobam: dma-controller@1dc4000 { 2712 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2713 reg = <0x0 0x01dc4000 0x0 0x28000>; 2714 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2715 #dma-cells = <1>; 2716 qcom,ee = <0>; 2717 qcom,controlled-remotely; 2718 num-channels = <20>; 2719 qcom,num-ees = <4>; 2720 iommus = <&apps_smmu 0x480 0x00>, 2721 <&apps_smmu 0x481 0x00>; 2722 }; 2723 2724 ice: crypto@1d88000 { 2725 compatible = "qcom,qcs8300-inline-crypto-engine", 2726 "qcom,inline-crypto-engine"; 2727 reg = <0x0 0x01d88000 0x0 0x18000>; 2728 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2729 }; 2730 2731 crypto: crypto@1dfa000 { 2732 compatible = "qcom,qcs8300-qce", "qcom,sm8150-qce", "qcom,qce"; 2733 reg = <0x0 0x01dfa000 0x0 0x6000>; 2734 dmas = <&cryptobam 4>, <&cryptobam 5>; 2735 dma-names = "rx", "tx"; 2736 iommus = <&apps_smmu 0x480 0x0>, 2737 <&apps_smmu 0x481 0x0>; 2738 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS 2739 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2740 interconnect-names = "memory"; 2741 }; 2742 2743 tcsr_mutex: hwlock@1f40000 { 2744 compatible = "qcom,tcsr-mutex"; 2745 reg = <0x0 0x01f40000 0x0 0x20000>; 2746 #hwlock-cells = <1>; 2747 }; 2748 2749 tcsr: syscon@1fc0000 { 2750 compatible = "qcom,qcs8300-tcsr", "syscon"; 2751 reg = <0x0 0x1fc0000 0x0 0x30000>; 2752 }; 2753 2754 remoteproc_adsp: remoteproc@3000000 { 2755 compatible = "qcom,qcs8300-adsp-pas", "qcom,sa8775p-adsp-pas"; 2756 reg = <0x0 0x3000000 0x0 0x00100>; 2757 2758 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2759 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2760 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2761 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2762 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2763 interrupt-names = "wdog", 2764 "fatal", 2765 "ready", 2766 "handover", 2767 "stop-ack"; 2768 2769 clocks = <&rpmhcc RPMH_CXO_CLK>; 2770 clock-names = "xo"; 2771 2772 power-domains = <&rpmhpd RPMHPD_LCX>, 2773 <&rpmhpd RPMHPD_LMX>; 2774 power-domain-names = "lcx", 2775 "lmx"; 2776 2777 memory-region = <&adsp_mem>; 2778 2779 qcom,qmp = <&aoss_qmp>; 2780 2781 qcom,smem-states = <&smp2p_adsp_out 0>; 2782 qcom,smem-state-names = "stop"; 2783 2784 status = "disabled"; 2785 2786 remoteproc_adsp_glink: glink-edge { 2787 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2788 IPCC_MPROC_SIGNAL_GLINK_QMP 2789 IRQ_TYPE_EDGE_RISING>; 2790 mboxes = <&ipcc IPCC_CLIENT_LPASS 2791 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2792 2793 label = "lpass"; 2794 qcom,remote-pid = <2>; 2795 2796 fastrpc { 2797 compatible = "qcom,fastrpc"; 2798 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2799 label = "adsp"; 2800 memory-region = <&adsp_rpc_remote_heap_mem>; 2801 qcom,vmids = <QCOM_SCM_VMID_LPASS 2802 QCOM_SCM_VMID_ADSP_HEAP>; 2803 #address-cells = <1>; 2804 #size-cells = <0>; 2805 2806 compute-cb@3 { 2807 compatible = "qcom,fastrpc-compute-cb"; 2808 reg = <3>; 2809 iommus = <&apps_smmu 0x2003 0x0>; 2810 dma-coherent; 2811 }; 2812 2813 compute-cb@4 { 2814 compatible = "qcom,fastrpc-compute-cb"; 2815 reg = <4>; 2816 iommus = <&apps_smmu 0x2004 0x0>; 2817 dma-coherent; 2818 }; 2819 2820 compute-cb@5 { 2821 compatible = "qcom,fastrpc-compute-cb"; 2822 reg = <5>; 2823 iommus = <&apps_smmu 0x2005 0x0>; 2824 dma-coherent; 2825 }; 2826 }; 2827 2828 gpr { 2829 compatible = "qcom,gpr"; 2830 qcom,glink-channels = "adsp_apps"; 2831 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2832 qcom,intents = <512 20>; 2833 #address-cells = <1>; 2834 #size-cells = <0>; 2835 2836 q6apm: service@1 { 2837 compatible = "qcom,q6apm"; 2838 reg = <GPR_APM_MODULE_IID>; 2839 #sound-dai-cells = <0>; 2840 qcom,protection-domain = "avs/audio", 2841 "msm/adsp/audio_pd"; 2842 2843 q6apmbedai: bedais { 2844 compatible = "qcom,q6apm-lpass-dais"; 2845 #sound-dai-cells = <1>; 2846 }; 2847 2848 q6apmdai: dais { 2849 compatible = "qcom,q6apm-dais"; 2850 iommus = <&apps_smmu 0x2001 0x0>; 2851 }; 2852 }; 2853 2854 q6prm: service@2 { 2855 compatible = "qcom,q6prm"; 2856 reg = <GPR_PRM_MODULE_IID>; 2857 qcom,protection-domain = "avs/audio", 2858 "msm/adsp/audio_pd"; 2859 2860 q6prmcc: clock-controller { 2861 compatible = "qcom,q6prm-lpass-clocks"; 2862 #clock-cells = <2>; 2863 }; 2864 }; 2865 }; 2866 }; 2867 }; 2868 2869 lpass_ag_noc: interconnect@3c40000 { 2870 compatible = "qcom,qcs8300-lpass-ag-noc"; 2871 reg = <0x0 0x03c40000 0x0 0x17200>; 2872 #interconnect-cells = <2>; 2873 qcom,bcm-voters = <&apps_bcm_voter>; 2874 }; 2875 2876 ctcu@4001000 { 2877 compatible = "qcom,qcs8300-ctcu", "qcom,sa8775p-ctcu"; 2878 reg = <0x0 0x04001000 0x0 0x1000>; 2879 2880 clocks = <&aoss_qmp>; 2881 clock-names = "apb"; 2882 2883 in-ports { 2884 #address-cells = <1>; 2885 #size-cells = <0>; 2886 2887 port@0 { 2888 reg = <0>; 2889 2890 ctcu_in0: endpoint { 2891 remote-endpoint = <&etr0_out>; 2892 }; 2893 }; 2894 2895 port@1 { 2896 reg = <1>; 2897 2898 ctcu_in1: endpoint { 2899 remote-endpoint = <&etr1_out>; 2900 }; 2901 }; 2902 }; 2903 }; 2904 2905 stm@4002000 { 2906 compatible = "arm,coresight-stm", "arm,primecell"; 2907 reg = <0x0 0x04002000 0x0 0x1000>, 2908 <0x0 0x16280000 0x0 0x180000>; 2909 reg-names = "stm-base", 2910 "stm-stimulus-base"; 2911 2912 clocks = <&aoss_qmp>; 2913 clock-names = "apb_pclk"; 2914 2915 out-ports { 2916 port { 2917 stm_out: endpoint { 2918 remote-endpoint = <&funnel0_in7>; 2919 }; 2920 }; 2921 }; 2922 }; 2923 2924 tpda@4004000 { 2925 compatible = "qcom,coresight-tpda", "arm,primecell"; 2926 reg = <0x0 0x04004000 0x0 0x1000>; 2927 2928 clocks = <&aoss_qmp>; 2929 clock-names = "apb_pclk"; 2930 2931 in-ports { 2932 #address-cells = <1>; 2933 #size-cells = <0>; 2934 2935 port@0 { 2936 reg = <0>; 2937 2938 swao_rep_out0: endpoint { 2939 remote-endpoint = <&qdss_rep_in>; 2940 }; 2941 }; 2942 2943 port@1 { 2944 reg = <1>; 2945 2946 qdss_tpda_in1: endpoint { 2947 remote-endpoint = <&qdss_tpdm1_out>; 2948 }; 2949 }; 2950 }; 2951 2952 out-ports { 2953 port { 2954 qdss_tpda_out: endpoint { 2955 remote-endpoint = <&funnel0_in6>; 2956 }; 2957 }; 2958 }; 2959 }; 2960 2961 tpdm@400f000 { 2962 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2963 reg = <0x0 0x0400f000 0x0 0x1000>; 2964 2965 clocks = <&aoss_qmp>; 2966 clock-names = "apb_pclk"; 2967 2968 qcom,cmb-element-bits = <32>; 2969 qcom,cmb-msrs-num = <32>; 2970 2971 out-ports { 2972 port { 2973 qdss_tpdm1_out: endpoint { 2974 remote-endpoint = <&qdss_tpda_in1>; 2975 }; 2976 }; 2977 }; 2978 }; 2979 2980 funnel@4041000 { 2981 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2982 reg = <0x0 0x04041000 0x0 0x1000>; 2983 2984 clocks = <&aoss_qmp>; 2985 clock-names = "apb_pclk"; 2986 2987 in-ports { 2988 #address-cells = <1>; 2989 #size-cells = <0>; 2990 2991 port@6 { 2992 reg = <6>; 2993 2994 funnel0_in6: endpoint { 2995 remote-endpoint = <&qdss_tpda_out>; 2996 }; 2997 }; 2998 2999 port@7 { 3000 reg = <7>; 3001 3002 funnel0_in7: endpoint { 3003 remote-endpoint = <&stm_out>; 3004 }; 3005 }; 3006 }; 3007 3008 out-ports { 3009 port { 3010 funnel0_out: endpoint { 3011 remote-endpoint = <&qdss_funnel_in0>; 3012 }; 3013 }; 3014 }; 3015 }; 3016 3017 funnel@4042000 { 3018 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3019 reg = <0x0 0x04042000 0x0 0x1000>; 3020 3021 clocks = <&aoss_qmp>; 3022 clock-names = "apb_pclk"; 3023 3024 in-ports { 3025 #address-cells = <1>; 3026 #size-cells = <0>; 3027 3028 port@4 { 3029 reg = <4>; 3030 3031 funnel1_in4: endpoint { 3032 remote-endpoint = <&apss_funnel1_out>; 3033 }; 3034 }; 3035 3036 port@5 { 3037 reg = <5>; 3038 3039 funnel1_in5: endpoint { 3040 remote-endpoint = <&dlct0_funnel_out>; 3041 }; 3042 }; 3043 3044 port@6 { 3045 reg = <6>; 3046 3047 funnel1_in6: endpoint { 3048 remote-endpoint = <&dlmm_funnel_out>; 3049 }; 3050 }; 3051 3052 port@7 { 3053 reg = <7>; 3054 3055 funnel1_in7: endpoint { 3056 remote-endpoint = <&dlst_ch_funnel_out>; 3057 }; 3058 }; 3059 }; 3060 3061 out-ports { 3062 port { 3063 funnel1_out: endpoint { 3064 remote-endpoint = <&qdss_funnel_in1>; 3065 }; 3066 }; 3067 }; 3068 }; 3069 3070 funnel@4045000 { 3071 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3072 reg = <0x0 0x04045000 0x0 0x1000>; 3073 3074 clocks = <&aoss_qmp>; 3075 clock-names = "apb_pclk"; 3076 3077 in-ports { 3078 #address-cells = <1>; 3079 #size-cells = <0>; 3080 3081 port@0 { 3082 reg = <0>; 3083 3084 qdss_funnel_in0: endpoint { 3085 remote-endpoint = <&funnel0_out>; 3086 }; 3087 }; 3088 3089 port@1 { 3090 reg = <1>; 3091 3092 qdss_funnel_in1: endpoint { 3093 remote-endpoint = <&funnel1_out>; 3094 }; 3095 }; 3096 }; 3097 3098 out-ports { 3099 port { 3100 qdss_funnel_out: endpoint { 3101 remote-endpoint = <&aoss_funnel_in7>; 3102 }; 3103 }; 3104 }; 3105 }; 3106 3107 replicator@4046000 { 3108 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3109 reg = <0x0 0x04046000 0x0 0x1000>; 3110 3111 clocks = <&aoss_qmp>; 3112 clock-names = "apb_pclk"; 3113 3114 in-ports { 3115 port { 3116 qdss_rep_in: endpoint { 3117 remote-endpoint = <&swao_rep_out0>; 3118 }; 3119 }; 3120 }; 3121 3122 out-ports { 3123 port { 3124 qdss_rep_out0: endpoint { 3125 remote-endpoint = <&etr_rep_in>; 3126 }; 3127 }; 3128 }; 3129 }; 3130 3131 tmc@4048000 { 3132 compatible = "arm,coresight-tmc", "arm,primecell"; 3133 reg = <0x0 0x04048000 0x0 0x1000>; 3134 3135 clocks = <&aoss_qmp>; 3136 clock-names = "apb_pclk"; 3137 iommus = <&apps_smmu 0x04c0 0x00>; 3138 3139 arm,scatter-gather; 3140 3141 in-ports { 3142 port { 3143 etr0_in: endpoint { 3144 remote-endpoint = <&etr_rep_out0>; 3145 }; 3146 }; 3147 }; 3148 3149 out-ports { 3150 port { 3151 etr0_out: endpoint { 3152 remote-endpoint = <&ctcu_in0>; 3153 }; 3154 }; 3155 }; 3156 }; 3157 3158 replicator@404e000 { 3159 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3160 reg = <0x0 0x0404e000 0x0 0x1000>; 3161 3162 clocks = <&aoss_qmp>; 3163 clock-names = "apb_pclk"; 3164 3165 in-ports { 3166 port { 3167 etr_rep_in: endpoint { 3168 remote-endpoint = <&qdss_rep_out0>; 3169 }; 3170 }; 3171 }; 3172 3173 out-ports { 3174 #address-cells = <1>; 3175 #size-cells = <0>; 3176 3177 port@0 { 3178 reg = <0>; 3179 3180 etr_rep_out0: endpoint { 3181 remote-endpoint = <&etr0_in>; 3182 }; 3183 }; 3184 3185 port@1 { 3186 reg = <1>; 3187 3188 etr_rep_out1: endpoint { 3189 remote-endpoint = <&etr1_in>; 3190 }; 3191 }; 3192 }; 3193 }; 3194 3195 tmc@404f000 { 3196 compatible = "arm,coresight-tmc", "arm,primecell"; 3197 reg = <0x0 0x0404f000 0x0 0x1000>; 3198 3199 clocks = <&aoss_qmp>; 3200 clock-names = "apb_pclk"; 3201 iommus = <&apps_smmu 0x04a0 0x40>; 3202 3203 arm,scatter-gather; 3204 arm,buffer-size = <0x400000>; 3205 3206 in-ports { 3207 port { 3208 etr1_in: endpoint { 3209 remote-endpoint = <&etr_rep_out1>; 3210 }; 3211 }; 3212 }; 3213 3214 out-ports { 3215 port { 3216 etr1_out: endpoint { 3217 remote-endpoint = <&ctcu_in1>; 3218 }; 3219 }; 3220 }; 3221 }; 3222 3223 tpdm@4841000 { 3224 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3225 reg = <0x0 0x04841000 0x0 0x1000>; 3226 3227 clocks = <&aoss_qmp>; 3228 clock-names = "apb_pclk"; 3229 3230 qcom,cmb-element-bits = <32>; 3231 qcom,cmb-msrs-num = <32>; 3232 3233 out-ports { 3234 port { 3235 prng_tpdm_out: endpoint { 3236 remote-endpoint = <&dlct0_tpda_in19>; 3237 }; 3238 }; 3239 }; 3240 }; 3241 3242 tpdm@4850000 { 3243 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3244 reg = <0x0 0x04850000 0x0 0x1000>; 3245 3246 clocks = <&aoss_qmp>; 3247 clock-names = "apb_pclk"; 3248 3249 qcom,cmb-element-bits = <64>; 3250 qcom,cmb-msrs-num = <32>; 3251 qcom,dsb-element-bits = <32>; 3252 qcom,dsb-msrs-num = <32>; 3253 3254 out-ports { 3255 port { 3256 pimem_tpdm_out: endpoint { 3257 remote-endpoint = <&dlct0_tpda_in25>; 3258 }; 3259 }; 3260 }; 3261 }; 3262 3263 tpdm@4860000 { 3264 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3265 reg = <0x0 0x04860000 0x0 0x1000>; 3266 3267 clocks = <&aoss_qmp>; 3268 clock-names = "apb_pclk"; 3269 3270 qcom,dsb-element-bits = <32>; 3271 qcom,dsb-msrs-num = <32>; 3272 3273 out-ports { 3274 port { 3275 dlst_ch_tpdm0_out: endpoint { 3276 remote-endpoint = <&dlst_ch_tpda_in8>; 3277 }; 3278 }; 3279 }; 3280 }; 3281 3282 tpda@4864000 { 3283 compatible = "qcom,coresight-tpda", "arm,primecell"; 3284 reg = <0x0 0x04864000 0x0 0x1000>; 3285 3286 clocks = <&aoss_qmp>; 3287 clock-names = "apb_pclk"; 3288 3289 in-ports { 3290 #address-cells = <1>; 3291 #size-cells = <0>; 3292 3293 port@8 { 3294 reg = <8>; 3295 3296 dlst_ch_tpda_in8: endpoint { 3297 remote-endpoint = <&dlst_ch_tpdm0_out>; 3298 }; 3299 }; 3300 }; 3301 3302 out-ports { 3303 port { 3304 dlst_ch_tpda_out: endpoint { 3305 remote-endpoint = <&dlst_ch_funnel_in0>; 3306 }; 3307 }; 3308 }; 3309 }; 3310 3311 funnel@4865000 { 3312 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3313 reg = <0x0 0x04865000 0x0 0x1000>; 3314 3315 clocks = <&aoss_qmp>; 3316 clock-names = "apb_pclk"; 3317 3318 in-ports { 3319 #address-cells = <1>; 3320 #size-cells = <0>; 3321 3322 port@0 { 3323 reg = <0>; 3324 3325 dlst_ch_funnel_in0: endpoint { 3326 remote-endpoint = <&dlst_ch_tpda_out>; 3327 }; 3328 }; 3329 3330 port@4 { 3331 reg = <4>; 3332 3333 dlst_ch_funnel_in4: endpoint { 3334 remote-endpoint = <&dlst_funnel_out>; 3335 }; 3336 }; 3337 3338 port@6 { 3339 reg = <6>; 3340 3341 dlst_ch_funnel_in6: endpoint { 3342 remote-endpoint = <&gdsp_funnel_out>; 3343 }; 3344 }; 3345 }; 3346 3347 out-ports { 3348 port { 3349 dlst_ch_funnel_out: endpoint { 3350 remote-endpoint = <&funnel1_in7>; 3351 }; 3352 }; 3353 }; 3354 }; 3355 3356 tpdm@4980000 { 3357 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3358 reg = <0x0 0x04980000 0x0 0x1000>; 3359 3360 clocks = <&aoss_qmp>; 3361 clock-names = "apb_pclk"; 3362 3363 qcom,dsb-element-bits = <32>; 3364 qcom,dsb-msrs-num = <32>; 3365 3366 out-ports { 3367 port { 3368 turing2_tpdm_out: endpoint { 3369 remote-endpoint = <&turing2_funnel_in0>; 3370 }; 3371 }; 3372 }; 3373 }; 3374 3375 funnel@4983000 { 3376 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3377 reg = <0x0 0x04983000 0x0 0x1000>; 3378 3379 clocks = <&aoss_qmp>; 3380 clock-names = "apb_pclk"; 3381 3382 in-ports { 3383 port { 3384 turing2_funnel_in0: endpoint { 3385 remote-endpoint = <&turing2_tpdm_out>; 3386 }; 3387 }; 3388 }; 3389 3390 out-ports { 3391 port { 3392 turing2_funnel_out0: endpoint { 3393 remote-endpoint = <&gdsp_tpda_in5>; 3394 }; 3395 }; 3396 }; 3397 }; 3398 3399 tpdm@4ac0000 { 3400 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3401 reg = <0x0 0x04ac0000 0x0 0x1000>; 3402 3403 clocks = <&aoss_qmp>; 3404 clock-names = "apb_pclk"; 3405 3406 qcom,dsb-element-bits = <32>; 3407 qcom,dsb-msrs-num = <32>; 3408 3409 out-ports { 3410 port { 3411 dlmm_tpdm0_out: endpoint { 3412 remote-endpoint = <&dlmm_tpda_in27>; 3413 }; 3414 }; 3415 }; 3416 }; 3417 3418 tpda@4ac4000 { 3419 compatible = "qcom,coresight-tpda", "arm,primecell"; 3420 reg = <0x0 0x04ac4000 0x0 0x1000>; 3421 3422 clocks = <&aoss_qmp>; 3423 clock-names = "apb_pclk"; 3424 3425 in-ports { 3426 #address-cells = <1>; 3427 #size-cells = <0>; 3428 3429 port@1b { 3430 reg = <27>; 3431 3432 dlmm_tpda_in27: endpoint { 3433 remote-endpoint = <&dlmm_tpdm0_out>; 3434 }; 3435 }; 3436 }; 3437 3438 out-ports { 3439 port { 3440 dlmm_tpda_out: endpoint { 3441 remote-endpoint = <&dlmm_funnel_in0>; 3442 }; 3443 }; 3444 }; 3445 }; 3446 3447 funnel@4ac5000 { 3448 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3449 reg = <0x0 0x04ac5000 0x0 0x1000>; 3450 3451 clocks = <&aoss_qmp>; 3452 clock-names = "apb_pclk"; 3453 3454 in-ports { 3455 port { 3456 dlmm_funnel_in0: endpoint { 3457 remote-endpoint = <&dlmm_tpda_out>; 3458 }; 3459 }; 3460 }; 3461 3462 out-ports { 3463 port { 3464 dlmm_funnel_out: endpoint { 3465 remote-endpoint = <&funnel1_in6>; 3466 }; 3467 }; 3468 }; 3469 }; 3470 3471 tpdm@4ad0000 { 3472 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3473 reg = <0x0 0x04ad0000 0x0 0x1000>; 3474 3475 clocks = <&aoss_qmp>; 3476 clock-names = "apb_pclk"; 3477 3478 qcom,dsb-element-bits = <32>; 3479 qcom,dsb-msrs-num = <32>; 3480 3481 out-ports { 3482 port { 3483 dlct0_tpdm0_out: endpoint { 3484 remote-endpoint = <&dlct0_tpda_in26>; 3485 }; 3486 }; 3487 }; 3488 }; 3489 3490 tpda@4ad3000 { 3491 compatible = "qcom,coresight-tpda", "arm,primecell"; 3492 reg = <0x0 0x04ad3000 0x0 0x1000>; 3493 3494 clocks = <&aoss_qmp>; 3495 clock-names = "apb_pclk"; 3496 3497 in-ports { 3498 #address-cells = <1>; 3499 #size-cells = <0>; 3500 3501 port@13 { 3502 reg = <19>; 3503 3504 dlct0_tpda_in19: endpoint { 3505 remote-endpoint = <&prng_tpdm_out>; 3506 }; 3507 }; 3508 3509 port@19 { 3510 reg = <25>; 3511 3512 dlct0_tpda_in25: endpoint { 3513 remote-endpoint = <&pimem_tpdm_out>; 3514 }; 3515 }; 3516 3517 port@1a { 3518 reg = <26>; 3519 3520 dlct0_tpda_in26: endpoint { 3521 remote-endpoint = <&dlct0_tpdm0_out>; 3522 }; 3523 }; 3524 }; 3525 3526 out-ports { 3527 port { 3528 dlct0_tpda_out: endpoint { 3529 remote-endpoint = <&dlct0_funnel_in0>; 3530 }; 3531 }; 3532 }; 3533 }; 3534 3535 funnel@4ad4000 { 3536 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3537 reg = <0x0 0x04ad4000 0x0 0x1000>; 3538 3539 clocks = <&aoss_qmp>; 3540 clock-names = "apb_pclk"; 3541 3542 in-ports { 3543 #address-cells = <1>; 3544 #size-cells = <0>; 3545 3546 port@0 { 3547 reg = <0>; 3548 3549 dlct0_funnel_in0: endpoint { 3550 remote-endpoint = <&dlct0_tpda_out>; 3551 }; 3552 }; 3553 3554 port@4 { 3555 reg = <4>; 3556 3557 dlct0_funnel_in4: endpoint { 3558 remote-endpoint = <&ddr_funnel5_out>; 3559 }; 3560 }; 3561 }; 3562 3563 out-ports { 3564 port { 3565 dlct0_funnel_out: endpoint { 3566 remote-endpoint = <&funnel1_in5>; 3567 }; 3568 }; 3569 }; 3570 }; 3571 3572 funnel@4b04000 { 3573 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3574 reg = <0x0 0x04b04000 0x0 0x1000>; 3575 3576 clocks = <&aoss_qmp>; 3577 clock-names = "apb_pclk"; 3578 3579 in-ports { 3580 #address-cells = <1>; 3581 #size-cells = <0>; 3582 3583 port@6 { 3584 reg = <6>; 3585 3586 aoss_funnel_in6: endpoint { 3587 remote-endpoint = <&aoss_tpda_out>; 3588 }; 3589 }; 3590 3591 port@7 { 3592 reg = <7>; 3593 3594 aoss_funnel_in7: endpoint { 3595 remote-endpoint = <&qdss_funnel_out>; 3596 }; 3597 }; 3598 }; 3599 3600 out-ports { 3601 port { 3602 aoss_funnel_out: endpoint { 3603 remote-endpoint = <&etf0_in>; 3604 }; 3605 }; 3606 }; 3607 }; 3608 3609 tmc_etf: tmc@4b05000 { 3610 compatible = "arm,coresight-tmc", "arm,primecell"; 3611 reg = <0x0 0x04b05000 0x0 0x1000>; 3612 3613 clocks = <&aoss_qmp>; 3614 clock-names = "apb_pclk"; 3615 3616 in-ports { 3617 port { 3618 etf0_in: endpoint { 3619 remote-endpoint = <&aoss_funnel_out>; 3620 }; 3621 }; 3622 }; 3623 3624 out-ports { 3625 port { 3626 etf0_out: endpoint { 3627 remote-endpoint = <&swao_rep_in>; 3628 }; 3629 }; 3630 }; 3631 }; 3632 3633 replicator@4b06000 { 3634 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3635 reg = <0x0 0x04b06000 0x0 0x1000>; 3636 3637 clocks = <&aoss_qmp>; 3638 clock-names = "apb_pclk"; 3639 3640 in-ports { 3641 port { 3642 swao_rep_in: endpoint { 3643 remote-endpoint = <&etf0_out>; 3644 }; 3645 }; 3646 }; 3647 3648 out-ports { 3649 #address-cells = <1>; 3650 #size-cells = <0>; 3651 3652 port@1 { 3653 reg = <1>; 3654 3655 swao_rep_out1: endpoint { 3656 remote-endpoint = <&eud_in>; 3657 }; 3658 }; 3659 }; 3660 }; 3661 3662 tpda@4b08000 { 3663 compatible = "qcom,coresight-tpda", "arm,primecell"; 3664 reg = <0x0 0x04b08000 0x0 0x1000>; 3665 3666 clocks = <&aoss_qmp>; 3667 clock-names = "apb_pclk"; 3668 3669 in-ports { 3670 #address-cells = <1>; 3671 #size-cells = <0>; 3672 3673 port@0 { 3674 reg = <0>; 3675 3676 aoss_tpda_in0: endpoint { 3677 remote-endpoint = <&aoss_tpdm0_out>; 3678 }; 3679 }; 3680 3681 port@1 { 3682 reg = <1>; 3683 3684 aoss_tpda_in1: endpoint { 3685 remote-endpoint = <&aoss_tpdm1_out>; 3686 }; 3687 }; 3688 3689 port@2 { 3690 reg = <2>; 3691 3692 aoss_tpda_in2: endpoint { 3693 remote-endpoint = <&aoss_tpdm2_out>; 3694 }; 3695 }; 3696 3697 port@3 { 3698 reg = <3>; 3699 3700 aoss_tpda_in3: endpoint { 3701 remote-endpoint = <&aoss_tpdm3_out>; 3702 }; 3703 }; 3704 3705 port@4 { 3706 reg = <4>; 3707 3708 aoss_tpda_in4: endpoint { 3709 remote-endpoint = <&aoss_tpdm4_out>; 3710 }; 3711 }; 3712 }; 3713 3714 out-ports { 3715 port { 3716 aoss_tpda_out: endpoint { 3717 remote-endpoint = <&aoss_funnel_in6>; 3718 }; 3719 }; 3720 }; 3721 }; 3722 3723 tpdm@4b09000 { 3724 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3725 reg = <0x0 0x04b09000 0x0 0x1000>; 3726 3727 clocks = <&aoss_qmp>; 3728 clock-names = "apb_pclk"; 3729 3730 qcom,cmb-element-bits = <64>; 3731 qcom,cmb-msrs-num = <32>; 3732 3733 out-ports { 3734 port { 3735 aoss_tpdm0_out: endpoint { 3736 remote-endpoint = <&aoss_tpda_in0>; 3737 }; 3738 }; 3739 }; 3740 }; 3741 3742 tpdm@4b0a000 { 3743 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3744 reg = <0x0 0x04b0a000 0x0 0x1000>; 3745 3746 clocks = <&aoss_qmp>; 3747 clock-names = "apb_pclk"; 3748 3749 qcom,cmb-element-bits = <64>; 3750 qcom,cmb-msrs-num = <32>; 3751 3752 out-ports { 3753 port { 3754 aoss_tpdm1_out: endpoint { 3755 remote-endpoint = <&aoss_tpda_in1>; 3756 }; 3757 }; 3758 }; 3759 }; 3760 3761 tpdm@4b0b000 { 3762 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3763 reg = <0x0 0x04b0b000 0x0 0x1000>; 3764 3765 clocks = <&aoss_qmp>; 3766 clock-names = "apb_pclk"; 3767 3768 qcom,cmb-element-bits = <64>; 3769 qcom,cmb-msrs-num = <32>; 3770 3771 out-ports { 3772 port { 3773 aoss_tpdm2_out: endpoint { 3774 remote-endpoint = <&aoss_tpda_in2>; 3775 }; 3776 }; 3777 }; 3778 }; 3779 3780 tpdm@4b0c000 { 3781 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3782 reg = <0x0 0x04b0c000 0x0 0x1000>; 3783 3784 clocks = <&aoss_qmp>; 3785 clock-names = "apb_pclk"; 3786 3787 qcom,cmb-element-bits = <64>; 3788 qcom,cmb-msrs-num = <32>; 3789 3790 out-ports { 3791 port { 3792 aoss_tpdm3_out: endpoint { 3793 remote-endpoint = <&aoss_tpda_in3>; 3794 }; 3795 }; 3796 }; 3797 }; 3798 3799 tpdm@4b0d000 { 3800 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3801 reg = <0x0 0x04b0d000 0x0 0x1000>; 3802 3803 clocks = <&aoss_qmp>; 3804 clock-names = "apb_pclk"; 3805 3806 qcom,dsb-element-bits = <32>; 3807 qcom,dsb-msrs-num = <32>; 3808 3809 out-ports { 3810 port { 3811 aoss_tpdm4_out: endpoint { 3812 remote-endpoint = <&aoss_tpda_in4>; 3813 }; 3814 }; 3815 }; 3816 }; 3817 3818 cti@4b13000 { 3819 compatible = "arm,coresight-cti", "arm,primecell"; 3820 reg = <0x0 0x04b13000 0x0 0x1000>; 3821 3822 clocks = <&aoss_qmp>; 3823 clock-names = "apb_pclk"; 3824 }; 3825 3826 tpdm@4b80000 { 3827 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3828 reg = <0x0 0x04b80000 0x0 0x1000>; 3829 3830 clocks = <&aoss_qmp>; 3831 clock-names = "apb_pclk"; 3832 3833 qcom,dsb-element-bits = <32>; 3834 qcom,dsb-msrs-num = <32>; 3835 3836 out-ports { 3837 port { 3838 turing0_tpdm0_out: endpoint { 3839 remote-endpoint = <&turing0_tpda_in0>; 3840 }; 3841 }; 3842 }; 3843 }; 3844 3845 tpda@4b86000 { 3846 compatible = "qcom,coresight-tpda", "arm,primecell"; 3847 reg = <0x0 0x04b86000 0x0 0x1000>; 3848 3849 clocks = <&aoss_qmp>; 3850 clock-names = "apb_pclk"; 3851 3852 in-ports { 3853 port { 3854 turing0_tpda_in0: endpoint { 3855 remote-endpoint = <&turing0_tpdm0_out>; 3856 }; 3857 }; 3858 }; 3859 3860 out-ports { 3861 port { 3862 turing0_tpda_out: endpoint { 3863 remote-endpoint = <&turing0_funnel_in0>; 3864 }; 3865 }; 3866 }; 3867 }; 3868 3869 funnel@4b87000 { 3870 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3871 reg = <0x0 0x04b87000 0x0 0x1000>; 3872 3873 clocks = <&aoss_qmp>; 3874 clock-names = "apb_pclk"; 3875 3876 in-ports { 3877 port { 3878 turing0_funnel_in0: endpoint { 3879 remote-endpoint = <&turing0_tpda_out>; 3880 }; 3881 }; 3882 }; 3883 3884 out-ports { 3885 port { 3886 turing0_funnel_out: endpoint { 3887 remote-endpoint = <&gdsp_funnel_in4>; 3888 }; 3889 }; 3890 }; 3891 }; 3892 3893 cti@4b8b000 { 3894 compatible = "arm,coresight-cti", "arm,primecell"; 3895 reg = <0x0 0x04b8b000 0x0 0x1000>; 3896 3897 clocks = <&aoss_qmp>; 3898 clock-names = "apb_pclk"; 3899 }; 3900 3901 tpdm@4c40000 { 3902 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3903 reg = <0x0 0x04c40000 0x0 0x1000>; 3904 3905 clocks = <&aoss_qmp>; 3906 clock-names = "apb_pclk"; 3907 3908 qcom,dsb-element-bits = <32>; 3909 qcom,dsb-msrs-num = <32>; 3910 3911 out-ports { 3912 port { 3913 gdsp_tpdm0_out: endpoint { 3914 remote-endpoint = <&gdsp_tpda_in8>; 3915 }; 3916 }; 3917 }; 3918 }; 3919 3920 tpda@4c44000 { 3921 compatible = "qcom,coresight-tpda", "arm,primecell"; 3922 reg = <0x0 0x04c44000 0x0 0x1000>; 3923 3924 clocks = <&aoss_qmp>; 3925 clock-names = "apb_pclk"; 3926 3927 in-ports { 3928 #address-cells = <1>; 3929 #size-cells = <0>; 3930 3931 port@5 { 3932 reg = <5>; 3933 3934 gdsp_tpda_in5: endpoint { 3935 remote-endpoint = <&turing2_funnel_out0>; 3936 }; 3937 }; 3938 3939 port@8 { 3940 reg = <8>; 3941 3942 gdsp_tpda_in8: endpoint { 3943 remote-endpoint = <&gdsp_tpdm0_out>; 3944 }; 3945 }; 3946 }; 3947 3948 out-ports { 3949 port { 3950 gdsp_tpda_out: endpoint { 3951 remote-endpoint = <&gdsp_funnel_in0>; 3952 }; 3953 }; 3954 }; 3955 }; 3956 3957 funnel@4c45000 { 3958 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3959 reg = <0x0 0x04c45000 0x0 0x1000>; 3960 3961 clocks = <&aoss_qmp>; 3962 clock-names = "apb_pclk"; 3963 3964 in-ports { 3965 #address-cells = <1>; 3966 #size-cells = <0>; 3967 3968 port@0 { 3969 reg = <0>; 3970 3971 gdsp_funnel_in0: endpoint { 3972 remote-endpoint = <&gdsp_tpda_out>; 3973 }; 3974 }; 3975 3976 port@4 { 3977 reg = <4>; 3978 3979 gdsp_funnel_in4: endpoint { 3980 remote-endpoint = <&turing0_funnel_out>; 3981 }; 3982 }; 3983 }; 3984 3985 out-ports { 3986 port { 3987 gdsp_funnel_out: endpoint { 3988 remote-endpoint = <&dlst_ch_funnel_in6>; 3989 }; 3990 }; 3991 }; 3992 }; 3993 3994 tpdm@4c50000 { 3995 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3996 reg = <0x0 0x04c50000 0x0 0x1000>; 3997 3998 clocks = <&aoss_qmp>; 3999 clock-names = "apb_pclk"; 4000 4001 qcom,dsb-element-bits = <32>; 4002 qcom,dsb-msrs-num = <32>; 4003 4004 out-ports { 4005 port { 4006 dlst_tpdm0_out: endpoint { 4007 remote-endpoint = <&dlst_tpda_in8>; 4008 }; 4009 }; 4010 }; 4011 }; 4012 4013 tpda@4c54000 { 4014 compatible = "qcom,coresight-tpda", "arm,primecell"; 4015 reg = <0x0 0x04c54000 0x0 0x1000>; 4016 4017 clocks = <&aoss_qmp>; 4018 clock-names = "apb_pclk"; 4019 4020 in-ports { 4021 #address-cells = <1>; 4022 #size-cells = <0>; 4023 4024 port@8 { 4025 reg = <8>; 4026 4027 dlst_tpda_in8: endpoint { 4028 remote-endpoint = <&dlst_tpdm0_out>; 4029 }; 4030 }; 4031 }; 4032 4033 out-ports { 4034 port { 4035 dlst_tpda_out: endpoint { 4036 remote-endpoint = <&dlst_funnel_in0>; 4037 }; 4038 }; 4039 }; 4040 }; 4041 4042 funnel@4c55000 { 4043 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4044 reg = <0x0 0x04c55000 0x0 0x1000>; 4045 4046 clocks = <&aoss_qmp>; 4047 clock-names = "apb_pclk"; 4048 4049 in-ports { 4050 port { 4051 dlst_funnel_in0: endpoint { 4052 remote-endpoint = <&dlst_tpda_out>; 4053 }; 4054 }; 4055 }; 4056 4057 out-ports { 4058 port { 4059 dlst_funnel_out: endpoint { 4060 remote-endpoint = <&dlst_ch_funnel_in4>; 4061 }; 4062 }; 4063 }; 4064 }; 4065 4066 tpdm@4e00000 { 4067 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4068 reg = <0x0 0x04e00000 0x0 0x1000>; 4069 4070 clocks = <&aoss_qmp>; 4071 clock-names = "apb_pclk"; 4072 4073 qcom,dsb-element-bits = <32>; 4074 qcom,dsb-msrs-num = <32>; 4075 qcom,cmb-element-bits = <32>; 4076 qcom,cmb-msrs-num = <32>; 4077 4078 out-ports { 4079 port { 4080 ddr_tpdm3_out: endpoint { 4081 remote-endpoint = <&ddr_tpda_in4>; 4082 }; 4083 }; 4084 }; 4085 }; 4086 4087 tpda@4e03000 { 4088 compatible = "qcom,coresight-tpda", "arm,primecell"; 4089 reg = <0x0 0x04e03000 0x0 0x1000>; 4090 4091 clocks = <&aoss_qmp>; 4092 clock-names = "apb_pclk"; 4093 4094 in-ports { 4095 #address-cells = <1>; 4096 #size-cells = <0>; 4097 4098 port@0 { 4099 reg = <0>; 4100 4101 ddr_tpda_in0: endpoint { 4102 remote-endpoint = <&ddr_funnel0_out0>; 4103 }; 4104 }; 4105 4106 port@1 { 4107 reg = <1>; 4108 4109 ddr_tpda_in1: endpoint { 4110 remote-endpoint = <&ddr_funnel1_out0>; 4111 }; 4112 }; 4113 4114 port@4 { 4115 reg = <4>; 4116 4117 ddr_tpda_in4: endpoint { 4118 remote-endpoint = <&ddr_tpdm3_out>; 4119 }; 4120 }; 4121 }; 4122 4123 out-ports { 4124 port { 4125 ddr_tpda_out: endpoint { 4126 remote-endpoint = <&ddr_funnel5_in0>; 4127 }; 4128 }; 4129 }; 4130 }; 4131 4132 funnel@4e04000 { 4133 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4134 reg = <0x0 0x04e04000 0x0 0x1000>; 4135 4136 clocks = <&aoss_qmp>; 4137 clock-names = "apb_pclk"; 4138 4139 in-ports { 4140 port { 4141 ddr_funnel5_in0: endpoint { 4142 remote-endpoint = <&ddr_tpda_out>; 4143 }; 4144 }; 4145 }; 4146 4147 out-ports { 4148 port { 4149 ddr_funnel5_out: endpoint { 4150 remote-endpoint = <&dlct0_funnel_in4>; 4151 }; 4152 }; 4153 }; 4154 }; 4155 4156 tpdm@4e10000 { 4157 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4158 reg = <0x0 0x04e10000 0x0 0x1000>; 4159 4160 clocks = <&aoss_qmp>; 4161 clock-names = "apb_pclk"; 4162 4163 qcom,dsb-element-bits = <32>; 4164 qcom,dsb-msrs-num = <32>; 4165 4166 out-ports { 4167 port { 4168 ddr_tpdm0_out: endpoint { 4169 remote-endpoint = <&ddr_funnel0_in0>; 4170 }; 4171 }; 4172 }; 4173 }; 4174 4175 funnel@4e12000 { 4176 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4177 reg = <0x0 0x04e12000 0x0 0x1000>; 4178 4179 clocks = <&aoss_qmp>; 4180 clock-names = "apb_pclk"; 4181 4182 in-ports { 4183 port { 4184 ddr_funnel0_in0: endpoint { 4185 remote-endpoint = <&ddr_tpdm0_out>; 4186 }; 4187 }; 4188 }; 4189 4190 out-ports { 4191 port { 4192 ddr_funnel0_out0: endpoint { 4193 remote-endpoint = <&ddr_tpda_in0>; 4194 }; 4195 }; 4196 }; 4197 }; 4198 4199 tpdm@4e20000 { 4200 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4201 reg = <0x0 0x04e20000 0x0 0x1000>; 4202 4203 clocks = <&aoss_qmp>; 4204 clock-names = "apb_pclk"; 4205 4206 qcom,dsb-element-bits = <32>; 4207 qcom,dsb-msrs-num = <32>; 4208 4209 out-ports { 4210 port { 4211 ddr_tpdm1_out: endpoint { 4212 remote-endpoint = <&ddr_funnel1_in0>; 4213 }; 4214 }; 4215 }; 4216 }; 4217 4218 funnel@4e22000 { 4219 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4220 reg = <0x0 0x04e22000 0x0 0x1000>; 4221 4222 clocks = <&aoss_qmp>; 4223 clock-names = "apb_pclk"; 4224 4225 in-ports { 4226 port { 4227 ddr_funnel1_in0: endpoint { 4228 remote-endpoint = <&ddr_tpdm1_out>; 4229 }; 4230 }; 4231 }; 4232 4233 out-ports { 4234 port { 4235 ddr_funnel1_out0: endpoint { 4236 remote-endpoint = <&ddr_tpda_in1>; 4237 }; 4238 }; 4239 }; 4240 }; 4241 4242 etm@6040000 { 4243 compatible = "arm,primecell"; 4244 reg = <0x0 0x06040000 0x0 0x1000>; 4245 cpu = <&cpu0>; 4246 4247 clocks = <&aoss_qmp>; 4248 clock-names = "apb_pclk"; 4249 4250 arm,coresight-loses-context-with-cpu; 4251 qcom,skip-power-up; 4252 4253 out-ports { 4254 port { 4255 etm0_out: endpoint { 4256 remote-endpoint = <&apss_funnel0_in0>; 4257 }; 4258 }; 4259 }; 4260 }; 4261 4262 etm@6140000 { 4263 compatible = "arm,primecell"; 4264 reg = <0x0 0x06140000 0x0 0x1000>; 4265 cpu = <&cpu1>; 4266 4267 clocks = <&aoss_qmp>; 4268 clock-names = "apb_pclk"; 4269 4270 arm,coresight-loses-context-with-cpu; 4271 qcom,skip-power-up; 4272 4273 out-ports { 4274 port { 4275 etm1_out: endpoint { 4276 remote-endpoint = <&apss_funnel0_in1>; 4277 }; 4278 }; 4279 }; 4280 }; 4281 4282 etm@6240000 { 4283 compatible = "arm,primecell"; 4284 reg = <0x0 0x06240000 0x0 0x1000>; 4285 cpu = <&cpu2>; 4286 4287 clocks = <&aoss_qmp>; 4288 clock-names = "apb_pclk"; 4289 4290 arm,coresight-loses-context-with-cpu; 4291 qcom,skip-power-up; 4292 4293 out-ports { 4294 port { 4295 etm2_out: endpoint { 4296 remote-endpoint = <&apss_funnel0_in2>; 4297 }; 4298 }; 4299 }; 4300 }; 4301 4302 etm@6340000 { 4303 compatible = "arm,primecell"; 4304 reg = <0x0 0x06340000 0x0 0x1000>; 4305 cpu = <&cpu3>; 4306 4307 clocks = <&aoss_qmp>; 4308 clock-names = "apb_pclk"; 4309 4310 arm,coresight-loses-context-with-cpu; 4311 qcom,skip-power-up; 4312 4313 out-ports { 4314 port { 4315 etm3_out: endpoint { 4316 remote-endpoint = <&apss_funnel0_in3>; 4317 }; 4318 }; 4319 }; 4320 }; 4321 4322 etm@6440000 { 4323 compatible = "arm,primecell"; 4324 reg = <0x0 0x06440000 0x0 0x1000>; 4325 cpu = <&cpu4>; 4326 4327 clocks = <&aoss_qmp>; 4328 clock-names = "apb_pclk"; 4329 4330 arm,coresight-loses-context-with-cpu; 4331 qcom,skip-power-up; 4332 4333 out-ports { 4334 port { 4335 etm4_out: endpoint { 4336 remote-endpoint = <&apss_funnel0_in4>; 4337 }; 4338 }; 4339 }; 4340 }; 4341 4342 etm@6540000 { 4343 compatible = "arm,primecell"; 4344 reg = <0x0 0x06540000 0x0 0x1000>; 4345 cpu = <&cpu5>; 4346 4347 clocks = <&aoss_qmp>; 4348 clock-names = "apb_pclk"; 4349 4350 arm,coresight-loses-context-with-cpu; 4351 qcom,skip-power-up; 4352 4353 out-ports { 4354 port { 4355 etm5_out: endpoint { 4356 remote-endpoint = <&apss_funnel0_in5>; 4357 }; 4358 }; 4359 }; 4360 }; 4361 4362 etm@6640000 { 4363 compatible = "arm,primecell"; 4364 reg = <0x0 0x06640000 0x0 0x1000>; 4365 cpu = <&cpu6>; 4366 4367 clocks = <&aoss_qmp>; 4368 clock-names = "apb_pclk"; 4369 4370 arm,coresight-loses-context-with-cpu; 4371 qcom,skip-power-up; 4372 4373 out-ports { 4374 port { 4375 etm6_out: endpoint { 4376 remote-endpoint = <&apss_funnel0_in6>; 4377 }; 4378 }; 4379 }; 4380 }; 4381 4382 etm@6740000 { 4383 compatible = "arm,primecell"; 4384 reg = <0x0 0x06740000 0x0 0x1000>; 4385 cpu = <&cpu7>; 4386 4387 clocks = <&aoss_qmp>; 4388 clock-names = "apb_pclk"; 4389 4390 arm,coresight-loses-context-with-cpu; 4391 qcom,skip-power-up; 4392 4393 out-ports { 4394 port { 4395 etm7_out: endpoint { 4396 remote-endpoint = <&apss_funnel0_in7>; 4397 }; 4398 }; 4399 }; 4400 }; 4401 4402 funnel@6800000 { 4403 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4404 reg = <0x0 0x06800000 0x0 0x1000>; 4405 4406 clocks = <&aoss_qmp>; 4407 clock-names = "apb_pclk"; 4408 4409 in-ports { 4410 #address-cells = <1>; 4411 #size-cells = <0>; 4412 4413 port@0 { 4414 reg = <0>; 4415 4416 apss_funnel0_in0: endpoint { 4417 remote-endpoint = <&etm0_out>; 4418 }; 4419 }; 4420 4421 port@1 { 4422 reg = <1>; 4423 4424 apss_funnel0_in1: endpoint { 4425 remote-endpoint = <&etm1_out>; 4426 }; 4427 }; 4428 4429 port@2 { 4430 reg = <2>; 4431 4432 apss_funnel0_in2: endpoint { 4433 remote-endpoint = <&etm2_out>; 4434 }; 4435 }; 4436 4437 port@3 { 4438 reg = <3>; 4439 4440 apss_funnel0_in3: endpoint { 4441 remote-endpoint = <&etm3_out>; 4442 }; 4443 }; 4444 4445 port@4 { 4446 reg = <4>; 4447 4448 apss_funnel0_in4: endpoint { 4449 remote-endpoint = <&etm4_out>; 4450 }; 4451 }; 4452 4453 port@5 { 4454 reg = <5>; 4455 4456 apss_funnel0_in5: endpoint { 4457 remote-endpoint = <&etm5_out>; 4458 }; 4459 }; 4460 4461 port@6 { 4462 reg = <6>; 4463 4464 apss_funnel0_in6: endpoint { 4465 remote-endpoint = <&etm6_out>; 4466 }; 4467 }; 4468 4469 port@7 { 4470 reg = <7>; 4471 4472 apss_funnel0_in7: endpoint { 4473 remote-endpoint = <&etm7_out>; 4474 }; 4475 }; 4476 }; 4477 4478 out-ports { 4479 port { 4480 apss_funnel0_out: endpoint { 4481 remote-endpoint = <&apss_funnel1_in0>; 4482 }; 4483 }; 4484 }; 4485 }; 4486 4487 funnel@6810000 { 4488 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4489 reg = <0x0 0x06810000 0x0 0x1000>; 4490 4491 clocks = <&aoss_qmp>; 4492 clock-names = "apb_pclk"; 4493 4494 in-ports { 4495 #address-cells = <1>; 4496 #size-cells = <0>; 4497 4498 port@0 { 4499 reg = <0>; 4500 4501 apss_funnel1_in0: endpoint { 4502 remote-endpoint = <&apss_funnel0_out>; 4503 }; 4504 }; 4505 4506 port@3 { 4507 reg = <3>; 4508 4509 apss_funnel1_in3: endpoint { 4510 remote-endpoint = <&apss_tpda_out>; 4511 }; 4512 }; 4513 }; 4514 4515 out-ports { 4516 port { 4517 apss_funnel1_out: endpoint { 4518 remote-endpoint = <&funnel1_in4>; 4519 }; 4520 }; 4521 }; 4522 }; 4523 4524 cti@682b000 { 4525 compatible = "arm,coresight-cti", "arm,primecell"; 4526 reg = <0x0 0x0682b000 0x0 0x1000>; 4527 4528 clocks = <&aoss_qmp>; 4529 clock-names = "apb_pclk"; 4530 }; 4531 4532 tpdm@6860000 { 4533 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4534 reg = <0x0 0x06860000 0x0 0x1000>; 4535 4536 clocks = <&aoss_qmp>; 4537 clock-names = "apb_pclk"; 4538 4539 qcom,cmb-element-bits = <64>; 4540 qcom,cmb-msrs-num = <32>; 4541 4542 out-ports { 4543 port { 4544 apss_tpdm3_out: endpoint { 4545 remote-endpoint = <&apss_tpda_in3>; 4546 }; 4547 }; 4548 }; 4549 }; 4550 4551 tpdm@6861000 { 4552 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4553 reg = <0x0 0x06861000 0x0 0x1000>; 4554 4555 clocks = <&aoss_qmp>; 4556 clock-names = "apb_pclk"; 4557 4558 qcom,dsb-element-bits = <32>; 4559 qcom,dsb-msrs-num = <32>; 4560 4561 out-ports { 4562 port { 4563 apss_tpdm4_out: endpoint { 4564 remote-endpoint = <&apss_tpda_in4>; 4565 }; 4566 }; 4567 }; 4568 }; 4569 4570 tpda@6863000 { 4571 compatible = "qcom,coresight-tpda", "arm,primecell"; 4572 reg = <0x0 0x06863000 0x0 0x1000>; 4573 4574 clocks = <&aoss_qmp>; 4575 clock-names = "apb_pclk"; 4576 4577 in-ports { 4578 #address-cells = <1>; 4579 #size-cells = <0>; 4580 4581 port@0 { 4582 reg = <0>; 4583 4584 apss_tpda_in0: endpoint { 4585 remote-endpoint = <&apss_tpdm0_out>; 4586 }; 4587 }; 4588 4589 port@1 { 4590 reg = <1>; 4591 4592 apss_tpda_in1: endpoint { 4593 remote-endpoint = <&apss_tpdm1_out>; 4594 }; 4595 }; 4596 4597 port@2 { 4598 reg = <2>; 4599 4600 apss_tpda_in2: endpoint { 4601 remote-endpoint = <&apss_tpdm2_out>; 4602 }; 4603 }; 4604 4605 port@3 { 4606 reg = <3>; 4607 4608 apss_tpda_in3: endpoint { 4609 remote-endpoint = <&apss_tpdm3_out>; 4610 }; 4611 }; 4612 4613 port@4 { 4614 reg = <4>; 4615 4616 apss_tpda_in4: endpoint { 4617 remote-endpoint = <&apss_tpdm4_out>; 4618 }; 4619 }; 4620 }; 4621 4622 out-ports { 4623 port { 4624 apss_tpda_out: endpoint { 4625 remote-endpoint = <&apss_funnel1_in3>; 4626 }; 4627 }; 4628 }; 4629 }; 4630 4631 tpdm@68a0000 { 4632 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4633 reg = <0x0 0x068a0000 0x0 0x1000>; 4634 4635 clocks = <&aoss_qmp>; 4636 clock-names = "apb_pclk"; 4637 4638 qcom,cmb-element-bits = <32>; 4639 qcom,cmb-msrs-num = <32>; 4640 4641 out-ports { 4642 port { 4643 apss_tpdm1_out: endpoint { 4644 remote-endpoint = <&apss_tpda_in1>; 4645 }; 4646 }; 4647 }; 4648 }; 4649 4650 tpdm@68b0000 { 4651 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4652 reg = <0x0 0x068b0000 0x0 0x1000>; 4653 4654 clocks = <&aoss_qmp>; 4655 clock-names = "apb_pclk"; 4656 4657 qcom,cmb-element-bits = <32>; 4658 qcom,cmb-msrs-num = <32>; 4659 4660 out-ports { 4661 port { 4662 apss_tpdm0_out: endpoint { 4663 remote-endpoint = <&apss_tpda_in0>; 4664 }; 4665 }; 4666 }; 4667 }; 4668 4669 tpdm@68c0000 { 4670 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4671 reg = <0x0 0x068c0000 0x0 0x1000>; 4672 4673 clocks = <&aoss_qmp>; 4674 clock-names = "apb_pclk"; 4675 4676 qcom,dsb-element-bits = <32>; 4677 qcom,dsb-msrs-num = <32>; 4678 4679 out-ports { 4680 port { 4681 apss_tpdm2_out: endpoint { 4682 remote-endpoint = <&apss_tpda_in2>; 4683 }; 4684 }; 4685 }; 4686 }; 4687 4688 cti@68e0000 { 4689 compatible = "arm,coresight-cti", "arm,primecell"; 4690 reg = <0x0 0x068e0000 0x0 0x1000>; 4691 4692 clocks = <&aoss_qmp>; 4693 clock-names = "apb_pclk"; 4694 }; 4695 4696 cti@68f0000 { 4697 compatible = "arm,coresight-cti", "arm,primecell"; 4698 reg = <0x0 0x068f0000 0x0 0x1000>; 4699 4700 clocks = <&aoss_qmp>; 4701 clock-names = "apb_pclk"; 4702 }; 4703 4704 cti@6900000 { 4705 compatible = "arm,coresight-cti", "arm,primecell"; 4706 reg = <0x0 0x06900000 0x0 0x1000>; 4707 4708 clocks = <&aoss_qmp>; 4709 clock-names = "apb_pclk"; 4710 }; 4711 4712 sdhc_1: mmc@87c4000 { 4713 compatible = "qcom,qcs8300-sdhci", "qcom,sdhci-msm-v5"; 4714 reg = <0x0 0x087c4000 0x0 0x1000>, 4715 <0x0 0x087c5000 0x0 0x1000>; 4716 reg-names = "hc", 4717 "cqhci"; 4718 4719 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 4720 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>; 4721 interrupt-names = "hc_irq", 4722 "pwr_irq"; 4723 4724 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 4725 <&gcc GCC_SDCC1_APPS_CLK>, 4726 <&rpmhcc RPMH_CXO_CLK>; 4727 clock-names = "iface", 4728 "core", 4729 "xo"; 4730 4731 resets = <&gcc GCC_SDCC1_BCR>; 4732 4733 power-domains = <&rpmhpd RPMHPD_CX>; 4734 operating-points-v2 = <&sdhc1_opp_table>; 4735 iommus = <&apps_smmu 0x0 0x0>; 4736 interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS 4737 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4738 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4739 &config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>; 4740 interconnect-names = "sdhc-ddr", 4741 "cpu-sdhc"; 4742 4743 qcom,dll-config = <0x000f64ee>; 4744 qcom,ddr-config = <0x80040868>; 4745 supports-cqe; 4746 dma-coherent; 4747 4748 status = "disabled"; 4749 4750 sdhc1_opp_table: opp-table { 4751 compatible = "operating-points-v2"; 4752 4753 opp-50000000 { 4754 opp-hz = /bits/ 64 <50000000>; 4755 required-opps = <&rpmhpd_opp_low_svs>; 4756 }; 4757 4758 opp-100000000 { 4759 opp-hz = /bits/ 64 <100000000>; 4760 required-opps = <&rpmhpd_opp_svs>; 4761 }; 4762 4763 opp-200000000 { 4764 opp-hz = /bits/ 64 <200000000>; 4765 required-opps = <&rpmhpd_opp_svs_l1>; 4766 }; 4767 4768 opp-384000000 { 4769 opp-hz = /bits/ 64 <384000000>; 4770 required-opps = <&rpmhpd_opp_nom>; 4771 }; 4772 }; 4773 }; 4774 4775 usb_1_hsphy: phy@8904000 { 4776 compatible = "qcom,qcs8300-usb-hs-phy", 4777 "qcom,usb-snps-hs-7nm-phy"; 4778 reg = <0x0 0x08904000 0x0 0x400>; 4779 4780 clocks = <&rpmhcc RPMH_CXO_CLK>; 4781 clock-names = "ref"; 4782 4783 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; 4784 4785 #phy-cells = <0>; 4786 4787 status = "disabled"; 4788 }; 4789 4790 usb_2_hsphy: phy@8906000 { 4791 compatible = "qcom,qcs8300-usb-hs-phy", 4792 "qcom,usb-snps-hs-7nm-phy"; 4793 reg = <0x0 0x08906000 0x0 0x400>; 4794 4795 clocks = <&rpmhcc RPMH_CXO_CLK>; 4796 clock-names = "ref"; 4797 4798 resets = <&gcc GCC_USB2_PHY_SEC_BCR>; 4799 4800 #phy-cells = <0>; 4801 4802 status = "disabled"; 4803 }; 4804 4805 usb_qmpphy: phy@8907000 { 4806 compatible = "qcom,qcs8300-qmp-usb3-uni-phy"; 4807 reg = <0x0 0x08907000 0x0 0x2000>; 4808 4809 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4810 <&gcc GCC_USB_CLKREF_EN>, 4811 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 4812 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4813 clock-names = "aux", 4814 "ref", 4815 "com_aux", 4816 "pipe"; 4817 4818 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 4819 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 4820 reset-names = "phy", "phy_phy"; 4821 4822 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4823 4824 #clock-cells = <0>; 4825 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 4826 4827 #phy-cells = <0>; 4828 4829 status = "disabled"; 4830 }; 4831 4832 serdes0: phy@8909000 { 4833 compatible = "qcom,qcs8300-dwmac-sgmii-phy", "qcom,sa8775p-dwmac-sgmii-phy"; 4834 reg = <0x0 0x08909000 0x0 0x00000e10>; 4835 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 4836 clock-names = "sgmi_ref"; 4837 #phy-cells = <0>; 4838 status = "disabled"; 4839 }; 4840 4841 refgen: regulator@891c000 { 4842 compatible = "qcom,qcs8300-refgen-regulator", 4843 "qcom,sm8250-refgen-regulator"; 4844 reg = <0x0 0x0891c000 0x0 0x84>; 4845 }; 4846 4847 gpu: gpu@3d00000 { 4848 compatible = "qcom,adreno-623.0", "qcom,adreno"; 4849 reg = <0x0 0x03d00000 0x0 0x40000>, 4850 <0x0 0x03d9e000 0x0 0x1000>, 4851 <0x0 0x03d61000 0x0 0x800>; 4852 reg-names = "kgsl_3d0_reg_memory", 4853 "cx_mem", 4854 "cx_dbgc"; 4855 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4856 iommus = <&adreno_smmu 0 0xc00>, 4857 <&adreno_smmu 1 0xc00>; 4858 operating-points-v2 = <&gpu_opp_table>; 4859 qcom,gmu = <&gmu>; 4860 interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 4861 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4862 interconnect-names = "gfx-mem"; 4863 #cooling-cells = <2>; 4864 4865 nvmem-cells = <&gpu_speed_bin>; 4866 nvmem-cell-names = "speed_bin"; 4867 4868 status = "disabled"; 4869 4870 gpu_zap_shader: zap-shader { 4871 memory-region = <&gpu_microcode_mem>; 4872 }; 4873 4874 gpu_opp_table: opp-table { 4875 compatible = "operating-points-v2"; 4876 4877 opp-877000000 { 4878 opp-hz = /bits/ 64 <877000000>; 4879 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4880 opp-peak-kBps = <12484375>; 4881 opp-supported-hw = <0x1>; 4882 }; 4883 4884 opp-780000000 { 4885 opp-hz = /bits/ 64 <780000000>; 4886 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4887 opp-peak-kBps = <10687500>; 4888 opp-supported-hw = <0x1>; 4889 }; 4890 4891 opp-599000000 { 4892 opp-hz = /bits/ 64 <599000000>; 4893 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4894 opp-peak-kBps = <8171875>; 4895 opp-supported-hw = <0x3>; 4896 }; 4897 4898 opp-479000000 { 4899 opp-hz = /bits/ 64 <479000000>; 4900 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4901 opp-peak-kBps = <5285156>; 4902 opp-supported-hw = <0x3>; 4903 }; 4904 }; 4905 }; 4906 4907 gmu: gmu@3d6a000 { 4908 compatible = "qcom,adreno-gmu-623.0", "qcom,adreno-gmu"; 4909 reg = <0x0 0x03d6a000 0x0 0x34000>, 4910 <0x0 0x03de0000 0x0 0x10000>, 4911 <0x0 0x0b290000 0x0 0x10000>; 4912 reg-names = "gmu", "rscc", "gmu_pdc"; 4913 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4914 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4915 interrupt-names = "hfi", "gmu"; 4916 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 4917 <&gpucc GPU_CC_CXO_CLK>, 4918 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4919 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4920 <&gpucc GPU_CC_AHB_CLK>, 4921 <&gpucc GPU_CC_HUB_CX_INT_CLK>; 4922 clock-names = "gmu", 4923 "cxo", 4924 "axi", 4925 "memnoc", 4926 "ahb", 4927 "hub"; 4928 power-domains = <&gpucc GPU_CC_CX_GDSC>, 4929 <&gpucc GPU_CC_GX_GDSC>; 4930 power-domain-names = "cx", 4931 "gx"; 4932 iommus = <&adreno_smmu 5 0xc00>; 4933 operating-points-v2 = <&gmu_opp_table>; 4934 4935 gmu_opp_table: opp-table { 4936 compatible = "operating-points-v2"; 4937 4938 opp-500000000 { 4939 opp-hz = /bits/ 64 <500000000>; 4940 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4941 }; 4942 }; 4943 }; 4944 4945 gpucc: clock-controller@3d90000 { 4946 compatible = "qcom,qcs8300-gpucc"; 4947 reg = <0x0 0x03d90000 0x0 0xa000>; 4948 clocks = <&rpmhcc RPMH_CXO_CLK>, 4949 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 4950 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 4951 clock-names = "bi_tcxo", 4952 "gcc_gpu_gpll0_clk_src", 4953 "gcc_gpu_gpll0_div_clk_src"; 4954 #clock-cells = <1>; 4955 #reset-cells = <1>; 4956 #power-domain-cells = <1>; 4957 }; 4958 4959 adreno_smmu: iommu@3da0000 { 4960 compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu", 4961 "qcom,smmu-500", "arm,mmu-500"; 4962 reg = <0x0 0x3da0000 0x0 0x20000>; 4963 #iommu-cells = <2>; 4964 #global-interrupts = <2>; 4965 4966 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 4967 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 4968 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 4969 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 4970 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 4971 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 4972 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 4973 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 4974 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 4975 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 4976 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 4977 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 4978 4979 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4980 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 4981 <&gpucc GPU_CC_AHB_CLK>, 4982 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 4983 <&gpucc GPU_CC_CX_GMU_CLK>, 4984 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 4985 <&gpucc GPU_CC_HUB_AON_CLK>; 4986 4987 clock-names = "gcc_gpu_memnoc_gfx_clk", 4988 "gcc_gpu_snoc_dvm_gfx_clk", 4989 "gpu_cc_ahb_clk", 4990 "gpu_cc_hlos1_vote_gpu_smmu_clk", 4991 "gpu_cc_cx_gmu_clk", 4992 "gpu_cc_hub_cx_int_clk", 4993 "gpu_cc_hub_aon_clk"; 4994 power-domains = <&gpucc GPU_CC_CX_GDSC>; 4995 dma-coherent; 4996 }; 4997 4998 pmu@9091000 { 4999 compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 5000 reg = <0x0 0x9091000 0x0 0x1000>; 5001 5002 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>; 5003 5004 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 5005 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5006 5007 operating-points-v2 = <&llcc_bwmon_opp_table>; 5008 5009 llcc_bwmon_opp_table: opp-table { 5010 compatible = "operating-points-v2"; 5011 5012 opp-0 { 5013 opp-peak-kBps = <762000>; 5014 }; 5015 5016 opp-1 { 5017 opp-peak-kBps = <1720000>; 5018 }; 5019 5020 opp-2 { 5021 opp-peak-kBps = <2086000>; 5022 }; 5023 5024 opp-3 { 5025 opp-peak-kBps = <2601000>; 5026 }; 5027 5028 opp-4 { 5029 opp-peak-kBps = <2929000>; 5030 }; 5031 5032 opp-5 { 5033 opp-peak-kBps = <5931000>; 5034 }; 5035 5036 opp-6 { 5037 opp-peak-kBps = <6515000>; 5038 }; 5039 5040 opp-7 { 5041 opp-peak-kBps = <7984000>; 5042 }; 5043 5044 opp-8 { 5045 opp-peak-kBps = <10437000>; 5046 }; 5047 5048 opp-9 { 5049 opp-peak-kBps = <12195000>; 5050 }; 5051 }; 5052 }; 5053 5054 pmu@90b5400 { 5055 compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon"; 5056 reg = <0x0 0x90b5400 0x0 0x600>; 5057 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 5058 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5059 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 5060 5061 operating-points-v2 = <&cpu_bwmon_opp_table>; 5062 5063 cpu_bwmon_opp_table: opp-table { 5064 compatible = "operating-points-v2"; 5065 5066 opp-0 { 5067 opp-peak-kBps = <9155000>; 5068 }; 5069 5070 opp-1 { 5071 opp-peak-kBps = <12298000>; 5072 }; 5073 5074 opp-2 { 5075 opp-peak-kBps = <14236000>; 5076 }; 5077 5078 opp-3 { 5079 opp-peak-kBps = <16265000>; 5080 }; 5081 }; 5082 }; 5083 5084 pmu@90b6400 { 5085 compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon"; 5086 reg = <0x0 0x90b6400 0x0 0x600>; 5087 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 5088 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5089 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 5090 5091 operating-points-v2 = <&cpu_bwmon_opp_table>; 5092 }; 5093 5094 dc_noc: interconnect@90e0000 { 5095 compatible = "qcom,qcs8300-dc-noc"; 5096 reg = <0x0 0x090e0000 0x0 0x5080>; 5097 #interconnect-cells = <2>; 5098 qcom,bcm-voters = <&apps_bcm_voter>; 5099 }; 5100 5101 gem_noc: interconnect@9100000 { 5102 compatible = "qcom,qcs8300-gem-noc"; 5103 reg = <0x0 0x9100000 0x0 0xf7080>; 5104 #interconnect-cells = <2>; 5105 qcom,bcm-voters = <&apps_bcm_voter>; 5106 }; 5107 5108 llcc: system-cache-controller@9200000 { 5109 compatible = "qcom,qcs8300-llcc"; 5110 reg = <0x0 0x09200000 0x0 0x80000>, 5111 <0x0 0x09300000 0x0 0x80000>, 5112 <0x0 0x09400000 0x0 0x80000>, 5113 <0x0 0x09500000 0x0 0x80000>, 5114 <0x0 0x09a00000 0x0 0x80000>; 5115 reg-names = "llcc0_base", 5116 "llcc1_base", 5117 "llcc2_base", 5118 "llcc3_base", 5119 "llcc_broadcast_base"; 5120 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 5121 }; 5122 5123 usb_1: usb@a600000 { 5124 compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3"; 5125 reg = <0x0 0x0a600000 0x0 0xfc100>; 5126 5127 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 5128 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 5129 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 5130 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 5131 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 5132 clock-names = "cfg_noc", 5133 "core", 5134 "iface", 5135 "sleep", 5136 "mock_utmi"; 5137 5138 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5139 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 5140 assigned-clock-rates = <19200000>, <200000000>; 5141 5142 interrupts-extended = <&intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 5143 <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 5144 <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 5145 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 5146 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 5147 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; 5148 interrupt-names = "dwc_usb3", 5149 "pwr_event", 5150 "hs_phy_irq", 5151 "dp_hs_phy_irq", 5152 "dm_hs_phy_irq", 5153 "ss_phy_irq"; 5154 5155 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 5156 required-opps = <&rpmhpd_opp_nom>; 5157 5158 resets = <&gcc GCC_USB30_PRIM_BCR>; 5159 interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 5160 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5161 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 5162 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; 5163 interconnect-names = "usb-ddr", "apps-usb"; 5164 5165 iommus = <&apps_smmu 0x80 0x0>; 5166 phys = <&usb_1_hsphy>, <&usb_qmpphy>; 5167 phy-names = "usb2-phy", "usb3-phy"; 5168 snps,dis_enblslpm_quirk; 5169 snps,dis-u1-entry-quirk; 5170 snps,dis-u2-entry-quirk; 5171 snps,dis_u2_susphy_quirk; 5172 snps,dis_u3_susphy_quirk; 5173 5174 wakeup-source; 5175 5176 status = "disabled"; 5177 }; 5178 5179 usb_2: usb@a400000 { 5180 compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3"; 5181 reg = <0x0 0x0a400000 0x0 0xfc100>; 5182 5183 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 5184 <&gcc GCC_USB20_MASTER_CLK>, 5185 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 5186 <&gcc GCC_USB20_SLEEP_CLK>, 5187 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 5188 clock-names = "cfg_noc", 5189 "core", 5190 "iface", 5191 "sleep", 5192 "mock_utmi"; 5193 5194 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 5195 <&gcc GCC_USB20_MASTER_CLK>; 5196 assigned-clock-rates = <19200000>, <120000000>; 5197 5198 interrupts-extended = <&intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 5199 <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 5200 <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 5201 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 5202 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 5203 interrupt-names = "dwc_usb3", 5204 "pwr_event", 5205 "hs_phy_irq", 5206 "dp_hs_phy_irq", 5207 "dm_hs_phy_irq"; 5208 5209 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 5210 required-opps = <&rpmhpd_opp_nom>; 5211 5212 resets = <&gcc GCC_USB20_PRIM_BCR>; 5213 5214 interconnects = <&aggre1_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 5215 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5216 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 5217 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>; 5218 interconnect-names = "usb-ddr", "apps-usb"; 5219 5220 iommus = <&apps_smmu 0x20 0x0>; 5221 5222 phys = <&usb_2_hsphy>; 5223 phy-names = "usb2-phy"; 5224 maximum-speed = "high-speed"; 5225 5226 snps,dis-u1-entry-quirk; 5227 snps,dis-u2-entry-quirk; 5228 snps,dis_u2_susphy_quirk; 5229 snps,dis_u3_susphy_quirk; 5230 snps,dis_enblslpm_quirk; 5231 5232 qcom,select-utmi-as-pipe-clk; 5233 wakeup-source; 5234 5235 status = "disabled"; 5236 }; 5237 5238 iris: video-codec@aa00000 { 5239 compatible = "qcom,qcs8300-iris"; 5240 5241 reg = <0x0 0x0aa00000 0x0 0xf0000>; 5242 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 5243 5244 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 5245 <&videocc VIDEO_CC_MVS0_GDSC>, 5246 <&rpmhpd RPMHPD_MX>, 5247 <&rpmhpd RPMHPD_MMCX>; 5248 power-domain-names = "venus", 5249 "vcodec0", 5250 "mxc", 5251 "mmcx"; 5252 5253 operating-points-v2 = <&iris_opp_table>; 5254 5255 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 5256 <&videocc VIDEO_CC_MVS0C_CLK>, 5257 <&videocc VIDEO_CC_MVS0_CLK>; 5258 clock-names = "iface", 5259 "core", 5260 "vcodec0_core"; 5261 5262 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5263 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 5264 <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS 5265 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5266 interconnect-names = "cpu-cfg", 5267 "video-mem"; 5268 5269 memory-region = <&video_mem>; 5270 5271 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 5272 reset-names = "bus"; 5273 5274 iommus = <&apps_smmu 0x0880 0x0400>, 5275 <&apps_smmu 0x0887 0x0400>; 5276 dma-coherent; 5277 5278 status = "disabled"; 5279 5280 iris_opp_table: opp-table { 5281 compatible = "operating-points-v2"; 5282 5283 opp-366000000 { 5284 opp-hz = /bits/ 64 <366000000>; 5285 required-opps = <&rpmhpd_opp_svs_l1>, 5286 <&rpmhpd_opp_svs_l1>; 5287 }; 5288 5289 opp-444000000 { 5290 opp-hz = /bits/ 64 <444000000>; 5291 required-opps = <&rpmhpd_opp_nom>, 5292 <&rpmhpd_opp_nom>; 5293 }; 5294 5295 opp-533000000 { 5296 opp-hz = /bits/ 64 <533000000>; 5297 required-opps = <&rpmhpd_opp_turbo>, 5298 <&rpmhpd_opp_turbo>; 5299 }; 5300 5301 opp-560000000 { 5302 opp-hz = /bits/ 64 <560000000>; 5303 required-opps = <&rpmhpd_opp_turbo_l1>, 5304 <&rpmhpd_opp_turbo_l1>; 5305 }; 5306 }; 5307 }; 5308 5309 videocc: clock-controller@abf0000 { 5310 compatible = "qcom,qcs8300-videocc"; 5311 reg = <0x0 0x0abf0000 0x0 0x10000>; 5312 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 5313 <&rpmhcc RPMH_CXO_CLK>, 5314 <&rpmhcc RPMH_CXO_CLK_A>, 5315 <&sleep_clk>; 5316 power-domains = <&rpmhpd RPMHPD_MMCX>; 5317 #clock-cells = <1>; 5318 #reset-cells = <1>; 5319 #power-domain-cells = <1>; 5320 }; 5321 5322 camss: isp@ac78000 { 5323 compatible = "qcom,qcs8300-camss"; 5324 5325 reg = <0x0 0xac78000 0x0 0x1000>, 5326 <0x0 0xac7a000 0x0 0xf00>, 5327 <0x0 0xac7c000 0x0 0xf00>, 5328 <0x0 0xac84000 0x0 0xf00>, 5329 <0x0 0xac88000 0x0 0xf00>, 5330 <0x0 0xac8c000 0x0 0xf00>, 5331 <0x0 0xac90000 0x0 0xf00>, 5332 <0x0 0xac94000 0x0 0xf00>, 5333 <0x0 0xac9c000 0x0 0x2000>, 5334 <0x0 0xac9e000 0x0 0x2000>, 5335 <0x0 0xaca0000 0x0 0x2000>, 5336 <0x0 0xacac000 0x0 0x400>, 5337 <0x0 0xacad000 0x0 0x400>, 5338 <0x0 0xacae000 0x0 0x400>, 5339 <0x0 0xac4d000 0x0 0xf000>, 5340 <0x0 0xac60000 0x0 0xf000>, 5341 <0x0 0xac85000 0x0 0xd00>, 5342 <0x0 0xac89000 0x0 0xd00>, 5343 <0x0 0xac8d000 0x0 0xd00>, 5344 <0x0 0xac91000 0x0 0xd00>, 5345 <0x0 0xac95000 0x0 0xd00>; 5346 reg-names = "csid_wrapper", 5347 "csid0", 5348 "csid1", 5349 "csid_lite0", 5350 "csid_lite1", 5351 "csid_lite2", 5352 "csid_lite3", 5353 "csid_lite4", 5354 "csiphy0", 5355 "csiphy1", 5356 "csiphy2", 5357 "tpg0", 5358 "tpg1", 5359 "tpg2", 5360 "vfe0", 5361 "vfe1", 5362 "vfe_lite0", 5363 "vfe_lite1", 5364 "vfe_lite2", 5365 "vfe_lite3", 5366 "vfe_lite4"; 5367 5368 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 5369 <&camcc CAM_CC_CORE_AHB_CLK>, 5370 <&camcc CAM_CC_CPAS_AHB_CLK>, 5371 <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, 5372 <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, 5373 <&camcc CAM_CC_CPAS_IFE_0_CLK>, 5374 <&camcc CAM_CC_CPAS_IFE_1_CLK>, 5375 <&camcc CAM_CC_CSID_CLK>, 5376 <&camcc CAM_CC_CSIPHY0_CLK>, 5377 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 5378 <&camcc CAM_CC_CSIPHY1_CLK>, 5379 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 5380 <&camcc CAM_CC_CSIPHY2_CLK>, 5381 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 5382 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, 5383 <&gcc GCC_CAMERA_HF_AXI_CLK>, 5384 <&gcc GCC_CAMERA_SF_AXI_CLK>, 5385 <&camcc CAM_CC_ICP_AHB_CLK>, 5386 <&camcc CAM_CC_IFE_0_CLK>, 5387 <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, 5388 <&camcc CAM_CC_IFE_1_CLK>, 5389 <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, 5390 <&camcc CAM_CC_IFE_LITE_CLK>, 5391 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 5392 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 5393 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 5394 clock-names = "camnoc_axi", 5395 "core_ahb", 5396 "cpas_ahb", 5397 "cpas_fast_ahb_clk", 5398 "cpas_vfe_lite", 5399 "cpas_vfe0", 5400 "cpas_vfe1", 5401 "csid", 5402 "csiphy0", 5403 "csiphy0_timer", 5404 "csiphy1", 5405 "csiphy1_timer", 5406 "csiphy2", 5407 "csiphy2_timer", 5408 "csiphy_rx", 5409 "gcc_axi_hf", 5410 "gcc_axi_sf", 5411 "icp_ahb", 5412 "vfe0", 5413 "vfe0_fast_ahb", 5414 "vfe1", 5415 "vfe1_fast_ahb", 5416 "vfe_lite", 5417 "vfe_lite_ahb", 5418 "vfe_lite_cphy_rx", 5419 "vfe_lite_csid"; 5420 5421 interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>, 5422 <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>, 5423 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 5424 <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 5425 <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, 5426 <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, 5427 <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, 5428 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 5429 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 5430 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 5431 <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>, 5432 <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>, 5433 <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>, 5434 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 5435 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 5436 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 5437 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, 5438 <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, 5439 <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, 5440 <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>; 5441 interrupt-names = "csid0", 5442 "csid1", 5443 "csid_lite0", 5444 "csid_lite1", 5445 "csid_lite2", 5446 "csid_lite3", 5447 "csid_lite4", 5448 "csiphy0", 5449 "csiphy1", 5450 "csiphy2", 5451 "tpg0", 5452 "tpg1", 5453 "tpg2", 5454 "vfe0", 5455 "vfe1", 5456 "vfe_lite0", 5457 "vfe_lite1", 5458 "vfe_lite2", 5459 "vfe_lite3", 5460 "vfe_lite4"; 5461 5462 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5463 &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 5464 <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS 5465 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5466 interconnect-names = "ahb", 5467 "hf_0"; 5468 5469 iommus = <&apps_smmu 0x2400 0x20>; 5470 5471 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5472 power-domain-names = "top"; 5473 5474 status = "disabled"; 5475 5476 ports { 5477 #address-cells = <1>; 5478 #size-cells = <0>; 5479 5480 port@0 { 5481 reg = <0>; 5482 }; 5483 5484 port@1 { 5485 reg = <1>; 5486 }; 5487 5488 port@2 { 5489 reg = <2>; 5490 }; 5491 }; 5492 }; 5493 5494 camcc: clock-controller@ade0000 { 5495 compatible = "qcom,qcs8300-camcc"; 5496 reg = <0x0 0x0ade0000 0x0 0x20000>; 5497 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 5498 <&rpmhcc RPMH_CXO_CLK>, 5499 <&rpmhcc RPMH_CXO_CLK_A>, 5500 <&sleep_clk>; 5501 power-domains = <&rpmhpd RPMHPD_MMCX>; 5502 #clock-cells = <1>; 5503 #reset-cells = <1>; 5504 #power-domain-cells = <1>; 5505 }; 5506 5507 mdss: display-subsystem@ae00000 { 5508 compatible = "qcom,qcs8300-mdss"; 5509 reg = <0x0 0x0ae00000 0x0 0x1000>; 5510 reg-names = "mdss"; 5511 5512 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 5513 5514 clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, 5515 <&gcc GCC_DISP_HF_AXI_CLK>, 5516 <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>; 5517 5518 resets = <&dispcc MDSS_DISP_CC_MDSS_CORE_BCR>; 5519 5520 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 5521 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5522 <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS 5523 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5524 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5525 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5526 interconnect-names = "mdp0-mem", 5527 "mdp1-mem", 5528 "cpu-cfg"; 5529 5530 power-domains = <&dispcc MDSS_DISP_CC_MDSS_CORE_GDSC>; 5531 5532 iommus = <&apps_smmu 0x1000 0x402>; 5533 5534 interrupt-controller; 5535 #interrupt-cells = <1>; 5536 5537 #address-cells = <2>; 5538 #size-cells = <2>; 5539 ranges; 5540 5541 status = "disabled"; 5542 5543 mdss_mdp: display-controller@ae01000 { 5544 compatible = "qcom,qcs8300-dpu", "qcom,sa8775p-dpu"; 5545 reg = <0x0 0x0ae01000 0x0 0x8f000>, 5546 <0x0 0x0aeb0000 0x0 0x2008>; 5547 reg-names = "mdp", "vbif"; 5548 5549 interrupts-extended = <&mdss 0>; 5550 5551 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5552 <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, 5553 <&dispcc MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, 5554 <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>, 5555 <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>; 5556 clock-names = "nrt_bus", 5557 "iface", 5558 "lut", 5559 "core", 5560 "vsync"; 5561 5562 assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>; 5563 assigned-clock-rates = <19200000>; 5564 5565 operating-points-v2 = <&mdp_opp_table>; 5566 power-domains = <&rpmhpd RPMHPD_MMCX>; 5567 5568 ports { 5569 #address-cells = <1>; 5570 #size-cells = <0>; 5571 5572 port@0 { 5573 reg = <0>; 5574 5575 dpu_intf0_out: endpoint { 5576 remote-endpoint = <&mdss_dp0_in>; 5577 }; 5578 }; 5579 }; 5580 5581 mdp_opp_table: opp-table { 5582 compatible = "operating-points-v2"; 5583 5584 opp-375000000 { 5585 opp-hz = /bits/ 64 <375000000>; 5586 required-opps = <&rpmhpd_opp_svs_l1>; 5587 }; 5588 5589 opp-500000000 { 5590 opp-hz = /bits/ 64 <500000000>; 5591 required-opps = <&rpmhpd_opp_nom>; 5592 }; 5593 5594 opp-575000000 { 5595 opp-hz = /bits/ 64 <575000000>; 5596 required-opps = <&rpmhpd_opp_turbo>; 5597 }; 5598 5599 opp-650000000 { 5600 opp-hz = /bits/ 64 <650000000>; 5601 required-opps = <&rpmhpd_opp_turbo_l1>; 5602 }; 5603 }; 5604 }; 5605 5606 mdss_dp0_phy: phy@aec2a00 { 5607 compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy"; 5608 5609 reg = <0x0 0x0aec2a00 0x0 0x19c>, 5610 <0x0 0x0aec2200 0x0 0xec>, 5611 <0x0 0x0aec2600 0x0 0xec>, 5612 <0x0 0x0aec2000 0x0 0x1c8>; 5613 5614 clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 5615 <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>; 5616 clock-names = "aux", 5617 "cfg_ahb"; 5618 5619 power-domains = <&rpmhpd RPMHPD_MX>; 5620 5621 #clock-cells = <1>; 5622 #phy-cells = <0>; 5623 5624 status = "disabled"; 5625 }; 5626 5627 mdss_dp0: displayport-controller@af54000 { 5628 compatible = "qcom,qcs8300-dp", "qcom,sa8775p-dp"; 5629 5630 reg = <0x0 0x0af54000 0x0 0x200>, 5631 <0x0 0x0af54200 0x0 0x200>, 5632 <0x0 0x0af55000 0x0 0xc00>, 5633 <0x0 0x0af56000 0x0 0x09c>, 5634 <0x0 0x0af57000 0x0 0x09c>, 5635 <0x0 0x0af58000 0x0 0x09c>, 5636 <0x0 0x0af59000 0x0 0x09c>, 5637 <0x0 0x0af5a000 0x0 0x23c>, 5638 <0x0 0x0af5b000 0x0 0x23c>; 5639 5640 interrupts-extended = <&mdss 12>; 5641 5642 clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, 5643 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 5644 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, 5645 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5646 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 5647 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, 5648 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, 5649 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; 5650 clock-names = "core_iface", 5651 "core_aux", 5652 "ctrl_link", 5653 "ctrl_link_iface", 5654 "stream_pixel", 5655 "stream_1_pixel", 5656 "stream_2_pixel", 5657 "stream_3_pixel"; 5658 assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5659 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 5660 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, 5661 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, 5662 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; 5663 assigned-clock-parents = <&mdss_dp0_phy 0>, 5664 <&mdss_dp0_phy 1>, 5665 <&mdss_dp0_phy 1>, 5666 <&mdss_dp0_phy 1>, 5667 <&mdss_dp0_phy 1>; 5668 phys = <&mdss_dp0_phy>; 5669 phy-names = "dp"; 5670 5671 operating-points-v2 = <&dp_opp_table>; 5672 power-domains = <&rpmhpd RPMHPD_MMCX>; 5673 5674 #sound-dai-cells = <0>; 5675 5676 status = "disabled"; 5677 5678 ports { 5679 #address-cells = <1>; 5680 #size-cells = <0>; 5681 5682 port@0 { 5683 reg = <0>; 5684 5685 mdss_dp0_in: endpoint { 5686 remote-endpoint = <&dpu_intf0_out>; 5687 }; 5688 }; 5689 5690 port@1 { 5691 reg = <1>; 5692 5693 mdss_dp0_out: endpoint { }; 5694 }; 5695 }; 5696 5697 dp_opp_table: opp-table { 5698 compatible = "operating-points-v2"; 5699 5700 opp-160000000 { 5701 opp-hz = /bits/ 64 <160000000>; 5702 required-opps = <&rpmhpd_opp_low_svs>; 5703 }; 5704 5705 opp-270000000 { 5706 opp-hz = /bits/ 64 <270000000>; 5707 required-opps = <&rpmhpd_opp_svs>; 5708 }; 5709 5710 opp-540000000 { 5711 opp-hz = /bits/ 64 <540000000>; 5712 required-opps = <&rpmhpd_opp_svs_l1>; 5713 }; 5714 5715 opp-810000000 { 5716 opp-hz = /bits/ 64 <810000000>; 5717 required-opps = <&rpmhpd_opp_nom>; 5718 }; 5719 }; 5720 }; 5721 }; 5722 5723 dispcc: clock-controller@af00000 { 5724 compatible = "qcom,sa8775p-dispcc0"; 5725 reg = <0x0 0x0af00000 0x0 0x20000>; 5726 clocks = <&gcc GCC_DISP_AHB_CLK>, 5727 <&rpmhcc RPMH_CXO_CLK>, 5728 <&rpmhcc RPMH_CXO_CLK_A>, 5729 <&sleep_clk>, 5730 <&mdss_dp0_phy 0>, 5731 <&mdss_dp0_phy 1>, 5732 <0>, <0>, 5733 <0>, <0>, <0>, <0>; 5734 power-domains = <&rpmhpd RPMHPD_MMCX>; 5735 #clock-cells = <1>; 5736 #reset-cells = <1>; 5737 #power-domain-cells = <1>; 5738 }; 5739 5740 pdc: interrupt-controller@b220000 { 5741 compatible = "qcom,qcs8300-pdc", "qcom,pdc"; 5742 reg = <0x0 0xb220000 0x0 0x30000>, 5743 <0x0 0x17c000f0 0x0 0x64>; 5744 interrupt-parent = <&intc>; 5745 #interrupt-cells = <2>; 5746 interrupt-controller; 5747 qcom,pdc-ranges = <0 480 40>, 5748 <40 140 14>, 5749 <54 263 1>, 5750 <55 306 4>, 5751 <59 312 3>, 5752 <62 374 2>, 5753 <64 434 2>, 5754 <66 438 2>, 5755 <70 520 1>, 5756 <73 523 1>, 5757 <118 568 6>, 5758 <124 609 3>, 5759 <159 638 1>, 5760 <160 720 3>, 5761 <169 728 30>, 5762 <199 416 2>, 5763 <201 449 1>, 5764 <202 89 1>, 5765 <203 451 1>, 5766 <204 462 1>, 5767 <205 264 1>, 5768 <206 579 1>, 5769 <207 653 1>, 5770 <208 656 1>, 5771 <209 659 1>, 5772 <210 122 1>, 5773 <211 699 1>, 5774 <212 705 1>, 5775 <213 450 1>, 5776 <214 643 2>, 5777 <216 646 5>, 5778 <221 390 5>, 5779 <226 700 2>, 5780 <228 440 1>, 5781 <229 663 1>, 5782 <230 524 2>, 5783 <232 612 3>, 5784 <235 723 5>; 5785 }; 5786 5787 tsens2: thermal-sensor@c251000 { 5788 compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; 5789 reg = <0x0 0x0c251000 0x0 0x1000>, 5790 <0x0 0x0c224000 0x0 0x1000>; 5791 interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>, 5792 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 5793 interrupt-names = "uplow", "critical"; 5794 #qcom,sensors = <10>; 5795 #thermal-sensor-cells = <1>; 5796 }; 5797 5798 tsens3: thermal-sensor@c252000 { 5799 compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; 5800 reg = <0x0 0x0c252000 0x0 0x1000>, 5801 <0x0 0x0c225000 0x0 0x1000>; 5802 interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>, 5803 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; 5804 interrupt-names = "uplow", "critical"; 5805 #qcom,sensors = <10>; 5806 #thermal-sensor-cells = <1>; 5807 }; 5808 5809 tsens0: thermal-sensor@c263000 { 5810 compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; 5811 reg = <0x0 0x0c263000 0x0 0x1000>, 5812 <0x0 0x0c222000 0x0 0x1000>; 5813 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 5814 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 5815 interrupt-names = "uplow", "critical"; 5816 #qcom,sensors = <10>; 5817 #thermal-sensor-cells = <1>; 5818 }; 5819 5820 tsens1: thermal-sensor@c265000 { 5821 compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; 5822 reg = <0x0 0x0c265000 0x0 0x1000>, 5823 <0x0 0x0c223000 0x0 0x1000>; 5824 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 5825 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 5826 interrupt-names = "uplow", "critical"; 5827 #qcom,sensors = <10>; 5828 #thermal-sensor-cells = <1>; 5829 }; 5830 5831 aoss_qmp: power-management@c300000 { 5832 compatible = "qcom,qcs8300-aoss-qmp", "qcom,aoss-qmp"; 5833 reg = <0x0 0x0c300000 0x0 0x400>; 5834 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 5835 IPCC_MPROC_SIGNAL_GLINK_QMP 5836 IRQ_TYPE_EDGE_RISING>; 5837 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 5838 #clock-cells = <0>; 5839 }; 5840 5841 sram@c3f0000 { 5842 compatible = "qcom,rpmh-stats"; 5843 reg = <0x0 0x0c3f0000 0x0 0x400>; 5844 }; 5845 5846 spmi_bus: spmi@c440000 { 5847 compatible = "qcom,spmi-pmic-arb"; 5848 reg = <0x0 0x0c440000 0x0 0x1100>, 5849 <0x0 0x0c600000 0x0 0x2000000>, 5850 <0x0 0x0e600000 0x0 0x100000>, 5851 <0x0 0x0e700000 0x0 0xa0000>, 5852 <0x0 0x0c40a000 0x0 0x26000>; 5853 reg-names = "core", 5854 "chnls", 5855 "obsrvr", 5856 "intr", 5857 "cnfg"; 5858 qcom,channel = <0>; 5859 qcom,ee = <0>; 5860 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5861 interrupt-names = "periph_irq"; 5862 interrupt-controller; 5863 #interrupt-cells = <4>; 5864 #address-cells = <2>; 5865 #size-cells = <0>; 5866 }; 5867 5868 tlmm: pinctrl@f100000 { 5869 compatible = "qcom,qcs8300-tlmm"; 5870 reg = <0x0 0x0f100000 0x0 0x300000>; 5871 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5872 gpio-controller; 5873 #gpio-cells = <2>; 5874 gpio-ranges = <&tlmm 0 0 134>; 5875 interrupt-controller; 5876 #interrupt-cells = <2>; 5877 wakeup-parent = <&pdc>; 5878 5879 hs0_mi2s_active: hs0-mi2s-active-state { 5880 pins = "gpio106", "gpio107", "gpio108", "gpio109"; 5881 function = "hs0_mi2s"; 5882 drive-strength = <8>; 5883 bias-disable; 5884 }; 5885 5886 mi2s1_active: mi2s1-active-state { 5887 data0-pins { 5888 pins = "gpio100"; 5889 function = "mi2s1_data0"; 5890 drive-strength = <8>; 5891 bias-disable; 5892 }; 5893 5894 data1-pins { 5895 pins = "gpio101"; 5896 function = "mi2s1_data1"; 5897 drive-strength = <8>; 5898 bias-disable; 5899 }; 5900 5901 sclk-pins { 5902 pins = "gpio98"; 5903 function = "mi2s1_sck"; 5904 drive-strength = <8>; 5905 bias-disable; 5906 }; 5907 5908 ws-pins { 5909 pins = "gpio99"; 5910 function = "mi2s1_ws"; 5911 drive-strength = <8>; 5912 bias-disable; 5913 }; 5914 }; 5915 5916 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 5917 pins = "gpio17", "gpio18"; 5918 function = "qup0_se0"; 5919 }; 5920 5921 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 5922 pins = "gpio19", "gpio20"; 5923 function = "qup0_se1"; 5924 }; 5925 5926 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 5927 pins = "gpio33", "gpio34"; 5928 function = "qup0_se2"; 5929 }; 5930 5931 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 5932 pins = "gpio25", "gpio26"; 5933 function = "qup0_se3"; 5934 }; 5935 5936 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 5937 pins = "gpio29", "gpio30"; 5938 function = "qup0_se4"; 5939 }; 5940 5941 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 5942 pins = "gpio21", "gpio22"; 5943 function = "qup0_se5"; 5944 }; 5945 5946 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 5947 pins = "gpio80", "gpio81"; 5948 function = "qup0_se6"; 5949 }; 5950 5951 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 5952 pins = "gpio37", "gpio38"; 5953 function = "qup1_se0"; 5954 }; 5955 5956 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 5957 pins = "gpio39", "gpio40"; 5958 function = "qup1_se1"; 5959 }; 5960 5961 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 5962 pins = "gpio84", "gpio85"; 5963 function = "qup1_se2"; 5964 }; 5965 5966 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 5967 pins = "gpio41", "gpio42"; 5968 function = "qup1_se3"; 5969 }; 5970 5971 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 5972 pins = "gpio45", "gpio46"; 5973 function = "qup1_se4"; 5974 }; 5975 5976 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 5977 pins = "gpio49", "gpio50"; 5978 function = "qup1_se5"; 5979 }; 5980 5981 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 5982 pins = "gpio89", "gpio90"; 5983 function = "qup1_se6"; 5984 }; 5985 5986 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 5987 pins = "gpio91", "gpio92"; 5988 function = "qup1_se7"; 5989 }; 5990 5991 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 5992 pins = "gpio10", "gpio11"; 5993 function = "qup2_se0"; 5994 }; 5995 5996 qup_spi0_data_clk: qup-spi0-data-clk-state { 5997 pins = "gpio17", "gpio18", "gpio19"; 5998 function = "qup0_se0"; 5999 }; 6000 6001 qup_spi0_cs: qup-spi0-cs-state { 6002 pins = "gpio20"; 6003 function = "qup0_se0"; 6004 }; 6005 6006 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 6007 pins = "gpio20"; 6008 function = "gpio"; 6009 }; 6010 6011 qup_spi1_data_clk: qup-spi1-data-clk-state { 6012 pins = "gpio19", "gpio20", "gpio17"; 6013 function = "qup0_se1"; 6014 }; 6015 6016 qup_spi1_cs: qup-spi1-cs-state { 6017 pins = "gpio18"; 6018 function = "qup0_se1"; 6019 }; 6020 6021 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 6022 pins = "gpio18"; 6023 function = "gpio"; 6024 }; 6025 6026 qup_spi2_data_clk: qup-spi2-data-clk-state { 6027 pins = "gpio33", "gpio34", "gpio35"; 6028 function = "qup0_se2"; 6029 }; 6030 6031 qup_spi2_cs: qup-spi2-cs-state { 6032 pins = "gpio36"; 6033 function = "qup0_se2"; 6034 }; 6035 6036 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 6037 pins = "gpio36"; 6038 function = "gpio"; 6039 }; 6040 6041 qup_spi3_data_clk: qup-spi3-data-clk-state { 6042 pins = "gpio25", "gpio26", "gpio27"; 6043 function = "qup0_se3"; 6044 }; 6045 6046 qup_spi3_cs: qup-spi3-cs-state { 6047 pins = "gpio28"; 6048 function = "qup0_se3"; 6049 }; 6050 6051 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 6052 pins = "gpio28"; 6053 function = "gpio"; 6054 }; 6055 6056 qup_spi4_data_clk: qup-spi4-data-clk-state { 6057 pins = "gpio29", "gpio30", "gpio31"; 6058 function = "qup0_se4"; 6059 }; 6060 6061 qup_spi4_cs: qup-spi4-cs-state { 6062 pins = "gpio32"; 6063 function = "qup0_se4"; 6064 }; 6065 6066 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 6067 pins = "gpio32"; 6068 function = "gpio"; 6069 }; 6070 6071 qup_spi5_data_clk: qup-spi5-data-clk-state { 6072 pins = "gpio21", "gpio22", "gpio23"; 6073 function = "qup0_se5"; 6074 }; 6075 6076 qup_spi5_cs: qup-spi5-cs-state { 6077 pins = "gpio24"; 6078 function = "qup0_se5"; 6079 }; 6080 6081 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 6082 pins = "gpio24"; 6083 function = "gpio"; 6084 }; 6085 6086 qup_spi6_data_clk: qup-spi6-data-clk-state { 6087 pins = "gpio80", "gpio81", "gpio82"; 6088 function = "qup0_se6"; 6089 }; 6090 6091 qup_spi6_cs: qup-spi6-cs-state { 6092 pins = "gpio83"; 6093 function = "qup0_se6"; 6094 }; 6095 6096 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 6097 pins = "gpio83"; 6098 function = "gpio"; 6099 }; 6100 6101 qup_spi8_data_clk: qup-spi8-data-clk-state { 6102 pins = "gpio37", "gpio38", "gpio39"; 6103 function = "qup1_se0"; 6104 }; 6105 6106 qup_spi8_cs: qup-spi8-cs-state { 6107 pins = "gpio40"; 6108 function = "qup1_se0"; 6109 }; 6110 6111 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 6112 pins = "gpio40"; 6113 function = "gpio"; 6114 }; 6115 6116 qup_spi9_data_clk: qup-spi9-data-clk-state { 6117 pins = "gpio39", "gpio40", "gpio37"; 6118 function = "qup1_se1"; 6119 }; 6120 6121 qup_spi9_cs: qup-spi9-cs-state { 6122 pins = "gpio38"; 6123 function = "qup1_se1"; 6124 }; 6125 6126 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 6127 pins = "gpio38"; 6128 function = "gpio"; 6129 }; 6130 6131 qup_spi10_data_clk: qup-spi10-data-clk-state { 6132 pins = "gpio84", "gpio85", "gpio86"; 6133 function = "qup1_se2"; 6134 }; 6135 6136 qup_spi10_cs: qup-spi10-cs-state { 6137 pins = "gpio87"; 6138 function = "qup1_se2"; 6139 }; 6140 6141 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 6142 pins = "gpio87"; 6143 function = "gpio"; 6144 }; 6145 6146 qup_spi12_data_clk: qup-spi12-data-clk-state { 6147 pins = "gpio45", "gpio46", "gpio47"; 6148 function = "qup1_se4"; 6149 }; 6150 6151 qup_spi12_cs: qup-spi12-cs-state { 6152 pins = "gpio48"; 6153 function = "qup1_se4"; 6154 }; 6155 6156 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 6157 pins = "gpio48"; 6158 function = "gpio"; 6159 }; 6160 6161 qup_spi13_data_clk: qup-spi13-data-clk-state { 6162 pins = "gpio49", "gpio50", "gpio51"; 6163 function = "qup1_se5"; 6164 }; 6165 6166 qup_spi13_cs: qup-spi13-cs-state { 6167 pins = "gpio52"; 6168 function = "qup1_se5"; 6169 }; 6170 6171 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 6172 pins = "gpio52"; 6173 function = "gpio"; 6174 }; 6175 6176 qup_spi14_data_clk: qup-spi14-data-clk-state { 6177 pins = "gpio89", "gpio90", "gpio91"; 6178 function = "qup1_se6"; 6179 }; 6180 6181 qup_spi14_cs: qup-spi14-cs-state { 6182 pins = "gpio92"; 6183 function = "qup1_se6"; 6184 }; 6185 6186 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 6187 pins = "gpio92"; 6188 function = "gpio"; 6189 }; 6190 6191 qup_spi15_data_clk: qup-spi15-data-clk-state { 6192 pins = "gpio91", "gpio92", "gpio89"; 6193 function = "qup1_se7"; 6194 }; 6195 6196 qup_spi15_cs: qup-spi15-cs-state { 6197 pins = "gpio90"; 6198 function = "qup1_se7"; 6199 }; 6200 6201 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 6202 pins = "gpio90"; 6203 function = "gpio"; 6204 }; 6205 6206 qup_spi16_data_clk: qup-spi16-data-clk-state { 6207 pins = "gpio10", "gpio11", "gpio12"; 6208 function = "qup2_se0"; 6209 }; 6210 6211 qup_spi16_cs: qup-spi16-cs-state { 6212 pins = "gpio13"; 6213 function = "qup2_se0"; 6214 }; 6215 6216 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { 6217 pins = "gpio13"; 6218 function = "gpio"; 6219 }; 6220 6221 qup_uart0_cts: qup-uart0-cts-state { 6222 pins = "gpio17"; 6223 function = "qup0_se0"; 6224 }; 6225 6226 qup_uart0_rts: qup-uart0-rts-state { 6227 pins = "gpio18"; 6228 function = "qup0_se0"; 6229 }; 6230 6231 qup_uart0_tx: qup-uart0-tx-state { 6232 pins = "gpio19"; 6233 function = "qup0_se0"; 6234 }; 6235 6236 qup_uart0_rx: qup-uart0-rx-state { 6237 pins = "gpio20"; 6238 function = "qup0_se0"; 6239 }; 6240 6241 qup_uart1_cts: qup-uart1-cts-state { 6242 pins = "gpio19"; 6243 function = "qup0_se1"; 6244 }; 6245 6246 qup_uart1_rts: qup-uart1-rts-state { 6247 pins = "gpio20"; 6248 function = "qup0_se1"; 6249 }; 6250 6251 qup_uart1_tx: qup-uart1-tx-state { 6252 pins = "gpio17"; 6253 function = "qup0_se1"; 6254 }; 6255 6256 qup_uart1_rx: qup-uart1-rx-state { 6257 pins = "gpio18"; 6258 function = "qup0_se1"; 6259 }; 6260 6261 qup_uart2_cts: qup-uart2-cts-state { 6262 pins = "gpio33"; 6263 function = "qup0_se2"; 6264 }; 6265 6266 qup_uart2_rts: qup-uart2-rts-state { 6267 pins = "gpio34"; 6268 function = "qup0_se2"; 6269 }; 6270 6271 qup_uart2_tx: qup-uart2-tx-state { 6272 pins = "gpio35"; 6273 function = "qup0_se2"; 6274 }; 6275 6276 qup_uart2_rx: qup-uart2-rx-state { 6277 pins = "gpio36"; 6278 function = "qup0_se2"; 6279 }; 6280 6281 qup_uart3_cts: qup-uart3-cts-state { 6282 pins = "gpio25"; 6283 function = "qup0_se3"; 6284 }; 6285 6286 qup_uart3_rts: qup-uart3-rts-state { 6287 pins = "gpio26"; 6288 function = "qup0_se3"; 6289 }; 6290 6291 qup_uart3_tx: qup-uart3-tx-state { 6292 pins = "gpio27"; 6293 function = "qup0_se3"; 6294 }; 6295 6296 qup_uart3_rx: qup-uart3-rx-state { 6297 pins = "gpio28"; 6298 function = "qup0_se3"; 6299 }; 6300 6301 qup_uart4_cts: qup-uart4-cts-state { 6302 pins = "gpio29"; 6303 function = "qup0_se4"; 6304 }; 6305 6306 qup_uart4_rts: qup-uart4-rts-state { 6307 pins = "gpio30"; 6308 function = "qup0_se4"; 6309 }; 6310 6311 qup_uart4_tx: qup-uart4-tx-state { 6312 pins = "gpio31"; 6313 function = "qup0_se4"; 6314 }; 6315 6316 qup_uart4_rx: qup-uart4-rx-state { 6317 pins = "gpio32"; 6318 function = "qup0_se4"; 6319 }; 6320 6321 qup_uart5_cts: qup-uart5-cts-state { 6322 pins = "gpio21"; 6323 function = "qup0_se5"; 6324 }; 6325 6326 qup_uart5_rts: qup-uart5-rts-state { 6327 pins = "gpio22"; 6328 function = "qup0_se5"; 6329 }; 6330 6331 qup_uart5_tx: qup-uart5-tx-state { 6332 pins = "gpio23"; 6333 function = "qup0_se5"; 6334 }; 6335 6336 qup_uart5_rx: qup-uart5-rx-state { 6337 pins = "gpio23"; 6338 function = "qup0_se5"; 6339 }; 6340 6341 qup_uart6_cts: qup-uart6-cts-state { 6342 pins = "gpio80"; 6343 function = "qup0_se6"; 6344 }; 6345 6346 qup_uart6_rts: qup-uart6-rts-state { 6347 pins = "gpio81"; 6348 function = "qup0_se6"; 6349 }; 6350 6351 qup_uart6_tx: qup-uart6-tx-state { 6352 pins = "gpio82"; 6353 function = "qup0_se6"; 6354 }; 6355 6356 qup_uart6_rx: qup-uart6-rx-state { 6357 pins = "gpio83"; 6358 function = "qup0_se6"; 6359 }; 6360 6361 qup_uart7_tx: qup-uart7-tx-state { 6362 pins = "gpio43"; 6363 function = "qup0_se7"; 6364 }; 6365 6366 qup_uart7_rx: qup-uart7-rx-state { 6367 pins = "gpio44"; 6368 function = "qup0_se7"; 6369 }; 6370 6371 qup_uart8_cts: qup-uart8-cts-state { 6372 pins = "gpio37"; 6373 function = "qup1_se0"; 6374 }; 6375 6376 qup_uart8_rts: qup-uart8-rts-state { 6377 pins = "gpio38"; 6378 function = "qup1_se0"; 6379 }; 6380 6381 qup_uart8_tx: qup-uart8-tx-state { 6382 pins = "gpio39"; 6383 function = "qup1_se0"; 6384 }; 6385 6386 qup_uart8_rx: qup-uart8-rx-state { 6387 pins = "gpio40"; 6388 function = "qup1_se0"; 6389 }; 6390 6391 qup_uart9_cts: qup-uart9-cts-state { 6392 pins = "gpio39"; 6393 function = "qup1_se1"; 6394 }; 6395 6396 qup_uart9_rts: qup-uart9-rts-state { 6397 pins = "gpio40"; 6398 function = "qup1_se1"; 6399 }; 6400 6401 qup_uart9_tx: qup-uart9-tx-state { 6402 pins = "gpio37"; 6403 function = "qup1_se1"; 6404 }; 6405 6406 qup_uart9_rx: qup-uart9-rx-state { 6407 pins = "gpio38"; 6408 function = "qup1_se1"; 6409 }; 6410 6411 qup_uart10_cts: qup-uart10-cts-state { 6412 pins = "gpio84"; 6413 function = "qup1_se2"; 6414 }; 6415 6416 qup_uart10_rts: qup-uart10-rts-state { 6417 pins = "gpio84"; 6418 function = "qup1_se2"; 6419 }; 6420 6421 qup_uart10_tx: qup-uart10-tx-state { 6422 pins = "gpio85"; 6423 function = "qup1_se2"; 6424 }; 6425 6426 qup_uart10_rx: qup-uart10-rx-state { 6427 pins = "gpio87"; 6428 function = "qup1_se2"; 6429 }; 6430 6431 qup_uart11_tx: qup-uart11-tx-state { 6432 pins = "gpio41"; 6433 function = "qup1_se3"; 6434 }; 6435 6436 qup_uart11_rx: qup-uart11-rx-state { 6437 pins = "gpio42"; 6438 function = "qup1_se3"; 6439 }; 6440 6441 qup_uart12_cts: qup-uart12-cts-state { 6442 pins = "gpio45"; 6443 function = "qup1_se4"; 6444 }; 6445 6446 qup_uart12_rts: qup-uart12-rts-state { 6447 pins = "gpio46"; 6448 function = "qup1_se4"; 6449 }; 6450 6451 qup_uart12_tx: qup-uart12-tx-state { 6452 pins = "gpio47"; 6453 function = "qup1_se4"; 6454 }; 6455 6456 qup_uart12_rx: qup-uart12-rx-state { 6457 pins = "gpio48"; 6458 function = "qup1_se4"; 6459 }; 6460 6461 qup_uart13_cts: qup-uart13-cts-state { 6462 pins = "gpio49"; 6463 function = "qup1_se5"; 6464 }; 6465 6466 qup_uart13_rts: qup-uart13-rts-state { 6467 pins = "gpio50"; 6468 function = "qup1_se5"; 6469 }; 6470 6471 qup_uart13_tx: qup-uart13-tx-state { 6472 pins = "gpio51"; 6473 function = "qup1_se5"; 6474 }; 6475 6476 qup_uart13_rx: qup-uart13-rx-state { 6477 pins = "gpio52"; 6478 function = "qup1_se5"; 6479 }; 6480 6481 qup_uart14_cts: qup-uart14-cts-state { 6482 pins = "gpio89"; 6483 function = "qup1_se6"; 6484 }; 6485 6486 qup_uart14_rts: qup-uart14-rts-state { 6487 pins = "gpio90"; 6488 function = "qup1_se6"; 6489 }; 6490 6491 qup_uart14_tx: qup-uart14-tx-state { 6492 pins = "gpio91"; 6493 function = "qup1_se6"; 6494 }; 6495 6496 qup_uart14_rx: qup-uart14-rx-state { 6497 pins = "gpio92"; 6498 function = "qup1_se6"; 6499 }; 6500 6501 qup_uart15_cts: qup-uart15-cts-state { 6502 pins = "gpio91"; 6503 function = "qup1_se7"; 6504 }; 6505 6506 qup_uart15_rts: qup-uart15-rts-state { 6507 pins = "gpio92"; 6508 function = "qup1_se7"; 6509 }; 6510 6511 qup_uart15_tx: qup-uart15-tx-state { 6512 pins = "gpio89"; 6513 function = "qup1_se7"; 6514 }; 6515 6516 qup_uart15_rx: qup-uart15-rx-state { 6517 pins = "gpio90"; 6518 function = "qup1_se7"; 6519 }; 6520 6521 qup_uart16_cts: qup-uart16-cts-state { 6522 pins = "gpio10"; 6523 function = "qup2_se0"; 6524 }; 6525 6526 qup_uart16_rts: qup-uart16-rts-state { 6527 pins = "gpio11"; 6528 function = "qup2_se0"; 6529 }; 6530 6531 qup_uart16_tx: qup-uart16-tx-state { 6532 pins = "gpio12"; 6533 function = "qup2_se0"; 6534 }; 6535 6536 qup_uart16_rx: qup-uart16-rx-state { 6537 pins = "gpio13"; 6538 function = "qup2_se0"; 6539 }; 6540 6541 sdc1_state_on: sdc1-on-state { 6542 clk-pins { 6543 pins = "sdc1_clk"; 6544 drive-strength = <16>; 6545 bias-disable; 6546 }; 6547 6548 cmd-pins { 6549 pins = "sdc1_cmd"; 6550 drive-strength = <10>; 6551 bias-pull-up; 6552 }; 6553 6554 data-pins { 6555 pins = "sdc1_data"; 6556 drive-strength = <10>; 6557 bias-pull-up; 6558 }; 6559 6560 rclk-pins { 6561 pins = "sdc1_rclk"; 6562 bias-pull-down; 6563 }; 6564 }; 6565 6566 sdc1_state_off: sdc1-off-state { 6567 clk-pins { 6568 pins = "sdc1_clk"; 6569 drive-strength = <2>; 6570 bias-bus-hold; 6571 }; 6572 6573 cmd-pins { 6574 pins = "sdc1_cmd"; 6575 drive-strength = <2>; 6576 bias-bus-hold; 6577 }; 6578 6579 data-pins { 6580 pins = "sdc1_data"; 6581 drive-strength = <2>; 6582 bias-bus-hold; 6583 }; 6584 6585 rclk-pins { 6586 pins = "sdc1_rclk"; 6587 bias-bus-hold; 6588 }; 6589 }; 6590 }; 6591 6592 sram: sram@146d8000 { 6593 compatible = "qcom,qcs8300-imem", "syscon", "simple-mfd"; 6594 reg = <0x0 0x146d8000 0x0 0x1000>; 6595 ranges = <0x0 0x0 0x146d8000 0x1000>; 6596 6597 #address-cells = <1>; 6598 #size-cells = <1>; 6599 6600 pil-reloc@94c { 6601 compatible = "qcom,pil-reloc-info"; 6602 reg = <0x94c 0xc8>; 6603 }; 6604 }; 6605 6606 apps_smmu: iommu@15000000 { 6607 compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 6608 6609 reg = <0x0 0x15000000 0x0 0x100000>; 6610 #iommu-cells = <2>; 6611 #global-interrupts = <2>; 6612 dma-coherent; 6613 6614 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 6615 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 6616 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 6617 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 6618 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 6619 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 6620 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 6621 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 6622 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 6623 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 6624 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 6625 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 6626 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 6627 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 6628 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 6629 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 6630 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 6631 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 6632 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 6633 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 6634 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 6635 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 6636 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 6637 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 6638 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 6639 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 6640 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 6641 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 6642 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 6643 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 6644 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 6645 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 6646 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 6647 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 6648 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 6649 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 6650 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 6651 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 6652 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 6653 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 6654 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 6655 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 6656 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 6657 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 6658 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 6659 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 6660 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 6661 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 6662 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 6663 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 6664 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 6665 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 6666 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 6667 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 6668 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 6669 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 6670 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 6671 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 6672 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 6673 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 6674 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 6675 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 6676 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 6677 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 6678 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 6679 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 6680 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 6681 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 6682 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 6683 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 6684 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 6685 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 6686 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 6687 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 6688 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 6689 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 6690 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 6691 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 6692 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 6693 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 6694 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 6695 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 6696 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 6697 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 6698 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 6699 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 6700 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 6701 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 6702 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 6703 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 6704 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 6705 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 6706 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 6707 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 6708 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 6709 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 6710 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 6711 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 6712 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 6713 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 6714 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 6715 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 6716 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 6717 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 6718 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 6719 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 6720 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 6721 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 6722 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 6723 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 6724 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 6725 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 6726 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 6727 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 6728 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 6729 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 6730 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 6731 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 6732 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 6733 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 6734 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 6735 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 6736 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 6737 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 6738 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 6739 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 6740 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 6741 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 6742 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 6743 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>; 6744 }; 6745 6746 pcie_smmu: iommu@15200000 { 6747 compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 6748 reg = <0x0 0x15200000 0x0 0x80000>; 6749 #iommu-cells = <2>; 6750 #global-interrupts = <2>; 6751 dma-coherent; 6752 6753 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, 6754 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, 6755 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, 6756 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, 6757 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, 6758 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, 6759 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 6760 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 6761 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, 6762 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, 6763 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, 6764 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, 6765 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, 6766 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, 6767 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, 6768 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 6769 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, 6770 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 6771 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, 6772 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, 6773 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, 6774 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, 6775 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 6776 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 6777 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 6778 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 6779 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 6780 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 6781 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 6782 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 6783 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 6784 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 6785 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 6786 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, 6787 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 6788 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 6789 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, 6790 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, 6791 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 6792 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 6793 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, 6794 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, 6795 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, 6796 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, 6797 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, 6798 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 6799 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, 6800 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, 6801 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, 6802 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 6803 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 6804 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 6805 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 6806 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, 6807 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, 6808 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 6809 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 6810 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 6811 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 6812 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 6813 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 6814 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 6815 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 6816 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, 6817 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 6818 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 6819 }; 6820 6821 intc: interrupt-controller@17a00000 { 6822 compatible = "arm,gic-v3"; 6823 reg = <0x0 0x17a00000 0x0 0x10000>, 6824 <0x0 0x17a60000 0x0 0x100000>; 6825 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 6826 #interrupt-cells = <3>; 6827 interrupt-controller; 6828 #redistributor-regions = <1>; 6829 redistributor-stride = <0x0 0x20000>; 6830 }; 6831 6832 watchdog@17c10000 { 6833 compatible = "qcom,apss-wdt-qcs8300", "qcom,kpss-wdt"; 6834 reg = <0x0 0x17c10000 0x0 0x1000>; 6835 clocks = <&sleep_clk>; 6836 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 6837 }; 6838 6839 timer@17c20000 { 6840 compatible = "arm,armv7-timer-mem"; 6841 reg = <0x0 0x17c20000 0x0 0x1000>; 6842 ranges = <0x0 0x0 0x0 0x20000000>; 6843 #address-cells = <1>; 6844 #size-cells = <1>; 6845 6846 frame@17c21000 { 6847 reg = <0x17c21000 0x1000>, 6848 <0x17c22000 0x1000>; 6849 frame-number = <0>; 6850 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 6851 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 6852 }; 6853 6854 frame@17c23000 { 6855 reg = <0x17c23000 0x1000>; 6856 frame-number = <1>; 6857 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 6858 status = "disabled"; 6859 }; 6860 6861 frame@17c25000 { 6862 reg = <0x17c25000 0x1000>; 6863 frame-number = <2>; 6864 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 6865 status = "disabled"; 6866 }; 6867 6868 frame@17c27000 { 6869 reg = <0x17c27000 0x1000>; 6870 frame-number = <3>; 6871 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 6872 status = "disabled"; 6873 }; 6874 6875 frame@17c29000 { 6876 reg = <0x17c29000 0x1000>; 6877 frame-number = <4>; 6878 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 6879 status = "disabled"; 6880 }; 6881 6882 frame@17c2b000 { 6883 reg = <0x17c2b000 0x1000>; 6884 frame-number = <5>; 6885 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6886 status = "disabled"; 6887 }; 6888 6889 frame@17c2d000 { 6890 reg = <0x17c2d000 0x1000>; 6891 frame-number = <6>; 6892 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 6893 status = "disabled"; 6894 }; 6895 }; 6896 6897 apps_rsc: rsc@18200000 { 6898 compatible = "qcom,rpmh-rsc"; 6899 reg = <0x0 0x18200000 0x0 0x10000>, 6900 <0x0 0x18210000 0x0 0x10000>, 6901 <0x0 0x18220000 0x0 0x10000>; 6902 reg-names = "drv-0", 6903 "drv-1", 6904 "drv-2"; 6905 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 6906 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 6907 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 6908 6909 power-domains = <&system_pd>; 6910 label = "apps_rsc"; 6911 6912 qcom,tcs-offset = <0xd00>; 6913 qcom,drv-id = <2>; 6914 qcom,tcs-config = <ACTIVE_TCS 2>, 6915 <SLEEP_TCS 3>, 6916 <WAKE_TCS 3>, 6917 <CONTROL_TCS 0>; 6918 6919 apps_bcm_voter: bcm-voter { 6920 compatible = "qcom,bcm-voter"; 6921 }; 6922 6923 rpmhcc: clock-controller { 6924 compatible = "qcom,sa8775p-rpmh-clk"; 6925 #clock-cells = <1>; 6926 clocks = <&xo_board_clk>; 6927 clock-names = "xo"; 6928 }; 6929 6930 rpmhpd: power-controller { 6931 compatible = "qcom,qcs8300-rpmhpd"; 6932 #power-domain-cells = <1>; 6933 operating-points-v2 = <&rpmhpd_opp_table>; 6934 6935 rpmhpd_opp_table: opp-table { 6936 compatible = "operating-points-v2"; 6937 6938 rpmhpd_opp_ret: opp-0 { 6939 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 6940 }; 6941 6942 rpmhpd_opp_min_svs: opp-1 { 6943 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 6944 }; 6945 6946 rpmhpd_opp_low_svs: opp-2 { 6947 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 6948 }; 6949 6950 rpmhpd_opp_svs: opp-3 { 6951 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 6952 }; 6953 6954 rpmhpd_opp_svs_l1: opp-4 { 6955 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 6956 }; 6957 6958 rpmhpd_opp_nom: opp-5 { 6959 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 6960 }; 6961 6962 rpmhpd_opp_nom_l1: opp-6 { 6963 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 6964 }; 6965 6966 rpmhpd_opp_nom_l2: opp-7 { 6967 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 6968 }; 6969 6970 rpmhpd_opp_turbo: opp-8 { 6971 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 6972 }; 6973 6974 rpmhpd_opp_turbo_l1: opp-9 { 6975 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 6976 }; 6977 }; 6978 }; 6979 }; 6980 6981 epss_l3_cl0: interconnect@18590000 { 6982 compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3", 6983 "qcom,epss-l3"; 6984 reg = <0x0 0x18590000 0x0 0x1000>; 6985 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6986 clock-names = "xo", "alternate"; 6987 #interconnect-cells = <1>; 6988 }; 6989 6990 cpufreq_hw: cpufreq@18591000 { 6991 compatible = "qcom,qcs8300-cpufreq-epss", "qcom,cpufreq-epss"; 6992 reg = <0x0 0x18591000 0x0 0x1000>, 6993 <0x0 0x18593000 0x0 0x1000>, 6994 <0x0 0x18594000 0x0 0x1000>; 6995 reg-names = "freq-domain0", 6996 "freq-domain1", 6997 "freq-domain2"; 6998 6999 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 7000 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 7001 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 7002 interrupt-names = "dcvsh-irq-0", 7003 "dcvsh-irq-1", 7004 "dcvsh-irq-2"; 7005 7006 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 7007 clock-names = "xo", "alternate"; 7008 7009 #freq-domain-cells = <1>; 7010 }; 7011 7012 epss_l3_cl1: interconnect@18592000 { 7013 compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3", 7014 "qcom,epss-l3"; 7015 reg = <0x0 0x18592000 0x0 0x1000>; 7016 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 7017 clock-names = "xo", "alternate"; 7018 #interconnect-cells = <1>; 7019 }; 7020 7021 remoteproc_gpdsp: remoteproc@20c00000 { 7022 compatible = "qcom,qcs8300-gpdsp-pas", "qcom,sa8775p-gpdsp0-pas"; 7023 reg = <0x0 0x20c00000 0x0 0x10000>; 7024 7025 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 7026 <&smp2p_gpdsp_in 0 0>, 7027 <&smp2p_gpdsp_in 1 0>, 7028 <&smp2p_gpdsp_in 2 0>, 7029 <&smp2p_gpdsp_in 3 0>; 7030 interrupt-names = "wdog", 7031 "fatal", 7032 "ready", 7033 "handover", 7034 "stop-ack"; 7035 7036 clocks = <&rpmhcc RPMH_CXO_CLK>; 7037 clock-names = "xo"; 7038 7039 power-domains = <&rpmhpd RPMHPD_CX>, 7040 <&rpmhpd RPMHPD_MXC>; 7041 power-domain-names = "cx", 7042 "mxc"; 7043 7044 interconnects = <&gpdsp_anoc MASTER_DSP0 QCOM_ICC_TAG_ALWAYS 7045 &config_noc SLAVE_CLK_CTL QCOM_ICC_TAG_ALWAYS>; 7046 7047 memory-region = <&gpdsp_mem>; 7048 7049 qcom,qmp = <&aoss_qmp>; 7050 7051 qcom,smem-states = <&smp2p_gpdsp_out 0>; 7052 qcom,smem-state-names = "stop"; 7053 7054 status = "disabled"; 7055 7056 glink-edge { 7057 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 7058 IPCC_MPROC_SIGNAL_GLINK_QMP 7059 IRQ_TYPE_EDGE_RISING>; 7060 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 7061 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7062 7063 label = "gpdsp"; 7064 qcom,remote-pid = <17>; 7065 }; 7066 }; 7067 7068 ethernet0: ethernet@23040000 { 7069 compatible = "qcom,qcs8300-ethqos", "qcom,sa8775p-ethqos"; 7070 reg = <0x0 0x23040000 0x0 0x00010000>, 7071 <0x0 0x23056000 0x0 0x00000100>; 7072 reg-names = "stmmaceth", "rgmii"; 7073 7074 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 7075 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>; 7076 interrupt-names = "macirq", "sfty"; 7077 7078 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 7079 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 7080 <&gcc GCC_EMAC0_PTP_CLK>, 7081 <&gcc GCC_EMAC0_PHY_AUX_CLK>; 7082 clock-names = "stmmaceth", 7083 "pclk", 7084 "ptp_ref", 7085 "phyaux"; 7086 power-domains = <&gcc GCC_EMAC0_GDSC>; 7087 7088 phys = <&serdes0>; 7089 phy-names = "serdes"; 7090 7091 iommus = <&apps_smmu 0x120 0xf>; 7092 dma-coherent; 7093 7094 snps,tso; 7095 snps,pbl = <32>; 7096 rx-fifo-depth = <16384>; 7097 tx-fifo-depth = <20480>; 7098 7099 status = "disabled"; 7100 }; 7101 7102 nspa_noc: interconnect@260c0000 { 7103 compatible = "qcom,qcs8300-nspa-noc"; 7104 reg = <0x0 0x260c0000 0x0 0x16080>; 7105 #interconnect-cells = <2>; 7106 qcom,bcm-voters = <&apps_bcm_voter>; 7107 }; 7108 7109 remoteproc_cdsp: remoteproc@26300000 { 7110 compatible = "qcom,qcs8300-cdsp-pas", "qcom,sa8775p-cdsp0-pas"; 7111 reg = <0x0 0x26300000 0x0 0x10000>; 7112 7113 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 7114 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 7115 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 7116 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 7117 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 7118 interrupt-names = "wdog", 7119 "fatal", 7120 "ready", 7121 "handover", 7122 "stop-ack"; 7123 7124 clocks = <&rpmhcc RPMH_CXO_CLK>; 7125 clock-names = "xo"; 7126 7127 power-domains = <&rpmhpd RPMHPD_CX>, 7128 <&rpmhpd RPMHPD_MXC>, 7129 <&rpmhpd RPMHPD_NSP0>; 7130 7131 power-domain-names = "cx", 7132 "mxc", 7133 "nsp"; 7134 7135 interconnects = <&nspa_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 7136 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 7137 7138 memory-region = <&cdsp_mem>; 7139 7140 qcom,qmp = <&aoss_qmp>; 7141 7142 qcom,smem-states = <&smp2p_cdsp_out 0>; 7143 qcom,smem-state-names = "stop"; 7144 7145 status = "disabled"; 7146 7147 glink-edge { 7148 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 7149 IPCC_MPROC_SIGNAL_GLINK_QMP 7150 IRQ_TYPE_EDGE_RISING>; 7151 mboxes = <&ipcc IPCC_CLIENT_CDSP 7152 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7153 7154 label = "cdsp"; 7155 qcom,remote-pid = <5>; 7156 7157 fastrpc { 7158 compatible = "qcom,fastrpc"; 7159 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7160 label = "cdsp"; 7161 #address-cells = <1>; 7162 #size-cells = <0>; 7163 7164 compute-cb@1 { 7165 compatible = "qcom,fastrpc-compute-cb"; 7166 reg = <1>; 7167 iommus = <&apps_smmu 0x19c1 0x0440>, 7168 <&apps_smmu 0x1961 0x0400>; 7169 dma-coherent; 7170 }; 7171 7172 compute-cb@2 { 7173 compatible = "qcom,fastrpc-compute-cb"; 7174 reg = <2>; 7175 iommus = <&apps_smmu 0x19c2 0x0440>, 7176 <&apps_smmu 0x1962 0x0400>; 7177 dma-coherent; 7178 }; 7179 7180 compute-cb@3 { 7181 compatible = "qcom,fastrpc-compute-cb"; 7182 reg = <3>; 7183 iommus = <&apps_smmu 0x19c3 0x0440>, 7184 <&apps_smmu 0x1963 0x0400>; 7185 dma-coherent; 7186 }; 7187 7188 compute-cb@4 { 7189 compatible = "qcom,fastrpc-compute-cb"; 7190 reg = <4>; 7191 iommus = <&apps_smmu 0x19c4 0x0440>, 7192 <&apps_smmu 0x1964 0x0400>; 7193 dma-coherent; 7194 }; 7195 }; 7196 }; 7197 }; 7198 }; 7199 7200 thermal_zones: thermal-zones { 7201 aoss-0-thermal { 7202 thermal-sensors = <&tsens0 0>; 7203 7204 trips { 7205 aoss0-critical { 7206 temperature = <125000>; 7207 hysteresis = <1000>; 7208 type = "critical"; 7209 }; 7210 }; 7211 }; 7212 7213 cpu-0-0-0-thermal { 7214 thermal-sensors = <&tsens0 1>; 7215 7216 trips { 7217 cpu-critical { 7218 temperature = <125000>; 7219 hysteresis = <1000>; 7220 type = "critical"; 7221 }; 7222 }; 7223 }; 7224 7225 cpu-0-1-0-thermal { 7226 thermal-sensors = <&tsens0 2>; 7227 7228 trips { 7229 cpu-critical { 7230 temperature = <125000>; 7231 hysteresis = <1000>; 7232 type = "critical"; 7233 }; 7234 }; 7235 }; 7236 7237 cpu-0-2-0-thermal { 7238 thermal-sensors = <&tsens0 3>; 7239 7240 trips { 7241 cpu-critical { 7242 temperature = <125000>; 7243 hysteresis = <1000>; 7244 type = "critical"; 7245 }; 7246 }; 7247 }; 7248 7249 cpu-0-3-0-thermal { 7250 thermal-sensors = <&tsens0 4>; 7251 7252 trips { 7253 cpu-critical { 7254 temperature = <125000>; 7255 hysteresis = <1000>; 7256 type = "critical"; 7257 }; 7258 }; 7259 }; 7260 7261 gpuss-0-thermal { 7262 thermal-sensors = <&tsens0 5>; 7263 7264 trips { 7265 gpuss0_alert0: trip-point0 { 7266 temperature = <115000>; 7267 hysteresis = <5000>; 7268 type = "passive"; 7269 }; 7270 7271 gpuss0-critical { 7272 temperature = <125000>; 7273 hysteresis = <1000>; 7274 type = "critical"; 7275 }; 7276 }; 7277 7278 cooling-maps { 7279 map0 { 7280 trip = <&gpuss0_alert0>; 7281 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7282 }; 7283 }; 7284 }; 7285 7286 audio-thermal { 7287 thermal-sensors = <&tsens0 6>; 7288 7289 trips { 7290 audio-critical { 7291 temperature = <125000>; 7292 hysteresis = <1000>; 7293 type = "critical"; 7294 }; 7295 }; 7296 }; 7297 7298 camss-0-thermal { 7299 thermal-sensors = <&tsens0 7>; 7300 7301 trips { 7302 camss-critical { 7303 temperature = <125000>; 7304 hysteresis = <1000>; 7305 type = "critical"; 7306 }; 7307 }; 7308 }; 7309 7310 pcie-0-thermal { 7311 thermal-sensors = <&tsens0 8>; 7312 7313 trips { 7314 pcie-critical { 7315 temperature = <125000>; 7316 hysteresis = <1000>; 7317 type = "critical"; 7318 }; 7319 }; 7320 }; 7321 7322 cpuss-0-0-thermal { 7323 thermal-sensors = <&tsens0 9>; 7324 7325 trips { 7326 cpuss0-critical { 7327 temperature = <125000>; 7328 hysteresis = <1000>; 7329 type = "critical"; 7330 }; 7331 }; 7332 }; 7333 7334 aoss-1-thermal { 7335 thermal-sensors = <&tsens1 0>; 7336 7337 trips { 7338 aoss1-critical { 7339 temperature = <125000>; 7340 hysteresis = <1000>; 7341 type = "critical"; 7342 }; 7343 }; 7344 }; 7345 7346 cpu-0-0-1-thermal { 7347 thermal-sensors = <&tsens1 1>; 7348 7349 trips { 7350 cpu-critical { 7351 temperature = <125000>; 7352 hysteresis = <1000>; 7353 type = "critical"; 7354 }; 7355 }; 7356 }; 7357 7358 cpu-0-1-1-thermal { 7359 thermal-sensors = <&tsens1 2>; 7360 7361 trips { 7362 cpu-critical { 7363 temperature = <125000>; 7364 hysteresis = <1000>; 7365 type = "critical"; 7366 }; 7367 }; 7368 }; 7369 7370 cpu-0-2-1-thermal { 7371 thermal-sensors = <&tsens1 3>; 7372 7373 trips { 7374 cpu-critical { 7375 temperature = <125000>; 7376 hysteresis = <1000>; 7377 type = "critical"; 7378 }; 7379 }; 7380 }; 7381 7382 cpu-0-3-1-thermal { 7383 thermal-sensors = <&tsens1 4>; 7384 7385 trips { 7386 cpu-critical { 7387 temperature = <125000>; 7388 hysteresis = <1000>; 7389 type = "critical"; 7390 }; 7391 }; 7392 }; 7393 7394 gpuss-1-thermal { 7395 thermal-sensors = <&tsens1 5>; 7396 7397 trips { 7398 gpuss1_alert0: trip-point0 { 7399 temperature = <115000>; 7400 hysteresis = <5000>; 7401 type = "passive"; 7402 }; 7403 7404 gpuss1-critical { 7405 temperature = <125000>; 7406 hysteresis = <1000>; 7407 type = "critical"; 7408 }; 7409 }; 7410 7411 cooling-maps { 7412 map0 { 7413 trip = <&gpuss1_alert0>; 7414 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7415 }; 7416 }; 7417 }; 7418 7419 video-thermal { 7420 thermal-sensors = <&tsens1 6>; 7421 7422 trips { 7423 video-critical { 7424 temperature = <125000>; 7425 hysteresis = <1000>; 7426 type = "critical"; 7427 }; 7428 }; 7429 }; 7430 7431 camss-1-thermal { 7432 thermal-sensors = <&tsens1 7>; 7433 7434 trips { 7435 camss1-critical { 7436 temperature = <125000>; 7437 hysteresis = <1000>; 7438 type = "critical"; 7439 }; 7440 }; 7441 }; 7442 7443 pcie-1-thermal { 7444 thermal-sensors = <&tsens1 8>; 7445 7446 trips { 7447 pcie-critical { 7448 temperature = <125000>; 7449 hysteresis = <1000>; 7450 type = "critical"; 7451 }; 7452 }; 7453 }; 7454 7455 cpuss-0-1-thermal { 7456 thermal-sensors = <&tsens1 9>; 7457 7458 trips { 7459 cpuss0-critical { 7460 temperature = <125000>; 7461 hysteresis = <1000>; 7462 type = "critical"; 7463 }; 7464 }; 7465 }; 7466 7467 aoss-2-thermal { 7468 thermal-sensors = <&tsens2 0>; 7469 7470 trips { 7471 aoss2-critical { 7472 temperature = <125000>; 7473 hysteresis = <1000>; 7474 type = "critical"; 7475 }; 7476 }; 7477 }; 7478 7479 cpu-1-0-0-thermal { 7480 thermal-sensors = <&tsens2 1>; 7481 7482 trips { 7483 cpu-critical { 7484 temperature = <125000>; 7485 hysteresis = <1000>; 7486 type = "critical"; 7487 }; 7488 }; 7489 }; 7490 7491 cpu-1-1-0-thermal { 7492 thermal-sensors = <&tsens2 2>; 7493 7494 trips { 7495 cpu-critical { 7496 temperature = <125000>; 7497 hysteresis = <1000>; 7498 type = "critical"; 7499 }; 7500 }; 7501 }; 7502 7503 cpu-1-2-0-thermal { 7504 thermal-sensors = <&tsens2 3>; 7505 7506 trips { 7507 cpu-critical { 7508 temperature = <125000>; 7509 hysteresis = <1000>; 7510 type = "critical"; 7511 }; 7512 }; 7513 }; 7514 7515 cpu-1-3-0-thermal { 7516 thermal-sensors = <&tsens2 4>; 7517 7518 trips { 7519 cpu-critical { 7520 temperature = <125000>; 7521 hysteresis = <1000>; 7522 type = "critical"; 7523 }; 7524 }; 7525 }; 7526 7527 nsp-0-0-0-thermal { 7528 thermal-sensors = <&tsens2 5>; 7529 7530 trips { 7531 nsp-critical { 7532 temperature = <125000>; 7533 hysteresis = <1000>; 7534 type = "critical"; 7535 }; 7536 }; 7537 }; 7538 7539 nsp-0-1-0-thermal { 7540 thermal-sensors = <&tsens2 6>; 7541 7542 trips { 7543 nsp-critical { 7544 temperature = <125000>; 7545 hysteresis = <1000>; 7546 type = "critical"; 7547 }; 7548 }; 7549 }; 7550 7551 nsp-0-2-0-thermal { 7552 thermal-sensors = <&tsens2 7>; 7553 7554 trips { 7555 nsp-critical { 7556 temperature = <125000>; 7557 hysteresis = <1000>; 7558 type = "critical"; 7559 }; 7560 }; 7561 }; 7562 7563 ddrss-0-thermal { 7564 thermal-sensors = <&tsens2 8>; 7565 7566 trips { 7567 ddrss-critical { 7568 temperature = <125000>; 7569 hysteresis = <1000>; 7570 type = "critical"; 7571 }; 7572 }; 7573 }; 7574 7575 cpuss-1-0-thermal { 7576 thermal-sensors = <&tsens2 9>; 7577 7578 trips { 7579 cpuss1-critical { 7580 temperature = <125000>; 7581 hysteresis = <1000>; 7582 type = "critical"; 7583 }; 7584 }; 7585 }; 7586 7587 aoss-3-thermal { 7588 thermal-sensors = <&tsens3 0>; 7589 7590 trips { 7591 aoss3-critical { 7592 temperature = <125000>; 7593 hysteresis = <1000>; 7594 type = "critical"; 7595 }; 7596 }; 7597 }; 7598 7599 cpu-1-0-1-thermal { 7600 thermal-sensors = <&tsens3 1>; 7601 7602 trips { 7603 cpu-critical { 7604 temperature = <125000>; 7605 hysteresis = <1000>; 7606 type = "critical"; 7607 }; 7608 }; 7609 }; 7610 7611 cpu-1-1-1-thermal { 7612 thermal-sensors = <&tsens3 2>; 7613 7614 trips { 7615 cpu-critical { 7616 temperature = <125000>; 7617 hysteresis = <1000>; 7618 type = "critical"; 7619 }; 7620 }; 7621 }; 7622 7623 cpu-1-2-1-thermal { 7624 thermal-sensors = <&tsens3 3>; 7625 7626 trips { 7627 cpu-critical { 7628 temperature = <125000>; 7629 hysteresis = <1000>; 7630 type = "critical"; 7631 }; 7632 }; 7633 }; 7634 7635 cpu-1-3-1-thermal { 7636 thermal-sensors = <&tsens3 4>; 7637 7638 trips { 7639 cpu-critical { 7640 temperature = <125000>; 7641 hysteresis = <1000>; 7642 type = "critical"; 7643 }; 7644 }; 7645 }; 7646 7647 nsp-0-0-1-thermal { 7648 thermal-sensors = <&tsens3 5>; 7649 7650 trips { 7651 nsp-critical { 7652 temperature = <125000>; 7653 hysteresis = <1000>; 7654 type = "critical"; 7655 }; 7656 }; 7657 }; 7658 7659 nsp-0-1-1-thermal { 7660 thermal-sensors = <&tsens3 6>; 7661 7662 trips { 7663 nsp-critical { 7664 temperature = <125000>; 7665 hysteresis = <1000>; 7666 type = "critical"; 7667 }; 7668 }; 7669 }; 7670 7671 nsp-0-2-1-thermal { 7672 thermal-sensors = <&tsens3 7>; 7673 7674 trips { 7675 nsp-critical { 7676 temperature = <125000>; 7677 hysteresis = <1000>; 7678 type = "critical"; 7679 }; 7680 }; 7681 }; 7682 7683 ddrss-1-thermal { 7684 thermal-sensors = <&tsens3 8>; 7685 7686 trips { 7687 ddrss-critical { 7688 temperature = <125000>; 7689 hysteresis = <1000>; 7690 type = "critical"; 7691 }; 7692 }; 7693 }; 7694 7695 cpuss-1-1-thermal { 7696 thermal-sensors = <&tsens3 9>; 7697 7698 trips { 7699 cpuss1-critical { 7700 temperature = <125000>; 7701 hysteresis = <1000>; 7702 type = "critical"; 7703 }; 7704 }; 7705 }; 7706 }; 7707 7708 timer { 7709 compatible = "arm,armv8-timer"; 7710 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 7711 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 7712 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 7713 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 7714 }; 7715}; 7716