1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 */ 5 6/* 7 * Ethernet card for Lemans based Ride r3 boards. 8 * It supports 2x 2.5G - HSGMII (Marvell hsgmii) phy for Main domain 9 */ 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14/ { 15 aliases { 16 ethernet0 = ðernet0; 17 ethernet1 = ðernet1; 18 }; 19}; 20 21&tlmm { 22 ethernet0_default: ethernet0-default-state { 23 ethernet0_mdc: ethernet0-mdc-pins { 24 pins = "gpio8"; 25 function = "emac0_mdc"; 26 drive-strength = <16>; 27 bias-pull-up; 28 }; 29 30 ethernet0_mdio: ethernet0-mdio-pins { 31 pins = "gpio9"; 32 function = "emac0_mdio"; 33 drive-strength = <16>; 34 bias-pull-up; 35 }; 36 }; 37}; 38 39ðernet0 { 40 phy-handle = <&hsgmii_phy0>; 41 phy-mode = "2500base-x"; 42 43 pinctrl-0 = <ðernet0_default>; 44 pinctrl-names = "default"; 45 46 snps,mtl-rx-config = <&mtl_rx_setup>; 47 snps,mtl-tx-config = <&mtl_tx_setup>; 48 snps,ps-speed = <1000>; 49 50 status = "okay"; 51 52 mdio { 53 compatible = "snps,dwmac-mdio"; 54 #address-cells = <1>; 55 #size-cells = <0>; 56 57 hsgmii_phy0: phy@8 { 58 compatible = "ethernet-phy-id31c3.1c33"; 59 reg = <0x8>; 60 device_type = "ethernet-phy"; 61 interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; 62 reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; 63 reset-assert-us = <11000>; 64 reset-deassert-us = <70000>; 65 }; 66 67 hsgmii_phy1: phy@0 { 68 compatible = "ethernet-phy-id31c3.1c33"; 69 reg = <0x0>; 70 device_type = "ethernet-phy"; 71 interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; 72 reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; 73 reset-assert-us = <11000>; 74 reset-deassert-us = <70000>; 75 }; 76 }; 77 78 mtl_rx_setup: rx-queues-config { 79 snps,rx-queues-to-use = <4>; 80 snps,rx-sched-sp; 81 82 queue0 { 83 snps,dcb-algorithm; 84 snps,map-to-dma-channel = <0x0>; 85 snps,route-up; 86 snps,priority = <0x1>; 87 }; 88 89 queue1 { 90 snps,dcb-algorithm; 91 snps,map-to-dma-channel = <0x1>; 92 snps,route-ptp; 93 }; 94 95 queue2 { 96 snps,avb-algorithm; 97 snps,map-to-dma-channel = <0x2>; 98 snps,route-avcp; 99 }; 100 101 queue3 { 102 snps,avb-algorithm; 103 snps,map-to-dma-channel = <0x3>; 104 snps,priority = <0xc>; 105 }; 106 }; 107 108 mtl_tx_setup: tx-queues-config { 109 snps,tx-queues-to-use = <4>; 110 111 queue0 { 112 snps,dcb-algorithm; 113 }; 114 115 queue1 { 116 snps,dcb-algorithm; 117 }; 118 119 queue2 { 120 snps,avb-algorithm; 121 snps,send_slope = <0x1000>; 122 snps,idle_slope = <0x1000>; 123 snps,high_credit = <0x3e800>; 124 snps,low_credit = <0xffc18000>; 125 }; 126 127 queue3 { 128 snps,avb-algorithm; 129 snps,send_slope = <0x1000>; 130 snps,idle_slope = <0x1000>; 131 snps,high_credit = <0x3e800>; 132 snps,low_credit = <0xffc18000>; 133 }; 134 }; 135}; 136 137ðernet1 { 138 phy-handle = <&hsgmii_phy1>; 139 phy-mode = "2500base-x"; 140 141 snps,mtl-rx-config = <&mtl_rx_setup1>; 142 snps,mtl-tx-config = <&mtl_tx_setup1>; 143 snps,ps-speed = <1000>; 144 145 status = "okay"; 146 147 mtl_rx_setup1: rx-queues-config { 148 snps,rx-queues-to-use = <4>; 149 snps,rx-sched-sp; 150 151 queue0 { 152 snps,dcb-algorithm; 153 snps,map-to-dma-channel = <0x0>; 154 snps,route-up; 155 snps,priority = <0x1>; 156 }; 157 158 queue1 { 159 snps,dcb-algorithm; 160 snps,map-to-dma-channel = <0x1>; 161 snps,route-ptp; 162 }; 163 164 queue2 { 165 snps,avb-algorithm; 166 snps,map-to-dma-channel = <0x2>; 167 snps,route-avcp; 168 }; 169 170 queue3 { 171 snps,avb-algorithm; 172 snps,map-to-dma-channel = <0x3>; 173 snps,priority = <0xc>; 174 }; 175 }; 176 177 mtl_tx_setup1: tx-queues-config { 178 snps,tx-queues-to-use = <4>; 179 180 queue0 { 181 snps,dcb-algorithm; 182 }; 183 184 queue1 { 185 snps,dcb-algorithm; 186 }; 187 188 queue2 { 189 snps,avb-algorithm; 190 snps,send_slope = <0x1000>; 191 snps,idle_slope = <0x1000>; 192 snps,high_credit = <0x3e800>; 193 snps,low_credit = <0xffc18000>; 194 }; 195 196 queue3 { 197 snps,avb-algorithm; 198 snps,send_slope = <0x1000>; 199 snps,idle_slope = <0x1000>; 200 snps,high_credit = <0x3e800>; 201 snps,low_credit = <0xffc18000>; 202 }; 203 }; 204}; 205 206