1*b68fc459SWenmeng Liu// SPDX-License-Identifier: BSD-3-Clause 2*b68fc459SWenmeng Liu/* 3*b68fc459SWenmeng Liu * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4*b68fc459SWenmeng Liu */ 5*b68fc459SWenmeng Liu 6*b68fc459SWenmeng Liu/dts-v1/; 7*b68fc459SWenmeng Liu/plugin/; 8*b68fc459SWenmeng Liu 9*b68fc459SWenmeng Liu#include <dt-bindings/clock/qcom,sa8775p-camcc.h> 10*b68fc459SWenmeng Liu#include <dt-bindings/gpio/gpio.h> 11*b68fc459SWenmeng Liu 12*b68fc459SWenmeng Liu&{/} { 13*b68fc459SWenmeng Liu vreg_cam1_1p8: regulator-cam1 { 14*b68fc459SWenmeng Liu compatible = "regulator-fixed"; 15*b68fc459SWenmeng Liu regulator-name = "vreg_cam1"; 16*b68fc459SWenmeng Liu startup-delay-us = <10000>; 17*b68fc459SWenmeng Liu enable-active-high; 18*b68fc459SWenmeng Liu gpio = <&pmm8654au_0_gpios 8 GPIO_ACTIVE_HIGH>; 19*b68fc459SWenmeng Liu }; 20*b68fc459SWenmeng Liu}; 21*b68fc459SWenmeng Liu 22*b68fc459SWenmeng Liu&camss { 23*b68fc459SWenmeng Liu vdda-pll-supply = <&vreg_l1c>; 24*b68fc459SWenmeng Liu vdda-phy-supply = <&vreg_l4a>; 25*b68fc459SWenmeng Liu 26*b68fc459SWenmeng Liu status = "okay"; 27*b68fc459SWenmeng Liu 28*b68fc459SWenmeng Liu ports { 29*b68fc459SWenmeng Liu #address-cells = <1>; 30*b68fc459SWenmeng Liu #size-cells = <0>; 31*b68fc459SWenmeng Liu 32*b68fc459SWenmeng Liu port@1 { 33*b68fc459SWenmeng Liu reg = <1>; 34*b68fc459SWenmeng Liu 35*b68fc459SWenmeng Liu csiphy1_ep: endpoint { 36*b68fc459SWenmeng Liu clock-lanes = <7>; 37*b68fc459SWenmeng Liu data-lanes = <0 1 2 3>; 38*b68fc459SWenmeng Liu remote-endpoint = <&imx577_ep1>; 39*b68fc459SWenmeng Liu }; 40*b68fc459SWenmeng Liu }; 41*b68fc459SWenmeng Liu }; 42*b68fc459SWenmeng Liu}; 43*b68fc459SWenmeng Liu 44*b68fc459SWenmeng Liu&cci1 { 45*b68fc459SWenmeng Liu pinctrl-0 = <&cci1_0_default>; 46*b68fc459SWenmeng Liu pinctrl-1 = <&cci1_0_sleep>; 47*b68fc459SWenmeng Liu 48*b68fc459SWenmeng Liu status = "okay"; 49*b68fc459SWenmeng Liu}; 50*b68fc459SWenmeng Liu 51*b68fc459SWenmeng Liu&cci1_i2c0 { 52*b68fc459SWenmeng Liu #address-cells = <1>; 53*b68fc459SWenmeng Liu #size-cells = <0>; 54*b68fc459SWenmeng Liu 55*b68fc459SWenmeng Liu camera@1a { 56*b68fc459SWenmeng Liu compatible = "sony,imx577"; 57*b68fc459SWenmeng Liu reg = <0x1a>; 58*b68fc459SWenmeng Liu 59*b68fc459SWenmeng Liu reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; 60*b68fc459SWenmeng Liu pinctrl-0 = <&cam1_default>; 61*b68fc459SWenmeng Liu pinctrl-names = "default"; 62*b68fc459SWenmeng Liu 63*b68fc459SWenmeng Liu clocks = <&camcc CAM_CC_MCLK1_CLK>; 64*b68fc459SWenmeng Liu assigned-clocks = <&camcc CAM_CC_MCLK1_CLK>; 65*b68fc459SWenmeng Liu assigned-clock-rates = <24000000>; 66*b68fc459SWenmeng Liu 67*b68fc459SWenmeng Liu dovdd-supply = <&vreg_s4a>; 68*b68fc459SWenmeng Liu avdd-supply = <&vreg_cam1_1p8>; 69*b68fc459SWenmeng Liu 70*b68fc459SWenmeng Liu port { 71*b68fc459SWenmeng Liu imx577_ep1: endpoint { 72*b68fc459SWenmeng Liu clock-lanes = <7>; 73*b68fc459SWenmeng Liu link-frequencies = /bits/ 64 <600000000>; 74*b68fc459SWenmeng Liu data-lanes = <0 1 2 3>; 75*b68fc459SWenmeng Liu remote-endpoint = <&csiphy1_ep>; 76*b68fc459SWenmeng Liu }; 77*b68fc459SWenmeng Liu }; 78*b68fc459SWenmeng Liu }; 79*b68fc459SWenmeng Liu}; 80*b68fc459SWenmeng Liu 81*b68fc459SWenmeng Liu&tlmm { 82*b68fc459SWenmeng Liu cam1_default: cam1-default-state { 83*b68fc459SWenmeng Liu mclk-pins { 84*b68fc459SWenmeng Liu pins = "gpio73"; 85*b68fc459SWenmeng Liu function = "cam_mclk"; 86*b68fc459SWenmeng Liu drive-strength = <2>; 87*b68fc459SWenmeng Liu bias-disable; 88*b68fc459SWenmeng Liu }; 89*b68fc459SWenmeng Liu 90*b68fc459SWenmeng Liu rst-pins { 91*b68fc459SWenmeng Liu pins = "gpio133"; 92*b68fc459SWenmeng Liu function = "gpio"; 93*b68fc459SWenmeng Liu drive-strength = <2>; 94*b68fc459SWenmeng Liu bias-disable; 95*b68fc459SWenmeng Liu }; 96*b68fc459SWenmeng Liu }; 97*b68fc459SWenmeng Liu}; 98