1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,ipq5210-gcc.h> 8#include <dt-bindings/reset/qcom,ipq5210-gcc.h> 9 10/ { 11 #address-cells = <2>; 12 #size-cells = <2>; 13 interrupt-parent = <&intc>; 14 15 clocks { 16 sleep_clk: sleep-clk { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 }; 20 21 xo_board: xo-board-clk { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 }; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu@0 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a53"; 34 reg = <0x0>; 35 enable-method = "psci"; 36 next-level-cache = <&l2_0>; 37 }; 38 39 cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 reg = <0x1>; 43 enable-method = "psci"; 44 next-level-cache = <&l2_0>; 45 }; 46 47 cpu@2 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a53"; 50 reg = <0x2>; 51 enable-method = "psci"; 52 next-level-cache = <&l2_0>; 53 }; 54 55 cpu@3 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a53"; 58 reg = <0x3>; 59 enable-method = "psci"; 60 next-level-cache = <&l2_0>; 61 }; 62 63 l2_0: l2-cache { 64 compatible = "cache"; 65 cache-level = <2>; 66 cache-unified; 67 }; 68 }; 69 70 firmware { 71 optee { 72 compatible = "linaro,optee-tz"; 73 method = "smc"; 74 }; 75 76 scm { 77 compatible = "qcom,scm-ipq5210", "qcom,scm"; 78 }; 79 }; 80 81 memory@80000000 { 82 device_type = "memory"; 83 /* We expect the bootloader to fill in the size */ 84 reg = <0x0 0x80000000 0x0 0x0>; 85 }; 86 87 pmu { 88 compatible = "arm,cortex-a53-pmu"; 89 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 90 }; 91 92 psci { 93 compatible = "arm,psci-1.0"; 94 method = "smc"; 95 }; 96 97 reserved-memory { 98 #address-cells = <2>; 99 #size-cells = <2>; 100 ranges; 101 102 bootloader@87800000 { 103 reg = <0x0 0x87800000 0x0 0x400000>; 104 no-map; 105 }; 106 107 smem@87c00000 { 108 compatible = "qcom,smem"; 109 reg = <0x0 0x87c00000 0x0 0x40000>; 110 no-map; 111 112 hwlocks = <&tcsr_mutex 3>; 113 }; 114 115 tfa@87d00000 { 116 reg = <0x0 0x87d00000 0x0 0x80000>; 117 no-map; 118 }; 119 120 optee@87d80000 { 121 reg = <0x0 0x87d80000 0x0 0x280000>; 122 no-map; 123 }; 124 }; 125 126 soc@0 { 127 compatible = "simple-bus"; 128 #address-cells = <2>; 129 #size-cells = <2>; 130 dma-ranges = <0 0 0 0 0x10 0>; 131 ranges = <0 0 0 0 0x10 0>; 132 133 tlmm: pinctrl@1000000 { 134 compatible = "qcom,ipq5210-tlmm"; 135 reg = <0x0 0x01000000 0x0 0x300000>; 136 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 137 gpio-controller; 138 #gpio-cells = <2>; 139 gpio-ranges = <&tlmm 0 0 54>; 140 interrupt-controller; 141 #interrupt-cells = <2>; 142 }; 143 144 gcc: clock-controller@1800000 { 145 compatible = "qcom,ipq5210-gcc"; 146 reg = <0x0 0x01800000 0x0 0x40000>; 147 clocks = <&xo_board>, 148 <&sleep_clk>, 149 <0>, 150 <0>, 151 <0>, 152 <0>; 153 #clock-cells = <1>; 154 #reset-cells = <1>; 155 }; 156 157 tcsr_mutex: hwlock@1905000 { 158 compatible = "qcom,tcsr-mutex"; 159 reg = <0x0 0x01905000 0x0 0x20000>; 160 #hwlock-cells = <1>; 161 }; 162 163 qupv3: geniqup@1ac0000 { 164 compatible = "qcom,geni-se-qup"; 165 reg = <0x0 0x01ac0000 0x0 0x2000>; 166 clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>, 167 <&gcc GCC_QUPV3_AHB_SLV_CLK>; 168 clock-names = "m-ahb", "s-ahb"; 169 ranges; 170 #address-cells = <2>; 171 #size-cells = <2>; 172 173 uart1: serial@1a84000 { 174 compatible = "qcom,geni-debug-uart"; 175 reg = <0x0 0x01a84000 0x0 0x4000>; 176 clocks = <&gcc GCC_QUPV3_WRAP_SE1_CLK>; 177 clock-names = "se"; 178 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 179 180 status = "disabled"; 181 }; 182 }; 183 184 sdhc: mmc@7804000 { 185 compatible = "qcom,ipq5210-sdhci", "qcom,sdhci-msm-v5"; 186 reg = <0x0 0x07804000 0x0 0x1000>, 187 <0x0 0x07805000 0x0 0x1000>; 188 reg-names = "hc", 189 "cqhci"; 190 191 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 193 interrupt-names = "hc_irq", 194 "pwr_irq"; 195 196 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 197 <&gcc GCC_SDCC1_APPS_CLK>, 198 <&xo_board>; 199 clock-names = "iface", 200 "core", 201 "xo"; 202 non-removable; 203 204 status = "disabled"; 205 }; 206 207 intc: interrupt-controller@b000000 { 208 compatible = "qcom,msm-qgic2"; 209 interrupt-controller; 210 #interrupt-cells = <3>; 211 reg = <0x0 0xb000000 0x0 0x1000>, 212 <0x0 0xb002000 0x0 0x1000>, 213 <0x0 0xb001000 0x0 0x1000>, 214 <0x0 0xb004000 0x0 0x1000>; 215 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 216 #address-cells = <2>; 217 #size-cells = <2>; 218 ranges = <0 0 0 0x0b00c000 0 0x3000>; 219 220 v2m0: v2m@0 { 221 compatible = "arm,gic-v2m-frame"; 222 reg = <0x0 0x0 0x0 0xffd>; 223 msi-controller; 224 }; 225 226 v2m1: v2m@1000 { 227 compatible = "arm,gic-v2m-frame"; 228 reg = <0x0 0x00001000 0x0 0xffd>; 229 msi-controller; 230 }; 231 232 v2m2: v2m@2000 { 233 compatible = "arm,gic-v2m-frame"; 234 reg = <0x0 0x00002000 0x0 0xffd>; 235 msi-controller; 236 }; 237 }; 238 239 timer@b120000 { 240 compatible = "arm,armv7-timer-mem"; 241 reg = <0x0 0x0b120000 0x0 0x1000>; 242 ranges = <0 0 0 0x10000000>; 243 #address-cells = <1>; 244 #size-cells = <1>; 245 246 frame@b121000 { 247 frame-number = <0>; 248 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 250 reg = <0x0b121000 0x1000>, 251 <0x0b122000 0x1000>; 252 }; 253 254 frame@b123000 { 255 frame-number = <1>; 256 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 257 reg = <0x0b123000 0x1000>; 258 259 status = "disabled"; 260 }; 261 262 frame@b124000 { 263 frame-number = <2>; 264 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 265 reg = <0x0b124000 0x1000>; 266 267 status = "disabled"; 268 }; 269 270 frame@b125000 { 271 frame-number = <3>; 272 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 273 reg = <0x0b125000 0x1000>; 274 275 status = "disabled"; 276 }; 277 278 frame@b126000 { 279 frame-number = <4>; 280 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 281 reg = <0x0b126000 0x1000>; 282 283 status = "disabled"; 284 }; 285 286 frame@b127000 { 287 frame-number = <5>; 288 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 289 reg = <0x0b127000 0x1000>; 290 291 status = "disabled"; 292 }; 293 294 frame@b128000 { 295 frame-number = <6>; 296 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 297 reg = <0x0b128000 0x1000>; 298 299 status = "disabled"; 300 }; 301 }; 302 }; 303 304 timer { 305 compatible = "arm,armv8-timer"; 306 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 307 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 308 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 309 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 310 }; 311}; 312