1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6#include <dt-bindings/clock/qcom,eliza-gcc.h> 7#include <dt-bindings/clock/qcom,eliza-tcsr.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/interconnect/qcom,eliza-rpmh.h> 10#include <dt-bindings/interconnect/qcom,icc.h> 11#include <dt-bindings/interconnect/qcom,osm-l3.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/power/qcom,rpmhpd.h> 14#include <dt-bindings/soc/qcom,rpmh-rsc.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <2>; 24 #size-cells = <0>; 25 26 cpu0: cpu@0 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-a520"; 29 reg = <0x0 0x0>; 30 31 clocks = <&cpufreq_hw 0>; 32 33 power-domains = <&cpu_pd0>; 34 power-domain-names = "psci"; 35 36 enable-method = "psci"; 37 next-level-cache = <&l2_0>; 38 capacity-dmips-mhz = <1024>; 39 dynamic-power-coefficient = <100>; 40 41 qcom,freq-domain = <&cpufreq_hw 0>; 42 43 l2_0: l2-cache { 44 compatible = "cache"; 45 cache-level = <2>; 46 cache-unified; 47 next-level-cache = <&l3>; 48 49 l3: l3-cache { 50 compatible = "cache"; 51 cache-level = <3>; 52 cache-unified; 53 }; 54 }; 55 }; 56 57 cpu1: cpu@100 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a520"; 60 reg = <0x0 0x100>; 61 62 clocks = <&cpufreq_hw 0>; 63 64 power-domains = <&cpu_pd1>; 65 power-domain-names = "psci"; 66 67 enable-method = "psci"; 68 next-level-cache = <&l2_0>; 69 capacity-dmips-mhz = <1024>; 70 dynamic-power-coefficient = <100>; 71 72 qcom,freq-domain = <&cpufreq_hw 0>; 73 }; 74 75 cpu2: cpu@200 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a520"; 78 reg = <0x0 0x200>; 79 80 clocks = <&cpufreq_hw 0>; 81 82 power-domains = <&cpu_pd2>; 83 power-domain-names = "psci"; 84 85 enable-method = "psci"; 86 next-level-cache = <&l2_2>; 87 capacity-dmips-mhz = <1024>; 88 dynamic-power-coefficient = <100>; 89 90 qcom,freq-domain = <&cpufreq_hw 0>; 91 92 l2_2: l2-cache { 93 compatible = "cache"; 94 cache-level = <2>; 95 cache-unified; 96 next-level-cache = <&l3>; 97 }; 98 }; 99 100 cpu3: cpu@300 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a720"; 103 reg = <0x0 0x300>; 104 105 clocks = <&cpufreq_hw 1>; 106 107 power-domains = <&cpu_pd3>; 108 power-domain-names = "psci"; 109 110 enable-method = "psci"; 111 next-level-cache = <&l2_3>; 112 capacity-dmips-mhz = <1792>; 113 dynamic-power-coefficient = <238>; 114 115 qcom,freq-domain = <&cpufreq_hw 1>; 116 117 l2_3: l2-cache { 118 compatible = "cache"; 119 cache-level = <2>; 120 cache-unified; 121 next-level-cache = <&l3>; 122 }; 123 }; 124 125 cpu4: cpu@400 { 126 device_type = "cpu"; 127 compatible = "arm,cortex-a720"; 128 reg = <0x0 0x400>; 129 130 clocks = <&cpufreq_hw 1>; 131 132 power-domains = <&cpu_pd4>; 133 power-domain-names = "psci"; 134 135 enable-method = "psci"; 136 next-level-cache = <&l2_4>; 137 capacity-dmips-mhz = <1792>; 138 dynamic-power-coefficient = <238>; 139 140 qcom,freq-domain = <&cpufreq_hw 1>; 141 142 l2_4: l2-cache { 143 compatible = "cache"; 144 cache-level = <2>; 145 cache-unified; 146 next-level-cache = <&l3>; 147 }; 148 }; 149 150 cpu5: cpu@500 { 151 device_type = "cpu"; 152 compatible = "arm,cortex-a720"; 153 reg = <0x0 0x500>; 154 155 clocks = <&cpufreq_hw 1>; 156 157 power-domains = <&cpu_pd5>; 158 power-domain-names = "psci"; 159 160 enable-method = "psci"; 161 next-level-cache = <&l2_5>; 162 capacity-dmips-mhz = <1792>; 163 dynamic-power-coefficient = <238>; 164 165 qcom,freq-domain = <&cpufreq_hw 1>; 166 167 l2_5: l2-cache { 168 compatible = "cache"; 169 cache-level = <2>; 170 cache-unified; 171 next-level-cache = <&l3>; 172 }; 173 }; 174 175 cpu6: cpu@600 { 176 device_type = "cpu"; 177 compatible = "arm,cortex-a720"; 178 reg = <0x0 0x600>; 179 180 clocks = <&cpufreq_hw 1>; 181 182 power-domains = <&cpu_pd6>; 183 power-domain-names = "psci"; 184 185 enable-method = "psci"; 186 next-level-cache = <&l2_6>; 187 capacity-dmips-mhz = <1792>; 188 dynamic-power-coefficient = <238>; 189 190 qcom,freq-domain = <&cpufreq_hw 1>; 191 192 l2_6: l2-cache { 193 compatible = "cache"; 194 cache-level = <2>; 195 cache-unified; 196 next-level-cache = <&l3>; 197 }; 198 }; 199 200 cpu7: cpu@700 { 201 device_type = "cpu"; 202 compatible = "arm,cortex-x3"; 203 reg = <0x0 0x700>; 204 205 clocks = <&cpufreq_hw 2>; 206 207 power-domains = <&cpu_pd7>; 208 power-domain-names = "psci"; 209 210 enable-method = "psci"; 211 next-level-cache = <&l2_7>; 212 capacity-dmips-mhz = <1894>; 213 dynamic-power-coefficient = <588>; 214 215 qcom,freq-domain = <&cpufreq_hw 2>; 216 217 l2_7: l2-cache { 218 compatible = "cache"; 219 cache-level = <2>; 220 cache-unified; 221 next-level-cache = <&l3>; 222 }; 223 }; 224 225 cpu-map { 226 cluster0 { 227 core0 { 228 cpu = <&cpu0>; 229 }; 230 231 core1 { 232 cpu = <&cpu1>; 233 }; 234 235 core2 { 236 cpu = <&cpu2>; 237 }; 238 239 core3 { 240 cpu = <&cpu3>; 241 }; 242 243 core4 { 244 cpu = <&cpu4>; 245 }; 246 247 core5 { 248 cpu = <&cpu5>; 249 }; 250 251 core6 { 252 cpu = <&cpu6>; 253 }; 254 255 core7 { 256 cpu = <&cpu7>; 257 }; 258 }; 259 }; 260 261 idle-states { 262 entry-method = "psci"; 263 264 cluster0_c4: cpu-sleep-0 { 265 compatible = "arm,idle-state"; 266 idle-state-name = "silver-rail-power-collapse"; 267 arm,psci-suspend-param = <0x40000004>; 268 entry-latency-us = <550>; 269 exit-latency-us = <750>; 270 min-residency-us = <6700>; 271 }; 272 273 cluster1_c4: cpu-sleep-1 { 274 compatible = "arm,idle-state"; 275 idle-state-name = "gold-rail-power-collapse"; 276 arm,psci-suspend-param = <0x40000004>; 277 entry-latency-us = <550>; 278 exit-latency-us = <1050>; 279 min-residency-us = <7951>; 280 }; 281 282 cluster2_c4: cpu-sleep-2 { 283 compatible = "arm,idle-state"; 284 idle-state-name = "gold-plus-rail-power-collapse"; 285 arm,psci-suspend-param = <0x40000004>; 286 entry-latency-us = <500>; 287 exit-latency-us = <1350>; 288 min-residency-us = <7480>; 289 }; 290 }; 291 292 domain-idle-states { 293 cluster_sleep_0: cluster-sleep-0 { 294 compatible = "domain-idle-state"; 295 arm,psci-suspend-param = <0x41000044>; 296 entry-latency-us = <750>; 297 exit-latency-us = <2350>; 298 min-residency-us = <9144>; 299 }; 300 301 cluster_sleep_1: cluster-sleep-1 { 302 compatible = "domain-idle-state"; 303 arm,psci-suspend-param = <0x4100b344>; 304 entry-latency-us = <2800>; 305 exit-latency-us = <4400>; 306 min-residency-us = <10150>; 307 }; 308 }; 309 }; 310 311 firmware { 312 scm: scm { 313 compatible = "qcom,scm-eliza", "qcom,scm"; 314 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 315 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 316 qcom,dload-mode = <&tcsr 0x1a000>; 317 }; 318 }; 319 320 clk_virt: interconnect-0 { 321 compatible = "qcom,eliza-clk-virt"; 322 #interconnect-cells = <2>; 323 qcom,bcm-voters = <&apps_bcm_voter>; 324 }; 325 326 mc_virt: interconnect-1 { 327 compatible = "qcom,eliza-mc-virt"; 328 #interconnect-cells = <2>; 329 qcom,bcm-voters = <&apps_bcm_voter>; 330 }; 331 332 memory@a0000000 { 333 device_type = "memory"; 334 /* We expect the bootloader to fill in the size */ 335 reg = <0x0 0xa0000000 0x0 0x0>; 336 }; 337 338 psci { 339 compatible = "arm,psci-1.0"; 340 method = "smc"; 341 342 cpu_pd0: power-domain-cpu0 { 343 #power-domain-cells = <0>; 344 power-domains = <&cluster_pd>; 345 domain-idle-states = <&cluster0_c4>; 346 }; 347 348 cpu_pd1: power-domain-cpu1 { 349 #power-domain-cells = <0>; 350 power-domains = <&cluster_pd>; 351 domain-idle-states = <&cluster0_c4>; 352 }; 353 354 cpu_pd2: power-domain-cpu2 { 355 #power-domain-cells = <0>; 356 power-domains = <&cluster_pd>; 357 domain-idle-states = <&cluster0_c4>; 358 }; 359 360 cpu_pd3: power-domain-cpu3 { 361 #power-domain-cells = <0>; 362 power-domains = <&cluster_pd>; 363 domain-idle-states = <&cluster1_c4>; 364 }; 365 366 cpu_pd4: power-domain-cpu4 { 367 #power-domain-cells = <0>; 368 power-domains = <&cluster_pd>; 369 domain-idle-states = <&cluster1_c4>; 370 }; 371 372 cpu_pd5: power-domain-cpu5 { 373 #power-domain-cells = <0>; 374 power-domains = <&cluster_pd>; 375 domain-idle-states = <&cluster1_c4>; 376 }; 377 378 cpu_pd6: power-domain-cpu6 { 379 #power-domain-cells = <0>; 380 power-domains = <&cluster_pd>; 381 domain-idle-states = <&cluster1_c4>; 382 }; 383 384 cpu_pd7: power-domain-cpu7 { 385 #power-domain-cells = <0>; 386 power-domains = <&cluster_pd>; 387 domain-idle-states = <&cluster2_c4>; 388 }; 389 390 cluster_pd: power-domain-cluster { 391 #power-domain-cells = <0>; 392 domain-idle-states = <&cluster_sleep_0>, 393 <&cluster_sleep_1>; 394 }; 395 }; 396 397 reserved-memory { 398 #address-cells = <2>; 399 #size-cells = <2>; 400 ranges; 401 402 gunyah_hyp_mem: gunyah-hyp@80000000 { 403 reg = <0x0 0x80000000 0x0 0xe00000>; 404 no-map; 405 }; 406 407 cpusys_vm_mem: cpusys-vm-mem@80e00000 { 408 reg = <0x0 0x80e00000 0x0 0x40000>; 409 no-map; 410 }; 411 412 cpucp_mem: cpucp@81200000 { 413 reg = <0x0 0x81200000 0x0 0x200000>; 414 no-map; 415 }; 416 417 xbl_dtlog_mem: xbl-dtlog@81a00000 { 418 reg = <0x0 0x81a00000 0x0 0x40000>; 419 no-map; 420 }; 421 422 aop_image_mem: aop-image@81c00000 { 423 reg = <0x0 0x81c00000 0x0 0x60000>; 424 no-map; 425 }; 426 427 aop_cmd_db_mem: aop-cmd-db@81c60000 { 428 compatible = "qcom,cmd-db"; 429 reg = <0x0 0x81c60000 0x0 0x20000>; 430 no-map; 431 }; 432 433 /* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */ 434 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 { 435 reg = <0x0 0x81c80000 0x0 0x74000>; 436 no-map; 437 }; 438 439 /* Secdata region can be reused by apps */ 440 smem_mem: smem@81d00000 { 441 compatible = "qcom,smem"; 442 reg = <0x0 0x81d00000 0x0 0x200000>; 443 hwlocks = <&tcsr_mutex 3>; 444 no-map; 445 }; 446 447 cpucp_scandump_mem: cpucp-scandump@82000000 { 448 reg = <0x0 0x82200000 0x0 0x180000>; 449 no-map; 450 }; 451 452 adsp_mhi_mem: adsp-mhi@82380000 { 453 reg = <0x0 0x82380000 0x0 0x20000>; 454 no-map; 455 }; 456 457 soccp_sdi_mem: soccp-sdi@823a0000 { 458 reg = <0x0 0x823a0000 0x0 0x40000>; 459 no-map; 460 }; 461 462 pmic_minii_dump_mem: pmic-minii-dump@823e0000 { 463 reg = <0x0 0x823e0000 0x0 0x80000>; 464 no-map; 465 }; 466 467 pvmfw_mem: pvmfw@824a0000 { 468 reg = <0x0 0x824a0000 0x0 0x100000>; 469 no-map; 470 }; 471 472 hyp_db_mem: hyp-db@825a0000 { 473 reg = <0x0 0x825a0000 0x0 0x60000>; 474 no-map; 475 }; 476 477 global_sync_mem: global-sync@82600000 { 478 reg = <0x0 0x82600000 0x0 0x100000>; 479 no-map; 480 }; 481 482 tz_stat_mem: tz-stat@82700000 { 483 reg = <0x0 0x82700000 0x0 0x100000>; 484 no-map; 485 }; 486 487 qdss_mem: qdss@82800000 { 488 reg = <0x0 0x82800000 0x0 0x2000000>; 489 no-map; 490 }; 491 492 dsm_partition_1_mem: dsm-partition-1@84a00000 { 493 reg = <0x0 0x84a00000 0x0 0x3700000>; 494 no-map; 495 }; 496 497 mpss_mem: mpss@88100000 { 498 reg = <0x0 0x88100000 0x0 0xcd00000>; 499 no-map; 500 }; 501 502 q6_mpss_dtb_mem: q6-mpss-dtb@94e00000 { 503 reg = <0x0 0x94e00000 0x0 0x80000>; 504 no-map; 505 }; 506 507 ipa_fw_mem: ipa-fw@94e80000 { 508 reg = <0x0 0x94e80000 0x0 0x10000>; 509 no-map; 510 }; 511 512 ipa_gsi_mem: ipa-gsi@94e90000 { 513 reg = <0x0 0x94e90000 0x0 0xa000>; 514 no-map; 515 }; 516 517 gpu_micro_code_mem: gpu-micro-code@94e9a000 { 518 reg = <0x0 0x94e9a000 0x0 0x2000>; 519 no-map; 520 }; 521 522 camera_mem: camera@94f00000 { 523 reg = <0x0 0x94f00000 0x0 0x800000>; 524 no-map; 525 }; 526 527 camera_2_mem: camera-2@95700000 { 528 reg = <0x0 0x95700000 0x0 0x800000>; 529 no-map; 530 }; 531 532 video_mem: video@95f00000 { 533 reg = <0x0 0x95f00000 0x0 0x800000>; 534 no-map; 535 }; 536 537 soccp_mem: soccp@96700000 { 538 reg = <0x0 0x96700000 0x0 0x180000>; 539 no-map; 540 }; 541 542 wpss_mem: wpss@97000000 { 543 reg = <0x0 0x97000000 0x0 0x1900000>; 544 no-map; 545 }; 546 547 cdsp_mem: cdsp@98900000 { 548 reg = <0x0 0x98900000 0x0 0x1400000>; 549 no-map; 550 }; 551 552 q6_cdsp_dtb_mem: q6-cdsp-dtb@99d00000 { 553 reg = <0x0 0x99d00000 0x0 0x80000>; 554 no-map; 555 }; 556 557 q6_adsp_dtb_mem: q6-adsp-dtb@99d80000 { 558 reg = <0x0 0x99d80000 0x0 0x80000>; 559 no-map; 560 }; 561 562 adspslpi_mem: adspslpi@99e00000 { 563 reg = <0x0 0x99e00000 0x0 0x2a00000>; 564 no-map; 565 }; 566 567 wlan_msa_mem: wlan-msa@a6400000 { 568 reg = <0x0 0xa6400000 0x0 0xc00000>; 569 no-map; 570 }; 571 572 xbl_ramdump_mem: xbl-ramdump@b8000000 { 573 reg = <0x0 0xb8000000 0x0 0x1c0000>; 574 no-map; 575 }; 576 577 /* Merged tz_reserved, xbl_sc, and qtee regions */ 578 tz_merged_mem: tz-merged@d8000000 { 579 reg = <0x0 0xd8000000 0x0 0x600000>; 580 no-map; 581 }; 582 583 trust_ui_vm_mem: trust-ui-vm@f3800000 { 584 reg = <0x0 0xf3800000 0x0 0x4400000>; 585 no-map; 586 }; 587 588 oem_vm_mem: oem-vm@f7c00000 { 589 reg = <0x0 0xf7c00000 0x0 0x4c00000>; 590 no-map; 591 }; 592 593 llcc_lpi_mem: llcc-lpi@ff800000 { 594 reg = <0x0 0xff800000 0x0 0x180000>; 595 no-map; 596 }; 597 }; 598 599 soc: soc@0 { 600 compatible = "simple-bus"; 601 602 #address-cells = <2>; 603 #size-cells = <2>; 604 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; 605 ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; 606 607 gcc: clock-controller@100000 { 608 compatible = "qcom,eliza-gcc"; 609 reg = <0x0 0x00100000 0x0 0x1f4200>; 610 611 clocks = <&bi_tcxo_div2>, 612 <&sleep_clk>, 613 <0>, 614 <0>, 615 <&ufs_mem_phy 0>, 616 <&ufs_mem_phy 1>, 617 <&ufs_mem_phy 2>, 618 <0>; 619 620 power-domains = <&rpmhpd RPMHPD_CX>; 621 622 #clock-cells = <1>; 623 #reset-cells = <1>; 624 #power-domain-cells = <1>; 625 }; 626 627 qupv3_2: geniqup@8c0000 { 628 compatible = "qcom,geni-se-qup"; 629 reg = <0x0 0x008c0000 0x0 0x2000>; 630 631 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 632 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 633 clock-names = "m-ahb", 634 "s-ahb"; 635 636 iommus = <&apps_smmu 0x423 0x0>; 637 638 #address-cells = <2>; 639 #size-cells = <2>; 640 ranges; 641 642 uart14: serial@894000 { 643 compatible = "qcom,geni-uart"; 644 reg = <0x0 0x00894000 0x0 0x4000>; 645 646 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 647 648 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 649 clock-names = "se"; 650 651 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 652 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 653 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 654 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 655 interconnect-names = "qup-core", 656 "qup-config"; 657 658 pinctrl-0 = <&qup_uart14_default>; 659 pinctrl-names = "default"; 660 661 status = "disabled"; 662 }; 663 }; 664 665 config_noc: interconnect@1600000 { 666 compatible = "qcom,eliza-cnoc-cfg"; 667 reg = <0x0 0x01600000 0x0 0x5200>; 668 qcom,bcm-voters = <&apps_bcm_voter>; 669 #interconnect-cells = <2>; 670 }; 671 672 cnoc_main: interconnect@1500000 { 673 compatible = "qcom,eliza-cnoc-main"; 674 reg = <0x0 0x01500000 0x0 0x16080>; 675 qcom,bcm-voters = <&apps_bcm_voter>; 676 #interconnect-cells = <2>; 677 }; 678 679 system_noc: interconnect@1680000 { 680 compatible = "qcom,eliza-system-noc"; 681 reg = <0x0 0x01680000 0x0 0x40000>; 682 qcom,bcm-voters = <&apps_bcm_voter>; 683 #interconnect-cells = <2>; 684 }; 685 686 pcie_noc: interconnect@16c0000 { 687 compatible = "qcom,eliza-pcie-anoc"; 688 reg = <0x0 0x016c0000 0x0 0x11400>; 689 qcom,bcm-voters = <&apps_bcm_voter>; 690 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 691 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 692 #interconnect-cells = <2>; 693 }; 694 695 aggre1_noc: interconnect@16e0000 { 696 compatible = "qcom,eliza-aggre1-noc"; 697 reg = <0x0 0x016e0000 0x0 0x16400>; 698 qcom,bcm-voters = <&apps_bcm_voter>; 699 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 700 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 701 #interconnect-cells = <2>; 702 }; 703 704 aggre2_noc: interconnect@1700000 { 705 compatible = "qcom,eliza-aggre2-noc"; 706 reg = <0x0 0x01700000 0x0 0x1f400>; 707 qcom,bcm-voters = <&apps_bcm_voter>; 708 clocks = <&rpmhcc RPMH_IPA_CLK>; 709 #interconnect-cells = <2>; 710 }; 711 712 mmss_noc: interconnect@1780000 { 713 compatible = "qcom,eliza-mmss-noc"; 714 reg = <0x0 0x01780000 0x0 0x7d800>; 715 qcom,bcm-voters = <&apps_bcm_voter>; 716 #interconnect-cells = <2>; 717 }; 718 719 ufs_mem_phy: phy@1d80000 { 720 compatible = "qcom,eliza-qmp-ufs-phy", 721 "qcom,sm8650-qmp-ufs-phy"; 722 reg = <0x0 0x01d80000 0x0 0x2000>; 723 724 clocks = <&rpmhcc RPMH_CXO_CLK>, 725 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 726 <&tcsr TCSR_UFS_CLKREF_EN>; 727 clock-names = "ref", 728 "ref_aux", 729 "qref"; 730 731 resets = <&ufs_mem_hc 0>; 732 reset-names = "ufsphy"; 733 734 power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>; 735 736 #clock-cells = <1>; 737 #phy-cells = <0>; 738 739 status = "disabled"; 740 }; 741 742 ufs_mem_hc: ufshc@1d84000 { 743 compatible = "qcom,eliza-ufshc", 744 "qcom,ufshc", 745 "jedec,ufs-2.0"; 746 reg = <0x0 0x01d84000 0x0 0x3000>, 747 <0x0 0x01da0000 0x0 0x15000>; 748 reg-names = "std", 749 "mcq"; 750 751 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 752 753 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 754 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 755 <&gcc GCC_UFS_PHY_AHB_CLK>, 756 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 757 <&rpmhcc RPMH_LN_BB_CLK3>, 758 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 759 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 760 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 761 clock-names = "core_clk", 762 "bus_aggr_clk", 763 "iface_clk", 764 "core_clk_unipro", 765 "ref_clk", 766 "tx_lane0_sync_clk", 767 "rx_lane0_sync_clk", 768 "rx_lane1_sync_clk"; 769 770 operating-points-v2 = <&ufs_opp_table>; 771 772 resets = <&gcc GCC_UFS_PHY_BCR>; 773 reset-names = "rst"; 774 775 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 776 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 777 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 778 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 779 interconnect-names = "ufs-ddr", 780 "cpu-ufs"; 781 782 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 783 required-opps = <&rpmhpd_opp_nom>; 784 785 iommus = <&apps_smmu 0x60 0x0>; 786 dma-coherent; 787 788 msi-parent = <&gic_its 0x60>; 789 790 lanes-per-direction = <2>; 791 qcom,ice = <&ice>; 792 793 phys = <&ufs_mem_phy>; 794 phy-names = "ufsphy"; 795 796 #reset-cells = <1>; 797 798 status = "disabled"; 799 800 ufs_opp_table: opp-table { 801 compatible = "operating-points-v2"; 802 803 opp-100000000 { 804 opp-hz = /bits/ 64 <100000000>, 805 /bits/ 64 <0>, 806 /bits/ 64 <0>, 807 /bits/ 64 <100000000>, 808 /bits/ 64 <0>, 809 /bits/ 64 <0>, 810 /bits/ 64 <0>, 811 /bits/ 64 <0>; 812 required-opps = <&rpmhpd_opp_low_svs>; 813 }; 814 815 opp-201500000 { 816 opp-hz = /bits/ 64 <201500000>, 817 /bits/ 64 <0>, 818 /bits/ 64 <0>, 819 /bits/ 64 <201500000>, 820 /bits/ 64 <0>, 821 /bits/ 64 <0>, 822 /bits/ 64 <0>, 823 /bits/ 64 <0>; 824 required-opps = <&rpmhpd_opp_svs_l1>; 825 }; 826 827 opp-403000000 { 828 opp-hz = /bits/ 64 <403000000>, 829 /bits/ 64 <0>, 830 /bits/ 64 <0>, 831 /bits/ 64 <403000000>, 832 /bits/ 64 <0>, 833 /bits/ 64 <0>, 834 /bits/ 64 <0>, 835 /bits/ 64 <0>; 836 required-opps = <&rpmhpd_opp_nom>; 837 }; 838 }; 839 }; 840 841 ice: crypto@1d88000 { 842 compatible = "qcom,eliza-inline-crypto-engine", 843 "qcom,inline-crypto-engine"; 844 reg = <0x0 0x01d88000 0x0 0x18000>; 845 846 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 847 }; 848 849 tcsr_mutex: hwlock@1f40000 { 850 compatible = "qcom,tcsr-mutex"; 851 reg = <0x0 0x01f40000 0x0 0x20000>; 852 #hwlock-cells = <1>; 853 }; 854 855 tcsr: clock-controller@1fbf000 { 856 compatible = "qcom,eliza-tcsr", "syscon"; 857 reg = <0x0 0x01fbf000 0x0 0x21000>; 858 859 clocks = <&rpmhcc RPMH_CXO_CLK>; 860 861 #clock-cells = <1>; 862 #reset-cells = <1>; 863 }; 864 865 lpass_ag_noc: interconnect@7e40000 { 866 compatible = "qcom,eliza-lpass-ag-noc"; 867 reg = <0x0 0x07e40000 0x0 0xe080>; 868 qcom,bcm-voters = <&apps_bcm_voter>; 869 #interconnect-cells = <2>; 870 }; 871 872 lpass_lpiaon_noc: interconnect@7400000 { 873 compatible = "qcom,eliza-lpass-lpiaon-noc"; 874 reg = <0x0 0x07400000 0x0 0x19080>; 875 qcom,bcm-voters = <&apps_bcm_voter>; 876 #interconnect-cells = <2>; 877 }; 878 879 lpass_lpicx_noc: interconnect@7420000 { 880 compatible = "qcom,eliza-lpass-lpicx-noc"; 881 reg = <0x0 0x07420000 0x0 0x44080>; 882 qcom,bcm-voters = <&apps_bcm_voter>; 883 #interconnect-cells = <2>; 884 }; 885 886 pdc: interrupt-controller@b220000 { 887 compatible = "qcom,eliza-pdc", "qcom,pdc"; 888 reg = <0x0 0x0b220000 0x0 0x40000>, 889 <0x0 0x174000f0 0x0 0x64>; 890 891 qcom,pdc-ranges = <0 480 8>, <8 719 1>, <9 718 1>, 892 <10 230 1>, <11 724 1>, <12 716 1>, 893 <13 727 1>, <14 720 1>, <15 726 1>, 894 <16 721 1>, <17 262 1>, <18 70 1>, 895 <19 723 1>, <20 234 1>, <22 725 1>, 896 <23 231 1>, <24 504 5>, <30 510 8>, 897 <40 520 6>, <51 531 4>, <58 538 2>, 898 <61 541 5>, <66 92 1>, <67 547 13>, 899 <80 240 1>, <81 235 1>, <82 310 2>, 900 <84 248 1>, <85 241 1>, <86 238 2>, 901 <88 254 1>, <89 509 1>, <90 563 1>, 902 <91 259 2>, <93 201 1>, <94 246 1>, 903 <95 93 1>, <96 611 29>, <125 63 1>, 904 <126 366 2>, <128 374 1>, <129 377 1>, 905 <130 428 1>, <131 434 2>, <133 437 1>, 906 <134 452 2>, <136 458 2>, <138 464 11>, 907 <149 671 1>, <150 688 1>, <151 714 2>, 908 <153 722 1>, <154 255 1>, <155 269 2>, 909 <157 276 1>, <158 287 1>, <159 306 4>; 910 #interrupt-cells = <2>; 911 interrupt-parent = <&intc>; 912 interrupt-controller; 913 }; 914 915 tsens0: thermal-sensor@c228000 { 916 compatible = "qcom,eliza-tsens", "qcom,tsens-v2"; 917 reg = <0x0 0x0c228000 0x0 0x1000>, 918 <0x0 0x0c222000 0x0 0x1000>; 919 920 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 921 <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>; 922 interrupt-names = "uplow", 923 "critical"; 924 925 #qcom,sensors = <13>; 926 927 #thermal-sensor-cells = <1>; 928 }; 929 930 tsens1: thermal-sensor@c229000 { 931 compatible = "qcom,eliza-tsens", "qcom,tsens-v2"; 932 reg = <0x0 0x0c229000 0x0 0x1000>, 933 <0x0 0x0c223000 0x0 0x1000>; 934 935 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 937 interrupt-names = "uplow", 938 "critical"; 939 940 #qcom,sensors = <14>; 941 942 #thermal-sensor-cells = <1>; 943 }; 944 945 tsens2: thermal-sensor@c22a000 { 946 compatible = "qcom,eliza-tsens", "qcom,tsens-v2"; 947 reg = <0x0 0x0c22a000 0x0 0x1000>, 948 <0x0 0x0c224000 0x0 0x1000>; 949 950 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>; 952 interrupt-names = "uplow", 953 "critical"; 954 955 #qcom,sensors = <5>; 956 957 #thermal-sensor-cells = <1>; 958 }; 959 960 spmi: arbiter@c400000 { 961 compatible = "qcom,eliza-spmi-pmic-arb", 962 "qcom,x1e80100-spmi-pmic-arb"; 963 reg = <0x0 0x0c400000 0x0 0x3000>, 964 <0x0 0x0c500000 0x0 0x400000>, 965 <0x0 0x0c440000 0x0 0x80000>; 966 reg-names = "core", 967 "chnls", 968 "obsrvr"; 969 970 qcom,ee = <0>; 971 qcom,channel = <0>; 972 973 #address-cells = <2>; 974 #size-cells = <2>; 975 ranges; 976 977 spmi_bus0: spmi@c42d000 { 978 reg = <0x0 0x0c42d000 0x0 0x4000>, 979 <0x0 0x0c4c0000 0x0 0x10000>; 980 reg-names = "cnfg", 981 "intr"; 982 983 interrupt-names = "periph_irq"; 984 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 985 interrupt-controller; 986 #interrupt-cells = <4>; 987 988 #address-cells = <2>; 989 #size-cells = <0>; 990 }; 991 992 spmi_bus1: spmi@c432000 { 993 reg = <0x0 0x0c432000 0x0 0x4000>, 994 <0x0 0x0c4d0000 0x0 0x10000>; 995 reg-names = "cnfg", 996 "intr"; 997 998 interrupt-names = "periph_irq"; 999 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; 1000 interrupt-controller; 1001 #interrupt-cells = <4>; 1002 1003 #address-cells = <2>; 1004 #size-cells = <0>; 1005 }; 1006 }; 1007 1008 apps_smmu: iommu@15000000 { 1009 compatible = "qcom,eliza-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1010 reg = <0x0 0x15000000 0x0 0x100000>; 1011 1012 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1013 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1014 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1015 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1016 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1017 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1018 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1019 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1020 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1021 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1022 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1023 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1024 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1026 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1033 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1034 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1035 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1036 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1037 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1038 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1039 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1040 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1041 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1042 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1043 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1044 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1045 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1046 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1047 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1048 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1049 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1050 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1054 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1074 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1075 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1080 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1081 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1083 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 1093 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 1095 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>; 1125 1126 #iommu-cells = <2>; 1127 #global-interrupts = <1>; 1128 1129 dma-coherent; 1130 }; 1131 1132 intc: interrupt-controller@17100000 { 1133 compatible = "arm,gic-v3"; 1134 reg = <0x0 0x17100000 0x0 0x10000>, 1135 <0x0 0x17180000 0x0 0x200000>; 1136 1137 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1138 1139 #interrupt-cells = <3>; 1140 interrupt-controller; 1141 1142 #redistributor-regions = <1>; 1143 redistributor-stride = <0x0 0x40000>; 1144 1145 #address-cells = <2>; 1146 #size-cells = <2>; 1147 ranges; 1148 1149 gic_its: msi-controller@17140000 { 1150 compatible = "arm,gic-v3-its"; 1151 reg = <0x0 0x17140000 0x0 0x40000>; 1152 1153 msi-controller; 1154 #msi-cells = <1>; 1155 }; 1156 }; 1157 1158 apps_rsc: rsc@17a00000 { 1159 compatible = "qcom,rpmh-rsc"; 1160 reg = <0x0 0x17a00000 0x0 0x10000>, 1161 <0x0 0x17a10000 0x0 0x10000>, 1162 <0x0 0x17a20000 0x0 0x10000>; 1163 reg-names = "drv-0", 1164 "drv-1", 1165 "drv-2"; 1166 1167 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1170 1171 power-domains = <&cluster_pd>; 1172 label = "apps_rsc"; 1173 1174 qcom,tcs-offset = <0xd00>; 1175 qcom,drv-id = <2>; 1176 qcom,tcs-config = <ACTIVE_TCS 3>, 1177 <SLEEP_TCS 2>, 1178 <WAKE_TCS 2>, 1179 <CONTROL_TCS 0>; 1180 1181 apps_bcm_voter: bcm-voter { 1182 compatible = "qcom,bcm-voter"; 1183 }; 1184 1185 rpmhcc: clock-controller { 1186 compatible = "qcom,eliza-rpmh-clk"; 1187 #clock-cells = <1>; 1188 clocks = <&xo_board>; 1189 clock-names = "xo"; 1190 }; 1191 1192 rpmhpd: power-controller { 1193 compatible = "qcom,eliza-rpmhpd"; 1194 1195 operating-points-v2 = <&rpmhpd_opp_table>; 1196 1197 #power-domain-cells = <1>; 1198 1199 rpmhpd_opp_table: opp-table { 1200 compatible = "operating-points-v2"; 1201 1202 rpmhpd_opp_ret: opp-16 { 1203 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1204 }; 1205 1206 rpmhpd_opp_min_svs: opp-48 { 1207 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1208 }; 1209 1210 rpmhpd_opp_low_svs_d3: opp-50 { 1211 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>; 1212 }; 1213 1214 rpmhpd_opp_low_svs_d2: opp-52 { 1215 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 1216 }; 1217 1218 rpmhpd_opp_low_svs_d1: opp-56 { 1219 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 1220 }; 1221 1222 rpmhpd_opp_low_svs_d0: opp-60 { 1223 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 1224 }; 1225 1226 rpmhpd_opp_low_svs: opp-64 { 1227 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1228 }; 1229 1230 rpmhpd_opp_low_svs_l1: opp-80 { 1231 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 1232 }; 1233 1234 rpmhpd_opp_svs: opp-128 { 1235 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1236 }; 1237 1238 rpmhpd_opp_svs_l0: opp-144 { 1239 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 1240 }; 1241 1242 rpmhpd_opp_svs_l1: opp-192 { 1243 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1244 }; 1245 1246 rpmhpd_opp_svs_l2: opp-224 { 1247 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1248 }; 1249 1250 rpmhpd_opp_nom: opp-256 { 1251 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1252 }; 1253 1254 rpmhpd_opp_nom_l1: opp-320 { 1255 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1256 }; 1257 1258 rpmhpd_opp_nom_l2: opp-336 { 1259 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1260 }; 1261 1262 rpmhpd_opp_turbo: opp-384 { 1263 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1264 }; 1265 1266 rpmhpd_opp_turbo_l1: opp-416 { 1267 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1268 }; 1269 1270 rpmhpd_opp_turbo_l2: opp-432 { 1271 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>; 1272 }; 1273 1274 rpmhpd_opp_turbo_l3: opp-448 { 1275 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>; 1276 }; 1277 1278 rpmhpd_opp_turbo_l4: opp-452 { 1279 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>; 1280 }; 1281 1282 rpmhpd_opp_super_turbo_no_cpr: opp-480 { 1283 opp-level = <RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR>; 1284 }; 1285 }; 1286 }; 1287 }; 1288 1289 epss_l3: interconnect@17d90000 { 1290 compatible = "qcom,eliza-epss-l3", "qcom,epss-l3"; 1291 reg = <0x0 0x17d90000 0x0 0x1000>; 1292 1293 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 1294 clock-names = "xo", "alternate"; 1295 1296 #interconnect-cells = <1>; 1297 }; 1298 1299 cpufreq_hw: cpufreq@17d91000 { 1300 compatible = "qcom,eliza-cpufreq-epss", "qcom,cpufreq-epss"; 1301 reg = <0x0 0x17d91000 0x0 0x1000>, 1302 <0x0 0x17d92000 0x0 0x1000>, 1303 <0x0 0x17d93000 0x0 0x1000>; 1304 reg-names = "freq-domain0", 1305 "freq-domain1", 1306 "freq-domain2"; 1307 1308 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1309 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1310 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1311 interrupt-names = "dcvsh-irq-0", 1312 "dcvsh-irq-1", 1313 "dcvsh-irq-2"; 1314 1315 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 1316 clock-names = "xo", "alternate"; 1317 1318 #freq-domain-cells = <1>; 1319 #clock-cells = <1>; 1320 }; 1321 1322 tlmm: pinctrl@f100000 { 1323 compatible = "qcom,eliza-tlmm"; 1324 reg = <0x0 0x0f100000 0x0 0xf00000>; 1325 1326 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1327 1328 gpio-controller; 1329 #gpio-cells = <2>; 1330 1331 interrupt-controller; 1332 #interrupt-cells = <2>; 1333 1334 gpio-ranges = <&tlmm 0 0 184>; 1335 wakeup-parent = <&pdc>; 1336 1337 qup_uart14_default: qup-uart14-default-state { 1338 /* TX, RX */ 1339 pins = "gpio18", "gpio19"; 1340 function = "qup2_se5"; 1341 drive-strength = <2>; 1342 bias-pull-up; 1343 }; 1344 }; 1345 1346 gem_noc: interconnect@24100000 { 1347 compatible = "qcom,eliza-gem-noc"; 1348 reg = <0x0 0x24100000 0x0 0x163080>; 1349 qcom,bcm-voters = <&apps_bcm_voter>; 1350 #interconnect-cells = <2>; 1351 }; 1352 1353 nsp_noc: interconnect@320c0000 { 1354 compatible = "qcom,eliza-nsp-noc"; 1355 reg = <0x0 0x320c0000 0x0 0xe080>; 1356 qcom,bcm-voters = <&apps_bcm_voter>; 1357 #interconnect-cells = <2>; 1358 }; 1359 }; 1360 1361 thermal-zones { 1362 aoss0-thermal { 1363 thermal-sensors = <&tsens0 0>; 1364 1365 trips { 1366 aoss-hot { 1367 temperature = <110000>; 1368 hysteresis = <1000>; 1369 type = "hot"; 1370 }; 1371 1372 aoss-critical { 1373 temperature = <115000>; 1374 hysteresis = <0>; 1375 type = "critical"; 1376 }; 1377 }; 1378 }; 1379 1380 aoss1-thermal { 1381 thermal-sensors = <&tsens1 0>; 1382 1383 trips { 1384 aoss-hot { 1385 temperature = <110000>; 1386 hysteresis = <1000>; 1387 type = "hot"; 1388 }; 1389 1390 aoss-critical { 1391 temperature = <115000>; 1392 hysteresis = <0>; 1393 type = "critical"; 1394 }; 1395 }; 1396 }; 1397 1398 aoss2-thermal { 1399 thermal-sensors = <&tsens2 0>; 1400 1401 trips { 1402 aoss-hot { 1403 temperature = <110000>; 1404 hysteresis = <1000>; 1405 type = "hot"; 1406 }; 1407 1408 aoss-critical { 1409 temperature = <115000>; 1410 hysteresis = <0>; 1411 type = "critical"; 1412 }; 1413 }; 1414 }; 1415 1416 camera0-thermal { 1417 thermal-sensors = <&tsens1 12>; 1418 1419 trips { 1420 camera-hot { 1421 temperature = <110000>; 1422 hysteresis = <1000>; 1423 type = "hot"; 1424 }; 1425 1426 camera-critical { 1427 temperature = <115000>; 1428 hysteresis = <0>; 1429 type = "critical"; 1430 }; 1431 }; 1432 }; 1433 1434 camera1-thermal { 1435 thermal-sensors = <&tsens1 13>; 1436 1437 trips { 1438 camera-hot { 1439 temperature = <110000>; 1440 hysteresis = <1000>; 1441 type = "hot"; 1442 }; 1443 1444 camera-critical { 1445 temperature = <115000>; 1446 hysteresis = <0>; 1447 type = "critical"; 1448 }; 1449 }; 1450 }; 1451 1452 cpu0-thermal { 1453 thermal-sensors = <&tsens1 1>; 1454 1455 trips { 1456 cpu-critical { 1457 temperature = <110000>; 1458 hysteresis = <1000>; 1459 type = "critical"; 1460 }; 1461 }; 1462 }; 1463 1464 cpu1-thermal { 1465 thermal-sensors = <&tsens1 2>; 1466 1467 trips { 1468 cpu-critical { 1469 temperature = <110000>; 1470 hysteresis = <1000>; 1471 type = "critical"; 1472 }; 1473 }; 1474 }; 1475 1476 cpu2-thermal { 1477 thermal-sensors = <&tsens1 3>; 1478 1479 trips { 1480 cpu-critical { 1481 temperature = <110000>; 1482 hysteresis = <1000>; 1483 type = "critical"; 1484 }; 1485 }; 1486 }; 1487 1488 cpu3-top-thermal { 1489 thermal-sensors = <&tsens0 3>; 1490 1491 trips { 1492 cpu-critical { 1493 temperature = <110000>; 1494 hysteresis = <1000>; 1495 type = "critical"; 1496 }; 1497 }; 1498 }; 1499 1500 cpu3-bottom-thermal { 1501 thermal-sensors = <&tsens0 4>; 1502 1503 trips { 1504 cpu-critical { 1505 temperature = <110000>; 1506 hysteresis = <1000>; 1507 type = "critical"; 1508 }; 1509 }; 1510 }; 1511 1512 cpu4-top-thermal { 1513 thermal-sensors = <&tsens0 5>; 1514 1515 trips { 1516 cpu-critical { 1517 temperature = <110000>; 1518 hysteresis = <1000>; 1519 type = "critical"; 1520 }; 1521 }; 1522 }; 1523 1524 cpu4-bottom-thermal { 1525 thermal-sensors = <&tsens0 6>; 1526 1527 trips { 1528 cpu-critical { 1529 temperature = <110000>; 1530 hysteresis = <1000>; 1531 type = "critical"; 1532 }; 1533 }; 1534 }; 1535 1536 cpu5-top-thermal { 1537 thermal-sensors = <&tsens0 7>; 1538 1539 trips { 1540 cpu-critical { 1541 temperature = <110000>; 1542 hysteresis = <1000>; 1543 type = "critical"; 1544 }; 1545 }; 1546 }; 1547 1548 cpu5-bottom-thermal { 1549 thermal-sensors = <&tsens0 8>; 1550 1551 trips { 1552 cpu-critical { 1553 temperature = <110000>; 1554 hysteresis = <1000>; 1555 type = "critical"; 1556 }; 1557 }; 1558 }; 1559 1560 cpu6-top-thermal { 1561 thermal-sensors = <&tsens0 9>; 1562 1563 trips { 1564 cpu-critical { 1565 temperature = <110000>; 1566 hysteresis = <1000>; 1567 type = "critical"; 1568 }; 1569 }; 1570 }; 1571 1572 cpu6-bottom-thermal { 1573 thermal-sensors = <&tsens0 10>; 1574 1575 trips { 1576 cpu-critical { 1577 temperature = <110000>; 1578 hysteresis = <1000>; 1579 type = "critical"; 1580 }; 1581 }; 1582 }; 1583 1584 cpu7-top-thermal { 1585 thermal-sensors = <&tsens0 11>; 1586 1587 trips { 1588 cpu-critical { 1589 temperature = <110000>; 1590 hysteresis = <1000>; 1591 type = "critical"; 1592 }; 1593 }; 1594 }; 1595 1596 cpu7-bottom-thermal { 1597 thermal-sensors = <&tsens0 12>; 1598 1599 trips { 1600 cpu-critical { 1601 temperature = <110000>; 1602 hysteresis = <1000>; 1603 type = "critical"; 1604 }; 1605 }; 1606 }; 1607 1608 cpuss0-thermal { 1609 thermal-sensors = <&tsens0 1>; 1610 1611 trips { 1612 cpuss-hot { 1613 temperature = <110000>; 1614 hysteresis = <1000>; 1615 type = "hot"; 1616 }; 1617 1618 cpuss-critical { 1619 temperature = <115000>; 1620 hysteresis = <0>; 1621 type = "critical"; 1622 }; 1623 }; 1624 }; 1625 1626 cpuss1-thermal { 1627 thermal-sensors = <&tsens0 2>; 1628 1629 trips { 1630 cpuss-hot { 1631 temperature = <110000>; 1632 hysteresis = <1000>; 1633 type = "hot"; 1634 }; 1635 1636 cpuss-critical { 1637 temperature = <115000>; 1638 hysteresis = <0>; 1639 type = "critical"; 1640 }; 1641 }; 1642 }; 1643 1644 ddr-thermal { 1645 thermal-sensors = <&tsens1 11>; 1646 1647 trips { 1648 ddr-hot { 1649 temperature = <110000>; 1650 hysteresis = <1000>; 1651 type = "hot"; 1652 }; 1653 1654 ddr-critical { 1655 temperature = <115000>; 1656 hysteresis = <0>; 1657 type = "critical"; 1658 }; 1659 }; 1660 }; 1661 1662 gpuss0-thermal { 1663 polling-delay-passive = <10>; 1664 1665 thermal-sensors = <&tsens1 8>; 1666 1667 trips { 1668 gpu-alert { 1669 temperature = <95000>; 1670 hysteresis = <1000>; 1671 type = "passive"; 1672 }; 1673 1674 gpu-hot { 1675 temperature = <110000>; 1676 hysteresis = <1000>; 1677 type = "hot"; 1678 }; 1679 1680 gpu-critical { 1681 temperature = <115000>; 1682 hysteresis = <0>; 1683 type = "critical"; 1684 }; 1685 }; 1686 }; 1687 1688 gpuss1-thermal { 1689 polling-delay-passive = <10>; 1690 1691 thermal-sensors = <&tsens1 9>; 1692 1693 trips { 1694 gpu-alert { 1695 temperature = <95000>; 1696 hysteresis = <1000>; 1697 type = "passive"; 1698 }; 1699 1700 gpu-hot { 1701 temperature = <110000>; 1702 hysteresis = <1000>; 1703 type = "hot"; 1704 }; 1705 1706 gpu-critical { 1707 temperature = <115000>; 1708 hysteresis = <0>; 1709 type = "critical"; 1710 }; 1711 }; 1712 }; 1713 1714 modem0-thermal { 1715 thermal-sensors = <&tsens2 1>; 1716 1717 trips { 1718 modem-hot { 1719 temperature = <110000>; 1720 hysteresis = <1000>; 1721 type = "hot"; 1722 }; 1723 1724 modem-critical { 1725 temperature = <115000>; 1726 hysteresis = <0>; 1727 type = "critical"; 1728 }; 1729 }; 1730 }; 1731 1732 modem1-thermal { 1733 thermal-sensors = <&tsens2 2>; 1734 1735 trips { 1736 modem-hot { 1737 temperature = <110000>; 1738 hysteresis = <1000>; 1739 type = "hot"; 1740 }; 1741 1742 modem-critical { 1743 temperature = <115000>; 1744 hysteresis = <0>; 1745 type = "critical"; 1746 }; 1747 }; 1748 }; 1749 1750 modem2-thermal { 1751 thermal-sensors = <&tsens2 3>; 1752 1753 trips { 1754 modem-hot { 1755 temperature = <110000>; 1756 hysteresis = <1000>; 1757 type = "hot"; 1758 }; 1759 1760 modem-critical { 1761 temperature = <115000>; 1762 hysteresis = <0>; 1763 type = "critical"; 1764 }; 1765 }; 1766 }; 1767 1768 modem3-thermal { 1769 thermal-sensors = <&tsens2 4>; 1770 1771 trips { 1772 modem-hot { 1773 temperature = <110000>; 1774 hysteresis = <1000>; 1775 type = "hot"; 1776 }; 1777 1778 modem-critical { 1779 temperature = <115000>; 1780 hysteresis = <0>; 1781 type = "critical"; 1782 }; 1783 }; 1784 }; 1785 1786 nsphmx0-thermal { 1787 thermal-sensors = <&tsens1 6>; 1788 1789 trips { 1790 nsphmx-hot { 1791 temperature = <110000>; 1792 hysteresis = <1000>; 1793 type = "hot"; 1794 }; 1795 1796 nsphmx-critical { 1797 temperature = <115000>; 1798 hysteresis = <0>; 1799 type = "critical"; 1800 }; 1801 }; 1802 }; 1803 1804 nsphmx1-thermal { 1805 thermal-sensors = <&tsens1 7>; 1806 1807 trips { 1808 nsphmx-hot { 1809 temperature = <110000>; 1810 hysteresis = <1000>; 1811 type = "hot"; 1812 }; 1813 1814 nsphmx-critical { 1815 temperature = <115000>; 1816 hysteresis = <0>; 1817 type = "critical"; 1818 }; 1819 }; 1820 }; 1821 1822 nsphvx0-thermal { 1823 thermal-sensors = <&tsens1 4>; 1824 1825 trips { 1826 nsphvx-hot { 1827 temperature = <110000>; 1828 hysteresis = <1000>; 1829 type = "hot"; 1830 }; 1831 1832 nsphvx-critical { 1833 temperature = <115000>; 1834 hysteresis = <0>; 1835 type = "critical"; 1836 }; 1837 }; 1838 }; 1839 1840 nsphvx1-thermal { 1841 thermal-sensors = <&tsens1 5>; 1842 1843 trips { 1844 nsphvx-hot { 1845 temperature = <110000>; 1846 hysteresis = <1000>; 1847 type = "hot"; 1848 }; 1849 1850 nsphvx-critical { 1851 temperature = <115000>; 1852 hysteresis = <0>; 1853 type = "critical"; 1854 }; 1855 }; 1856 }; 1857 1858 video-thermal { 1859 thermal-sensors = <&tsens1 10>; 1860 1861 trips { 1862 video-hot { 1863 temperature = <110000>; 1864 hysteresis = <1000>; 1865 type = "hot"; 1866 }; 1867 1868 video-critical { 1869 temperature = <115000>; 1870 hysteresis = <0>; 1871 type = "critical"; 1872 }; 1873 }; 1874 }; 1875 }; 1876 1877 timer { 1878 compatible = "arm,armv8-timer"; 1879 1880 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1881 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1882 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1883 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 1884 }; 1885}; 1886