1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * (C) 2018 MediaTek Inc. 4 * Copyright (C) 2022 BayLibre SAS 5 * Fabien Parent <fparent@baylibre.com> 6 * Bernhard Rosenkränzer <bero@baylibre.com> 7 */ 8#include <dt-bindings/clock/mediatek,mt8365-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/phy/phy.h> 12#include <dt-bindings/power/mediatek,mt8365-power.h> 13 14/ { 15 compatible = "mediatek,mt8365"; 16 interrupt-parent = <&sysirq>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cluster0_opp: opp-table-0 { 25 compatible = "operating-points-v2"; 26 opp-shared; 27 28 opp-850000000 { 29 opp-hz = /bits/ 64 <850000000>; 30 opp-microvolt = <650000>; 31 }; 32 33 opp-918000000 { 34 opp-hz = /bits/ 64 <918000000>; 35 opp-microvolt = <668750>; 36 }; 37 38 opp-987000000 { 39 opp-hz = /bits/ 64 <987000000>; 40 opp-microvolt = <687500>; 41 }; 42 43 opp-1056000000 { 44 opp-hz = /bits/ 64 <1056000000>; 45 opp-microvolt = <706250>; 46 }; 47 48 opp-1125000000 { 49 opp-hz = /bits/ 64 <1125000000>; 50 opp-microvolt = <725000>; 51 }; 52 53 opp-1216000000 { 54 opp-hz = /bits/ 64 <1216000000>; 55 opp-microvolt = <750000>; 56 }; 57 58 opp-1308000000 { 59 opp-hz = /bits/ 64 <1308000000>; 60 opp-microvolt = <775000>; 61 }; 62 63 opp-1400000000 { 64 opp-hz = /bits/ 64 <1400000000>; 65 opp-microvolt = <800000>; 66 }; 67 68 opp-1466000000 { 69 opp-hz = /bits/ 64 <1466000000>; 70 opp-microvolt = <825000>; 71 }; 72 73 opp-1533000000 { 74 opp-hz = /bits/ 64 <1533000000>; 75 opp-microvolt = <850000>; 76 }; 77 78 opp-1633000000 { 79 opp-hz = /bits/ 64 <1633000000>; 80 opp-microvolt = <887500>; 81 }; 82 83 opp-1700000000 { 84 opp-hz = /bits/ 64 <1700000000>; 85 opp-microvolt = <912500>; 86 }; 87 88 opp-1767000000 { 89 opp-hz = /bits/ 64 <1767000000>; 90 opp-microvolt = <937500>; 91 }; 92 93 opp-1834000000 { 94 opp-hz = /bits/ 64 <1834000000>; 95 opp-microvolt = <962500>; 96 }; 97 98 opp-1917000000 { 99 opp-hz = /bits/ 64 <1917000000>; 100 opp-microvolt = <993750>; 101 }; 102 103 opp-2001000000 { 104 opp-hz = /bits/ 64 <2001000000>; 105 opp-microvolt = <1025000>; 106 }; 107 }; 108 109 cpu-map { 110 cluster0 { 111 core0 { 112 cpu = <&cpu0>; 113 }; 114 core1 { 115 cpu = <&cpu1>; 116 }; 117 core2 { 118 cpu = <&cpu2>; 119 }; 120 core3 { 121 cpu = <&cpu3>; 122 }; 123 }; 124 }; 125 126 cpu0: cpu@0 { 127 device_type = "cpu"; 128 compatible = "arm,cortex-a53"; 129 reg = <0x0>; 130 #cooling-cells = <2>; 131 enable-method = "psci"; 132 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 133 i-cache-size = <0x8000>; 134 i-cache-line-size = <64>; 135 i-cache-sets = <256>; 136 d-cache-size = <0x8000>; 137 d-cache-line-size = <64>; 138 d-cache-sets = <256>; 139 next-level-cache = <&l2>; 140 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 141 <&apmixedsys CLK_APMIXED_MAINPLL>; 142 clock-names = "cpu", "intermediate"; 143 operating-points-v2 = <&cluster0_opp>; 144 }; 145 146 cpu1: cpu@1 { 147 device_type = "cpu"; 148 compatible = "arm,cortex-a53"; 149 reg = <0x1>; 150 #cooling-cells = <2>; 151 enable-method = "psci"; 152 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 153 i-cache-size = <0x8000>; 154 i-cache-line-size = <64>; 155 i-cache-sets = <256>; 156 d-cache-size = <0x8000>; 157 d-cache-line-size = <64>; 158 d-cache-sets = <256>; 159 next-level-cache = <&l2>; 160 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 161 <&apmixedsys CLK_APMIXED_MAINPLL>; 162 clock-names = "cpu", "intermediate", "armpll"; 163 operating-points-v2 = <&cluster0_opp>; 164 }; 165 166 cpu2: cpu@2 { 167 device_type = "cpu"; 168 compatible = "arm,cortex-a53"; 169 reg = <0x2>; 170 #cooling-cells = <2>; 171 enable-method = "psci"; 172 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 173 i-cache-size = <0x8000>; 174 i-cache-line-size = <64>; 175 i-cache-sets = <256>; 176 d-cache-size = <0x8000>; 177 d-cache-line-size = <64>; 178 d-cache-sets = <256>; 179 next-level-cache = <&l2>; 180 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 181 <&apmixedsys CLK_APMIXED_MAINPLL>; 182 clock-names = "cpu", "intermediate", "armpll"; 183 operating-points-v2 = <&cluster0_opp>; 184 }; 185 186 cpu3: cpu@3 { 187 device_type = "cpu"; 188 compatible = "arm,cortex-a53"; 189 reg = <0x3>; 190 #cooling-cells = <2>; 191 enable-method = "psci"; 192 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 193 i-cache-size = <0x8000>; 194 i-cache-line-size = <64>; 195 i-cache-sets = <256>; 196 d-cache-size = <0x8000>; 197 d-cache-line-size = <64>; 198 d-cache-sets = <256>; 199 next-level-cache = <&l2>; 200 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 201 <&apmixedsys CLK_APMIXED_MAINPLL>; 202 clock-names = "cpu", "intermediate", "armpll"; 203 operating-points-v2 = <&cluster0_opp>; 204 }; 205 206 idle-states { 207 entry-method = "psci"; 208 209 CPU_MCDI: cpu-mcdi { 210 compatible = "arm,idle-state"; 211 local-timer-stop; 212 arm,psci-suspend-param = <0x00010001>; 213 entry-latency-us = <300>; 214 exit-latency-us = <200>; 215 min-residency-us = <1000>; 216 }; 217 218 CLUSTER_MCDI: cluster-mcdi { 219 compatible = "arm,idle-state"; 220 local-timer-stop; 221 arm,psci-suspend-param = <0x01010001>; 222 entry-latency-us = <350>; 223 exit-latency-us = <250>; 224 min-residency-us = <1200>; 225 }; 226 227 CLUSTER_DPIDLE: cluster-dpidle { 228 compatible = "arm,idle-state"; 229 local-timer-stop; 230 arm,psci-suspend-param = <0x01010004>; 231 entry-latency-us = <300>; 232 exit-latency-us = <800>; 233 min-residency-us = <3300>; 234 }; 235 }; 236 237 l2: l2-cache { 238 compatible = "cache"; 239 cache-level = <2>; 240 cache-size = <0x80000>; 241 cache-line-size = <64>; 242 cache-sets = <512>; 243 cache-unified; 244 }; 245 }; 246 247 clk26m: oscillator { 248 compatible = "fixed-clock"; 249 #clock-cells = <0>; 250 clock-frequency = <26000000>; 251 clock-output-names = "clk26m"; 252 }; 253 254 psci { 255 compatible = "arm,psci-1.0"; 256 method = "smc"; 257 }; 258 259 soc { 260 #address-cells = <2>; 261 #size-cells = <2>; 262 compatible = "simple-bus"; 263 ranges; 264 265 gic: interrupt-controller@c000000 { 266 compatible = "arm,gic-v3"; 267 #interrupt-cells = <3>; 268 interrupt-parent = <&gic>; 269 interrupt-controller; 270 reg = <0 0x0c000000 0 0x10000>, /* GICD */ 271 <0 0x0c080000 0 0x80000>, /* GICR */ 272 <0 0x0c400000 0 0x2000>, /* GICC */ 273 <0 0x0c410000 0 0x1000>, /* GICH */ 274 <0 0x0c420000 0 0x2000>; /* GICV */ 275 276 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 277 }; 278 279 topckgen: syscon@10000000 { 280 compatible = "mediatek,mt8365-topckgen", "syscon"; 281 reg = <0 0x10000000 0 0x1000>; 282 #clock-cells = <1>; 283 }; 284 285 infracfg: syscon@10001000 { 286 compatible = "mediatek,mt8365-infracfg", "syscon"; 287 reg = <0 0x10001000 0 0x1000>; 288 #clock-cells = <1>; 289 }; 290 291 pericfg: syscon@10003000 { 292 compatible = "mediatek,mt8365-pericfg", "syscon"; 293 reg = <0 0x10003000 0 0x1000>; 294 #clock-cells = <1>; 295 }; 296 297 syscfg_pctl: syscfg-pctl@10005000 { 298 compatible = "mediatek,mt8365-syscfg", "syscon"; 299 reg = <0 0x10005000 0 0x1000>; 300 }; 301 302 scpsys: syscon@10006000 { 303 compatible = "mediatek,mt8365-scpsys", "syscon", "simple-mfd"; 304 reg = <0 0x10006000 0 0x1000>; 305 306 /* System Power Manager */ 307 spm: power-controller { 308 compatible = "mediatek,mt8365-power-controller"; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 #power-domain-cells = <1>; 312 313 /* power domains of the SoC */ 314 power-domain@MT8365_POWER_DOMAIN_MM { 315 reg = <MT8365_POWER_DOMAIN_MM>; 316 clocks = <&topckgen CLK_TOP_MM_SEL>, 317 <&mmsys CLK_MM_MM_SMI_COMMON>, 318 <&mmsys CLK_MM_MM_SMI_COMM0>, 319 <&mmsys CLK_MM_MM_SMI_COMM1>, 320 <&mmsys CLK_MM_MM_SMI_LARB0>; 321 clock-names = "mm", "mm-0", "mm-1", 322 "mm-2", "mm-3"; 323 #power-domain-cells = <0>; 324 mediatek,infracfg = <&infracfg>; 325 mediatek,infracfg-nao = <&infracfg_nao>; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 329 power-domain@MT8365_POWER_DOMAIN_CAM { 330 reg = <MT8365_POWER_DOMAIN_CAM>; 331 clocks = <&camsys CLK_CAM_LARB2>, 332 <&camsys CLK_CAM_SENIF>, 333 <&camsys CLK_CAMSV0>, 334 <&camsys CLK_CAMSV1>, 335 <&camsys CLK_CAM_FDVT>, 336 <&camsys CLK_CAM_WPE>; 337 clock-names = "cam-0", "cam-1", 338 "cam-2", "cam-3", 339 "cam-4", "cam-5"; 340 #power-domain-cells = <0>; 341 mediatek,infracfg = <&infracfg>; 342 mediatek,smi = <&smi_common>; 343 }; 344 345 power-domain@MT8365_POWER_DOMAIN_VDEC { 346 reg = <MT8365_POWER_DOMAIN_VDEC>; 347 #power-domain-cells = <0>; 348 mediatek,smi = <&smi_common>; 349 }; 350 351 power-domain@MT8365_POWER_DOMAIN_VENC { 352 reg = <MT8365_POWER_DOMAIN_VENC>; 353 #power-domain-cells = <0>; 354 mediatek,smi = <&smi_common>; 355 }; 356 357 power-domain@MT8365_POWER_DOMAIN_APU { 358 reg = <MT8365_POWER_DOMAIN_APU>; 359 clocks = <&infracfg CLK_IFR_APU_AXI>, 360 <&apu CLK_APU_IPU_CK>, 361 <&apu CLK_APU_AXI>, 362 <&apu CLK_APU_JTAG>, 363 <&apu CLK_APU_IF_CK>, 364 <&apu CLK_APU_EDMA>, 365 <&apu CLK_APU_AHB>; 366 clock-names = "apu", "apu-0", 367 "apu-1", "apu-2", 368 "apu-3", "apu-4", 369 "apu-5"; 370 #power-domain-cells = <0>; 371 mediatek,infracfg = <&infracfg>; 372 mediatek,smi = <&smi_common>; 373 }; 374 }; 375 376 power-domain@MT8365_POWER_DOMAIN_CONN { 377 reg = <MT8365_POWER_DOMAIN_CONN>; 378 clocks = <&topckgen CLK_TOP_CONN_32K>, 379 <&topckgen CLK_TOP_CONN_26M>; 380 clock-names = "conn", "conn1"; 381 #power-domain-cells = <0>; 382 mediatek,infracfg = <&infracfg>; 383 }; 384 385 power-domain@MT8365_POWER_DOMAIN_MFG { 386 reg = <MT8365_POWER_DOMAIN_MFG>; 387 clocks = <&topckgen CLK_TOP_MFG_SEL>; 388 clock-names = "mfg"; 389 #power-domain-cells = <0>; 390 mediatek,infracfg = <&infracfg>; 391 }; 392 393 power-domain@MT8365_POWER_DOMAIN_AUDIO { 394 reg = <MT8365_POWER_DOMAIN_AUDIO>; 395 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 396 <&infracfg CLK_IFR_AUDIO>, 397 <&infracfg CLK_IFR_AUD_26M_BK>; 398 clock-names = "audio", "audio1", "audio2"; 399 #power-domain-cells = <0>; 400 mediatek,infracfg = <&infracfg>; 401 }; 402 403 power-domain@MT8365_POWER_DOMAIN_DSP { 404 reg = <MT8365_POWER_DOMAIN_DSP>; 405 clocks = <&topckgen CLK_TOP_DSP_SEL>, 406 <&topckgen CLK_TOP_DSP_26M>; 407 clock-names = "dsp", "dsp1"; 408 #power-domain-cells = <0>; 409 mediatek,infracfg = <&infracfg>; 410 }; 411 }; 412 }; 413 414 watchdog: watchdog@10007000 { 415 compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt"; 416 reg = <0 0x10007000 0 0x100>; 417 #reset-cells = <1>; 418 }; 419 420 pio: pinctrl@1000b000 { 421 compatible = "mediatek,mt8365-pinctrl"; 422 reg = <0 0x1000b000 0 0x1000>; 423 mediatek,pctl-regmap = <&syscfg_pctl>; 424 gpio-controller; 425 #gpio-cells = <2>; 426 interrupt-controller; 427 #interrupt-cells = <2>; 428 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 429 }; 430 431 apmixedsys: syscon@1000c000 { 432 compatible = "mediatek,mt8365-apmixedsys", "syscon"; 433 reg = <0 0x1000c000 0 0x1000>; 434 #clock-cells = <1>; 435 }; 436 437 pwrap: pwrap@1000d000 { 438 compatible = "mediatek,mt8365-pwrap"; 439 reg = <0 0x1000d000 0 0x1000>; 440 reg-names = "pwrap"; 441 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&infracfg CLK_IFR_PWRAP_SPI>, 443 <&infracfg CLK_IFR_PMIC_AP>, 444 <&infracfg CLK_IFR_PWRAP_SYS>, 445 <&infracfg CLK_IFR_PWRAP_TMR>; 446 clock-names = "spi", "wrap", "sys", "tmr"; 447 }; 448 449 keypad: keypad@10010000 { 450 compatible = "mediatek,mt6779-keypad"; 451 reg = <0 0x10010000 0 0x1000>; 452 wakeup-source; 453 interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>; 454 clocks = <&clk26m>; 455 clock-names = "kpd"; 456 status = "disabled"; 457 }; 458 459 mcucfg: syscon@10200000 { 460 compatible = "mediatek,mt8365-mcucfg", "syscon"; 461 reg = <0 0x10200000 0 0x2000>; 462 #clock-cells = <1>; 463 }; 464 465 sysirq: interrupt-controller@10200a80 { 466 compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq"; 467 interrupt-controller; 468 #interrupt-cells = <3>; 469 interrupt-parent = <&gic>; 470 reg = <0 0x10200a80 0 0x20>; 471 }; 472 473 iommu: iommu@10205000 { 474 compatible = "mediatek,mt8365-m4u"; 475 reg = <0 0x10205000 0 0x1000>; 476 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_LOW>; 477 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>; 478 #iommu-cells = <1>; 479 }; 480 481 infracfg_nao: infracfg@1020e000 { 482 compatible = "mediatek,mt8365-infracfg", "syscon"; 483 reg = <0 0x1020e000 0 0x1000>; 484 #clock-cells = <1>; 485 }; 486 487 rng: rng@1020f000 { 488 compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng"; 489 reg = <0 0x1020f000 0 0x100>; 490 clocks = <&infracfg CLK_IFR_TRNG>; 491 clock-names = "rng"; 492 }; 493 494 apdma: dma-controller@11000280 { 495 compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma"; 496 reg = <0 0x11000280 0 0x80>, 497 <0 0x11000300 0 0x80>, 498 <0 0x11000380 0 0x80>, 499 <0 0x11000400 0 0x80>, 500 <0 0x11000580 0 0x80>, 501 <0 0x11000600 0 0x80>; 502 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>, 503 <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>, 504 <GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>, 505 <GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>, 506 <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>, 507 <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 508 dma-requests = <6>; 509 clocks = <&infracfg CLK_IFR_AP_DMA>; 510 clock-names = "apdma"; 511 #dma-cells = <1>; 512 }; 513 514 uart0: serial@11002000 { 515 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 516 reg = <0 0x11002000 0 0x1000>; 517 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>; 518 clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>; 519 clock-names = "baud", "bus"; 520 dmas = <&apdma 0>, <&apdma 1>; 521 dma-names = "tx", "rx"; 522 status = "disabled"; 523 }; 524 525 uart1: serial@11003000 { 526 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 527 reg = <0 0x11003000 0 0x1000>; 528 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>; 529 clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>; 530 clock-names = "baud", "bus"; 531 dmas = <&apdma 2>, <&apdma 3>; 532 dma-names = "tx", "rx"; 533 status = "disabled"; 534 }; 535 536 uart2: serial@11004000 { 537 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 538 reg = <0 0x11004000 0 0x1000>; 539 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>; 540 clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>; 541 clock-names = "baud", "bus"; 542 dmas = <&apdma 4>, <&apdma 5>; 543 dma-names = "tx", "rx"; 544 status = "disabled"; 545 }; 546 547 pwm: pwm@11006000 { 548 compatible = "mediatek,mt8365-pwm"; 549 reg = <0 0x11006000 0 0x1000>; 550 #pwm-cells = <2>; 551 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 552 clocks = <&infracfg CLK_IFR_PWM_HCLK>, 553 <&infracfg CLK_IFR_PWM>, 554 <&infracfg CLK_IFR_PWM1>, 555 <&infracfg CLK_IFR_PWM2>, 556 <&infracfg CLK_IFR_PWM3>; 557 clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; 558 }; 559 560 i2c0: i2c@11007000 { 561 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 562 reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>; 563 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>; 564 clock-div = <1>; 565 clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>; 566 clock-names = "main", "dma"; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 status = "disabled"; 570 }; 571 572 i2c1: i2c@11008000 { 573 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 574 reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>; 575 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>; 576 clock-div = <1>; 577 clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>; 578 clock-names = "main", "dma"; 579 #address-cells = <1>; 580 #size-cells = <0>; 581 status = "disabled"; 582 }; 583 584 i2c2: i2c@11009000 { 585 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 586 reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>; 587 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>; 588 clock-div = <1>; 589 clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>; 590 clock-names = "main", "dma"; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 status = "disabled"; 594 }; 595 596 spi: spi@1100a000 { 597 compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi"; 598 reg = <0 0x1100a000 0 0x100>; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>; 602 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 603 <&topckgen CLK_TOP_SPI_SEL>, 604 <&infracfg CLK_IFR_SPI0>; 605 clock-names = "parent-clk", "sel-clk", "spi-clk"; 606 status = "disabled"; 607 }; 608 609 i2c3: i2c@1100f000 { 610 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 611 reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; 612 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>; 613 clock-div = <1>; 614 clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>; 615 clock-names = "main", "dma"; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 status = "disabled"; 619 }; 620 621 ssusb: usb@11201000 { 622 compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; 623 reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; 624 reg-names = "mac", "ippc"; 625 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>; 626 phys = <&u2port0 PHY_TYPE_USB2>, 627 <&u2port1 PHY_TYPE_USB2>; 628 clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 629 <&infracfg CLK_IFR_SSUSB_REF>, 630 <&infracfg CLK_IFR_SSUSB_SYS>, 631 <&infracfg CLK_IFR_ICUSB>; 632 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 633 #address-cells = <2>; 634 #size-cells = <2>; 635 ranges; 636 status = "disabled"; 637 638 usb_host: usb@11200000 { 639 compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci"; 640 reg = <0 0x11200000 0 0x1000>; 641 reg-names = "mac"; 642 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>; 643 clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 644 <&infracfg CLK_IFR_SSUSB_REF>, 645 <&infracfg CLK_IFR_SSUSB_SYS>, 646 <&infracfg CLK_IFR_ICUSB>, 647 <&infracfg CLK_IFR_SSUSB_XHCI>; 648 clock-names = "sys_ck", "ref_ck", "mcu_ck", 649 "dma_ck", "xhci_ck"; 650 status = "disabled"; 651 }; 652 }; 653 654 mmc0: mmc@11230000 { 655 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 656 reg = <0 0x11230000 0 0x1000>, 657 <0 0x11cd0000 0 0x1000>; 658 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>; 659 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, 660 <&infracfg CLK_IFR_MSDC0_HCLK>, 661 <&infracfg CLK_IFR_MSDC0_SRC>; 662 clock-names = "source", "hclk", "source_cg"; 663 status = "disabled"; 664 }; 665 666 mmc1: mmc@11240000 { 667 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 668 reg = <0 0x11240000 0 0x1000>, 669 <0 0x11c90000 0 0x1000>; 670 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>; 671 clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, 672 <&infracfg CLK_IFR_MSDC1_HCLK>, 673 <&infracfg CLK_IFR_MSDC1_SRC>; 674 clock-names = "source", "hclk", "source_cg"; 675 status = "disabled"; 676 }; 677 678 mmc2: mmc@11250000 { 679 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 680 reg = <0 0x11250000 0 0x1000>, 681 <0 0x11c60000 0 0x1000>; 682 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>; 683 clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>, 684 <&infracfg CLK_IFR_MSDC2_HCLK>, 685 <&infracfg CLK_IFR_MSDC2_SRC>, 686 <&infracfg CLK_IFR_MSDC2_BK>, 687 <&infracfg CLK_IFR_AP_MSDC0>; 688 clock-names = "source", "hclk", "source_cg", 689 "bus_clk", "sys_cg"; 690 status = "disabled"; 691 }; 692 693 ethernet: ethernet@112a0000 { 694 compatible = "mediatek,mt8365-eth"; 695 reg = <0 0x112a0000 0 0x1000>; 696 mediatek,pericfg = <&infracfg>; 697 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&topckgen CLK_TOP_ETH_SEL>, 699 <&infracfg CLK_IFR_NIC_AXI>, 700 <&infracfg CLK_IFR_NIC_SLV_AXI>; 701 clock-names = "core", "reg", "trans"; 702 status = "disabled"; 703 }; 704 705 u3phy: t-phy@11cc0000 { 706 compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; 707 #address-cells = <1>; 708 #size-cells = <1>; 709 ranges = <0 0 0x11cc0000 0x9000>; 710 711 u2port0: usb-phy@0 { 712 reg = <0x0 0x400>; 713 clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 714 <&topckgen CLK_TOP_USB20_48M_EN>; 715 clock-names = "ref", "da_ref"; 716 #phy-cells = <1>; 717 }; 718 719 u2port1: usb-phy@1000 { 720 reg = <0x1000 0x400>; 721 clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 722 <&topckgen CLK_TOP_USB20_48M_EN>; 723 clock-names = "ref", "da_ref"; 724 #phy-cells = <1>; 725 }; 726 }; 727 728 mmsys: syscon@14000000 { 729 compatible = "mediatek,mt8365-mmsys", "syscon"; 730 reg = <0 0x14000000 0 0x1000>; 731 #clock-cells = <1>; 732 }; 733 734 smi_common: smi@14002000 { 735 compatible = "mediatek,mt8365-smi-common"; 736 reg = <0 0x14002000 0 0x1000>; 737 clocks = <&mmsys CLK_MM_MM_SMI_COMMON>, 738 <&mmsys CLK_MM_MM_SMI_COMMON>, 739 <&mmsys CLK_MM_MM_SMI_COMM0>, 740 <&mmsys CLK_MM_MM_SMI_COMM1>; 741 clock-names = "apb", "smi", "gals0", "gals1"; 742 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 743 }; 744 745 larb0: larb@14003000 { 746 compatible = "mediatek,mt8365-smi-larb", 747 "mediatek,mt8186-smi-larb"; 748 reg = <0 0x14003000 0 0x1000>; 749 mediatek,smi = <&smi_common>; 750 clocks = <&mmsys CLK_MM_MM_SMI_LARB0>, 751 <&mmsys CLK_MM_MM_SMI_LARB0>; 752 clock-names = "apb", "smi"; 753 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 754 mediatek,larb-id = <0>; 755 }; 756 757 camsys: syscon@15000000 { 758 compatible = "mediatek,mt8365-imgsys", "syscon"; 759 reg = <0 0x15000000 0 0x1000>; 760 #clock-cells = <1>; 761 }; 762 763 larb2: larb@15001000 { 764 compatible = "mediatek,mt8365-smi-larb", 765 "mediatek,mt8186-smi-larb"; 766 reg = <0 0x15001000 0 0x1000>; 767 mediatek,smi = <&smi_common>; 768 clocks = <&mmsys CLK_MM_MM_SMI_IMG>, 769 <&camsys CLK_CAM_LARB2>; 770 clock-names = "apb", "smi"; 771 power-domains = <&spm MT8365_POWER_DOMAIN_CAM>; 772 mediatek,larb-id = <2>; 773 }; 774 775 vdecsys: syscon@16000000 { 776 compatible = "mediatek,mt8365-vdecsys", "syscon"; 777 reg = <0 0x16000000 0 0x1000>; 778 #clock-cells = <1>; 779 }; 780 781 larb3: larb@16010000 { 782 compatible = "mediatek,mt8365-smi-larb", 783 "mediatek,mt8186-smi-larb"; 784 reg = <0 0x16010000 0 0x1000>; 785 mediatek,smi = <&smi_common>; 786 clocks = <&vdecsys CLK_VDEC_LARB1>, 787 <&vdecsys CLK_VDEC_LARB1>; 788 clock-names = "apb", "smi"; 789 power-domains = <&spm MT8365_POWER_DOMAIN_VDEC>; 790 mediatek,larb-id = <3>; 791 }; 792 793 vencsys: syscon@17000000 { 794 compatible = "mediatek,mt8365-vencsys", "syscon"; 795 reg = <0 0x17000000 0 0x1000>; 796 #clock-cells = <1>; 797 }; 798 799 larb1: larb@17010000 { 800 compatible = "mediatek,mt8365-smi-larb", 801 "mediatek,mt8186-smi-larb"; 802 reg = <0 0x17010000 0 0x1000>; 803 mediatek,smi = <&smi_common>; 804 clocks = <&vencsys CLK_VENC>, <&vencsys CLK_VENC>; 805 clock-names = "apb", "smi"; 806 power-domains = <&spm MT8365_POWER_DOMAIN_VENC>; 807 mediatek,larb-id = <1>; 808 }; 809 810 apu: syscon@19020000 { 811 compatible = "mediatek,mt8365-apu", "syscon"; 812 reg = <0 0x19020000 0 0x1000>; 813 #clock-cells = <1>; 814 }; 815 }; 816 817 timer { 818 compatible = "arm,armv8-timer"; 819 interrupt-parent = <&gic>; 820 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 821 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 822 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 823 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 824 }; 825 826 system_clk: dummy13m { 827 compatible = "fixed-clock"; 828 clock-frequency = <13000000>; 829 #clock-cells = <0>; 830 }; 831 832 systimer: timer@10017000 { 833 compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer"; 834 reg = <0 0x10017000 0 0x100>; 835 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 836 clocks = <&system_clk>; 837 clock-names = "clk13m"; 838 }; 839}; 840