1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2025, Altera Corporation 4 */ 5#include "socfpga_agilex5.dtsi" 6 7/ { 8 model = "SoCFPGA Agilex5 SoCDK - Modular development kit"; 9 compatible = "intel,socfpga-agilex5-socdk-modular", "intel,socfpga-agilex5"; 10 11 aliases { 12 serial0 = &uart0; 13 ethernet2 = &gmac2; 14 }; 15 16 chosen { 17 stdout-path = "serial0:115200n8"; 18 }; 19 20 leds { 21 compatible = "gpio-leds"; 22 23 led0 { 24 label = "hps_led0"; 25 gpios = <&porta 0x0 GPIO_ACTIVE_HIGH>; 26 linux,default-trigger = "heartbeat"; 27 }; 28 }; 29 30 memory@80000000 { 31 device_type = "memory"; 32 /* We expect the bootloader to fill in the reg */ 33 reg = <0x0 0x80000000 0x0 0x0>; 34 }; 35}; 36 37&gpio0 { 38 status = "okay"; 39}; 40 41&gpio1 { 42 status = "okay"; 43}; 44 45&gmac2 { 46 status = "okay"; 47 phy-mode = "rgmii-id"; 48 phy-handle = <&emac2_phy0>; 49 max-frame-size = <9000>; 50 51 mdio0 { 52 compatible = "snps,dwmac-mdio"; 53 #address-cells = <1>; 54 #size-cells = <0>; 55 56 emac2_phy0: ethernet-phy@0 { 57 reg = <0>; 58 }; 59 }; 60}; 61 62&osc1 { 63 clock-frequency = <25000000>; 64}; 65 66&qspi { 67 status = "okay"; 68 flash@0 { 69 compatible = "micron,mt25qu02g", "jedec,spi-nor"; 70 reg = <0>; 71 spi-max-frequency = <100000000>; 72 m25p,fast-read; 73 cdns,read-delay = <2>; 74 cdns,tshsl-ns = <50>; 75 cdns,tsd2d-ns = <50>; 76 cdns,tchsh-ns = <4>; 77 cdns,tslch-ns = <4>; 78 spi-tx-bus-width = <4>; 79 spi-rx-bus-width = <4>; 80 81 partitions { 82 compatible = "fixed-partitions"; 83 #address-cells = <1>; 84 #size-cells = <1>; 85 86 qspi_boot: partition@0 { 87 label = "u-boot"; 88 reg = <0x0 0x04200000>; 89 }; 90 91 root: partition@4200000 { 92 label = "root"; 93 reg = <0x04200000 0x0be00000>; 94 }; 95 }; 96 }; 97}; 98 99&smmu { 100 status = "okay"; 101}; 102 103&uart0 { 104 status = "okay"; 105}; 106 107&watchdog0 { 108 status = "okay"; 109}; 110