xref: /linux/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi (revision 115e74a29b530d121891238e9551c4bcdf7b04b5) 
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright 2024 NXP
4 *
5 * Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
6 *          Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
7 *          Larisa Grigore <larisa.grigore@nxp.com>
8 */
9
10&pinctrl {
11	can0_pins: can0-pins {
12		can0-grp0 {
13			pinmux = <0x2c1>;
14			output-enable;
15			slew-rate = <133>;
16		};
17
18		can0-grp1 {
19			pinmux = <0x2b0>;
20			input-enable;
21			slew-rate = <133>;
22		};
23
24		can0-grp2 {
25			pinmux = <0x2012>;
26		};
27	};
28
29	can2_pins: can2-pins {
30		can2-grp0 {
31			pinmux = <0x1b2>;
32			output-enable;
33			slew-rate = <133>;
34		};
35
36		can2-grp1 {
37			pinmux = <0x1c0>;
38			input-enable;
39			slew-rate = <133>;
40		};
41
42		can2-grp2 {
43			pinmux = <0x2782>;
44		};
45	};
46
47	can3_pins: can3-pins {
48		can3-grp0 {
49			pinmux = <0x192>;
50			output-enable;
51			slew-rate = <133>;
52		};
53
54		can3-grp1 {
55			pinmux = <0x1a0>;
56			input-enable;
57			slew-rate = <133>;
58		};
59
60		can3-grp2 {
61			pinmux = <0x2792>;
62		};
63	};
64
65	i2c0_pins: i2c0-pins {
66		i2c0-grp0 {
67			pinmux = <0x101>, <0x111>;
68			drive-open-drain;
69			output-enable;
70			input-enable;
71			slew-rate = <133>;
72		};
73
74		i2c0-grp1 {
75			pinmux = <0x2352>, <0x2362>;
76		};
77	};
78
79	i2c0_gpio_pins: i2c0-gpio-pins {
80		i2c0-gpio-grp0 {
81			pinmux = <0x100>, <0x110>;
82			drive-open-drain;
83			output-enable;
84			input-enable;
85			slew-rate = <133>;
86		};
87
88		i2c0-gpio-grp1 {
89			pinmux = <0x2350>, <0x2360>;
90		};
91	};
92
93	i2c1_pins: i2c1-pins {
94		i2c1-grp0 {
95			pinmux = <0x131>, <0x141>;
96			drive-open-drain;
97			output-enable;
98			input-enable;
99			slew-rate = <133>;
100		};
101
102		i2c1-grp1 {
103			pinmux = <0x2cd2>, <0x2ce2>;
104		};
105	};
106
107	i2c1_gpio_pins: i2c1-gpio-pins {
108		i2c1-gpio-grp0 {
109			pinmux = <0x130>, <0x140>;
110			drive-open-drain;
111			output-enable;
112			input-enable;
113			slew-rate = <133>;
114		};
115
116		i2c1-gpio-grp1 {
117			pinmux = <0x2cd0>, <0x2ce0>;
118		};
119	};
120
121	i2c2_pins: i2c2-pins {
122		i2c2-grp0 {
123			pinmux = <0x151>, <0x161>;
124			drive-open-drain;
125			output-enable;
126			input-enable;
127			slew-rate = <133>;
128		};
129
130		i2c2-grp1 {
131			pinmux = <0x2cf2>, <0x2d02>;
132		};
133	};
134
135	i2c2_gpio_pins: i2c2-gpio-pins {
136		i2c2-gpio-grp0 {
137			pinmux = <0x150>, <0x160>;
138			drive-open-drain;
139			output-enable;
140			input-enable;
141			slew-rate = <133>;
142		};
143
144		i2c2-gpio-grp1 {
145			pinmux = <0x2cf0>, <0x2d00>;
146		};
147	};
148
149	i2c4_pins: i2c4-pins {
150		i2c4-grp0 {
151			pinmux = <0x211>, <0x222>;
152			drive-open-drain;
153			output-enable;
154			input-enable;
155			slew-rate = <133>;
156		};
157
158		i2c4-grp1 {
159			pinmux = <0x2d43>, <0x2d33>;
160		};
161	};
162
163	i2c4_gpio_pins: i2c4-gpio-pins {
164		i2c4-gpio-grp0 {
165			pinmux = <0x210>, <0x220>;
166			drive-open-drain;
167			output-enable;
168			input-enable;
169			slew-rate = <133>;
170		};
171
172		i2c4-gpio-grp1 {
173			pinmux = <0x2d40>, <0x2d30>;
174		};
175	};
176
177	dspi1_pins: dspi1-pins {
178		dspi1-grp0 {
179			pinmux = <0x72>;
180			output-enable;
181			input-enable;
182			slew-rate = <150>;
183			bias-pull-up;
184		};
185
186		dspi1-grp1 {
187			pinmux = <0x62>;
188			output-enable;
189			slew-rate = <150>;
190		};
191
192		dspi1-grp2 {
193			pinmux = <0x83>;
194			output-enable;
195			input-enable;
196			slew-rate = <150>;
197		};
198
199		dspi1-grp3 {
200			pinmux = <0x5F0>;
201			input-enable;
202			slew-rate = <150>;
203			bias-pull-up;
204		};
205
206		dspi1-grp4 {
207			pinmux = <0x3D92>,
208				 <0x3DA2>,
209				 <0x3DB2>;
210		};
211	};
212
213	dspi5_pins: dspi5-pins {
214		dspi5-grp0 {
215			pinmux = <0x93>;
216			output-enable;
217			input-enable;
218			slew-rate = <150>;
219		};
220
221		dspi5-grp1 {
222			pinmux = <0xA0>;
223			input-enable;
224			slew-rate = <150>;
225			bias-pull-up;
226		};
227
228		dspi5-grp2 {
229			pinmux = <0x3ED2>,
230				 <0x3EE2>,
231				 <0x3EF2>;
232		};
233
234		dspi5-grp3 {
235			pinmux = <0xB3>;
236			output-enable;
237			slew-rate = <150>;
238		};
239
240		dspi5-grp4 {
241			pinmux = <0xC3>;
242			output-enable;
243			input-enable;
244			slew-rate = <150>;
245			bias-pull-up;
246		};
247	};
248};
249
250&can0 {
251	pinctrl-names = "default";
252	pinctrl-0 = <&can0_pins>;
253	status = "okay";
254};
255
256&can2 {
257	pinctrl-names = "default";
258	pinctrl-0 = <&can2_pins>;
259	status = "okay";
260};
261
262&can3 {
263	pinctrl-names = "default";
264	pinctrl-0 = <&can3_pins>;
265	status = "okay";
266};
267
268&i2c0 {
269	pinctrl-names = "default", "gpio";
270	pinctrl-0 = <&i2c0_pins>;
271	pinctrl-1 = <&i2c0_gpio_pins>;
272	status = "okay";
273};
274
275&i2c1 {
276	pinctrl-names = "default", "gpio";
277	pinctrl-0 = <&i2c1_pins>;
278	pinctrl-1 = <&i2c1_gpio_pins>;
279	status = "okay";
280};
281
282&i2c2 {
283	pinctrl-names = "default", "gpio";
284	pinctrl-0 = <&i2c2_pins>;
285	pinctrl-1 = <&i2c2_gpio_pins>;
286	status = "okay";
287};
288
289&i2c4 {
290	pinctrl-names = "default", "gpio";
291	pinctrl-0 = <&i2c4_pins>;
292	pinctrl-1 = <&i2c4_gpio_pins>;
293	status = "okay";
294};
295
296&spi1 {
297	pinctrl-0 = <&dspi1_pins>;
298	pinctrl-names = "default";
299	status = "okay";
300};
301
302&spi5 {
303	pinctrl-0 = <&dspi5_pins>;
304	pinctrl-names = "default";
305	status = "okay";
306};
307