1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Common dtsi for Variscite DART-MX95 4 * 5 * Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-95/dart-mx95/ 6 * 7 * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ 8 * 9 */ 10 11/dts-v1/; 12 13#include <dt-bindings/leds/common.h> 14#include <dt-bindings/usb/pd.h> 15#include "imx95.dtsi" 16 17/ { 18 model = "Variscite DART-MX95 Module"; 19 compatible = "variscite,var-dart-mx95", "fsl,imx95"; 20 21 memory@80000000 { 22 device_type = "memory"; 23 reg = <0x0 0x80000000 0 0x80000000>; 24 }; 25 26 reg_1p8v: regulator-1p8v { 27 compatible = "regulator-fixed"; 28 regulator-max-microvolt = <1800000>; 29 regulator-min-microvolt = <1800000>; 30 regulator-name = "+V1.8_SW"; 31 }; 32 33 reg_3p3v: regulator-3p3v { 34 compatible = "regulator-fixed"; 35 regulator-max-microvolt = <3300000>; 36 regulator-min-microvolt = <3300000>; 37 regulator-name = "+V3.3_SW"; 38 }; 39 40 reg_vref_1v8: regulator-adc-vref { 41 compatible = "regulator-fixed"; 42 regulator-name = "vref_1v8"; 43 regulator-min-microvolt = <1800000>; 44 regulator-max-microvolt = <1800000>; 45 }; 46 47 reg_audio: regulator-audio-vdd { 48 compatible = "regulator-fixed"; 49 regulator-name = "wm8904_supply"; 50 regulator-min-microvolt = <3300000>; 51 regulator-max-microvolt = <3300000>; 52 }; 53 54 reserved-memory { 55 ranges; 56 #address-cells = <2>; 57 #size-cells = <2>; 58 59 linux_cma: linux,cma { 60 compatible = "shared-dma-pool"; 61 alloc-ranges = <0 0x80000000 0 0x7F000000>; 62 reusable; 63 size = <0 0x3c000000>; 64 linux,cma-default; 65 }; 66 }; 67 68 sound-wm8904 { 69 compatible = "simple-audio-card"; 70 simple-audio-card,bitclock-master = <&codec_dai>; 71 simple-audio-card,format = "i2s"; 72 simple-audio-card,frame-master = <&codec_dai>; 73 simple-audio-card,mclk-fs = <256>; 74 simple-audio-card,name = "wm8904-audio"; 75 simple-audio-card,routing = 76 "Headphone Jack", "HPOUTL", 77 "Headphone Jack", "HPOUTR", 78 "IN2L", "Line In Jack", 79 "IN2R", "Line In Jack", 80 "IN1L", "Microphone Jack", 81 "IN1R", "Microphone Jack"; 82 simple-audio-card,widgets = 83 "Microphone", "Microphone Jack", 84 "Headphone", "Headphone Jack", 85 "Line", "Line In Jack"; 86 87 codec_dai: simple-audio-card,codec { 88 sound-dai = <&wm8904>; 89 }; 90 91 simple-audio-card,cpu { 92 sound-dai = <&sai3>; 93 }; 94 }; 95 96 wifi_pwrseq: wifi-pwrseq { 97 compatible = "mmc-pwrseq-simple"; 98 post-power-on-delay-ms = <100>; 99 power-off-delay-us = <10000>; 100 reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ 101 <&gpio2 27 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ 102 }; 103}; 104 105&adc1 { 106 vref-supply = <®_vref_1v8>; 107 status = "okay"; 108}; 109 110&enetc_port0 { 111 pinctrl-names = "default"; 112 pinctrl-0 = <&pinctrl_enetc0>; 113 phy-handle = <ðphy0>; 114 /* 115 * The required RGMII TX and RX 2ns delays are implemented directly 116 * in hardware via passive delay elements on the SOM PCB. 117 * No delay configuration is needed in software via PHY driver. 118 */ 119 phy-mode = "rgmii"; 120 status = "okay"; 121}; 122 123&lpi2c8 { 124 clock-frequency = <400000>; 125 pinctrl-names = "default","gpio","sleep"; 126 pinctrl-0 = <&pinctrl_lpi2c8>; 127 pinctrl-1 = <&pinctrl_lpi2c8_gpio>; 128 pinctrl-2 = <&pinctrl_lpi2c8_gpio>; 129 scl-gpios = <&gpio2 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 130 sda-gpios = <&gpio2 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 131 status = "okay"; 132 133 wm8904: audio-codec@1a { 134 compatible = "wlf,wm8904"; 135 reg = <0x1a>; 136 #sound-dai-cells = <0>; 137 clocks = <&scmi_clk IMX95_CLK_SAI3>; 138 clock-names = "mclk"; 139 AVDD-supply = <®_audio>; 140 CPVDD-supply = <®_audio>; 141 DBVDD-supply = <®_audio>; 142 DCVDD-supply = <®_audio>; 143 MICVDD-supply = <®_audio>; 144 wlf,drc-cfg-names = "default", "peaklimiter", "tradition", 145 "soft", "music"; 146 /* 147 * Config registers per name, respectively: 148 * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 149 * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 150 * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 151 * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 152 * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 153 */ 154 wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, 155 /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, 156 /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, 157 /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, 158 /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; 159 /* GPIO1 = DMIC_CLK, don't touch others */ 160 wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; 161 }; 162}; 163 164/* BT */ 165&lpuart5 { 166 pinctrl-names = "default"; 167 pinctrl-0 = <&pinctrl_uart5>, <&pinctrl_bt>; 168 status = "okay"; 169 170 bluetooth { 171 compatible = "nxp,88w8987-bt"; 172 }; 173}; 174 175&mu7 { 176 status = "okay"; 177}; 178 179&netc_emdio { 180 pinctrl-names = "default"; 181 pinctrl-0 = <&pinctrl_emdio>, <&pinctrl_phy0res>; 182 status = "okay"; 183 184 ethphy0: ethernet-phy@0 { 185 compatible = "ethernet-phy-ieee802.3-c22"; 186 reg = <0>; 187 reset-gpios = <&gpio5 16 GPIO_ACTIVE_LOW>; 188 reset-assert-us = <10000>; 189 reset-deassert-us = <100000>; 190 191 leds { 192 #address-cells = <1>; 193 #size-cells = <0>; 194 195 led@0 { 196 reg = <0>; 197 color = <LED_COLOR_ID_YELLOW>; 198 function = LED_FUNCTION_LAN; 199 linux,default-trigger = "netdev"; 200 }; 201 202 led@1 { 203 reg = <1>; 204 color = <LED_COLOR_ID_GREEN>; 205 function = LED_FUNCTION_LAN; 206 linux,default-trigger = "netdev"; 207 }; 208 }; 209 }; 210}; 211 212&netc_timer { 213 status = "okay"; 214}; 215 216&sai3 { 217 pinctrl-names = "default"; 218 pinctrl-0 = <&pinctrl_sai3>; 219 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 220 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 221 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 222 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 223 <&scmi_clk IMX95_CLK_SAI3>; 224 assigned-clock-parents = <0>, <0>, <0>, <0>, 225 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 226 assigned-clock-rates = <3932160000>, 227 <3612672000>, <393216000>, 228 <361267200>, <12288000>; 229 #sound-dai-cells = <0>; 230 fsl,sai-mclk-direction-output; 231 status = "okay"; 232}; 233 234/* eMMC */ 235&usdhc1 { 236 pinctrl-names = "default","state_100mhz","state_200mhz","sleep"; 237 pinctrl-0 = <&pinctrl_usdhc1>; 238 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 239 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 240 pinctrl-3 = <&pinctrl_usdhc1>; 241 bus-width = <8>; 242 non-removable; 243 no-sdio; 244 no-sd; 245 status = "okay"; 246}; 247 248/* WiFi */ 249&usdhc3 { 250 pinctrl-names = "default","state_100mhz","state_200mhz","sleep"; 251 pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>; 252 pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>; 253 pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>; 254 pinctrl-3 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>; 255 mmc-pwrseq = <&wifi_pwrseq>; 256 bus-width = <4>; 257 non-removable; 258 wakeup-source; 259 keep-power-in-suspend; 260 status = "okay"; 261}; 262 263&wdog3 { 264 fsl,ext-reset-output; 265 status = "okay"; 266}; 267 268&scmi_iomuxc { 269 pinctrl_bt: btgrp { 270 fsl,pins = < 271 IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x31e 272 >; 273 }; 274 275 pinctrl_emdio: emdiogrp { 276 fsl,pins = < 277 IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x57e 278 IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e 279 >; 280 }; 281 282 pinctrl_enetc0: enetc0grp { 283 fsl,pins = < 284 IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e 285 IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e 286 IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e 287 IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e 288 IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e 289 IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e 290 IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e 291 IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e 292 IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e 293 IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e 294 IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e 295 IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e 296 >; 297 }; 298 299 pinctrl_lpi2c8: lpi2c8grp { 300 fsl,pins = < 301 IMX95_PAD_GPIO_IO10__LPI2C8_SDA 0x40000b9e 302 IMX95_PAD_GPIO_IO11__LPI2C8_SCL 0x40000b9e 303 >; 304 }; 305 306 pinctrl_lpi2c8_gpio: lpi2c8gpiogrp { 307 fsl,pins = < 308 IMX95_PAD_GPIO_IO10__GPIO2_IO_BIT10 0x31e 309 IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x31e 310 >; 311 }; 312 313 pinctrl_phy0res: phy0resgrp { 314 fsl,pins = < 315 IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x31e 316 >; 317 }; 318 319 pinctrl_sai3: sai3grp { 320 fsl,pins = < 321 IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e 322 IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e 323 IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e 324 IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e 325 IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x31e 326 >; 327 }; 328 329 pinctrl_uart5: uart5grp { 330 fsl,pins = < 331 IMX95_PAD_GPIO_IO00__LPUART5_TX 0x31e 332 IMX95_PAD_GPIO_IO01__LPUART5_RX 0x31e 333 IMX95_PAD_GPIO_IO02__LPUART5_CTS_B 0x31e 334 IMX95_PAD_GPIO_IO03__LPUART5_RTS_B 0x31e 335 >; 336 }; 337 338 pinctrl_usdhc1: usdhc1grp { 339 fsl,pins = < 340 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e 341 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e 342 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 343 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 344 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 345 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 346 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 347 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 348 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 349 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 350 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 351 >; 352 }; 353 354 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 355 fsl,pins = < 356 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e 357 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e 358 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 359 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 360 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 361 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 362 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 363 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 364 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 365 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 366 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 367 >; 368 }; 369 370 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 371 fsl,pins = < 372 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe 373 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe 374 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 375 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 376 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 377 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 378 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 379 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 380 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 381 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 382 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 383 >; 384 }; 385 386 pinctrl_usdhc3_gpio: usdhc3gpiogrp { 387 fsl,pins = < 388 IMX95_PAD_GPIO_IO27__GPIO2_IO_BIT27 0x31e 389 IMX95_PAD_CCM_CLKO4__GPIO4_IO_BIT29 0x31e 390 >; 391 }; 392 393 pinctrl_usdhc3: usdhc3grp { 394 fsl,pins = < 395 IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e 396 IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e 397 IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e 398 IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e 399 IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e 400 IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e 401 >; 402 }; 403 404 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 405 fsl,pins = < 406 IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e 407 IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e 408 IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e 409 IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e 410 IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e 411 IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e 412 >; 413 }; 414 415 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 416 fsl,pins = < 417 IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe 418 IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe 419 IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe 420 IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe 421 IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe 422 IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe 423 >; 424 }; 425}; 426