1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Variscite Sonata carrier board for DART-MX95 4 * 5 * Link: https://variscite.com/carrier-boards/sonata-board/ 6 * 7 * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ 8 * 9 */ 10 11#include "imx95-var-dart.dtsi" 12 13/ { 14 model = "Variscite DART-MX95 on Sonata-Board"; 15 compatible = "variscite,var-dart-mx95-sonata", 16 "variscite,var-dart-mx95", 17 "fsl,imx95"; 18 19 aliases { 20 ethernet0 = &enetc_port0; 21 ethernet1 = &enetc_port1; 22 ethernet2 = &enetc_port2; 23 mmc0 = &usdhc1; 24 mmc1 = &usdhc2; 25 serial0 = &lpuart1; 26 }; 27 28 chosen { 29 stdout-path = &lpuart1; 30 }; 31 32 clk_osc_can0: clock-osc-40m { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <40000000>; 36 }; 37 38 typec_con: connector { 39 compatible = "usb-c-connector"; 40 data-role = "dual"; 41 label = "USB-C"; 42 op-sink-microwatt = <0>; 43 power-role = "dual"; 44 self-powered; 45 sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>; 46 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 47 try-power-role = "sink"; 48 49 ports { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 port@0 { 54 reg = <0>; 55 56 typec_con_hs: endpoint { 57 remote-endpoint = <&usb3_data_hs>; 58 }; 59 }; 60 61 port@1 { 62 reg = <1>; 63 64 typec_con_ss: endpoint { 65 remote-endpoint = <&usb3_data_ss>; 66 }; 67 }; 68 }; 69 }; 70 71 gpio-keys { 72 compatible = "gpio-keys"; 73 74 button-back { 75 gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>; 76 label = "Back"; 77 wakeup-source; 78 linux,code = <KEY_BACK>; 79 }; 80 81 button-down { 82 gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>; 83 label = "Down"; 84 wakeup-source; 85 linux,code = <KEY_DOWN>; 86 }; 87 88 button-home { 89 gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>; 90 label = "Home"; 91 wakeup-source; 92 linux,code = <KEY_HOME>; 93 }; 94 95 button-up { 96 gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>; 97 label = "Up"; 98 wakeup-source; 99 linux,code = <KEY_UP>; 100 }; 101 }; 102 103 gpio-leds { 104 compatible = "gpio-leds"; 105 pinctrl-names = "default"; 106 pinctrl-0 = <&pinctrl_gpio_leds>; 107 108 led-heartbeat { 109 label = "Heartbeat"; 110 gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; 111 linux,default-trigger = "heartbeat"; 112 }; 113 }; 114 115 reg_phy1_supply: regulator-phy1 { 116 compatible = "regulator-fixed"; 117 regulator-name = "SUPPLY_PHY1"; 118 regulator-min-microvolt = <3300000>; 119 regulator-max-microvolt = <3300000>; 120 gpio = <&pca6408_2 0 GPIO_ACTIVE_HIGH>; 121 enable-active-high; 122 startup-delay-us = <10000>; 123 regulator-always-on; 124 }; 125 126 reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { 127 compatible = "regulator-fixed"; 128 pinctrl-names = "default"; 129 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 130 regulator-name = "VDD_SD2_3V3"; 131 regulator-min-microvolt = <3300000>; 132 regulator-max-microvolt = <3300000>; 133 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 134 enable-active-high; 135 off-on-delay-us = <12000>; 136 }; 137 138 sfp0: sfp { 139 compatible = "sff,sfp"; 140 i2c-bus = <&lpi2c3>; 141 los-gpios = <&pca9534 1 GPIO_ACTIVE_HIGH>; 142 maximum-power-milliwatt = <2000>; 143 }; 144}; 145 146&enetc_port1 { 147 pinctrl-names = "default"; 148 pinctrl-0 = <&pinctrl_enetc1>; 149 phy-handle = <ðphy1>; 150 /* 151 * The required RGMII TX and RX 2ns delays are implemented directly 152 * in hardware via passive delay elements on the SOM PCB. 153 * No delay configuration is needed in software via PHY driver. 154 */ 155 phy-mode = "rgmii"; 156 status = "okay"; 157}; 158 159&enetc_port2 { 160 phy-mode = "10gbase-r"; 161 sfp = <&sfp0>; 162 status = "okay"; 163}; 164 165&flexcan1 { 166 pinctrl-names = "default"; 167 pinctrl-0 = <&pinctrl_flexcan1>; 168 status = "okay"; 169}; 170 171&lpi2c3 { 172 clock-frequency = <400000>; 173 pinctrl-names = "default", "gpio", "sleep"; 174 pinctrl-0 = <&pinctrl_lpi2c3>; 175 pinctrl-1 = <&pinctrl_lpi2c3_gpio>; 176 pinctrl-2 = <&pinctrl_lpi2c3_gpio>; 177 scl-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 178 sda-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 179 status = "okay"; 180 181 pca9534: gpio@22 { 182 compatible = "nxp,pca9534"; 183 reg = <0x22>; 184 gpio-controller; 185 #gpio-cells = <2>; 186 interrupt-parent = <&gpio5>; 187 interrupts = <17 IRQ_TYPE_LEVEL_LOW>; 188 189 pcie2-sel-hog { 190 gpio-hog; 191 gpios = <6 GPIO_ACTIVE_HIGH>; 192 output-low; 193 line-name = "pcie-clk-sw"; 194 }; 195 196 sfp-sel-hog { 197 gpio-hog; 198 gpios = <5 GPIO_ACTIVE_HIGH>; 199 output-high; 200 line-name = "sfp-sw"; 201 }; 202 }; 203 204 /* Capacitive touch controller */ 205 ft5x06_ts: touchscreen@38 { 206 compatible = "edt,edt-ft5206"; 207 reg = <0x38>; 208 pinctrl-names = "default"; 209 pinctrl-0 = <&pinctrl_captouch>; 210 reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>; 211 interrupt-parent = <&gpio5>; 212 interrupts = <13 IRQ_TYPE_EDGE_FALLING>; 213 touchscreen-size-x = <800>; 214 touchscreen-size-y = <480>; 215 touchscreen-inverted-x; 216 touchscreen-inverted-y; 217 wakeup-source; 218 }; 219 220 typec@3d { 221 compatible = "nxp,ptn5150"; 222 reg = <0x3d>; 223 pinctrl-names = "default"; 224 pinctrl-0 = <&pinctrl_ptn5150>; 225 interrupt-parent = <&gpio5>; 226 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; 227 228 port { 229 typec_dr_sw: endpoint { 230 remote-endpoint = <&usb3_drd_sw>; 231 }; 232 }; 233 }; 234 235 /* DS1337 RTC module */ 236 rtc@68 { 237 compatible = "dallas,ds1337"; 238 reg = <0x68>; 239 pinctrl-names = "default"; 240 pinctrl-0 = <&pinctrl_rtc>; 241 interrupt-parent = <&gpio5>; 242 interrupts = <12 IRQ_TYPE_EDGE_FALLING>; 243 wakeup-source; 244 }; 245}; 246 247&lpi2c4 { 248 clock-frequency = <400000>; 249 pinctrl-names = "default", "sleep"; 250 pinctrl-0 = <&pinctrl_lpi2c4>; 251 pinctrl-1 = <&pinctrl_lpi2c4>; 252 status = "okay"; 253}; 254 255&lpi2c8 { 256 pca6408_1: gpio@20 { 257 compatible = "nxp,pcal6408"; 258 reg = <0x20>; 259 gpio-controller; 260 #gpio-cells = <2>; 261 interrupt-parent = <&gpio5>; 262 interrupts = <17 IRQ_TYPE_LEVEL_LOW>; 263 }; 264 265 pca6408_2: gpio@21 { 266 compatible = "nxp,pcal6408"; 267 reg = <0x21>; 268 gpio-controller; 269 #gpio-cells = <2>; 270 interrupt-parent = <&gpio5>; 271 interrupts = <17 IRQ_TYPE_LEVEL_LOW>; 272 }; 273 274 st33ktpm2xi2c: tpm@2e { 275 compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; 276 reg = <0x2e>; 277 }; 278}; 279 280&lpspi7 { 281 pinctrl-names = "default"; 282 pinctrl-0 = <&pinctrl_lpspi7>; 283 cs-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; 284 status = "okay"; 285 286 /* Resistive touch controller */ 287 ads7846: touchscreen@0 { 288 compatible = "ti,ads7846"; 289 reg = <0>; 290 pinctrl-names = "default"; 291 pinctrl-0 = <&pinctrl_restouch>; 292 interrupt-parent = <&gpio2>; 293 interrupts = <24 IRQ_TYPE_EDGE_FALLING>; 294 pendown-gpio = <&gpio2 24 GPIO_ACTIVE_LOW>; 295 spi-max-frequency = <1500000>; 296 wakeup-source; 297 ti,x-min = /bits/ 16 <125>; 298 ti,x-max = /bits/ 16 <4008>; 299 ti,y-min = /bits/ 16 <282>; 300 ti,y-max = /bits/ 16 <3864>; 301 ti,x-plate-ohms = /bits/ 16 <180>; 302 ti,pressure-max = /bits/ 16 <255>; 303 ti,debounce-max = /bits/ 16 <10>; 304 ti,debounce-tol = /bits/ 16 <3>; 305 ti,debounce-rep = /bits/ 16 <1>; 306 ti,settle-delay-usec = /bits/ 16 <150>; 307 ti,keep-vref-on; 308 }; 309}; 310 311/* Console */ 312&lpuart1 { 313 pinctrl-names = "default"; 314 pinctrl-0 = <&pinctrl_uart1>; 315 status = "okay"; 316}; 317 318/* Header (J12.4, J12.6) */ 319&lpuart8 { 320 pinctrl-names = "default"; 321 pinctrl-0 = <&pinctrl_uart8>; 322 status = "okay"; 323}; 324 325&netc_emdio { 326 ethphy1: ethernet-phy@1 { 327 compatible = "ethernet-phy-ieee802.3-c22"; 328 reg = <1>; 329 reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; 330 reset-assert-us = <10000>; 331 reset-deassert-us = <100000>; 332 333 leds { 334 #address-cells = <1>; 335 #size-cells = <0>; 336 337 led@0 { 338 reg = <0>; 339 color = <LED_COLOR_ID_YELLOW>; 340 function = LED_FUNCTION_LAN; 341 linux,default-trigger = "netdev"; 342 }; 343 344 led@1 { 345 reg = <1>; 346 color = <LED_COLOR_ID_GREEN>; 347 function = LED_FUNCTION_LAN; 348 linux,default-trigger = "netdev"; 349 }; 350 }; 351 }; 352}; 353 354&pcie0 { 355 reset-gpio = <&pca6408_2 3 GPIO_ACTIVE_LOW>; 356 status = "okay"; 357}; 358 359&pcie1 { 360 reset-gpio = <&pca6408_2 2 GPIO_ACTIVE_LOW>; 361 status = "okay"; 362}; 363 364&usb2 { 365 dr_mode = "host"; 366 adp-disable; 367 hnp-disable; 368 srp-disable; 369 disable-over-current; 370 status = "okay"; 371}; 372 373&usb3 { 374 status = "okay"; 375}; 376 377&usb3_dwc3 { 378 dr_mode = "otg"; 379 hnp-disable; 380 srp-disable; 381 adp-disable; 382 usb-role-switch; 383 snps,dis-u1-entry-quirk; 384 snps,dis-u2-entry-quirk; 385 status = "okay"; 386 387 port { 388 usb3_drd_sw: endpoint { 389 remote-endpoint = <&typec_dr_sw>; 390 }; 391 }; 392 393 ports { 394 #address-cells = <1>; 395 #size-cells = <0>; 396 397 port@0 { 398 reg = <0>; 399 400 usb3_data_hs: endpoint { 401 remote-endpoint = <&typec_con_hs>; 402 }; 403 }; 404 405 port@1 { 406 reg = <1>; 407 usb3_data_ss: endpoint { 408 remote-endpoint = <&typec_con_ss>; 409 }; 410 }; 411 }; 412}; 413 414&usb3_phy { 415 fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <17>; 416 fsl,phy-pcs-tx-swing-full-percent = <100>; 417 fsl,phy-tx-preemp-amp-tune-microamp = <600>; 418 fsl,phy-tx-vboost-level-microvolt = <1156>; 419 status = "okay"; 420}; 421 422&usdhc2 { 423 pinctrl-names = "default","state_100mhz","state_200mhz","sleep"; 424 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 425 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 426 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 427 pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 428 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 429 vmmc-supply = <®_usdhc2_vmmc>; 430 bus-width = <4>; 431 status = "okay"; 432}; 433 434&scmi_iomuxc { 435 pinctrl-names = "default"; 436 pinctrl-0 = <&pinctrl_hog>; 437 438 pinctrl_hog: hoggrp { 439 fsl,pins = < 440 /* GPIO Expanders shared IRQ */ 441 IMX95_PAD_GPIO_IO37__GPIO5_IO_BIT17 0x31e 442 >; 443 }; 444 445 pinctrl_captouch: captouchgrp { 446 fsl,pins = < 447 IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x31e 448 >; 449 }; 450 451 pinctrl_enetc1: enetc1grp { 452 fsl,pins = < 453 IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x57e 454 IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e 455 IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x57e 456 IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x57e 457 IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x57e 458 IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x57e 459 IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x57e 460 IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e 461 IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e 462 IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e 463 IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e 464 IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x37e 465 >; 466 }; 467 468 pinctrl_flexcan1: flexcan1grp { 469 fsl,pins = < 470 IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e 471 IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e 472 >; 473 }; 474 475 pinctrl_gpio_leds: ledgrp { 476 fsl,pins = < 477 IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x31e 478 >; 479 }; 480 481 pinctrl_lpi2c3: lpi2c3grp { 482 fsl,pins = < 483 IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 484 IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 485 >; 486 }; 487 488 pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { 489 fsl,pins = < 490 IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x31e 491 IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x31e 492 >; 493 }; 494 495 pinctrl_lpi2c4: lpi2c4grp { 496 fsl,pins = < 497 IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e 498 IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e 499 >; 500 }; 501 502 pinctrl_lpspi7: lpspi7grp { 503 fsl,pins = < 504 /* j16.4 ADS7846 */ 505 IMX95_PAD_GPIO_IO04__GPIO2_IO_BIT4 0x3fe 506 /* j14.4 MCP2518FDT */ 507 IMX95_PAD_UART2_TXD__AONMIX_TOP_GPIO1_IO_BIT7 0x3fe 508 /* j25.2 spidev */ 509 IMX95_PAD_XSPI1_DATA4__GPIO5_IO_BIT4 0x3fe 510 IMX95_PAD_GPIO_IO05__LPSPI7_SIN 0x3fe 511 IMX95_PAD_GPIO_IO06__LPSPI7_SOUT 0x3fe 512 IMX95_PAD_GPIO_IO07__LPSPI7_SCK 0x3fe 513 >; 514 }; 515 516 pinctrl_ptn5150: ptn5150grp { 517 fsl,pins = < 518 IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e 519 >; 520 }; 521 522 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 523 fsl,pins = < 524 IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e 525 >; 526 }; 527 528 pinctrl_restouch: restouchgrp { 529 fsl,pins = < 530 IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24 0x31e 531 >; 532 }; 533 534 pinctrl_rtc: rtcgrp { 535 fsl,pins = < 536 IMX95_PAD_GPIO_IO32__GPIO5_IO_BIT12 0x31e 537 >; 538 }; 539 540 pinctrl_uart1: uart1grp { 541 fsl,pins = < 542 IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e 543 IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e 544 >; 545 }; 546 547 pinctrl_uart8: uart8grp { 548 fsl,pins = < 549 IMX95_PAD_GPIO_IO13__LPUART8_RX 0x31e 550 IMX95_PAD_GPIO_IO12__LPUART8_TX 0x31e 551 >; 552 }; 553 554 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 555 fsl,pins = < 556 IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e 557 >; 558 }; 559 560 pinctrl_usdhc2: usdhc2grp { 561 fsl,pins = < 562 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e 563 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e 564 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 565 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 566 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 567 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 568 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 569 >; 570 }; 571 572 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 573 fsl,pins = < 574 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e 575 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e 576 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 577 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 578 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 579 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 580 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 581 >; 582 }; 583 584 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 585 fsl,pins = < 586 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe 587 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe 588 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe 589 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe 590 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe 591 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe 592 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 593 >; 594 }; 595}; 596