xref: /linux/arch/arm64/boot/dts/freescale/imx95-tqma9596la.dtsi (revision cbe8aadf1551f3f4a853f24b3b96d9f0eea49c53) 
1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2/*
3 * Copyright (c) 2024-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
5 * Author: Alexander Stein
6 * Author: Markus Niebel
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/gpio/gpio.h>
12#include "imx95.dtsi"
13
14/ {
15	memory@80000000 {
16		device_type = "memory";
17		/*
18		 * DRAM base addr, size : 2048 MiB DRAM
19		 * should be corrected by bootloader
20		 */
21		reg = <0 0x80000000 0 0x80000000>;
22	};
23
24	reg_1v8: regulator-1v8 {
25		compatible = "regulator-fixed";
26		regulator-name = "V_1V8";
27		regulator-min-microvolt = <1800000>;
28		regulator-max-microvolt = <1800000>;
29		regulator-always-on;
30	};
31
32	reg_3v3: regulator-3v3 {
33		compatible = "regulator-fixed";
34		regulator-name = "V_3V3";
35		regulator-min-microvolt = <3300000>;
36		regulator-max-microvolt = <3300000>;
37		regulator-always-on;
38	};
39
40	reg_sdvmmc: regulator-sdvmmc {
41		compatible = "regulator-fixed";
42		pinctrl-names = "default";
43		pinctrl-0 = <&pinctrl_sdvmmc>;
44		regulator-name = "SD_PWR_EN";
45		regulator-min-microvolt = <3300000>;
46		regulator-max-microvolt = <3300000>;
47		gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
48		off-on-delay-us = <12000>;
49		enable-active-high;
50		/* can be enabled by mainboard with SD-Card support */
51		status = "disabled";
52	};
53};
54
55&adc1 {
56	vref-supply = <&reg_1v8>;
57};
58
59&flexspi1 {
60	pinctrl-names = "default";
61	pinctrl-0 = <&pinctrl_flexspi1>;
62	status = "okay";
63
64	flash0: flash@0 {
65		compatible = "jedec,spi-nor";
66		reg = <0>;
67		spi-max-frequency = <66000000>;
68		spi-tx-bus-width = <4>;
69		spi-rx-bus-width = <4>;
70		vcc-supply = <&reg_1v8>;
71
72		partitions {
73			compatible = "fixed-partitions";
74			#address-cells = <1>;
75			#size-cells = <1>;
76		};
77	};
78};
79
80/* System Manager */
81&gpio1 {
82	status = "reserved";
83};
84
85/* System Manager */
86&lpi2c1 {
87	status = "reserved";
88};
89
90&lpi2c2 {
91	clock-frequency = <400000>;
92	pinctrl-names = "default";
93	pinctrl-0 = <&pinctrl_lpi2c2>;
94	status = "okay";
95
96	pcf85063: rtc@51 {
97		compatible = "nxp,pcf85063a";
98		reg = <0x51>;
99		quartz-load-femtofarads = <7000>;
100	};
101
102	m24c64: eeprom@54 {
103		compatible = "atmel,24c64";
104		reg = <0x54>;
105		pagesize = <32>;
106		vcc-supply = <&reg_3v3>;
107	};
108
109	/* protectable identification memory (part of M24C64-D @54) */
110	eeprom@5c {
111		compatible = "atmel,24c64d-wl";
112		reg = <0x5c>;
113		pagesize = <32>;
114		vcc-supply = <&reg_3v3>;
115	};
116
117	imu@6b {
118		compatible = "st,ism330dhcx";
119		reg = <0x6b>;
120		vdd-supply = <&reg_3v3>;
121		vddio-supply = <&reg_3v3>;
122	};
123};
124
125&thermal_zones {
126	pf09-thermal {
127		polling-delay = <2000>;
128		polling-delay-passive = <250>;
129		thermal-sensors = <&scmi_sensor 2>;
130
131		trips {
132			pf09_alert: trip0 {
133				hysteresis = <2000>;
134				temperature = <140000>;
135				type = "passive";
136			};
137
138			pf09_crit: trip1 {
139				hysteresis = <2000>;
140				temperature = <155000>;
141				type = "critical";
142			};
143		};
144	};
145
146	pf53arm-thermal {
147		polling-delay = <2000>;
148		polling-delay-passive = <250>;
149		thermal-sensors = <&scmi_sensor 4>;
150
151		cooling-maps {
152			map0 {
153				trip = <&pf5301_alert>;
154				cooling-device =
155					<&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
156					<&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
157					<&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
158					<&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
159					<&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
160					<&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
161			};
162		};
163
164		trips {
165			pf5301_alert: trip0 {
166				hysteresis = <2000>;
167				temperature = <140000>;
168				type = "passive";
169			};
170
171			pf5301_crit: trip1 {
172				hysteresis = <2000>;
173				temperature = <155000>;
174				type = "critical";
175			};
176		};
177	};
178
179	pf53soc-thermal {
180		polling-delay = <2000>;
181		polling-delay-passive = <250>;
182		thermal-sensors = <&scmi_sensor 3>;
183
184		trips {
185			pf5302_alert: trip0 {
186				hysteresis = <2000>;
187				temperature = <140000>;
188				type = "passive";
189			};
190
191			pf5302_crit: trip1 {
192				hysteresis = <2000>;
193				temperature = <155000>;
194				type = "critical";
195			};
196		};
197	};
198};
199
200&usdhc1 {
201	pinctrl-names = "default", "state_100mhz", "state_200mhz";
202	pinctrl-0 = <&pinctrl_usdhc1>;
203	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
204	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
205	bus-width = <8>;
206	non-removable;
207	no-sdio;
208	no-sd;
209	status = "okay";
210};
211
212&wdog3 {
213	status = "okay";
214};
215
216&scmi_iomuxc {
217	pinctrl_flexspi1: flexspi1grp {
218		fsl,pins = <IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B	0x19e>,
219			   <IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0	0x19e>,
220			   <IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1	0x19e>,
221			   <IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2	0x19e>,
222			   <IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3	0x19e>,
223			   /* SION to allow clock loopback from pad */
224			   <IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK	0x4000019e>,
225			   <IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS		0x4000019e>;
226	};
227
228	pinctrl_lpi2c2: lpi2c2grp {
229		fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL	0x4000191e>,
230			   <IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA	0x4000191e>;
231	};
232
233	pinctrl_sdvmmc: sdvmmcgrp {
234		fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7	0x11e>;
235	};
236
237	pinctrl_usdhc1: usdhc1grp {
238		fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK	0x158e>,
239			   <IMX95_PAD_SD1_CMD__USDHC1_CMD	0x138e>,
240			   <IMX95_PAD_SD1_DATA0__USDHC1_DATA0	0x138e>,
241			   <IMX95_PAD_SD1_DATA1__USDHC1_DATA1	0x138e>,
242			   <IMX95_PAD_SD1_DATA2__USDHC1_DATA2	0x138e>,
243			   <IMX95_PAD_SD1_DATA3__USDHC1_DATA3	0x138e>,
244			   <IMX95_PAD_SD1_DATA4__USDHC1_DATA4	0x138e>,
245			   <IMX95_PAD_SD1_DATA5__USDHC1_DATA5	0x138e>,
246			   <IMX95_PAD_SD1_DATA6__USDHC1_DATA6	0x138e>,
247			   <IMX95_PAD_SD1_DATA7__USDHC1_DATA7	0x138e>,
248			   <IMX95_PAD_SD1_STROBE__USDHC1_STROBE	0x158e>;
249	};
250
251	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
252		fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK	0x158e>,
253			   <IMX95_PAD_SD1_CMD__USDHC1_CMD	0x138e>,
254			   <IMX95_PAD_SD1_DATA0__USDHC1_DATA0	0x138e>,
255			   <IMX95_PAD_SD1_DATA1__USDHC1_DATA1	0x138e>,
256			   <IMX95_PAD_SD1_DATA2__USDHC1_DATA2	0x138e>,
257			   <IMX95_PAD_SD1_DATA3__USDHC1_DATA3	0x138e>,
258			   <IMX95_PAD_SD1_DATA4__USDHC1_DATA4	0x138e>,
259			   <IMX95_PAD_SD1_DATA5__USDHC1_DATA5	0x138e>,
260			   <IMX95_PAD_SD1_DATA6__USDHC1_DATA6	0x138e>,
261			   <IMX95_PAD_SD1_DATA7__USDHC1_DATA7	0x138e>,
262			   <IMX95_PAD_SD1_STROBE__USDHC1_STROBE	0x158e>;
263	};
264
265	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
266		fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK	0x15fe>,
267			   <IMX95_PAD_SD1_CMD__USDHC1_CMD	0x13fe>,
268			   <IMX95_PAD_SD1_DATA0__USDHC1_DATA0	0x13fe>,
269			   <IMX95_PAD_SD1_DATA1__USDHC1_DATA1	0x13fe>,
270			   <IMX95_PAD_SD1_DATA2__USDHC1_DATA2	0x13fe>,
271			   <IMX95_PAD_SD1_DATA3__USDHC1_DATA3	0x13fe>,
272			   <IMX95_PAD_SD1_DATA4__USDHC1_DATA4	0x13fe>,
273			   <IMX95_PAD_SD1_DATA5__USDHC1_DATA5	0x13fe>,
274			   <IMX95_PAD_SD1_DATA6__USDHC1_DATA6	0x13fe>,
275			   <IMX95_PAD_SD1_DATA7__USDHC1_DATA7	0x13fe>,
276			   <IMX95_PAD_SD1_STROBE__USDHC1_STROBE	0x15fe>;
277	};
278};
279