1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2026 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/pwm/pwm.h> 9#include <dt-bindings/usb/pd.h> 10#include "imx95.dtsi" 11 12#define FALLING_EDGE 1 13#define RISING_EDGE 2 14 15#define BRD_SM_CTRL_SD3_WAKE 0x8000 /*!< PCAL6408A-0 */ 16#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 /*!< PCAL6408A-4 */ 17#define BRD_SM_CTRL_BT_WAKE 0x8002 /*!< PCAL6408A-5 */ 18#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /*!< PCAL6408A-6 */ 19#define BRD_SM_CTRL_BUTTON 0x8004 /*!< PCAL6408A-7 */ 20 21/ { 22 model = "NXP FRDM-IMX95-PRO"; 23 compatible = "fsl,imx95-19x19-frdm-pro", "fsl,imx95"; 24 25 aliases { 26 ethernet0 = &enetc_port0; 27 ethernet1 = &enetc_port1; 28 gpio0 = &gpio1; 29 gpio1 = &gpio2; 30 gpio2 = &gpio3; 31 gpio3 = &gpio4; 32 gpio4 = &gpio5; 33 i2c0 = &lpi2c1; 34 i2c1 = &lpi2c2; 35 i2c2 = &lpi2c3; 36 i2c3 = &lpi2c4; 37 mmc0 = &usdhc1; 38 mmc1 = &usdhc2; 39 serial0 = &lpuart1; 40 serial4 = &lpuart5; 41 }; 42 43 bt_sco_codec: bt-sco-codec { 44 compatible = "linux,bt-sco"; 45 #sound-dai-cells = <1>; 46 }; 47 48 flexcan1_phy: can-phy0 { 49 compatible = "nxp,tja1057"; 50 #phy-cells = <0>; 51 max-bitrate = <5000000>; 52 silent-gpios = <&i2c4_gpio_expander_22 11 GPIO_ACTIVE_HIGH>; 53 }; 54 55 flexcan3_phy: can-phy2 { 56 compatible = "nxp,tja1057"; 57 #phy-cells = <0>; 58 max-bitrate = <5000000>; 59 silent-gpios = <&i2c4_gpio_expander_22 13 GPIO_ACTIVE_HIGH>; 60 }; 61 62 chosen { 63 #address-cells = <2>; 64 #size-cells = <2>; 65 stdout-path = &lpuart1; 66 }; 67 68 reg_vref_1v8: regulator-1p8v { 69 compatible = "regulator-fixed"; 70 regulator-name = "+V1.8_SW"; 71 regulator-max-microvolt = <1800000>; 72 regulator-min-microvolt = <1800000>; 73 }; 74 75 reg_3p3v: regulator-3p3v { 76 compatible = "regulator-fixed"; 77 regulator-name = "+V3.3_SW"; 78 regulator-max-microvolt = <3300000>; 79 regulator-min-microvolt = <3300000>; 80 }; 81 82 reg_dcdc_3v3: regulator-dcdc-3v3 { 83 compatible = "regulator-fixed"; 84 regulator-name = "DCDC_3V3"; 85 regulator-always-on; 86 regulator-max-microvolt = <3300000>; 87 regulator-min-microvolt = <3300000>; 88 vin-supply = <®_dcdc_5v>; 89 gpio = <&i2c4_gpio_expander_22 18 GPIO_ACTIVE_HIGH>; 90 enable-active-high; 91 }; 92 93 reg_dcdc_5v: regulator-dcdc-5v { 94 compatible = "regulator-fixed"; 95 regulator-name = "DCDC_5V"; 96 regulator-always-on; 97 regulator-max-microvolt = <5000000>; 98 regulator-min-microvolt = <5000000>; 99 gpio = <&i2c4_gpio_expander_22 1 GPIO_ACTIVE_HIGH>; 100 enable-active-high; 101 }; 102 103 reg_exp_1v8: regulator-exp-1v8 { 104 compatible = "regulator-fixed"; 105 regulator-name = "EXP_1V8"; 106 regulator-max-microvolt = <1800000>; 107 regulator-min-microvolt = <1800000>; 108 gpio = <&i2c4_gpio_expander_22 10 GPIO_ACTIVE_HIGH>; 109 enable-active-high; 110 }; 111 112 reg_exp_3v3: regulator-exp-3v3 { 113 compatible = "regulator-fixed"; 114 regulator-name = "EXP_3V3"; 115 regulator-max-microvolt = <3300000>; 116 regulator-min-microvolt = <3300000>; 117 vin-supply = <®_dcdc_3v3>; 118 gpio = <&i2c4_gpio_expander_22 6 GPIO_ACTIVE_HIGH>; 119 enable-active-high; 120 }; 121 122 reg_exp_5v: regulator-exp-5v { 123 compatible = "regulator-fixed"; 124 regulator-name = "EXP_5V"; 125 regulator-always-on; 126 regulator-max-microvolt = <5000000>; 127 regulator-min-microvolt = <5000000>; 128 vin-supply = <®_dcdc_5v>; 129 gpio = <&i2c4_gpio_expander_22 5 GPIO_ACTIVE_HIGH>; 130 enable-active-high; 131 }; 132 133 reg_exp_12v: regulator-exp-12v { 134 compatible = "regulator-fixed"; 135 regulator-name = "VCCEXP_12V"; 136 regulator-always-on; 137 regulator-max-microvolt = <12000000>; 138 regulator-min-microvolt = <12000000>; 139 gpio = <&i2c4_gpio_expander_22 17 GPIO_ACTIVE_HIGH>; 140 enable-active-high; 141 }; 142 143 reg_m2_mkey_1_pwr: regulator-m2-mkey-1-pwr { 144 compatible = "regulator-fixed"; 145 regulator-name = "M.2-power-mkey-1"; 146 regulator-always-on; 147 regulator-max-microvolt = <3300000>; 148 regulator-min-microvolt = <3300000>; 149 gpio = <&i2c3_gpio_expander_20 4 GPIO_ACTIVE_HIGH>; 150 enable-active-high; 151 }; 152 153 reg_m2_mkey_2_pwr: regulator-m2-mkey-2-pwr { 154 compatible = "regulator-fixed"; 155 regulator-name = "M.2-power-mkey-2"; 156 regulator-always-on; 157 regulator-max-microvolt = <3300000>; 158 regulator-min-microvolt = <3300000>; 159 gpio = <&i2c3_gpio_expander_20 6 GPIO_ACTIVE_HIGH>; 160 enable-active-high; 161 }; 162 163 reg_m2_ekey_pwr: regulator-m2-pwr { 164 compatible = "regulator-fixed"; 165 regulator-name = "M.2-power-ekey"; 166 regulator-always-on; 167 regulator-max-microvolt = <3300000>; 168 regulator-min-microvolt = <3300000>; 169 gpio = <&i2c4_gpio_expander_22 7 GPIO_ACTIVE_HIGH>; 170 enable-active-high; 171 }; 172 173 reg_usdhc2_vmmc: regulator-usdhc2 { 174 compatible = "regulator-fixed"; 175 regulator-name = "VDD_SD2_3V3"; 176 off-on-delay-us = <12000>; 177 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 178 pinctrl-names = "default"; 179 regulator-max-microvolt = <3300000>; 180 regulator-min-microvolt = <3300000>; 181 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 182 enable-active-high; 183 }; 184 185 reg_usdhc3_vmmc: regulator-usdhc3 { 186 compatible = "regulator-fixed"; 187 regulator-name = "WLAN_EN"; 188 regulator-max-microvolt = <3300000>; 189 regulator-min-microvolt = <3300000>; 190 vin-supply = <®_m2_ekey_pwr>; 191 gpio = <&i2c4_gpio_expander_22 8 GPIO_ACTIVE_HIGH>; 192 enable-active-high; 193 /* 194 * IW612 wifi chip needs more delay than other wifi chips to complete 195 * the host interface initialization after power up, otherwise the 196 * internal state of IW612 may be unstable, resulting in the failure of 197 * the SDIO3.0 switch voltage. 198 */ 199 startup-delay-us = <20000>; 200 }; 201 202 reg_usb_vbus: regulator-vbus { 203 compatible = "regulator-fixed"; 204 regulator-name = "USB_VBUS"; 205 regulator-max-microvolt = <5000000>; 206 regulator-min-microvolt = <5000000>; 207 gpio = <&i2c4_gpio_expander_22 0 GPIO_ACTIVE_HIGH>; 208 enable-active-high; 209 }; 210 211 reserved-memory { 212 ranges; 213 #address-cells = <2>; 214 #size-cells = <2>; 215 216 linux_cma: linux,cma { 217 compatible = "shared-dma-pool"; 218 alloc-ranges = <0 0x80000000 0 0x7F000000>; 219 reusable; 220 size = <0 0x3c000000>; 221 linux,cma-default; 222 }; 223 }; 224 225 sound-bt-sco { 226 compatible = "simple-audio-card"; 227 simple-audio-card,bitclock-inversion; 228 simple-audio-card,bitclock-master = <&btcpu>; 229 simple-audio-card,format = "dsp_a"; 230 simple-audio-card,frame-master = <&btcpu>; 231 simple-audio-card,name = "bt-sco-audio"; 232 233 simple-audio-card,codec { 234 sound-dai = <&bt_sco_codec 1>; 235 }; 236 237 btcpu: simple-audio-card,cpu { 238 dai-tdm-slot-num = <2>; 239 dai-tdm-slot-width = <16>; 240 sound-dai = <&sai5>; 241 }; 242 }; 243 244 sound-micfil { 245 compatible = "fsl,imx-audio-card"; 246 model = "micfil-audio"; 247 248 pri-dai-link { 249 format = "i2s"; 250 link-name = "micfil hifi"; 251 252 cpu { 253 sound-dai = <&micfil>; 254 }; 255 }; 256 }; 257 258 sound-mqs { 259 compatible = "audio-graph-card2"; 260 links = <&sai1_port1>; 261 label = "mqs-audio"; 262 }; 263 264 usdhc3_pwrseq: usdhc3-pwrseq { 265 compatible = "mmc-pwrseq-simple"; 266 reset-gpios = <&i2c4_gpio_expander_22 9 GPIO_ACTIVE_LOW>; 267 }; 268 269 memory@80000000 { 270 reg = <0x0 0x80000000 0 0x80000000>; 271 device_type = "memory"; 272 }; 273}; 274 275&adc1 { 276 vref-supply = <®_vref_1v8>; 277 status = "okay"; 278}; 279 280&enetc_port0 { 281 phy-handle = <ðphy0>; 282 phy-mode = "rgmii-id"; 283 pinctrl-0 = <&pinctrl_enetc0>; 284 pinctrl-names = "default"; 285 status = "okay"; 286}; 287 288&enetc_port1 { 289 phy-handle = <ðphy1>; 290 phy-mode = "rgmii-id"; 291 pinctrl-0 = <&pinctrl_enetc1>; 292 pinctrl-names = "default"; 293 status = "okay"; 294}; 295 296&flexcan1 { 297 phys = <&flexcan1_phy>; 298 pinctrl-0 = <&pinctrl_flexcan1>; 299 pinctrl-names = "default"; 300 status = "reserved"; 301}; 302 303&flexcan3 { 304 phys = <&flexcan3_phy>; 305 pinctrl-0 = <&pinctrl_flexcan3>; 306 pinctrl-names = "default"; 307 status = "okay"; 308}; 309 310&lpi2c3 { 311 clock-frequency = <400000>; 312 pinctrl-0 = <&pinctrl_lpi2c3>; 313 pinctrl-names = "default"; 314 status = "okay"; 315 316 i2c3_gpio_expander_20: i2c3-gpio-expander@20 { 317 compatible = "nxp,pcal6416"; 318 reg = <0x20>; 319 #interrupt-cells = <2>; 320 interrupt-controller; 321 interrupt-parent = <&gpio5>; 322 interrupts = <14 IRQ_TYPE_LEVEL_LOW>; 323 #gpio-cells = <2>; 324 gpio-controller; 325 pinctrl-0 = <&pinctrl_pcal6416>; 326 pinctrl-names = "default"; 327 }; 328 329 ptn5110: tcpc@50 { 330 compatible = "nxp,ptn5110", "tcpci"; 331 reg = <0x50>; 332 interrupt-parent = <&gpio5>; 333 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 334 pinctrl-0 = <&pinctrl_ptn5110>; 335 pinctrl-names = "default"; 336 337 typec_con: connector { 338 compatible = "usb-c-connector"; 339 data-role = "dual"; 340 label = "USB-C"; 341 op-sink-microwatt = <0>; 342 power-role = "dual"; 343 self-powered; 344 sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>; 345 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 346 try-power-role = "sink"; 347 348 ports { 349 #address-cells = <1>; 350 #size-cells = <0>; 351 352 port@0 { 353 reg = <0>; 354 355 typec_con_hs: endpoint { 356 remote-endpoint = <&usb3_data_hs>; 357 }; 358 }; 359 360 port@1 { 361 reg = <1>; 362 363 typec_con_ss: endpoint { 364 remote-endpoint = <&usb3_data_ss>; 365 }; 366 }; 367 }; 368 }; 369 }; 370}; 371 372&lpi2c4 { 373 clock-frequency = <400000>; 374 pinctrl-0 = <&pinctrl_lpi2c4>; 375 pinctrl-names = "default"; 376 status = "okay"; 377 378 i2c4_gpio_expander_22: i2c4-gpio-expander@22 { 379 compatible = "nxp,pcal6524"; 380 reg = <0x22>; 381 #gpio-cells = <2>; 382 gpio-controller; 383 gpio-line-names = "USB2 Power Enable", 384 "DCDC5V Enable", 385 "", 386 "SE Enable", 387 "", 388 "EXP 5V Enable", 389 "EXP 3V3 Enable", 390 "WIFI Power Enable", 391 "M2 DIS1 B", 392 "WIFI SD3 Reset", 393 "EXP 1V8 Enable", 394 "CAN1 Standby", 395 "M2 DIS2", 396 "CAN2 Standby", 397 "ETH 10G IO4", 398 "ETH 10G IO3", 399 "SPI3/GPIO select", 400 "EXP 12V Enable", 401 "DCDC 3V3 Enable", 402 "PCIE1 Reset", 403 "", 404 "ETH 10G CLK Enable", 405 "LVDS to HDMI converter IT6263 reset", 406 ""; 407 408 /* When high, select lpspi; When low, select gpio. */ 409 lpspi-gpio-sel-hog { 410 gpios = <16 GPIO_ACTIVE_HIGH>; 411 gpio-hog; 412 output-high; 413 }; 414 }; 415}; 416 417&lpuart1 { 418 /* console */ 419 pinctrl-names = "default"; 420 pinctrl-0 = <&pinctrl_uart1>; 421 status = "okay"; 422}; 423 424&lpuart5 { 425 /* BT */ 426 pinctrl-names = "default"; 427 pinctrl-0 = <&pinctrl_uart5>; 428 status = "okay"; 429 430 bluetooth { 431 compatible = "nxp,88w8987-bt"; 432 }; 433}; 434 435&micfil { 436 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 437 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 438 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 439 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 440 <&scmi_clk IMX95_CLK_PDM>; 441 assigned-clock-parents = <0>, <0>, <0>, <0>, 442 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 443 assigned-clock-rates = <3932160000>, 444 <3612672000>, <393216000>, 445 <361267200>, <49152000>; 446 #sound-dai-cells = <0>; 447 pinctrl-0 = <&pinctrl_pdm>; 448 pinctrl-names = "default"; 449 status = "okay"; 450}; 451 452&mqs1 { 453 clocks = <&scmi_clk IMX95_CLK_SAI1>; 454 clock-names = "mclk"; 455 pinctrl-0 = <&pinctrl_mqs1>; 456 pinctrl-names = "default"; 457 status = "okay"; 458 459 mqs1_port: port { 460 mqs1_ep: endpoint { 461 dai-format = "left_j"; 462 remote-endpoint = <&sai1_port1_ep>; 463 }; 464 }; 465}; 466 467&netc_blk_ctrl { 468 status = "okay"; 469}; 470 471&netc_emdio { 472 pinctrl-0 = <&pinctrl_emdio>; 473 pinctrl-names = "default"; 474 status = "okay"; 475 476 ethphy0: ethernet-phy@1 { 477 reg = <1>; 478 reset-assert-us = <10000>; 479 reset-deassert-us = <80000>; 480 reset-gpios = <&i2c3_gpio_expander_20 1 GPIO_ACTIVE_LOW>; 481 }; 482 483 ethphy1: ethernet-phy@2 { 484 reg = <2>; 485 reset-assert-us = <10000>; 486 reset-deassert-us = <80000>; 487 reset-gpios = <&i2c3_gpio_expander_20 2 GPIO_ACTIVE_LOW>; 488 }; 489}; 490 491&netc_timer { 492 status = "okay"; 493}; 494 495&netcmix_blk_ctrl { 496 status = "okay"; 497}; 498 499&pcie0 { 500 pinctrl-0 = <&pinctrl_pcie0>; 501 pinctrl-names = "default"; 502 reset-gpio = <&i2c4_gpio_expander_22 19 GPIO_ACTIVE_LOW>; 503 vpcie-supply = <®_m2_mkey_1_pwr>; 504 status = "okay"; 505}; 506 507&pcie1 { 508 pinctrl-0 = <&pinctrl_pcie1>; 509 pinctrl-names = "default"; 510 reset-gpio = <&i2c3_gpio_expander_20 9 GPIO_ACTIVE_LOW>; 511 vpcie-supply = <®_m2_mkey_2_pwr>; 512 status = "okay"; 513}; 514 515&sai1 { 516 clocks = <&scmi_clk IMX95_CLK_BUSAON>, <&dummy>, 517 <&scmi_clk IMX95_CLK_SAI1>, <&dummy>, 518 <&dummy>, <&scmi_clk IMX95_CLK_AUDIOPLL1>, 519 <&scmi_clk IMX95_CLK_AUDIOPLL2>; 520 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; 521 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 522 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 523 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 524 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 525 <&scmi_clk IMX95_CLK_SAI1>; 526 assigned-clock-parents = <0>, <0>, <0>, <0>, 527 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 528 assigned-clock-rates = <3932160000>, 529 <3612672000>, <393216000>, 530 <361267200>, <24576000>; 531 #sound-dai-cells = <0>; 532 fsl,sai-mclk-direction-output; 533 status = "okay"; 534 535 ports { 536 #address-cells = <1>; 537 #size-cells = <0>; 538 539 /* leave unconnected - no RX in the context of MQS */ 540 port@0 { 541 reg = <0>; 542 543 endpoint { 544 }; 545 }; 546 547 sai1_port1: port@1 { 548 reg = <1>; 549 mclk-fs = <512>; 550 551 sai1_port1_ep: endpoint { 552 dai-format = "left_j"; 553 system-clock-direction-out; 554 bitclock-master; 555 frame-master; 556 remote-endpoint = <&mqs1_ep>; 557 }; 558 }; 559 }; 560}; 561 562&sai5 { 563 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 564 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 565 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 566 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 567 <&scmi_clk IMX95_CLK_SAI5>; 568 assigned-clock-parents = <0>, <0>, <0>, <0>, 569 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 570 assigned-clock-rates = <3932160000>, 571 <3612672000>, <393216000>, 572 <361267200>, <12288000>; 573 #sound-dai-cells = <0>; 574 pinctrl-0 = <&pinctrl_sai5>; 575 pinctrl-names = "default"; 576 fsl,sai-mclk-direction-output; 577 status = "okay"; 578}; 579 580&scmi_iomuxc { 581 pinctrl-0 = <&pinctrl_hog>; 582 pinctrl-names = "default"; 583 584 pinctrl_emdio: emdiogrp { 585 fsl,pins = < 586 IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x50e 587 IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e 588 >; 589 }; 590 591 pinctrl_enetc0: enetc0grp { 592 fsl,pins = < 593 IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e 594 IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e 595 IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e 596 IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e 597 IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e 598 IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e 599 IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e 600 IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e 601 IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e 602 IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e 603 IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e 604 IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e 605 >; 606 }; 607 608 pinctrl_enetc1: enetc1grp { 609 fsl,pins = < 610 IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x50e 611 IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x50e 612 IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x50e 613 IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x50e 614 IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e 615 IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e 616 IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e 617 IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x58e 618 IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e 619 IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e 620 IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e 621 IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e 622 >; 623 }; 624 625 pinctrl_flexcan1: flexcan1grp { 626 fsl,pins = < 627 IMX95_PAD_SAI1_TXD0__AONMIX_TOP_CAN1_TX 0x39e 628 IMX95_PAD_SAI1_TXC__AONMIX_TOP_CAN1_RX 0x39e 629 >; 630 }; 631 632 pinctrl_flexcan3: flexcan3grp { 633 fsl,pins = < 634 IMX95_PAD_CCM_CLKO3__CAN3_TX 0x39e 635 IMX95_PAD_CCM_CLKO4__CAN3_RX 0x39e 636 >; 637 }; 638 639 pinctrl_hog: hoggrp { 640 fsl,pins = < 641 IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x31e 642 >; 643 }; 644 645 pinctrl_lpi2c3: lpi2c3grp { 646 fsl,pins = < 647 IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 648 IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 649 >; 650 }; 651 652 pinctrl_lpi2c4: lpi2c4grp { 653 fsl,pins = < 654 IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e 655 IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e 656 >; 657 }; 658 659 pinctrl_mqs1: mqs1grp { 660 fsl,pins = < 661 IMX95_PAD_SAI1_TXFS__AONMIX_TOP_MQS1_LEFT 0x31e 662 IMX95_PAD_SAI1_RXD0__AONMIX_TOP_MQS1_RIGHT 0x31e 663 >; 664 }; 665 666 pinctrl_pcal6416: pcal6416grp { 667 fsl,pins = < 668 IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e 669 >; 670 }; 671 672 pinctrl_pcie0: pcie0grp { 673 fsl,pins = < 674 IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x4000031e 675 >; 676 }; 677 678 pinctrl_pcie1: pcie1grp { 679 fsl,pins = < 680 IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x4000031e 681 >; 682 }; 683 684 pinctrl_pdm: pdmgrp { 685 fsl,pins = < 686 IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e 687 IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e 688 >; 689 }; 690 691 pinctrl_ptn5110: ptn5110grp { 692 fsl,pins = < 693 IMX95_PAD_XSPI1_DQS__GPIO5_IO_BIT8 0x31e 694 >; 695 }; 696 697 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 698 fsl,pins = < 699 IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e 700 >; 701 }; 702 703 pinctrl_sai5: sai5grp { 704 fsl,pins = < 705 IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x31e 706 IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK 0x31e 707 IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC 0x31e 708 IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x31e 709 >; 710 }; 711 712 pinctrl_uart1: uart1grp { 713 fsl,pins = < 714 IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e 715 IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e 716 >; 717 }; 718 719 pinctrl_uart5: uart5grp { 720 fsl,pins = < 721 IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 722 IMX95_PAD_DAP_TDI__LPUART5_RX 0x31e 723 IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 724 IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 725 >; 726 }; 727 728 pinctrl_usdhc1: usdhc1grp { 729 fsl,pins = < 730 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e 731 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e 732 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 733 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 734 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 735 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 736 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 737 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 738 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 739 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 740 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 741 >; 742 }; 743 744 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 745 fsl,pins = < 746 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e 747 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e 748 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 749 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 750 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 751 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 752 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 753 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 754 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 755 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 756 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 757 >; 758 }; 759 760 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 761 fsl,pins = < 762 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe 763 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe 764 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 765 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 766 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 767 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 768 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 769 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 770 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 771 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 772 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 773 >; 774 }; 775 776 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 777 fsl,pins = < 778 IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e 779 >; 780 }; 781 782 pinctrl_usdhc2: usdhc2grp { 783 fsl,pins = < 784 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e 785 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e 786 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 787 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 788 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 789 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 790 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 791 >; 792 }; 793 794 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 795 fsl,pins = < 796 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e 797 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e 798 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 799 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 800 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 801 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 802 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 803 >; 804 }; 805 806 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 807 fsl,pins = < 808 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e 809 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e 810 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 811 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 812 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 813 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 814 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 815 >; 816 }; 817 818 pinctrl_usdhc3: usdhc3grp { 819 fsl,pins = < 820 IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e 821 IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e 822 IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e 823 IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e 824 IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e 825 IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e 826 >; 827 }; 828 829 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 830 fsl,pins = < 831 IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e 832 IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e 833 IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e 834 IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e 835 IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e 836 IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e 837 >; 838 }; 839 840 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 841 fsl,pins = < 842 IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe 843 IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe 844 IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe 845 IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe 846 IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe 847 IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe 848 >; 849 }; 850}; 851 852&scmi_misc { 853 nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE FALLING_EDGE 854 BRD_SM_CTRL_PCIE1_WAKE FALLING_EDGE 855 BRD_SM_CTRL_BT_WAKE FALLING_EDGE 856 BRD_SM_CTRL_PCIE2_WAKE FALLING_EDGE 857 BRD_SM_CTRL_BUTTON FALLING_EDGE>; 858}; 859 860&thermal_zones { 861 pf09-thermal { 862 polling-delay = <2000>; 863 polling-delay-passive = <250>; 864 thermal-sensors = <&scmi_sensor 2>; 865 866 trips { 867 pf09_alert: trip0 { 868 hysteresis = <2000>; 869 temperature = <140000>; 870 type = "passive"; 871 }; 872 873 pf09_crit: trip1 { 874 hysteresis = <2000>; 875 temperature = <155000>; 876 type = "critical"; 877 }; 878 }; 879 }; 880 881 pf53arm-thermal { 882 polling-delay = <2000>; 883 polling-delay-passive = <250>; 884 thermal-sensors = <&scmi_sensor 4>; 885 886 cooling-maps { 887 map0 { 888 cooling-device = <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 889 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 890 <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 891 <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 892 <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 893 <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 894 trip = <&pf5301_alert>; 895 }; 896 }; 897 898 trips { 899 pf5301_alert: trip0 { 900 hysteresis = <2000>; 901 temperature = <140000>; 902 type = "passive"; 903 }; 904 905 pf5301_crit: trip1 { 906 hysteresis = <2000>; 907 temperature = <155000>; 908 type = "critical"; 909 }; 910 }; 911 }; 912 913 pf53soc-thermal { 914 polling-delay = <2000>; 915 polling-delay-passive = <250>; 916 thermal-sensors = <&scmi_sensor 3>; 917 918 trips { 919 pf5302_alert: trip0 { 920 hysteresis = <2000>; 921 temperature = <140000>; 922 type = "passive"; 923 }; 924 925 pf5302_crit: trip1 { 926 hysteresis = <2000>; 927 temperature = <155000>; 928 type = "critical"; 929 }; 930 }; 931 }; 932}; 933 934&usb2 { 935 disable-over-current; 936 dr_mode = "host"; 937 vbus-supply = <®_usb_vbus>; 938 status = "okay"; 939}; 940 941&usb3 { 942 status = "okay"; 943}; 944 945&usb3_dwc3 { 946 adp-disable; 947 dr_mode = "otg"; 948 hnp-disable; 949 role-switch-default-mode = "peripheral"; 950 srp-disable; 951 usb-role-switch; 952 snps,dis-u1-entry-quirk; 953 snps,dis-u2-entry-quirk; 954 status = "okay"; 955 956 port { 957 usb3_data_hs: endpoint { 958 remote-endpoint = <&typec_con_hs>; 959 }; 960 }; 961}; 962 963&usb3_phy { 964 orientation-switch; 965 fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <17>; 966 fsl,phy-pcs-tx-swing-full-percent = <100>; 967 fsl,phy-tx-preemp-amp-tune-microamp = <600>; 968 fsl,phy-tx-vboost-level-microvolt = <1156>; 969 fsl,phy-tx-vref-tune-percent = <100>; 970 status = "okay"; 971 972 port { 973 usb3_data_ss: endpoint { 974 remote-endpoint = <&typec_con_ss>; 975 }; 976 }; 977}; 978 979&usdhc1 { 980 bus-width = <8>; 981 non-removable; 982 no-sd; 983 no-sdio; 984 pinctrl-0 = <&pinctrl_usdhc1>; 985 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 986 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 987 pinctrl-3 = <&pinctrl_usdhc1>; 988 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 989 status = "okay"; 990}; 991 992&usdhc2 { 993 bus-width = <4>; 994 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 995 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 996 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 997 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 998 pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 999 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 1000 vmmc-supply = <®_usdhc2_vmmc>; 1001 status = "okay"; 1002}; 1003 1004&usdhc3 { 1005 bus-width = <4>; 1006 keep-power-in-suspend; 1007 mmc-pwrseq = <&usdhc3_pwrseq>; 1008 non-removable; 1009 pinctrl-0 = <&pinctrl_usdhc3>; 1010 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 1011 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 1012 pinctrl-3 = <&pinctrl_usdhc3>; 1013 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 1014 vmmc-supply = <®_usdhc3_vmmc>; 1015 wakeup-source; 1016 status = "okay"; 1017}; 1018 1019&wdog3 { 1020 status = "okay"; 1021}; 1022